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| i.MX23 Applications Processor Reference Manual IMX23RM Rev. 1 11/2009 Preliminary--Subject to Change Without Notice How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. 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Document Number: IMX23RM Rev. 1, 11/2009 Preliminary--Subject to Change Without Notice Contents Paragraph Number Title Contents Page Number Chapter 1 Product Overview 1.1 1.2 1.2.1 1.2.2 1.2.2.1 1.2.2.2 1.2.2.3 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 1.2.11 1.2.12 1.2.12.1 1.2.12.2 1.2.13 1.2.14 1.2.15 1.2.16 1.2.17 1.2.18 1.2.19 1.2.19.1 1.2.19.2 1.2.19.3 1.2.19.4 1.2.20 1.2.21 1.2.22 1.2.23 1.2.24 1.2.25 Hardware Features ........................................................................................................... 1-2 i.MX23 Product Features ................................................................................................. 1-5 ARM 926 Processor Core ............................................................................................ 1-7 System Buses ............................................................................................................... 1-7 AXI Bus ................................................................................................................... 1-9 AHB Bus.................................................................................................................. 1-9 APB Buses ............................................................................................................... 1-9 On-Chip RAM and ROM .......................................................................................... 1-10 External Memory Interface........................................................................................ 1-10 On-Chip One-Time-Programmable (OCOTP) ROM ................................................ 1-12 Interrupt Collector...................................................................................................... 1-12 DMA Controller......................................................................................................... 1-12 Clock Generation Subsystem..................................................................................... 1-13 Power Management Unit ........................................................................................... 1-13 USB Interface ............................................................................................................ 1-14 General-Purpose Media Interface (GPMI) ................................................................ 1-15 Hardware Acceleration for ECC for Robust External Storage .................................. 1-15 Reed-Solomon ECC Engine .................................................................................. 1-16 Bose Ray-Choudhury Hocquenghem ECC Engine ............................................... 1-16 Data Co-Processor (DCP)--Memory Copy, Crypto, and Color-Space Converter.................................................................................... 1-17 Mixed Signal Audio Subsystem ................................................................................ 1-17 Master Digital Control Unit (DIGCTL)..................................................................... 1-19 Synchronous Serial Port (SSP) .................................................................................. 1-19 I2C Interface............................................................................................................... 1-19 General-Purpose Input/Output (GPIO)...................................................................... 1-19 Display Processing..................................................................................................... 1-19 Display Controller / LCD Interface (LCDIF)........................................................ 1-20 Pixel Processing Pipeline (PXP)............................................................................ 1-21 PAL/NTSC TV-Encoder ........................................................................................ 1-21 Video DAC ............................................................................................................ 1-22 SPDIF Transmitter ..................................................................................................... 1-22 Dual Serial Audio Interfaces...................................................................................... 1-22 Timers and Rotary Decoder ....................................................................................... 1-22 UARTs ....................................................................................................................... 1-22 Low-Resolution ADC, Touch-Screen Interface, and Temperature Sensor................ 1-23 Pulse Width Modulator (PWM) Controller ............................................................... 1-23 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice i Contents Paragraph Number 1.2.26 Title Page Number Real-Time Clock, Alarm, Watchdog, Persistent Bits................................................. 1-24 Chapter 2 Characteristics and Specifications 2.1 2.2 2.3 2.3.1 2.4 2.4.1 2.4.2 2.4.3 Absolute Maximum Ratings ............................................................................................ 2-1 Recommended Operating Conditions .............................................................................. 2-2 DC Characteristics ........................................................................................................... 2-4 Recommended Operating Conditions for Specific Clock Targets............................... 2-9 AC Characteristics ......................................................................................................... 2-12 EMI Electrical Specifications .................................................................................... 2-12 I2C Electrical Specifications...................................................................................... 2-14 LCD AC Output Electrical Specifications................................................................. 2-15 Chapter 3 ARM CPU Complex 3.1 3.2 3.2.1 3.2.2 3.2.3 3.3 ARM 926 Processor Core ................................................................................................ 3-1 JTAG Debugger ............................................................................................................... 3-3 JTAG READ ID........................................................................................................... 3-3 JTAG Hardware Reset ................................................................................................. 3-3 JTAG Interaction with CPUCLK................................................................................. 3-4 Embedded Trace Macrocell (ETM) Interface (169BGA-only) ....................................... 3-4 Chapter 4 Clock Generation and Control 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.3.1 4.2.3.2 4.2.3.3 4.3 4.3.1 4.3.2 4.3.2.1 4.3.2.1.1 4.3.3 Overview.......................................................................................................................... 4-1 Clock Structure ................................................................................................................ 4-1 Table of System Clocks ............................................................................................... 4-2 Logical Diagram of Clock Domains............................................................................ 4-4 Clock Domain Description .......................................................................................... 4-5 CLK_P, CLK_H....................................................................................................... 4-5 CLK_EMI ................................................................................................................ 4-6 System Clocks ......................................................................................................... 4-6 CLKCTRL Digital Clock Divider ................................................................................... 4-6 Integer Clock Divide Mode ......................................................................................... 4-6 Fractional Clock Divide Mode .................................................................................... 4-7 Fractional Clock Divide Example, Divide by 3.5.................................................... 4-7 Fractional ClockDivide Example, Divide by 3/8 ................................................ 4-8 Gated Clock Divide Mode ........................................................................................... 4-8 i.MX23 Applications Processor Reference Manual, Rev. 1 ii Preliminary--Subject to Change Without Notice Freescale Semiconductor Contents Paragraph Number 4.4 4.5 4.6 4.7 4.8 Title Page Number Clock Frequency Management ........................................................................................ 4-9 Analog Clock Control ...................................................................................................... 4-9 CPU and EMI Clock Programming ................................................................................. 4-9 Chip Reset...................................................................................................................... 4-10 Programmable Registers ................................................................................................ 4-11 Chapter 5 Interrupt Collector 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.3 5.4 Overview.......................................................................................................................... 5-1 Operation ......................................................................................................................... 5-2 Nesting of Multi-Level IRQ Interrupts........................................................................ 5-4 FIQ Generation ............................................................................................................ 5-6 Interrupt Sources.......................................................................................................... 5-6 CPU Wait-for-Interrupt Mode...................................................................................... 5-9 Behavior During Reset................................................................................................... 5-10 Programmable Registers ................................................................................................ 5-10 Chapter 6 Digital Control and On-Chip RAM 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 Overview.......................................................................................................................... 6-1 SRAM Controls ............................................................................................................... 6-2 Miscellaneous Controls.................................................................................................... 6-3 Performance Monitoring.............................................................................................. 6-3 High-Entropy PRN Seed.............................................................................................. 6-4 Write-Once Register .................................................................................................... 6-4 Microseconds Counter ................................................................................................. 6-4 Programmable Registers .................................................................................................. 6-4 Chapter 7 On-Chip OTP (OCOTP) Controller 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.4 Overview.......................................................................................................................... 7-1 Operation ......................................................................................................................... 7-2 Software Read Sequence ............................................................................................. 7-4 Software Write Sequence............................................................................................. 7-5 Write Postamble........................................................................................................... 7-6 Shadow Registers and Hardware Capability Bus ........................................................ 7-6 Behavior During Reset..................................................................................................... 7-7 Programmable Registers .................................................................................................. 7-7 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice iii Contents Paragraph Number Title Chapter 8 USB High-Speed Host/Device Controller 8.1 8.2 8.3 8.4 8.4.1 8.5 8.5.1 8.6 Overview.......................................................................................................................... 8-1 USB Programmed I/O (PIO) Target Interface ................................................................. 8-3 USB DMA Interface ........................................................................................................ 8-3 USB UTM Interface......................................................................................................... 8-3 Digital/Analog Loopback Test Mode .......................................................................... 8-3 USB Controller Flowcharts ............................................................................................. 8-4 References.................................................................................................................... 8-7 Programmable Registers .................................................................................................. 8-7 Chapter 9 Integrated USB 2.0 PHY 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.4.1 9.2.4.2 9.2.4.3 9.2.4.4 9.2.4.5 9.2.4.6 9.2.4.7 9.2.4.8 9.2.5 9.2.5.1 9.2.5.2 9.2.5.3 9.2.5.4 9.2.5.5 9.2.6 9.3 9.4 Overview.......................................................................................................................... 9-1 Operation ......................................................................................................................... 9-2 UTMI ........................................................................................................................... 9-2 Digital Transmitter....................................................................................................... 9-2 Digital Receiver ........................................................................................................... 9-2 Analog Receiver .......................................................................................................... 9-2 HS Differential Receiver ......................................................................................... 9-3 Squelch Detector...................................................................................................... 9-3 FS Differential Receiver .......................................................................................... 9-4 HS Disconnect Detector .......................................................................................... 9-4 USB Plugged-In Detector ........................................................................................ 9-4 Single-Ended USB_DP Receiver ............................................................................ 9-4 Single-Ended USB_DN Receiver............................................................................ 9-4 9X Oversample Module........................................................................................... 9-4 Analog Transmitter ...................................................................................................... 9-4 Switchable High-Speed 45 Termination Resistors................................................ 9-5 Full-Speed Differential Driver................................................................................. 9-5 High-Speed Differential Driver ............................................................................... 9-5 Switchable 1.5K USB_DP Pullup Resistor........................................................... 9-5 Switchable 15K USB_DP Pulldown Resistor ....................................................... 9-5 Recommended Register Configuration for USB Certification .................................... 9-7 Behavior During Reset..................................................................................................... 9-8 Programmable Registers .................................................................................................. 9-8 Page Number i.MX23 Applications Processor Reference Manual, Rev. 1 iv Preliminary--Subject to Change Without Notice Freescale Semiconductor Contents Paragraph Number Title Chapter 10 AHB-to-APBH Bridge with DMA 10.1 10.2 10.3 10.3.1 10.4 10.5 Overview........................................................................................................................ 10-1 AHBH DMA.................................................................................................................. 10-2 Implementation Examples ............................................................................................. 10-7 NAND Read Status Polling Example ........................................................................ 10-7 Behavior During Reset................................................................................................... 10-9 Programmable Registers ................................................................................................ 10-9 Chapter 11 AHB-to-APBX Bridge with DMA 11.1 11.2 11.3 11.4 11.5 Overview........................................................................................................................ 11-1 APBX DMA .................................................................................................................. 11-2 DMA Chain Example .................................................................................................... 11-6 Behavior During Reset................................................................................................... 11-7 Programmable Registers ................................................................................................ 11-8 Chapter 12 External Memory Interface (EMI) 12.1 12.1.1 12.2 12.2.1 12.2.2 12.2.2.1 12.2.2.2 12.2.2.3 12.2.3 12.2.3.1 12.2.3.2 12.2.4 12.2.5 12.2.6 12.2.6.1 12.2.6.2 12.2.6.3 12.2.6.4 12.2.6.5 Overview........................................................................................................................ 12-1 AHB Address Ranges ................................................................................................ 12-2 DRAM Controller .......................................................................................................... 12-3 Delay Compensation Circuit (DCC).......................................................................... 12-3 Address Mapping....................................................................................................... 12-3 DDR Address Mapping Options............................................................................ 12-4 Memory Controller Address Control..................................................................... 12-5 Out-of-Range Address Checking........................................................................... 12-5 Read Data Capture ..................................................................................................... 12-6 DQS Gating Control .............................................................................................. 12-7 mDDR Read Data Timing Registers ..................................................................... 12-8 Write Data Timing ..................................................................................................... 12-9 DRAM Clock Programmable Delay........................................................................ 12-11 Low-Power Operation.............................................................................................. 12-12 Low-Power Modes............................................................................................... 12-12 Low-Power Mode Control ................................................................................... 12-13 Automatic Entry................................................................................................... 12-13 Manual "On-Demand" Entry ............................................................................... 12-14 Register Programming ......................................................................................... 12-15 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice v Page Number Contents Paragraph Number 12.2.6.6 12.2.6.7 12.2.6.8 12.2.7 12.3 12.4 12.4.1 12.4.2 12.4.3 12.5 12.6 12.6.1 12.6.1.1 12.6.1.2 12.6.1.3 12.6.1.4 12.6.2 12.6.2.1 12.6.2.2 12.6.2.3 12.6.2.4 12.6.3 12.6.3.1 12.6.3.2 12.6.3.3 12.6.3.4 12.6.4 12.6.4.1 12.6.4.2 Title Page Number Refresh Masking.................................................................................................. 12-16 Mobile DDR Devices .......................................................................................... 12-17 Partial Array Self-Refresh ................................................................................... 12-17 EMI Clock Frequency Change Requirements ......................................................... 12-17 Power Management ..................................................................................................... 12-18 AXI/AHB Port Arbitration .......................................................................................... 12-18 Legacy Timestamp Mode ........................................................................................ 12-19 Timestamp/write-priority Hybrid Mode .................................................................. 12-19 Port Priority Mode ................................................................................................... 12-20 Programmable Registers .............................................................................................. 12-20 EMI Memory Parameters and Register Settings.......................................................... 12-68 Mobile DDR (5 nsec) Parameters............................................................................ 12-68 Bypass Cutoff ...................................................................................................... 12-68 Bypass Mode Enabled ......................................................................................... 12-68 Bypass Mode Disabled ........................................................................................ 12-69 Example Register Settings................................................................................... 12-69 Mobile DDR (6 nsec)............................................................................................... 12-70 Bypass Cutoff ...................................................................................................... 12-71 Bypass Mode Enabled ......................................................................................... 12-71 Bypass Mode Disabled ........................................................................................ 12-71 Example Register Settings................................................................................... 12-72 Mobile DDR (7.5 nsec)............................................................................................ 12-73 Bypass Cutoff ...................................................................................................... 12-73 Bypass Mode Enabled ......................................................................................... 12-74 Bypass Mode Disabled ........................................................................................ 12-74 Example Register Settings................................................................................... 12-74 DDR ......................................................................................................................... 12-76 Bypass Mode Disabled ........................................................................................ 12-76 Example Register Settings................................................................................... 12-77 Chapter 13 General-Purpose Media Interface (GPMI) 13.1 13.2 13.2.1 13.2.2 13.2.3 13.2.4 13.2.5 13.2.6 Overview........................................................................................................................ 13-1 GPMI NAND Flash Mode ............................................................................................. 13-2 Multiple NAND Flash Support.................................................................................. 13-3 GPMI NAND Flash Timing and Clocking ................................................................ 13-3 Basic NAND Flash Timing........................................................................................ 13-4 High-Speed NAND Flash Timing ............................................................................. 13-4 NAND Flash Command and Address Timing Example............................................ 13-6 Hardware BCH/ECC (ECC8) Interface..................................................................... 13-6 i.MX23 Applications Processor Reference Manual, Rev. 1 vi Preliminary--Subject to Change Without Notice Freescale Semiconductor Contents Paragraph Number 13.3 13.4 Title Page Number Behavior During Reset................................................................................................... 13-8 Programmable Registers ................................................................................................ 13-9 Chapter 14 8-Symbol Correcting ECC Accelerator (ECC8) 14.1 14.2 14.2.1 14.2.2 14.2.2.1 14.2.2.2 14.2.3 14.2.3.1 14.2.3.2 14.2.4 14.3 14.4 Overview........................................................................................................................ 14-1 Operation ....................................................................................................................... 14-4 Reed-Solomon ECC Accelerator ............................................................................... 14-8 Reed-Solomon ECC Encoding for NAND Writes................................................... 14-11 DMA Structure Code Example............................................................................ 14-15 Using the ECC8 Encoder..................................................................................... 14-18 Reed-Solomon ECC Decoding for NAND Reads ................................................... 14-19 DMA Structure Code Example............................................................................ 14-23 Using the Decoder ............................................................................................... 14-25 Interrupts.................................................................................................................. 14-27 Behavior During Reset................................................................................................. 14-28 Programmable Registers .............................................................................................. 14-28 Chapter 15 20-BIT Correcting ECC Accelerator (BCH) 15.1 15.2 15.2.1 15.2.2 15.2.3 15.2.3.1 15.2.3.2 15.2.4 15.3 15.4 15.4.1 15.4.1.1 15.4.1.2 15.4.2 15.4.2.1 15.4.2.2 15.4.3 15.5 15.6 Overview........................................................................................................................ 15-1 Operation ....................................................................................................................... 15-3 BCH Limitations and Assumptions ........................................................................... 15-4 Flash Page Layout...................................................................................................... 15-4 Determining the ECC layout for a device.................................................................. 15-6 4K+218 flash, 10 bytes metadata, 512 byte data blocks, separate metadata ......... 15-6 4K+128 flash, 10 bytes metadata, 512 byte data blocks, separate metadata ......... 15-6 Data buffers in system memory ................................................................................. 15-7 Memory to Memory (Loopback) Operation .................................................................. 15-9 Programming the BCH/GPMI Interfaces .................................................................... 15-10 BCH Encoding for NAND Writes ........................................................................... 15-10 DMA Structure Code Example............................................................................ 15-13 Using the BCH Encoder ...................................................................................... 15-16 BCH Decoding for NAND Reads............................................................................ 15-17 DMA Structure Code Example............................................................................ 15-20 Using the Decoder ............................................................................................... 15-23 Interrupts.................................................................................................................. 15-25 Behavior During Reset................................................................................................. 15-26 Programmable Registers .............................................................................................. 15-26 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice vii Contents Paragraph Number Title Chapter 16 Data Co-Processor (DCP) 16.1 16.1.1 16.2 16.2.1 16.2.2 16.2.2.1 16.2.2.2 16.2.2.3 16.2.3 16.2.4 16.2.4.1 16.2.4.2 16.2.5 16.2.5.1 16.2.5.2 16.2.5.3 16.2.5.4 16.2.5.4.1 16.2.5.4.2 16.2.5.4.3 16.2.5.4.4 16.2.5.4.5 16.2.5.4.6 16.2.5.4.7 16.2.5.4.8 16.2.5.4.9 16.2.6 16.2.6.1 16.2.6.2 16.2.6.3 16.2.6.4 16.3 Overview........................................................................................................................ 16-1 DCP Limitations for Software ................................................................................... 16-3 Operation ....................................................................................................................... 16-4 Memory Copy, Blit, and Fill Functionality................................................................ 16-4 Advanced Encryption Standard (AES) ...................................................................... 16-5 Key Storage............................................................................................................ 16-5 OTP Key ................................................................................................................ 16-5 Encryption Modes.................................................................................................. 16-5 Hashing ...................................................................................................................... 16-7 Managing DCP Channel Arbitration and Performance ............................................. 16-7 DCP Arbitration..................................................................................................... 16-8 Channel Recovery Timers ..................................................................................... 16-8 Programming Channel Operations............................................................................. 16-9 Virtual Channels .................................................................................................... 16-9 Context Switching ............................................................................................... 16-10 Working with Semaphores................................................................................... 16-11 Work Packet Structure ......................................................................................... 16-11 Next Command Address Field ........................................................................ 16-12 Control0 Field.................................................................................................. 16-12 Control1 Field.................................................................................................. 16-14 Source Buffer................................................................................................... 16-15 Destination Buffer ........................................................................................... 16-15 Buffer Size Field.............................................................................................. 16-15 Payload Pointer................................................................................................ 16-16 Status................................................................................................................ 16-16 Payload ............................................................................................................ 16-17 Programming Other DCP Functions........................................................................ 16-17 Basic Memory Copy Programming Example...................................................... 16-17 Basic Hash Operation Programming Example .................................................... 16-18 Basic Cipher Operation Programming Example ................................................. 16-20 Multi-Buffer Scatter/Gather Cipher and Hash Operation Programming Example ................................................................... 16-21 Programmable Registers .............................................................................................. 16-24 Chapter 17 Pixel Pipeline (PXP) 17.1 Overview........................................................................................................................ 17-1 i.MX23 Applications Processor Reference Manual, Rev. 1 viii Preliminary--Subject to Change Without Notice Freescale Semiconductor Page Number Contents Paragraph Number 17.1.1 17.1.2 17.2 17.2.1 17.2.2 17.2.3 17.2.3.1 17.2.3.1.1 17.2.3.1.2 17.2.3.1.3 17.2.3.1.4 17.2.4 17.2.5 17.2.6 17.2.7 17.2.8 17.2.9 17.2.10 17.2.11 17.2.12 17.3 17.3.1 17.3.2 17.3.3 17.3.4 17.3.5 17.3.6 17.4 Title Page Number Image Support............................................................................................................ 17-2 PXP Limitations/Issues.............................................................................................. 17-3 Operation ....................................................................................................................... 17-3 Pixel Handling ........................................................................................................... 17-4 S0 Cropping/Masking ................................................................................................ 17-5 Scaling ....................................................................................................................... 17-7 Scaling Operation .................................................................................................. 17-8 Bilinear Image Scaling Filter............................................................................. 17-9 YUV 4:2:2 Image Scaling ............................................................................... 17-10 YUV 4:2:0 Image Scaling ............................................................................... 17-11 Out-of-Range Image Access............................................................................ 17-12 Colorspace Conversion............................................................................................ 17-13 Overlays ................................................................................................................... 17-14 Alpha Blending........................................................................................................ 17-16 Color Key................................................................................................................. 17-16 Raster Operations (ROPs)........................................................................................ 17-17 Rotation.................................................................................................................... 17-18 In-place Rendering................................................................................................... 17-20 Interlaced Video Support ......................................................................................... 17-21 Queueing Frame Operations .................................................................................... 17-21 Examples...................................................................................................................... 17-22 Basic QVGA Example............................................................................................. 17-22 Basic QVGA with Overlays .................................................................................... 17-24 Cropped QVGA Example........................................................................................ 17-25 Upscale QVGA to VGA with Overlays................................................................... 17-27 Downscale VGA to WQVGA (480x272) to fill screen ........................................... 17-29 Downscale VGA to QVGA with Overlapping Overlays......................................... 17-31 Programmable Registers .............................................................................................. 17-33 Chapter 18 LCD Interface (LCDIF) 18.1 18.2 18.2.1 18.2.1.1 18.2.1.2 18.2.2 18.2.3 18.2.4 18.2.5 Overview........................................................................................................................ 18-1 Operation ....................................................................................................................... 18-1 Bus Interface Mechanisms......................................................................................... 18-3 PIO Operation........................................................................................................ 18-3 Bus Master Operation ............................................................................................ 18-3 Write Datapath ........................................................................................................... 18-4 LCDIF Interrupts ..................................................................................................... 18-10 Initializing the LCDIF ............................................................................................. 18-11 System Interface ...................................................................................................... 18-12 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice ix Contents Paragraph Number 18.2.5.1 18.2.6 18.2.6.1 18.2.7 18.2.7.1 18.2.8 18.2.9 18.3 18.4 Title Page Number Code Example to initialize LCDIF in System mode ........................................... 18-13 VSYNC Interface..................................................................................................... 18-13 Code Example to initialize LCDIF in VSYNC mode ......................................... 18-14 DOTCLK Interface .................................................................................................. 18-14 Code Example...................................................................................................... 18-16 ITU-R BT.656 Digital Video Interface (DVI) ......................................................... 18-16 LCDIF Pin Usage by Interface Mode ...................................................................... 18-17 Behavior During Reset................................................................................................. 18-19 Programmable Registers .............................................................................................. 18-20 Chapter 19 TV-Out NTSC/PAL Encoder 19.1 19.2 19.3 19.4 Implementation .............................................................................................................. 19-1 Unsupported DVE features ............................................................................................ 19-2 Programming Example .................................................................................................. 19-2 Programmable Registers ................................................................................................ 19-4 Chapter 20 Video DAC 20.1 20.2 Overview........................................................................................................................ 20-1 Details of Operations ..................................................................................................... 20-1 Chapter 21 Synchronous Serial Ports (SSP) 21.1 21.2 21.3 21.4 21.5 21.5.1 21.5.2 21.5.2.1 21.5.2.2 21.5.3 21.5.4 21.5.5 21.5.6 21.6 Overview........................................................................................................................ 21-1 External Pins .................................................................................................................. 21-2 Bit Rate Generation ....................................................................................................... 21-3 Frame Format for SPI and SSI....................................................................................... 21-3 Motorola SPI Mode ....................................................................................................... 21-4 SPI DMA Mode ......................................................................................................... 21-4 Motorola SPI Frame Format ...................................................................................... 21-4 Clock Polarity ........................................................................................................ 21-4 Clock Phase ........................................................................................................... 21-4 Motorola SPI Format with Polarity=0, Phase=0........................................................ 21-4 Motorola SPI Format with Polarity=0, Phase=1........................................................ 21-6 Motorola SPI Format with Polarity=1, Phase=0........................................................ 21-7 Motorola SPI Format with Polarity=1, Phase=1........................................................ 21-8 Winbond SPI Mode........................................................................................................ 21-9 i.MX23 Applications Processor Reference Manual, Rev. 1 x Preliminary--Subject to Change Without Notice Freescale Semiconductor Contents Paragraph Number 21.7 21.8 21.8.1 21.8.2 21.8.2.1 21.8.2.2 21.8.3 21.8.4 21.8.5 21.9 21.10 Title Page Number Texas Instruments Synchronous Serial Interface (SSI) Mode ....................................... 21-9 SD/SDIO/MMC Mode................................................................................................. 21-10 SD/MMC Command/Response Transfer ................................................................. 21-11 SD/MMC Data Block Transfer................................................................................ 21-12 SD/MMC Multiple Block Transfers .................................................................... 21-13 SD/MMC Block Transfer CRC Protection.......................................................... 21-14 SDIO Interrupts........................................................................................................ 21-14 SD/MMC Mode Error Handling.............................................................................. 21-14 SD/MMC Clock Control.......................................................................................... 21-17 Behavior During Reset................................................................................................. 21-18 Programmable Registers .............................................................................................. 21-18 Chapter 22 Timers and Rotary Decoder 22.1 22.2 22.2.1 22.2.2 22.2.3 22.3 22.3.1 22.3.2 22.4 Overview........................................................................................................................ 22-1 Timers ............................................................................................................................ 22-2 Using External Signals as Inputs ............................................................................... 22-4 Timer 3 and Duty Cycle Mode .................................................................................. 22-4 Testing Timer 3 Duty Cycle Modes........................................................................... 22-6 Rotary Decoder .............................................................................................................. 22-6 Testing the Rotary Decoder ....................................................................................... 22-9 Behavior During Reset............................................................................................... 22-9 Programmable Registers ................................................................................................ 22-9 Chapter 23 Real-Time Clock, Alarm, Watchdog, Persistent Bits 23.1 23.2 23.3 23.4 23.4.1 23.5 23.6 23.7 23.8 Overview........................................................................................................................ 23-1 Programming and Enabling the RTC Clock .................................................................. 23-4 RTC Persistent Register Copy Control .......................................................................... 23-4 Real-Time Clock Function............................................................................................. 23-6 Behavior During Reset............................................................................................... 23-7 Millisecond Resolution Timing Function ...................................................................... 23-7 Alarm Clock Function ................................................................................................... 23-7 Watchdog Reset Function .............................................................................................. 23-8 Programmable Registers ................................................................................................ 23-8 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice xi Contents Paragraph Number Title Chapter 24 Pulse-Width Modulator (PWM) Controller 24.1 24.2 24.2.1 24.2.2 24.2.3 24.3 24.4 Overview........................................................................................................................ 24-1 Operation ....................................................................................................................... 24-1 Multi-Chip Attachment Mode ................................................................................... 24-4 Channel 2 Analog Enable Function ........................................................................... 24-5 Channel Output Cutoff Using Module Clock Gate ................................................... 24-5 Behavior During Reset................................................................................................... 24-6 Programmable Registers ................................................................................................ 24-6 Chapter 25 I Interface 2C Page Number 25.1 25.2 25.2.1 25.2.2 25.2.2.1 25.2.2.2 25.2.2.3 25.2.2.4 25.2.2.5 25.2.3 25.2.3.1 25.2.3.2 25.3 25.3.1 25.3.1.1 25.4 Overview........................................................................................................................ 25-1 Operation ....................................................................................................................... 25-2 I2C Interrupt Sources ................................................................................................. 25-2 I2C Bus Protocol ........................................................................................................ 25-3 Simple Device Transactions .................................................................................. 25-5 Typical EEPROM Transactions............................................................................. 25-6 Master Mode Protocol ........................................................................................... 25-7 Clock Generation ................................................................................................... 25-7 Master Mode Operation......................................................................................... 25-7 Programming Examples........................................................................................... 25-12 Five Byte Master Write Using DMA................................................................... 25-12 Reading 256 Bytes from an EEPROM ................................................................ 25-14 Behavior During Reset................................................................................................. 25-16 Pinmux Selection During Reset............................................................................... 25-16 Correct and Incorrect Reset Examples ................................................................ 25-16 Programmable Registers .............................................................................................. 25-16 Chapter 26 Application UART 26.1 26.2 26.2.1 26.2.2 26.2.3 26.2.4 26.2.5 Overview........................................................................................................................ 26-1 Operation ....................................................................................................................... 26-2 Fractional Baud Rate Divider .................................................................................... 26-3 UART Character Frame ............................................................................................. 26-3 DMA Operation ......................................................................................................... 26-3 Data Transmission or Reception................................................................................ 26-4 Error Bits.................................................................................................................... 26-4 i.MX23 Applications Processor Reference Manual, Rev. 1 xii Preliminary--Subject to Change Without Notice Freescale Semiconductor Contents Paragraph Number 26.2.6 26.2.7 26.3 26.4 Title Page Number Overrun Bit ................................................................................................................ 26-4 Disabling the FIFOs................................................................................................... 26-5 Behavior During Reset................................................................................................... 26-5 Programmable Registers ................................................................................................ 26-5 Chapter 27 Debug UART 27.1 27.2 27.2.1 27.2.2 27.2.3 27.2.4 27.2.5 27.2.6 27.3 Overview........................................................................................................................ 27-1 Operation ....................................................................................................................... 27-2 Fractional Baud Rate Divider .................................................................................... 27-2 UART Character Frame ............................................................................................. 27-3 Data Transmission or Reception................................................................................ 27-3 Error Bits.................................................................................................................... 27-4 Overrun Bit ................................................................................................................ 27-4 Disabling the FIFOs................................................................................................... 27-4 Programmable Registers ................................................................................................ 27-4 Chapter 28 AUDIOIN/ADC 28.1 28.2 28.2.1 28.2.2 28.2.3 28.2.4 28.3 28.4 Overview........................................................................................................................ 28-1 Operation ....................................................................................................................... 28-2 AUDIOIN DMA ........................................................................................................ 28-4 ADC Sample Rate Converter and Internal Operation ............................................... 28-5 Line-In ....................................................................................................................... 28-8 Microphone................................................................................................................ 28-8 Behavior During Reset................................................................................................... 28-9 Programmable Registers ................................................................................................ 28-9 Chapter 29 AUDIOOUT/DAC 29.1 29.2 29.2.1 29.2.2 29.2.3 29.2.4 29.2.4.1 29.2.4.2 Overview........................................................................................................................ 29-1 Operation ....................................................................................................................... 29-2 AUDIOOUT DMA .................................................................................................... 29-4 DAC Sample Rate Converter and Internal Operation ............................................... 29-5 Reference Control Settings ........................................................................................ 29-8 Headphone ................................................................................................................. 29-8 Board Components .............................................................................................. 29-10 Capless Mode Operation...................................................................................... 29-11 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice xiii Contents Paragraph Number 29.2.5 29.2.5.1 29.2.5.2 29.3 29.4 Title Page Number Speaker Amplifier.................................................................................................... 29-11 Overview.............................................................................................................. 29-11 Details of Operations ........................................................................................... 29-12 Behavior During Reset................................................................................................. 29-13 Programmable Registers .............................................................................................. 29-13 Chapter 30 SPDIF Transmitter 30.1 30.2 30.2.1 30.2.2 30.2.3 30.2.4 30.3 Overview........................................................................................................................ 30-1 Operation ....................................................................................................................... 30-1 Interrupts.................................................................................................................... 30-4 Clocking..................................................................................................................... 30-4 DMA Operation ......................................................................................................... 30-5 PIO Debug Mode ....................................................................................................... 30-6 Programmable Registers ................................................................................................ 30-7 Chapter 31 Serial Audio Interface (SAIF) (BGA169 Only) 31.1 31.2 31.2.1 31.2.2 31.2.3 31.2.4 31.2.5 31.2.6 31.2.7 31.3 Overview........................................................................................................................ 31-1 Operation ....................................................................................................................... 31-2 Sample Rate Programming and Codec Clocking Operation ..................................... 31-3 Transmit Operation .................................................................................................... 31-6 Receive Operation...................................................................................................... 31-7 DMA Interface........................................................................................................... 31-8 PCM Data FIFO......................................................................................................... 31-8 Serial Frame Formats................................................................................................. 31-9 Pin Timing ............................................................................................................... 31-10 Programmable Registers .............................................................................................. 31-10 Chapter 32 Power Supply 32.1 32.2 32.2.1 32.2.1.1 32.2.1.2 32.3 32.3.1 Overview........................................................................................................................ 32-1 DC-DC Converters ........................................................................................................ 32-2 DC-DC Operation ...................................................................................................... 32-2 Brownout/Error Detection .................................................................................... 32-3 DC-DC Extended Battery Life Features................................................................ 32-3 Linear Regulators........................................................................................................... 32-6 USB Compliance Features......................................................................................... 32-6 i.MX23 Applications Processor Reference Manual, Rev. 1 xiv Preliminary--Subject to Change Without Notice Freescale Semiconductor Contents Paragraph Number 32.3.2 32.3.2.1 32.3.2.2 32.3.2.3 32.3.3 32.3.4 32.3.4.1 32.3.5 32.4 32.4.1 32.4.2 32.4.3 32.5 32.6 32.7 32.8 32.9 32.9.1 32.9.2 32.9.3 32.9.4 32.9.5 32.9.6 32.9.7 32.9.8 32.10 32.11 Title Page Number 5V to Battery Power Interaction ................................................................................ 32-7 Battery Power to 5-V Power.................................................................................. 32-7 5-V Power to Battery Power.................................................................................. 32-7 5-V Power and Battery Power ............................................................................... 32-8 Power-Up Sequence................................................................................................... 32-8 Power-Down Sequence.............................................................................................. 32-9 Powered-Down State ............................................................................................. 32-9 Reset Sequence .......................................................................................................... 32-9 PSWITCH Pin Functions............................................................................................... 32-9 Power On ................................................................................................................. 32-10 Power Down ............................................................................................................ 32-10 Software Functions/Recovery Mode ....................................................................... 32-10 Battery Monitor............................................................................................................ 32-12 Battery Charger ............................................................................................................ 32-12 Silicon Speed Sensor ................................................................................................... 32-13 Interrupts ...................................................................................................................... 32-14 Proper Power Supply Protection.................................................................................. 32-14 Power Supply Protection Goal................................................................................. 32-14 Power Supply Input Voltage Protection................................................................... 32-15 PWDN_BATTBRNOUT and PWDN_5VBRNOUT Details .................................. 32-15 VDD5V Input Protection ......................................................................................... 32-15 DCDC Input Protection ........................................................................................... 32-16 DCDC Output Protection......................................................................................... 32-17 PWD_OFF Bit Usage .............................................................................................. 32-17 Power Supply Protection Summary......................................................................... 32-17 DC-DC Converter Efficiency ...................................................................................... 32-18 Programmable Registers .............................................................................................. 32-18 Chapter 33 Low-Resolution ADC and Touch-Screen Interface 33.1 33.2 33.2.1 33.2.2 33.2.3 33.2.4 33.3 33.4 Overview........................................................................................................................ 33-1 Operation ....................................................................................................................... 33-2 External Temperature Sensing with a Diode ............................................................. 33-3 Internal Die Temperature Sensing ............................................................................. 33-4 Scheduling Conversions ............................................................................................ 33-4 Delay Channels .......................................................................................................... 33-5 Behavior During Reset................................................................................................... 33-6 Programmable Registers ................................................................................................ 33-8 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice xv Contents Paragraph Number Title Chapter 34 Serial JTAG (SJTAG) 34.1 34.2 34.2.1 34.2.2 34.2.3 34.2.4 34.2.5 34.2.6 34.2.7 34.2.8 Overview........................................................................................................................ 34-1 Operation ....................................................................................................................... 34-2 Debugger Async Start Phase...................................................................................... 34-3 i.MX23 Timing Mark Phase ...................................................................................... 34-3 Debugger Send TDI, Mode Phase ............................................................................. 34-4 i.MX23 Wait For Return Clock Phase ....................................................................... 34-4 i.MX23 Sends TDO and Return Clock Timing Phase............................................... 34-4 i.MX23 Terminate Phase ........................................................................................... 34-5 SJTAG External Pin................................................................................................... 34-5 Selecting Serial JTAG or Six-Wire JTAG Mode ....................................................... 34-6 Chapter 35 Boot Modes 35.1 35.1.1 35.1.2 35.2 35.2.1 35.2.2 35.3 35.4 35.4.1 35.4.2 35.5 35.6 35.6.1 35.6.2 35.7 35.7.1 35.7.2 35.7.3 35.8 35.8.1 35.8.2 35.8.3 35.8.3.1 35.8.3.2 Boot Modes.................................................................................................................... 35-1 Boot Pins Definition and Mode Selection ................................................................. 35-1 Boot Mode Selection Map ......................................................................................... 35-2 OTP eFuse and Persistent Bit Definitions ..................................................................... 35-3 OTP eFuse.................................................................................................................. 35-3 Persistent Bits ............................................................................................................ 35-5 Memory Map ................................................................................................................. 35-6 General Boot Procedure................................................................................................. 35-6 Preparing Bootable Images........................................................................................ 35-7 Constructing Image to Be Loaded by Boot Loader ................................................... 35-7 I2C Boot Mode............................................................................................................... 35-8 SPI Boot Mode............................................................................................................... 35-8 Media Format............................................................................................................. 35-9 SSP............................................................................................................................. 35-9 SD/MMC Boot Mode .................................................................................................. 35-10 Boot Control Block (BCB) ...................................................................................... 35-11 Master Boot Record (MBR) .................................................................................... 35-12 Device Identification................................................................................................ 35-12 NAND Boot Mode....................................................................................................... 35-12 NAND Control Block (NCB) .................................................................................. 35-12 NAND Patch Boot using NCB ................................................................................ 35-16 Expected NAND Layout.......................................................................................... 35-16 NAND Config Block ........................................................................................... 35-18 Single Error Correct and Double Error Detect (SEC-DED) Hamming............... 35-18 i.MX23 Applications Processor Reference Manual, Rev. 1 xvi Preliminary--Subject to Change Without Notice Freescale Semiconductor Page Number Contents Paragraph Number 35.8.3.3 35.8.3.4 35.8.3.5 35.8.3.6 35.8.3.7 35.8.3.8 35.8.3.9 35.8.3.10 35.8.4 35.8.4.1 35.8.4.2 35.8.4.3 35.8.4.4 35.8.4.5 35.8.4.6 35.9 35.9.1 35.9.2 35.9.3 35.9.4 Title Page Number Logical Drive Layout Block ................................................................................ 35-19 Firmware Layout on the NAND .......................................................................... 35-20 Recovery From a Failed Boot Firmware Image Read ......................................... 35-20 Bad Block Handling in the ROM ........................................................................ 35-21 NAND Control Block Structure and Definitions................................................. 35-24 Logical Drive Layout Block Structure and Definitions....................................... 35-27 Discovered Bad Block Table Header Layout Block Structure and Definitions................................................................................. 35-28 Discovered Bad Block Table Layout Block Structure and Definitions ............... 35-29 Typical NAND Page Organization .......................................................................... 35-29 BCH ECC Page Organization.............................................................................. 35-29 2K Page Organization on the NAND for RS-4 Bit ECC..................................... 35-30 In-Memory Organization for RS-4 Bit ECC........................................................ 35-31 Metadata .............................................................................................................. 35-31 4K Page Organization on the NAND for RS-8 Bit ECC..................................... 35-32 In-Memory Organization for RS-8 Bit ECC........................................................ 35-32 USB Boot Driver ......................................................................................................... 35-33 Boot Loader Transfer Controller (BLTC) ................................................................ 35-33 Plug-in Transfer Controller (PITC) ......................................................................... 35-34 USB IDs and Serial Number.................................................................................... 35-34 USB Recovery Mode ............................................................................................... 35-34 Chapter 36 Pin Descriptions 36.1 36.2 Pin Definitions for 128-Pin LQFP ................................................................................. 36-2 Pin Definitions for 169-Pin BGA .................................................................................. 36-9 Chapter 37 Pin Control and GPIO 37.1 37.2 37.2.1 37.2.2 37.2.2.1 37.2.2.1.1 37.2.2.2 37.2.3 37.2.3.1 37.2.3.2 Overview........................................................................................................................ 37-1 Operation ....................................................................................................................... 37-1 Reset Configuration ................................................................................................... 37-2 Pin Interface Multiplexing ......................................................................................... 37-3 Pin Drive Strength Selection ................................................................................. 37-8 Pin Voltage Selection......................................................................................... 37-8 Pullup/Pulldown Selection..................................................................................... 37-8 GPIO Interface......................................................................................................... 37-10 Output Operation ................................................................................................. 37-10 Input Operation.................................................................................................... 37-11 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice xvii Contents Paragraph Number 37.2.3.3 37.3 37.4 Title Page Number Input Interrupt Operation..................................................................................... 37-12 Behavior During Reset................................................................................................. 37-15 Programmable Registers .............................................................................................. 37-15 Chapter 38 Digital Video Encoder Programmers' Manual 38.1 38.2 38.2.1 38.2.2 38.2.3 38.2.4 38.2.5 38.2.6 38.2.7 38.2.8 38.2.9 38.2.10 38.2.11 38.2.12 38.2.13 38.2.14 38.2.15 38.3 38.4 38.4.1 38.4.2 38.4.3 38.4.4 38.4.5 38.4.6 38.4.7 38.4.8 38.4.9 Functional Overview...................................................................................................... 38-1 Block Diagram and Implementation Overview ............................................................. 38-1 DU -- Data Input Unit................................................................................................ 38-3 ES -- External Sync Unit ........................................................................................... 38-3 SG -- Sync Generation Unit....................................................................................... 38-3 FU -- Frequency Generation Unit.............................................................................. 38-3 LU -- Low-pass and Other Signal Conditioning Filter Unit...................................... 38-3 MX -- RGB Matrix Unit ............................................................................................ 38-3 YU -- Y(luma)-main Unit .......................................................................................... 38-4 CU -- Chroma-main Unit........................................................................................... 38-4 Int -- Interpolation Block ........................................................................................... 38-4 OU -- (Composite) Output Unit................................................................................. 38-4 D/A -- D/A Selection Muxes ..................................................................................... 38-4 MV -- Macrovision Unit ............................................................................................ 38-4 WU -- WSS and CGMS Unit..................................................................................... 38-4 CC -- Closed Caption Unit......................................................................................... 38-5 HI -- Host Interface Unit............................................................................................ 38-5 Registers......................................................................................................................... 38-5 Function and Programming of Controls ...................................................................... 38-10 Register 0 ................................................................................................................. 38-10 Register 1 ................................................................................................................. 38-12 Register 2 ................................................................................................................. 38-12 Registers 3 and 4...................................................................................................... 38-12 Register 5 ................................................................................................................. 38-13 Register 6 ................................................................................................................. 38-13 Register group 8....................................................................................................... 38-13 Macrovision Registers ............................................................................................. 38-14 Register group 10..................................................................................................... 38-14 Chapter 39 Register Macro Usage 39.1 39.2 39.2.1 Background .................................................................................................................... 39-1 Naming Convention....................................................................................................... 39-2 Multi-Instance Blocks................................................................................................ 39-4 i.MX23 Applications Processor Reference Manual, Rev. 1 xviii Preliminary--Subject to Change Without Notice Freescale Semiconductor Contents Paragraph Number 39.2.1.1 39.3 39.3.1 39.3.2 39.3.3 39.3.4 39.3.5 39.3.6 39.3.7 39.3.8 39.3.9 39.3.10 39.3.10.1 39.3.10.1.1 39.4 39.5 39.6 Title Page Number Examples................................................................................................................ 39-4 Examples........................................................................................................................ 39-4 Setting 1-Bit Wide Field ............................................................................................ 39-4 Clearing 1-Bit Wide Field.......................................................................................... 39-5 Toggling 1-Bit Wide Field ......................................................................................... 39-5 Modifying n-Bit Wide Field ...................................................................................... 39-5 Modifying Multiple Fields......................................................................................... 39-5 Writing Entire Register (All Fields Updated at Once)............................................... 39-6 Reading a Bit Field .................................................................................................... 39-6 Reading Entire Register ............................................................................................. 39-6 Accessing Multiple Instance Register........................................................................ 39-6 Correct Way to Soft Reset a Block ............................................................................ 39-7 Pinmux Selection During Reset............................................................................. 39-7 Correct and Incorrect Reset Examples .............................................................. 39-8 Summary Preferred ........................................................................................................ 39-8 Summary Alternate Syntax............................................................................................ 39-8 Assembly Example ........................................................................................................ 39-9 Chapter 40 Memory Map Chapter 41 i.MX23 Part Numbers and Ordering Information Chapter 42 Package Drawings 42.1 42.2 169-Pin Ball Grid Array (BGA) .................................................................................... 42-2 128-Pin Low-Profile Quad Flat Package (LQFP).......................................................... 42-3 Appendix A Revision History A.1 Changes From Revision 0 to Revision 1 ........................................................................ A-1 Appendix B Register Names Appendix C Acronyms and Abbreviations i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice xix Contents Paragraph Number Title Page Number i.MX23 Applications Processor Reference Manual, Rev. 1 xx Preliminary--Subject to Change Without Notice Freescale Semiconductor Figures Figure Number 1-1 1-2 1-3 1-4 1-5 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 6-1 6-2 7-1 7-2 8-1 8-2 8-3 8-4 8-5 9-1 9-2 9-3 10-1 10-2 10-3 11-1 11-2 11-3 12-1 Title Figures Page Number System Block Diagram ........................................................................................................... 1-6 i.MX23 SoC Block Diagram................................................................................................... 1-8 Physical Memory Map .......................................................................................................... 1-11 Mixed Signal Audio Elements .............................................................................................. 1-18 Display Processing Sub-System............................................................................................ 1-20 DCDC Efficiency vs. Battery Voltage (VDDD=1.05V, Low VDDD Load)........................... 2-6 DCDC Efficiency vs. Battery Voltage (VDDD=1.28V, Medium VDDD Load) .................... 2-6 DCDC Efficiency vs. Battery Voltage (VDDD=1.55V, High VDDD Load) .......................... 2-7 i.MX23 EMI mDDR DRAM Input AC Timing.................................................................... 2-12 i.MX23 EMI mDDR DRAM Output AC Timing ................................................................. 2-13 I2C Bus Timing Diagram ...................................................................................................... 2-14 LCD AC Output Timing Digram .......................................................................................... 2-15 ARM926 RISC Processor Core .............................................................................................. 3-2 ARM Programmable Registers ............................................................................................... 3-3 Logical Diagram of Clock Domains ....................................................................................... 4-4 Fractional Clock divide; 3/8 example ..................................................................................... 4-8 Divide Range 1 < div < 2........................................................................................................ 4-9 Reset Logic Functional Diagram .......................................................................................... 4-11 Interrupt Collector System Diagram ....................................................................................... 5-2 Interrupt Collector IRQ/FIQ Logic for Source 33 .................................................................. 5-3 IRQ Control Flow ................................................................................................................... 5-4 Nesting of Multi-Level IRQ Interrupts ................................................................................... 5-5 Digital Control (DIGCTL) Block Diagram ............................................................................ 6-2 On-Chip RAM Partitioning..................................................................................................... 6-2 On-Chip OTP (OCOTP) Controller Block Diagram .............................................................. 7-2 OCOTP Allocation.................................................................................................................. 7-3 USB 2.0 Device Controller Block Diagram............................................................................ 8-2 USB 2.0 Check_USB_Plugged_In Flowchart ........................................................................ 8-4 USB 2.0 USB PHY Startup Flowchart ................................................................................... 8-5 USB 2.0 PHY PLL Suspend Flowchart .................................................................................. 8-6 UTMI Powerdown .................................................................................................................. 8-6 USB 2.0 PHY Block Diagram ................................................................................................ 9-1 USB 2.0 PHY Analog Transceiver Block Diagram................................................................ 9-3 USB 2.0 PHY Transmitter Block Diagram............................................................................. 9-6 AHB-to-APBH Bridge DMA Block Diagram ...................................................................... 10-2 AHB-to-APBH Bridge DMA Channel Command Structure ................................................ 10-3 AHB-to-APBH Bridge DMA NAND Read Status Polling with DMA Sense Command .... 10-8 AHB-to-APBX Bridge DMA Block Diagram ...................................................................... 11-2 AHB-to-APBX Bridge DMA Channel Command Structure ................................................ 11-4 AHB-to-APBX Bridge DMA AUDIOOUT (DAC) Example Command Chain .................. 11-7 External Memory Interface (EMI) Top-Level Block Diagram ............................................. 12-2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice -i Figures Figure Number 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 13-1 13-2 13-3 13-4 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 16-1 16-2 16-3 16-4 Title Page Number DRAM Controller AHB Address Breakdown ...................................................................... 12-2 DRAM Controller Architecture ............................................................................................ 12-3 Memory Controller Memory Map: Maximum...................................................................... 12-4 Example Memory Map: 10 Row Bits, 11 Column Bits ........................................................ 12-5 DQS Read Timing................................................................................................................. 12-7 DQS Gating........................................................................................................................... 12-8 DRAM DQS Arrival Time Requirements............................................................................. 12-9 DQS Write Timing .............................................................................................................. 12-10 Write Data and DQS Relationship ...................................................................................... 12-10 Write Data with Programmable Delays .............................................................................. 12-11 WR_DQS_SHIFT Delay Setting Example ......................................................................... 12-11 DRAM Clock Programmable Delay ................................................................................... 12-12 General-Purpose Media Interface Controller Block Diagram .............................................. 13-2 BASIC NAND Flash Timing ................................................................................................ 13-4 NAND Flash Read Path Timing ........................................................................................... 13-5 NAND Flash Command and Address Timing Example ....................................................... 13-6 Hardware 8-Symbol Correcting ECC Accelerator (ECC8) Block Diagram......................... 14-3 ECC-Protected 2K NAND Page Data--NAND Memory Footprint .................................... 14-5 ECC-Protected 2K NAND Page Data--System Memory Footprint .................................... 14-6 ECC-Protected 4K NAND Page Data--NAND Memory Footprint .................................... 14-7 ECC-Protected 4K NAND Page Data--System Memory Footprint .................................... 14-8 ECC8 Reed-Solomon Encode Flowchart............................................................................ 14-12 ECC8 DMA Descriptor Legend.......................................................................................... 14-13 ECC8 Reed-Solomon Encode DMA Descriptor Chain ...................................................... 14-14 ECC8 Reed-Solomon Decode Flowchart ........................................................................... 14-20 ECC8 Reed-Solomon Block Coding--Decoder for t=8 ..................................................... 14-21 ECC8 Reed-Solomon Decode DMA Descriptor Chain...................................................... 14-22 Hardware BCH Accelerator .................................................................................................. 15-3 Block Pipeline while Reading Flash ..................................................................................... 15-4 FLASH Page Layout Options ............................................................................................... 15-5 BCH Data Buffers in Memory .............................................................................................. 15-8 Memory-to-Memory Operations........................................................................................... 15-9 BCH Encode Flowchart ...................................................................................................... 15-11 BCH DMA Descriptor Legend ........................................................................................... 15-11 BCH Encode DMA Descriptor Chain................................................................................. 15-12 BCH Decode Flowchart ...................................................................................................... 15-18 BCH Decode DMA Descriptor Chain ................................................................................ 15-20 Data Co-Processor (DCP) Block Diagram............................................................................ 16-1 Cipher Block Chaining (CBC) Mode Encryption................................................................. 16-6 Cipher Block Chaining (CBC) Mode Decryption................................................................. 16-7 DCP Arbitration .................................................................................................................... 16-8 i.MX23 Applications Processor Reference Manual, Rev. 1 -ii Preliminary--Subject to Change Without Notice Freescale Semiconductor Figures Figure Number 16-5 16-6 16-7 16-8 16-9 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14 17-15 17-16 17-17 17-18 17-19 17-20 17-21 17-22 17-23 17-24 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 19-1 21-1 21-2 Title Page Number DCP Work Packet Structure................................................................................................ 16-12 Basic Memory Copy Operation .......................................................................................... 16-18 Basic Hash Operation.......................................................................................................... 16-19 Basic Cipher Operation ....................................................................................................... 16-20 Multi-Buffer Scatter/Gather Cipher and Hash Operation ................................................... 16-22 Pixel Pipeline (PXP) Block Diagram.................................................................................... 17-1 Pixel Pipeline (PXP) Data Flow............................................................................................ 17-2 Pixel Pipeline (PXP) Macro Blocks...................................................................................... 17-4 Pixel Pipeline (PXP) Cropping ............................................................................................. 17-5 Pixel Pipeline (PXP) Scaling and Cropping Example .......................................................... 17-6 Invalid PXP Cropping Examples .......................................................................................... 17-7 Computing Pixel Value in Output Frame Buffer................................................................... 17-9 YUV Samples for 4:2:2 Formats ........................................................................................ 17-10 YUV Samples for 4:2:0 Formats ........................................................................................ 17-11 Examples for Scaled Chroma Output Pixel ........................................................................ 17-12 Scan Line Sample Positions................................................................................................ 17-12 Pixel Pipeline Overlay Support........................................................................................... 17-15 Pixel Pipeline (PXP) Colorkey Example ............................................................................ 17-17 Pixel Pipeline (PXP) Rotation Example 1 .......................................................................... 17-18 Pixel Pipeline (PXP) Rotation Example 2 .......................................................................... 17-19 Pixel Pipeline (PXP) Rotation and Flip Definition............................................................. 17-19 Pixel Pipeline (PXP) Rotation Plus Flip Definition............................................................ 17-20 Example: RGB Equivalent of YUV image ......................................................................... 17-23 Example: QVGA with Overlays ......................................................................................... 17-24 Example: QVGA with Overlays ......................................................................................... 17-25 Example: Cropped QVGA .................................................................................................. 17-27 Example: Upscale QVGA to VGA with Overlays.............................................................. 17-29 Example: Downscale VGA to WQVGA (480x272) to fill screen...................................... 17-31 Example: Downscale VGA to QVGA with Overlapping Overlays.................................... 17-33 LCDIF Top Level Diagram ................................................................................................... 18-2 LCDIF Write DataPath.......................................................................................................... 18-6 8-Bit LCDIF Register Programming--Example A .............................................................. 18-7 8-Bit LCDIF Register Programming--Example B............................................................... 18-8 16-Bit LCDIF Register Programming--Example A ............................................................ 18-9 16-Bit LCDIF Register Programming--Example B........................................................... 18-10 LCD Interface Signals in System Write Mode.................................................................... 18-12 LCD Interface Signals in DOTCLK Mode ......................................................................... 18-15 LCDIF Interface Signals in ITU-R BT.656 Digital Video Interface Mode ........................ 18-17 TV Encoder Block Diagram ................................................................................................. 19-1 Synchronous Serial Port Block Diagram .............................................................................. 21-2 Motorola SPI Frame Format (Single Transfer) with POLARITY=0 and PHASE=0 ........... 21-5 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice -iii Figures Figure Number 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 22-1 22-2 22-3 22-4 22-5 22-6 22-7 23-1 23-2 23-3 24-1 24-2 24-3 24-4 25-1 25-2 25-3 25-4 25-5 25-6 25-7 25-8 25-9 26-1 26-2 27-1 27-2 28-1 28-2 Title Page Number Motorola SPI Frame Format with POLARITY=0 and PHASE=0 ....................................... 21-5 Motorola SPI Frame Format (Single Transfer) with POLARITY=1 and PHASE=0 ......................................................................................... 21-6 Motorola SPI Frame Format (Single Transfer) with POLARITY=1 and PHASE=0 ......................................................................................... 21-7 Motorola SPI Frame Format (Continuous Transfer) with POLARITY=1 and PHASE=0 ......................................................................................... 21-7 Motorola SPI Frame Format with POLARITY=1 and PHASE=1 ....................................... 21-8 Fast Read Dual and Quad Output Diagram .......................................................................... 21-9 Texas Instruments Synchronous Serial Frame Format (Single Transfer) ........................... 21-10 Texas Instruments Synchronous Serial Frame Format (Continuous Transfer) ................... 21-10 SD/MMC Block Transfer Flowchart .................................................................................. 21-16 Timers and Rotary Decoder Block Diagram......................................................................... 22-2 Timer 0, Timer 1, or Timer 2 Detail...................................................................................... 22-3 Timer 3 Detail ....................................................................................................................... 22-5 Pulse-Width Measurement Mode.......................................................................................... 22-6 Detail of Rotary Decoder ...................................................................................................... 22-7 Rotary Decoding Mode--Debouncing Rotary A and B Inputs ............................................ 22-8 Rotary Decoding Mode--Input Transitions.......................................................................... 22-9 RTC, Watchdog, Alarm, and Persistent Bits Block Diagram ............................................... 23-3 RTC Initialization Sequence ................................................................................................. 23-4 RTC Writing to a Master Register from CPU ....................................................................... 23-6 Pulse-Width Modulation Controller (PWM) Block Diagram ............................................... 24-2 PWM Output Example.......................................................................................................... 24-3 PWM Differential Output Pair Example............................................................................... 24-4 PWM Output Driver.............................................................................................................. 24-5 I2C Interface Block Diagram ................................................................................................ 25-2 I2C Data and Clock Timing................................................................................................... 25-4 I2C Data and Clock Timing Generation................................................................................ 25-5 I2C Master Mode Flow Chart--Initial States ....................................................................... 25-9 I2C Master Mode Flow Chart--Receive States .................................................................. 25-10 I2C Master Mode Flow Chart--Transmit States................................................................. 25-11 I2C Master Mode Flow Chart--Send Stop States............................................................... 25-12 I2C Writing Five Bytes........................................................................................................ 25-13 I2C Reading 256 Bytes from an EEPROM......................................................................... 25-14 Application UART Block Diagram....................................................................................... 26-2 Application UART Character Frame .................................................................................... 26-3 Debug UART Block Diagram............................................................................................... 27-2 Debug UART Character Frame............................................................................................. 27-3 AUDIOIN/ADC Block Diagram .......................................................................................... 28-2 AUDIOIn/ADC Block Diagram ........................................................................................... 28-4 i.MX23 Applications Processor Reference Manual, Rev. 1 -iv Preliminary--Subject to Change Without Notice Freescale Semiconductor Figures Figure Number 28-3 28-4 28-5 29-1 29-2 29-3 29-4 29-5 29-6 29-7 29-8 30-1 30-2 30-3 31-1 31-2 32-1 32-2 32-3 33-1 33-2 33-3 34-1 34-2 34-3 34-4 35-1 35-2 35-3 35-4 35-5 35-6 35-7 35-8 35-9 35-10 35-11 35-12 35-13 35-14 35-15 Title Page Number Variable-Rate A/D Converter................................................................................................ 28-7 External Microphone Bias Generation.................................................................................. 28-8 Internal Microphone Bias Generation................................................................................... 28-9 Functional AUDIOOUT/DAC Block Diagram .................................................................... 29-2 AUDIOOUT/DAC Block Diagram ...................................................................................... 29-4 Stereo Sigma Delta D/A Converter....................................................................................... 29-7 Conventional Stereo Headphone Application Circuit........................................................... 29-8 Stereo Headphone Application Circuit with Common Node................................................ 29-9 Stereo Headphone Common Short Detection and Powerdown Circuit .............................. 29-10 Stereo Headphone L/R Short Detection and Powerdown Circuit ....................................... 29-10 Speaker Amplifier with External Speaker .......................................................................... 29-12 SPDIF Transmitter Block Diagram....................................................................................... 30-2 SPDIF Flow Chart................................................................................................................. 30-3 SPDIF DMA Two-Block Transmit Example ........................................................................ 30-5 Serial Audio Interface (SAIF) Block Diagram ..................................................................... 31-2 Frame Formats Supported by SAIF .................................................................................... 31-10 Power Supply Block Diagram............................................................................................... 32-2 Brownout Detection Flowchart ............................................................................................. 32-5 Power-Up, Power-Down, and Reset Flow Chart ................................................................ 32-11 Low-Resolution ADC and Touch-Screen Interface Block Diagram..................................... 33-2 Low-Resolution ADC Successive Approximation Unit ....................................................... 33-7 Using Delay Channels to Oversample a Touch-Screen ........................................................ 33-8 Serial JTAG (SJTAG) Block Diagram .................................................................................. 34-2 SJTAG Clock Relationships................................................................................................. 34-2 SJTAG Phases of Operation for One JTAG Clock ............................................................... 34-3 SJTAG Drivers ...................................................................................................................... 34-5 Boot Loader Memory Map ................................................................................................... 35-6 Creating a Boot Loader Image .............................................................................................. 35-8 FindBootControlBlocks Flowchart ..................................................................................... 35-14 Block Search Flowchart ...................................................................................................... 35-15 Expected NAND Layout ..................................................................................................... 35-17 Layout of Boot Page Containing NCB ............................................................................... 35-18 NAND Layout--Multiple NANDs ..................................................................................... 35-20 Boot Image Recovery.......................................................................................................... 35-21 Bad Block Search................................................................................................................ 35-23 DBBT Layout...................................................................................................................... 35-24 Valid layout for 2112 bytes sized page................................................................................ 35-29 Valid layout for 4K bytes sized page .................................................................................. 35-30 2K Page Layout in NAND .................................................................................................. 35-30 2K Page Layout in On-Chip Memory................................................................................. 35-31 Redundant Area--2K.......................................................................................................... 35-32 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice -v Figures Figure Number 35-16 35-17 37-1 37-2 37-3 37-4 37-5 38-1 42-1 42-2 Title Page Number 4K Page in NAND .............................................................................................................. 35-32 4K Page Layout in On-Chip Memory................................................................................. 35-33 Pad Diagram.......................................................................................................................... 37-2 GPIO Output Setup Flowchart ............................................................................................ 37-11 GPIO Input Setup Flowchart............................................................................................... 37-12 GPIO Interrupt Flowchart ................................................................................................... 37-14 GPIO Interrupt Generation.................................................................................................. 37-15 Block Diagram of DVE......................................................................................................... 38-2 169-Pin BGA Package Drawing ........................................................................................... 42-2 128-Pin Low-Profile Quad Flat Pack (LQFP) Package Drawing ......................................... 42-3 i.MX23 Applications Processor Reference Manual, Rev. 1 -vi Preliminary--Subject to Change Without Notice Freescale Semiconductor Tables Table Number 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 4-1 5-1 6-1 9-1 10-1 10-2 10-3 11-1 11-2 11-3 12-1 12-2 12-89 12-90 12-91 12-92 12-93 12-94 12-95 12-96 12-97 Title Tables Page Number i.MX23 Functions by Package ................................................................................................ 1-1 Absolute Maximum Ratings ................................................................................................... 2-1 Electro-Static Discharge Immunity......................................................................................... 2-1 Recommended Power Supply Operating Conditions.............................................................. 2-2 Operating Temperature Conditions ......................................................................................... 2-2 Recommended Analog Operating Conditions ........................................................................ 2-3 PSWITCH Input Characteristics ............................................................................................. 2-4 Power Supply Characteristics ................................................................................................. 2-4 Non-EMI Digital Pin DC Characteristics ............................................................................... 2-7 EMI Digital Pin DC Characteristics........................................................................................ 2-8 External Devices Supported by the EMI................................................................................. 2-8 System Clocks......................................................................................................................... 2-9 Recommended Operating States - 169BGA Package ............................................................. 2-9 Recommended Operating States - 128QFP Package ............................................................ 2-10 Recommended Operating Conditions - CPU Clock (clk_p) ................................................. 2-10 Recommended Operating Conditions - AHB Clock (clk_h) ................................................ 2-10 Frequency vs. Voltage for EMICLK - 169-Pin BGA Package ............................................. 2-10 Frequency vs. Voltage for EMICLK - 128-Pin LQFP Package ............................................ 2-11 I2C Timing Parameters.......................................................................................................... 2-14 LCD AC Output Timing Parameters..................................................................................... 2-15 System Clocks......................................................................................................................... 4-2 i.MX23 Interrupt Sources ....................................................................................................... 5-6 On-Chip RAM Address Bits ................................................................................................... 6-3 USB PHY Terminator States................................................................................................... 9-7 APBH DMA Channel Assignments...................................................................................... 10-3 APBH DMA Commands ...................................................................................................... 10-4 DMA Channel Command Word in System Memory............................................................ 10-5 APBX DMA Channel Assignments...................................................................................... 11-3 APBX DMA Commands ...................................................................................................... 11-4 DMA Channel Command Word in System Memory............................................................ 11-5 Low-Power Mode Bit Fields............................................................................................... 12-15 Low-Power Mode Counters ................................................................................................ 12-16 Frequency Dependent Parameters....................................................................................... 12-68 Delays.................................................................................................................................. 12-68 DLL ..................................................................................................................................... 12-69 Delays.................................................................................................................................. 12-69 Frequency Dependent Parameters....................................................................................... 12-70 Delays.................................................................................................................................. 12-71 DLL ..................................................................................................................................... 12-71 Delays.................................................................................................................................. 12-71 Frequency Dependent Parameters....................................................................................... 12-73 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice -i Tables Table Number 12-98 12-99 12-100 12-101 12-102 12-103 15-1 15-2 15-3 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 18-1 18-2 21-1 21-2 21-3 21-4 21-5 21-6 21-7 22-1 22-2 Title Page Number Delays.................................................................................................................................. 12-74 DLL ..................................................................................................................................... 12-74 Delays.................................................................................................................................. 12-74 Frequency Dependent Parameters....................................................................................... 12-76 DLL ..................................................................................................................................... 12-76 Delays.................................................................................................................................. 12-76 Settings for 4K+218 FLASH ................................................................................................ 15-6 Settings for 4K+128 FLASH ................................................................................................ 15-7 Status Block Completion Codes ........................................................................................... 15-8 DCP Context Buffer Layout................................................................................................ 16-10 DCP Next Command Address Field ................................................................................... 16-12 DCP Control0 Field ............................................................................................................ 16-13 DCP Function Enable Bits .................................................................................................. 16-13 DCP Control1 Field ............................................................................................................ 16-14 DCP Source Buffer Field .................................................................................................... 16-15 DCP Destination Buffer Field ............................................................................................. 16-15 DCP Buffer Size Field ........................................................................................................ 16-15 DCP Payload Buffer Pointer ............................................................................................... 16-16 DCP Status Field ................................................................................................................. 16-16 DCP Payload Field.............................................................................................................. 16-17 DCP Payload Allocation by Software................................................................................. 16-17 Coefficients for YUV and YCbCr Operation...................................................................... 17-14 Supported ROP Operations ................................................................................................. 17-17 Registers and Offsets........................................................................................................... 17-21 Register Use for Conversion ............................................................................................... 17-23 Register Use for Conversion ............................................................................................... 17-24 Register Use for Conversion ............................................................................................... 17-25 Register Use for Conversion ............................................................................................... 17-27 Register Use for Conversion ............................................................................................... 17-29 Register Use for Conversion ............................................................................................... 17-31 Pin Usage in System Mode and VSYNC Mode ................................................................. 18-17 Pin Usage in DOTCLK Mode and DVI Mode ................................................................... 18-18 SSP Pin Matrix...................................................................................................................... 21-2 SD/MMC Command/Response Transfer ............................................................................ 21-11 SD/MMC Command Regular Response Token .................................................................. 21-12 SD/MMC Command Regular Long Response Token......................................................... 21-12 SD/MMC Data Block Transfer 1-Bit Bus Mode ................................................................ 21-13 SD/MMC Data Block Transfer 4-Bit Bus Mode ................................................................ 21-13 SD/MMC Data Block Transfer 8-Bit Bus Mode ................................................................ 21-13 Timer State Machine Transitions .......................................................................................... 22-4 Rotary Decoder State Machine Transitions .......................................................................... 22-9 i.MX23 Applications Processor Reference Manual, Rev. 1 -ii Preliminary--Subject to Change Without Notice Freescale Semiconductor Tables Table Number 25-1 25-2 25-3 25-4 25-5 25-6 25-7 25-8 25-9 25-10 25-11 25-12 25-13 25-14 26-1 27-1 28-1 29-1 31-1 31-2 32-1 35-1 35-2 35-3 35-4 35-5 35-6 35-7 35-8 35-9 35-10 35-11 35-12 36-1 36-2 36-3 36-4 36-5 Title Page Number I2C Interrupt Condition in HW_I2C_CTRL1 ....................................................................... 25-3 I2C Transfer When the Interface is Transmitting as a Master............................................... 25-5 I2C Address Definitions........................................................................................................ 25-5 I2C Transfer "FM Tuner" Read of One Byte ........................................................................ 25-6 I2C Transfer "FM Tuner" Read of Three Bytes.................................................................... 25-6 I2C Transfer When Master is Writing One Byte of Data to a Slave ..................................... 25-6 I2C Transfer When Master is Writing Multiple Bytes to a Slave ......................................... 25-6 I2C Transfer When Master is Receiving One Byte of Data from a Slave............................. 25-7 I2C Transfer When Master is Receiving Multiple Bytes of Data from a Slave.................... 25-7 I2C Transfer When the Interface as Master is Transmitting One Byte of Data .................... 25-7 I2C Transfer When the Interface as Master is Receiving >1 Byte of Data from Slave ........ 25-7 I2C Transfer when Master is Receiving 1 Byte of Data from Slave Internal Subaddress ................................................................................................ 25-7 I2C Transfer When Master is Receiving >1 byte of Data from Slave Internal Subaddress ................................................................................................ 25-8 I2C Transfer When the Master Transmits 5 Bytes of Data to the Slave ............................. 25-13 Receive FIFO Bit Functions ................................................................................................. 26-5 Receive FIFO Bit Functions ................................................................................................. 27-4 Bit Field Values for Standard Sample Rates ......................................................................... 28-5 Bit Field Values for Standard Sample Rates ......................................................................... 29-5 HW_CLKCTRL_SAIF_DIV Values for Standard Sample Rates/ Oversample Base Rates.................................................................................................... 31-4 HW_DIGCTL_CTRL_SAIF_CLKMUX_SEL Programming ............................................. 31-6 Power System Interrupts ..................................................................................................... 32-14 ROM Supported Boot Modes ............................................................................................... 35-1 Boot Pins ............................................................................................................................... 35-1 Boot Mode Selection Map .................................................................................................... 35-2 General ROM Bits ................................................................................................................ 35-3 NAND/SD-MMC Related Bits ............................................................................................. 35-4 USB-Related Bits .................................................................................................................. 35-5 Persistent Bits........................................................................................................................ 35-5 SCK Clock Standard Values Lookup Table ....................................................................... 35-10 GPIO Pin Selection ............................................................................................................. 35-10 Bus Pin Selection ................................................................................................................ 35-11 Media Config Block Parameters ......................................................................................... 35-12 MBR Signature Bits ............................................................................................................ 35-12 Nomenclature for Pin Tables................................................................................................. 36-2 128-Pin LQFP Pin Definitions by Pin Name ........................................................................ 36-2 128-Pin LQFP Pin Definitions by Pin Number .................................................................... 36-5 128-Pin LQFP Connection Diagram--Top View ................................................................. 36-9 169-Pin BGA Pin Definitions by Pin Name ......................................................................... 36-9 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice -iii Tables Table Number 36-6 36-7 37-1 37-2 37-3 37-4 38-1 38-2 40-1 41-1 B-1 Title Page Number 169-Pin BGA Pin Definitions by Pin Number.................................................................... 36-13 169-Pin BGA Ball Map....................................................................................................... 36-18 Color Mapping for Pin Control Bank Tables ........................................................................ 37-3 Pin Multiplexing for 169-Pin BGA Package ........................................................................ 37-4 Pin Multiplexing for 128-Pin QFP Packages........................................................................ 37-6 i.MX23 Functions with Pullup Resistors .............................................................................. 37-9 Registers in the HI_unit Writeable by Host .......................................................................... 38-5 Hardwired Registers Values ................................................................................................ 38-16 Address Map for i.MX23 ...................................................................................................... 40-1 Part Numbers for i.MX23 Family Members ......................................................................... 41-1 Register Names and Addresses ...............................................................................................B-1 i.MX23 Applications Processor Reference Manual, Rev. 1 -iv Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 1 Product Overview The i.MX23 is an applications processor targeted at devices that require low power, high performance, high integration and quality audio and video playback. This chapter provides a general overview of the i.MX23 product and describes hardware features, application capability, design support, and additional documentation. See Table 1-1, and the pinout information in Chapter 36, "Pin Descriptions," for more detailed information about which functions described later in this document are supported in which package and part number. Table 1-1. i.MX23 Functions by Package Function External memory interface (2.5 V DDR, 1.8 V mDDR) LQFP128 64MB Maximum, 16-bit data, 13-bit address, 1 chip enable 8-bit data 4 (2 dedicated, 2 muxed) BGA169 128MB Maximum 16-bit data, 13-bit address, 2 chip enable 16-bit data 4 (3 dedicated, 1 muxed) Yes /w 8-bit NAND Yes Yes Yes Yes Yes Yes General-Purpose Media Interface (GPMI): * NAND data width * Number of external NANDs supported LCD Interface (LCDIF): * Up to 24-bit full-color parallel RGB mode * Up to 18-bit parallel RGB mode * 8-bit serial RGB mode * ITU-R BT.656 8-bit+clock mode * 8-bit system mode * Up to 18-bit parallel system mode * Up to 24 bit parallel system mode Serial Audio Interface (SAIF or I2S): * Interfaces supported (Note SAIF1/SAIF2 are muxed with LCD_DATA[8:16]) SPDIF Transmitter Low-Resolution ADC (LRADC): * Number supported * Touch-screen supported Application UART2: * Supported via dedicated pins No No Yes Yes Yes No No 0 No 2 (or 3 without 2.5 V DDR) No No 2 Yes 6 Yes Yes i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-1 Product Overview Table 1-1. i.MX23 Functions by Package (continued) Function Synchronous Serial Port 1 (SSP1): * Data width Synchronous Serial Port 2 (SSP2): * Data width (Note SSP2 is muxed with GPMI/NAND) Embedded Trace Macrocell (ETM) Pulse Width Modulation (PWM) Channels Rotary Encoder Mono speaker amplifier Real-Time Clock (RTC) Power Supply 4.2 V Regulated Output Single Channel 10-bit Video DAC (Composite output) LQFP128 BGA169 4-bit data 8-bit data No 3 Yes (Muxed with PWM / DEBUG UART pins) No 24 MHz Li-Ion Yes Yes 8-bit data 8-bit data Yes 5 Yes (Dedicated pins) Yes 32 kHz and 24 MHz Li-Ion Yes Yes 1.1 * Hardware Features ARM926 CPU Running at 454 MHz -- Integrated ARM926EJ-S CPU -- 16-Kbyte data cache and 16-Kbyte instruction cache -- ARM Embedded Trace Macrocell (ETM CoreSight 9) (169BGA only) -- One-wire JTAG interface -- Resistor-less boot mode selection using integrated OTP values 32 Kbytes of Integrated Low-Power On-Chip RAM 64 Kbytes of Integrated Mask-Programmable On-Chip ROM 1 Kbit of On-Chip One-Time-Programmable (OCOTP) ROM Universal Serial Bus (USB) High-Speed (Up to 480 Mb/s), Full-Speed (Up to 12 Mb/s) -- Full-speed/high-speed USB device and host functions -- Fully integrated full-speed/high-speed Physical Layer Protocol (PHY) -- Mass storage host-capable (uncertified by USB-IF) Power Management Unit -- Single inductor DC-DC switched converter with multi-channel output supporting Li-Ion batteries. -- Features multi-channel outputs for VDDIO (3.3 V), VDDD (1.2 V), VDDA (1.8 V), VDDM (2.5V) and regulated 4.2V source. -- Direct power from 5-V source (USB, wall power, or other source), with programmable current limits for load and battery charge circuits. i.MX23 Applications Processor Reference Manual, Rev. 1 * * * * * 1-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Product Overview * * * * * * -- Silicon speed and temperature sensors enable adaptive power management over temperature and silicon process. Audio Codec -- Stereo headphone DAC with 99 dB SNR -- Stereo ADC with 85 dB SNR -- Stereo headphone amplifier with short-circuit protection and direct drive to eliminate bulky capacitors -- Mono speaker amplifier (169-Pin BGA only) providing up to 2W rms output, running directly from the battery. -- Amplifiers are designed for click/pop free operation. -- Two stereo line inputs -- Microphone input -- SPDIF digital out 16-Channel Low-Resolution ADC -- 6 independent channels and 10 dedicated channels -- Resistive touchscreen controller -- Temperature sensor controller -- Absolute accuracy of 1.3% -- Up to 0.5% with bandgap calibration Security Features -- Read-only unique ID for digital rights management algorithms -- Secure boot using 128-bit AES hardware decryption -- SHA-1 hashing hardware -- Customer-programmed (OTP) 128 bit AES key is never visible to software. External Memory Interface (EMI) -- Provides memory-mapped (load/store) access to external memories -- Supports the following types DRAM: - 1.8-V Mobile DDR - Standard 2.5V DDR1 Wide Assortment of External Media Interfaces -- Up to four NAND flash memories with hardware management of device interleaving -- High-speed MMC, secure digital (SD) -- Hardware Reed-Solomon Error Correction Code (ECC) engine offers industry-leading protection and performance for NANDs. -- Hardware BCH ECC engine allowing for up to 20-bit correction and programmable redundant area. Dual Peripheral Bus Bridges with 18 DMA Channels -- Multiple peripheral clock domains save power while optimizing performance. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-3 Product Overview * * * * * * * * * -- Direct Memory Access (DMA) with sophisticated linked DMA command architecture saves power and off-loads the CPU. Highly Flexible Display Controller -- Up to 24-bit RGB (DOTCK) modes -- Up to 24-bit system-mode including VSYNC and WSYNC modes. -- Up to VGA (640x480) resolution at 60Hz LCD panel support -- 8-bit data ITU-R BT.656 D1 digital video stream output mode (PAL/NTSC), with on-the-fly RGB to YCbCr color-space-conversion. -- Flexible input formats Pixel Processing Pipeline (PXP) -- Provides full path from color-space conversion, scaling, alpha-blending to rotation without intermediate memory access -- Bi-linear scaling algorithm with cropping and letterboxing -- Alpha-blend, BITBLT, color-keying -- Memory efficient block-based rotation engine -- Supports up to eight overlays Integrated TV-Out Support -- Integrated PAL/NTSC TV-encoder fully pipelined to display controller's D1 resolution output stream -- Integrated low-power 10-bit Video DAC (VDAC) for composite analog video output. Data Co-Processor (DCP) -- AES 128-bit encryption/decryption -- SHA-1 hashing -- High-speed memory copy Three Universal Asynchronous Receiver-Transmitters (UARTs) -- Two high-speed application UARTs operating up to 3.25 Mb/s with hardware flow control and dual DMA. -- Debug UART operates at up to 115Kb/s using programmed I/O. I2C Master/Slave -- DMA control of an entire EEPROM or other device read/write transaction without CPU intervention Dual Synchronous Serial Ports (for SPI, MMC, SDIO, Triflash) -- Up to 52MHz external SSP clock for all modes, including SPI -- 1-bit, 4-bit and 8-bit MMC/SD/SDIO modes -- Compliant with SDIO Rev. 2.0 -- SPI with single, dual and quad modes. Four-Channel 16-Bit Timer with Rotary Decoder Five-Channel Pulse Width Modulator (PWM) i.MX23 Applications Processor Reference Manual, Rev. 1 1-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Product Overview * * * * * * Real-Time Clock -- Alarm clock can turn the system on. -- Uses the existing 24-MHz XTAL for low cost or optional low power crystal (32.768 kHz or 32.0 kHz), customer-selectable via OTP. SPDIF Transmitter Dual Serial Audio Interface (SAIF), Three Stereo Pairs -- Full-duplex stereo transmit and stereo receive operations -- Cell phone baseband processor connection and external ADCs and DACs -- Bluetooth hands-free connection -- Analog I/O for peripheral bus breakouts -- I2S, left-justified, right-justified, and non-standard formats Customer-Programmable One-Time-Programmable (OTP) ROM via Integrated eFuse Block -- Resistor-less boot mode selection -- 128-bit boot mode crypto key -- Boot mode specification of NAND characteristics for device that the customer is soldering to the board. This means no more costly delays waiting for new device support in the boot ROM. -- Fully software-programmable and accessible Flexible I/O Pins -- All digital pins have drive-strength controls as described in Section 37.2.2.1, "Pin Drive Strength Selection." -- Most non-EMI digital pins have general-purpose input/output (GPIO) mode. Offered in 128-Pin Low-Profile Quad Flat Pack (LQFP), and 169-Pin Ball Grid Array (BGA) 1.2 i.MX23 Product Features The i.MX23 offers long battery life, minimal external components through integration, high processing performance, and excellent software development and debug support. The i.MX23 is especially suited for multi-media applications requiring audio/video decode and rich display support. These requirements are achieved via the high-performance CPU, pixel processing and integrated display and TV-Out hardware. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-5 Product Overview Figure 1-1 shows a block diagram of a typical system based on the i.MX23. 32.768-KHz, 32KHz Crystal USB High-Speed USB Full-Speed Interrupt Control, 6xTimers, 18xDMAs, JTAG, Trace 24.0-MHz Crystal Line In Microphone 2xLine in Mic in Capless Direct-Drive Headphones DAC Amp Mic Headphone Headphone Amplifier Amplifier Speaker Amplifier OTP 1Kbit Host x 2, Debug Peer-to-Peer UI: Rotary UI: LED/ Switches Backlight / Beep MMC/SD/SDIO/ SPI FM Tuner eePROM Serial audio In/Out S/PDIF Out CD 1Control 2 + UARTs Interface USB 2.0 Device/Host USB Controller & PHY DualPLL XTAL, RTC, xtal ALARM PLL and CLKGEN Peripheral Rotary Decoder I2C Interface AMBA AXI/AHB 16K I$ 16K D$ i.MX233 DAC DAC General I/O Pin Multiplexer Purpose Input/Output GPIO / Pinctrl Pulse Width 2xSSP Interface SPI Interface I C Interface I2C Interface SAIF TX or RX I2C Interface S/PDIF TX I2C Interface BCH - ECC EMC Media Interface EMC RSEMC - ECC8 2 DSP ARM926 ADC ADC On-Chip ROM 16K x 32bits Mono Speaker Out On-Chip On-Chip RAM RAM 8K96K x x 32bits 24bits Temperature NAND Flash Crypto + CD Control memcpy Interface Pixel Pipeline CD Control (CSC, Scaling, Blending) Interface LowDCDC Resolution Converter ADC x16 Low Battery Resoluti Charger on ADC DCDC x 3 DCDC LDO x 4 Converter 4.2V Reg 1.2V 1.8V 3.3V 4.2V 2.5V mDDR (1.8V) DDR (2.5V) LCD / CCIR-656 SDRAM EMI Interface Display CD Control Controller Interface TV-Out NTSC/ PAL Encoder 1-Channel Video DAC Composite TV-Out UI: Buttons, Touch-Screen Rechargeable Li-ION Battery 5V Input (USB or Wall Supply) Figure 1-1. System Block Diagram The i.MX23 features low power consumption to enable long battery life in portable applications. The integrated power management unit includes a high-efficiency, on-chip DC-DC converter. The power management unit also includes an intelligent battery charger for Li-Ion cells and is designed to support adaptive voltage control (AVC), which can reduce system power consumption by half. AVC also allows the chip to operate at a higher peak CPU operating frequency than typical voltage control systems. The DC-DC converters and the clock generator can be reprogrammed on-the-fly to trade off power versus performance dynamically. To provide the maximum application flexibility, the i.MX23 integrates a wide range of I/O ports. It can efficiently interface to nearly any type of flash memory, serial peripheral bus, or LCD. It is also ready for advanced connectivity applications such as Bluetooth and WiFi via its integrated 4-bit SDIO controller and high-speed (3.25 Mb/s) UARTs. i.MX23 Applications Processor Reference Manual, Rev. 1 1-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Product Overview The i.MX23 also integrates an entire suite of analog components, including a high-resolution audio codec with headphone amplifier, 16-channel 12-bit ADC, 10-bit Video DAC, Mono Speaker Amplifier, high-current battery charger, linear regulators for 5-V operation, high-speed USB Host PHY, and various system monitoring and infrastructure systems. An ARM 926 EJ-S CPU with 32 Kbytes of on-chip SRAM and an integrated memory management unit provides the processing power needed to support advanced features such as audio cross-fading, as well as still picture and video decoding. Execution always begins in on-chip ROM after reset, unless overridden by the debugger. A number of devices are programmed only at initialization or application state change, such as DC-DC converter voltages, clock generator settings, etc. Certain other devices either operate in the crystal clock domain or have significant portions that operate in the crystal clock domain, e.g., ADC, DAC, PLL, etc. These devices operate on a slower speed asynchronous peripheral bus. Write posting in the ARM core, additional write post buffering in the peripheral AHB, and set/clear operations at the device registers make these operations efficient. 1.2.1 ARM 926 Processor Core The on-chip RISC processor core is an ARM, Ltd. 926EJ-S. This CPU implements the ARM v5TE instruction set architecture. The ARM9EJ-S has two instructions sets, a 32-bit instruction set used in the ARM state and a 16-bit instruction set used in Thumb state. The core offers the choice of running in the ARM state or the Thumb state or a mix of the two. This enables optimization for both code density and performance. The ARM CPU is described in Chapter 3, "ARM CPU Complex." The ARM RISC CPU is the central controller for the entire i.MX23 SOC, as shown in Figure 1-2. The ARM 926 core includes two AHB masters: * * AHB1--Used for instruction fetches AHB2--Used for data load/stores, page table accesses, DMA traffic, etc. 1.2.2 System Buses The i.MX23 uses buses based on ARM's Advanced Microcontroller Bus Architecture (AMBA) for the on-chip peripherals. The AMBA2 specification outlines two bus types: AHB and APB. The AMBA3 specification additionally outlines the AXI fabric. * AXI is the highest-performance AMBA bus that supports de-coupled R/W channels, multiple outstanding transactions, and out-of-order data capability. This leads to higher performance and more efficient use of external memory. AHB is a higher-performance bus that supports multiple masters such as the CPU and DMA controllers. The APB is a lower-speed peripheral bus. * * i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-7 Product Overview As shown in Figure 1-2, the i.MX23 uses a three-layer AHB, a high-performance AXI segment and two APBs: APBH and APBX. The APB buses are enhanced to include byte-write capability. APBH OTP PIN CTRL TVENC PIO PXP PIO GPM I SSP1 SSP0 LCD IF PIO M AHB- D ETM CS9 + JTAG EM I PIO ICO LL PIO DIC GTL BCH PIO ECC 8 PIO DCP PIO ARM 926EJ-S AHB- I M S OC RO M Controller S M 64KB R OM S M S AHB-to-APBH Bridge/DM A DM A Control 32KB SRAM 4 Port OC RAM Controller S S S S AHB-to-APBX Bridge/D M A D MA Control I 2C M SPDIF TX AHB AHB1 AHB2 APB X AXI2AHB LCDIF AXI 4-2 AHB3 SAIF TX/RX Audio Out Audio In DCP BCH ECC PXP m DD R/DD R M AXI DRAM CTLR RS ECC8 USB Host + PHY S S S M S M UART3 UART2 UART1 M ultichannel ADC/Touchscreen Clock Power/Reset Tim ers / Rotary Decode PW M USB PHY RTC /ALARM , W atchdog, Persistent Regs Figure 1-2. i.MX23 SoC Block Diagram i.MX23 Applications Processor Reference Manual, Rev. 1 1-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Product Overview 1.2.2.1 AXI Bus The AXI bus-segment on i.MX23 provides several high-bandwidth/performance-critical peripherals a tightly-coupled and efficient interface to Port-0 of the external memory controller. The peripherals are as follows: * DCP (Crypto/Memcpy) * PXP (Pixel Processing Pipeline) * LCDIF (Display Controller) * BCH-ECC Engine This connection also allows for a path to the On-Chip RAM and EMI as shown in the figure. The AXI bus-segment allows for each peripheral to issue multiple outstanding transactions allowing for higher-performance and more efficient memory bus usage. 1.2.2.2 * * * AHB Bus The AHB is the main high-performance system bus and is implemented in three layers, as follows: Layer 1 (AHB1)--CPU instruction access to OCRAM, OCROM, EMI Layer 2 (AHB2)--CPU data access to OCRAM, OCROM, all bridges, USB slaves, EMI Layer 3 (AHB3)--APBH DMA, APBX DMA, RS-ECC8 and USB masters, EMI The ARM926 instruction bus (AHB1) is a single-master layer, as is the ARM926 data bus (AHB2). The other two layers have multiple masters, as shown in Figure 1-2. The ARM926 data bus connects to the all slaves in the system, including RAMs, ROMs, bridge slaves, and USB slaves. The APB peripherals can act as AHB slaves through the AHB-APB bridge. The AHB has seven slaves: * * * * * USB slave On-chip RAM On-chip ROM Two APB bridges External memory Each layer of the AHB bus allows one active transaction at a time. A transaction is initiated by a master, controlled by an arbiter, and serviced by the slave at the corresponding address. A transaction can be as short as a single byte, or as long as a CPU cache line (32 bytes). For the USB, a transaction can be much longer, up to 512 bytes on its AHB layer. For more information, refer to the AMBA 2.0 specification. 1.2.2.3 APB Buses There are two APB peripheral buses on the i.MX23: * The APBH bus runs completely synchronously to the AHB's HCLK. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-9 Product Overview * The APBX bus runs in the independent XCLK clock domain that can be slowed down significantly for power reduction. The "H" in APBH denotes that the APBH is synchronous to HCLK, as compared to APBX, which runs on the crystal-derived XCLK. Figure 1-2 shows which blocks are controlled by which bus. See Section 1.2.7, "DMA Controller," for more information about these peripheral buses and their DMA bridges. 1.2.3 On-Chip RAM and ROM The i.MX23 includes 8Kx32-bit on-chip RAM implemented as a single physical bank with four AHB slave ports. Each access to the on-chip RAM requires at a minimum two HCLK cycles. The i.MX23 also includes 16Kx32-bit words of on-chip mask-programmable ROM. The ROM contains intitialization code written by Freescale. to handle the initial boot and hardware initialization. Software in this ROM offers a large number of boot configuration options, including manufacturing boot modes for burn-in and tester operation. Other boot modes are responsible for loading application code from off-chip into the on-chip RAM. It supports initial program loading from a number of sources: * * * NAND flash devices I2C master mode from EEPROM devices USB recovery mode At power-on time, the first instruction executed by the ARM core comes from this ROM. The reset boot vector is located at 0xFFFF0000. The on-chip boot code includes a firmware recovery mode. If the device fails to boot from NAND flash, or hard drive, for example, the device will attempt to boot from a PC host connected to its USB port. The on-chip RAM and ROM run on the AHB HCLK domain. Figure 1-3 shows the memory map for the AHB2 devices. 1.2.4 External Memory Interface The i.MX23 supports off-chip DRAM storage via the EMI controller, which is connected to the four internal AHB/AXI busses. The EMI supports multiple external memory types, including: * * 1.8-V Mobile DDR Standard 2.5V DDR1 i.MX23 Applications Processor Reference Manual, Rev. 1 1-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Product Overview The DRAM controller supports up to two external chip-select signal for the i.MX23 platform. Programmable registers within the DRAM controller allow great flexibility for device timings, low-power operation, and performance tuning. Note the diffences between the two package options: * * The 128-pin LQFP has 1 chip enable. The 169-pin BGA has 2 chip enables. The EMI uses two primary clocks: the AHB bus HCLK and the DRAM source clock EMI_CLK. The maximum specified frequencies for these two clocks can be found in Chapter 2, "Characteristics and Specifications. The memory controller operates at frequencies that are asynchronous to the rest of the i.MX23. The EMI consists of two major components: * * DRAM controller Delay compensation circuitry (DCC) 0xFFFFFFFF On-Chip ROM 0xFFFF0000 0xFFFEFFFF 0xC0000000 0x80100000 0x800FFFFF 0x80000000 0x7FFFFFFF ROM aliased through 1 Gbyte Default Slave Peripheral Space 128 Kbytes Default Slave 0x60000000 0x5FFFFFFF External DRAM 32767 Aliases of 32 Kbytes On-Chip SRAM 0x00008000 0x00007FFF On-Chip SRAM 32 Kbytes 0x00000000 Figure 1-3. Physical Memory Map i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-11 Product Overview 1.2.5 On-Chip One-Time-Programmable (OCOTP) ROM The i.MX23 contains 1024 bits (1Kb) of OTP ROM. The OTP is segmented into four distinct physical banks. Each bank is further divided logically into eight 32-bit words. The OTP serves several functions: * * * * * * Housing of hardware and software capability bits (copied into shadow registers) Housing of Freescale operations and unique-ID fields. Housing the customer-programmable cryptography key Four words for customer general use A 32-bit word is dedicated to controller read and write locking of the various OTP regions (copied into a shadow register) Storage of various ROM configuration bits Access to the OTP is done through a memory-mapped APBH slave interface. Each of the 32 words is memory-mapped on APBH for the purposes of reading (requires a bank-opening sequence). Writing to the OTP is done through an address and data interface, where software provides the OTP word number (one of 32) and a programming mask. For more information, see Chapter 7, "On-Chip OTP (OCOTP) Controller." 1.2.6 Interrupt Collector The i.MX23 contains a 128-bit vectored interrupt collector for the CPU's IRQ input and a separate non-vectored interrupt collection mechanism for the CPU's FIQ input. Each interrupt can be assigned to one of four levels of priority. The interrupt collector supports nesting of interrupts that preempt an interrupt service routine running at a lower priority level. Each of the 128 interrupts is assigned its own 32-bit programming register and can be set for HW source IRQ, SW source IRQ or HW source FIQ. The interrupt collector is described in Chapter 5, "Interrupt Collector." 1.2.7 DMA Controller Many peripherals on the i.MX23 use direct memory access (DMA) transfers. Some peripherals, such as the USB controller, make highly random accesses to system memory for a large number of descriptor, queue heads, and packet payload transfers. This highly random access nature is supported by integrating a dedicated DMA into the USB controller and connecting it directly to the high-speed AHB bus. Similarly, the RS-ECC8 error correction engine, the DCP (crypto/memcpy), BCH-ECC and LCD controller devices contain their own bus masters to allow for more random accesses to system memory. Other peripherals have a small number of highly sequential transactions, for example the ADC or DAC streams, SPDIF transmitter, etc. These devices share a centralized address generation and data transfer function that allows them to share a single shared master on the AHB. i.MX23 Applications Processor Reference Manual, Rev. 1 1-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Product Overview As mentioned previously, there are two AMBA peripheral buses on the i.MX23: * The APBH bus runs completely synchronously to the AHB's HCLK. * The APBX bus runs in an independent XLKC clock domain that can be slowed down significantly for power reduction. See Chapter 10, "AHB-to-APBH Bridge with DMA," and Chapter 11, "AHB-to-APBX Bridge with DMA," for more detailed information. Note that the AHB HCLK can run up to 133 MHz. The two bridge DMAs are controlled through linked DMA command lists. The CPU sets up the DMA command chains before starting the DMA. The DMA command chains include set-up information for a peripheral and associated DMA channel. The DMA controller reads the DMA command, writes any peripheral set up, tells the peripheral to start running and then transfers data, all without CPU intervention. The CPU can add commands to the end of a chain to keep data moving without interventions. The linked DMA command architecture offloads most of the real-time aspects of I/O control from the CPU to the DMA controller. This provides better system performance, while allowing longer interrupt latency tolerances for the CPU. 1.2.8 Clock Generation Subsystem The i.MX23 uses several different clock domains to provide clocks to the various subsystems, as shown in Figure 4-1. These clocks are either derived from the 24-MHz crystal or from the integrated high-speed PLL. The PLL output is fixed at 480 MHz. More details about the system clock architecture can be found in Chapter 4, "Clock Generation and Control." The system includes a real-time clock that can use either the 24-MHz system crystal or an optional low power crystal oscillator running at either 32.768 kHz or 32.0 kHz (customer-configurable via OTP). An integrated watchdog reset timer is also available for automatic recovery from errant code execution. See Chapter 23, "Real-Time Clock, Alarm, Watchdog, Persistent Bits," for more information about these features. 1.2.9 Power Management Unit The i.MX23 contains a sophisticated power management unit (PMU), including an integrated DC-DC converter, four linear regulators and a regulated 4.2V output. The PMU can operate from a Li-Ion battery using the DC-DC converter or a 5-V supply using the linear regulators and can automatically switch between them without interrupting operation. The PMU includes circuits for battery and system voltage brownout detection, as well as on-chip temperature, digital speed, and process monitoring. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-13 Product Overview The integrated PMU converter can be used to provide programmable power for the device as well as the entire application on up to five rails: * VDDIO (nominal 3.3V) - DC-DC or linear-regulator from 5V * VDDD (nominal 1.2V) - DC-DC or linear-regulator from VDDA * VDDA (nominal 1.8V) - DC-DC or linear-regulator from VDDIO * VDDM (nominal 2.5V) - linear-regulator from VDDIO * VDD4P2 (nominal 4.2V) - when connected to 5V source The 4.2V regulated output also allows for programmable current limits: * * * Total load plus battery charge current (5V Limit) Battery Charge current Load current - for both on-chip and off-chip circuits The 4.2V circuit is capable of adjusting distribution of current supply between the load and the battery-charger depending on programmed current-limits and load conditions. For example, when charging the battery, and exceeding the 5V current limit, the 4.2V regulator will steal current from the battery-charger circuit and divert it to the load circuit. The converter can be configured to operate from standard Li-Ion battery chemistries up to 4.2 volts. These converters use off-chip reactive components (L/C) in a pulse-width or frequency-modulated DC-DC converter. The real-time clock includes an alarm function that can be used to "wake-up" the DC-DC converters, which will then wake up the rest of the system. The power subsystem is described in Chapter 32, "Power Supply." 1.2.10 USB Interface The chip includes a high-speed Universal Serial Bus (USB) version 2.0 controller and integrated USB transceiver macrocell interface (UTMI) PHY. The i.MX23 device interface can be attached to USB 2.0 hosts and hubs running in the USB 2.0 high-speed mode at 480 Mbits per second. It can be attached to USB 2.0 full-speed interfaces at 12 Mbits per second. The USB controller and integrated PHY support high-speed Host modes for peer-to-peer file interchange. The i.MX23 has a high-current PWM channel that can be used with low-cost external components to generate up to 8 mA of 5 volts on the Host VBUS for Host session initiation. The USB controller can also be configured as a high-speed host. The USB subsystem is designed to make efficient use of system resources within the i.MX23. It contains a random-access DMA engine that reduces the interrupt load on the system and reduces the total bus bandwidth that must be dedicated to servicing the five on-chip physical endpoints. i.MX23 Applications Processor Reference Manual, Rev. 1 1-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Product Overview It is a dynamically configured port that can support up to five endpoints, each of which may be configured for bulk, interrupt, or isochronous transfers. The USB configuration information is read from on-chip memory via the USB controller's DMA. See Chapter 8, "USB High-Speed Host/Device Controller," and Chapter 9, "Integrated USB 2.0 PHY," for more information. 1.2.11 General-Purpose Media Interface (GPMI) The chip includes a general-purpose media interface (GPMI) controller that supports NAND devices (all packages). The NAND flash interface provides a state machine that provides all of the logic necessary to perform DMA functions between on-chip or off-chip RAM and up to four NAND flash devices. The controller and DMA are sophisticated enough to manage the sharing of a single 16 bit wide data bus among four NAND devices, without detailed CPU intervention. This allows the i.MX23 to provide unprecedented levels of NAND performance. The general-purpose media interface can be described as two fairly independent devices in one. The three operating modes are integrated into one overall state machine that can freely intermix cycles to different device types on the media interface. There are four chip selects on the media interface. Each chip select can be programmed to have a different type device installed. The GPMI pin timings are based on a dedicated clock divider from the PLL, allowing the CPU clock divider to change without affecting the GPMI. See Chapter 13, "General-Purpose Media Interface (GPMI)," for more information. 1.2.12 Hardware Acceleration for ECC for Robust External Storage The hardware ECC accelerator provides a forward error-correction function for improving the reliability of various storage media that may be attached to the i.MX23. Modern high-density NAND flash devices presume the existence of forward error-correction algorithms to correct some soft and/or hard bit errors within the device, allowing for higher device yields and, therefore, lower NAND device costs. The i.MX23 contains two separate Error Correction Code (ECC) hardware engines implemented the following algorithms: * * Reed-Solomon - Provides 4 or 8 bits/symbol correction (RS-ECC8). This is the same engine found in previous SoC products. Bose Ray-Choudhury Hocquenghem - Provides up to 20-bits correction (BCH-ECC) Both engines are tightly coupled to the GPMI and are for mutually exclusive use with completely separate programming models and DMA structures. The BCH engine supersedes the RS-ECC8 except in i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-15 Product Overview allowing for backwards compatibility of legacy NAND software drivers written specifically for the RS-ECC8. 1.2.12.1 * * Reed-Solomon ECC Engine The RS-ECC module consists of two different error correcting code processors: Four-symbol error correcting (9 bits/symbol) Reed-Solomon encoder/decoder Eight-symbol error correcting (9 bits/symbol) Reed-Solomon encoder/decoder The Reed-Solomon modes are used for storage elements that have a higher native defect probability, such as MLC NAND. It can correct up to four 9-bit symbols over a 512-byte block in a 2-Kbyte paged device or up to eight 9-bit symbols over a 512-byte block in a 4-Kbyte paged device. Both of these error correction encoder/decoders use DMA transfers to move data from system memory completely in parallel with the CPU performing other useful work. For storage read transfers, the ECC8 controller uses its AHB bus master to transfer data directly to system memory. In addition, the ECC8 automatically corrects errors in the read data buffers in system memory without CPU assistance. The ECC8 includes one more significant enhancement, namely, it provides four-symbol error correction for the 9 or 16 byte metadata stored in the redundant area of the NAND device. See Chapter 14, "8-Symbol Correcting ECC Accelerator (ECC8)," for more information. 1.2.12.2 Bose Ray-Choudhury Hocquenghem ECC Engine The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder module is capable of correcting from 2 to 20 single bit errors within a block of data no larger than about 900 bytes (512 bytes is typical) in applications such as protecting data and resources stored on modern NAND flash devices. The correction level in the BCH block is programmable to provide flexibility for varying applications and configurations of flash page size. The design can be programmed to encode protection of 2, 4, 8, 10, 12, 14, 16, 18, or 20 bit errors when writing flash and to correct the corresponding number of errors on decode. The correction level when decoding MUST be programmed to the same correction level as was used during the encode phase. BCH-codes are a type of block-code, which implies that all error-correction is performed over a block of N-symbols. The BCH operation will be performed over GF(213 = 8192), which is the Galois Field consisting of 8191 one-bit symbols. BCH encoding (or encode for any block-code) can be performed by two algorithms: systematic encoding or multiplicative encoding. Systematic encoding is the process of reading all the symbols which constitute a block, dividing continuously these symbols by the generator polynomial for the GF(8192) and appending the resulting t parity symbols to the block to create a BCH codeword (where t is the number of correctable bits). i.MX23 Applications Processor Reference Manual, Rev. 1 1-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Product Overview The BCH sits on the AXI fabric with close coupling to both the GPMI and external memory controller. See Chapter 15, "20-BIT Correcting ECC Accelerator (BCH)." 1.2.13 Data Co-Processor (DCP)--Memory Copy, Crypto, and Color-Space Converter The i.MX23 SOC contains a data co-processor consisting of four virtual channels. Each channel is essentially a memory-to-memory copy engine. The linked list control structure can be used to move byte-aligned blocks of data from a source to a destination. In the process of copying from one place to another, the DCP can be programmed to encrypt or decrypt the block using AES-128 in one of several chaining modes. An SHA-1 hash can be calculated as part of the memory-copy operation. See Chapter 16, "Data Co-Processor (DCP)," for more information. 1.2.14 Mixed Signal Audio Subsystem The i.MX23 contains an integrated high-quality mixed signal audio subsystem, including high-quality sigma delta D/A and A/D converters, as shown in Figure 1-4. The chip includes a low-noise headphone driver that allows it to directly drive low-impedance (16) headphones. The direct drive, or "capless" mode, removes the need for large expensive DC blocking capacitors in the headphone circuit. The headphone power amplifier can detect headphone shorts and report them via the interrupt collector. A digitally programmable master volume control allows user control of the headphone volume. Use of the headphone amplifier volume control is recommended as the digital control may reduce SNR performance. Annoying clicks and pops are eliminated by zero-crossing updates in the volume/mute circuits and by headphone driver startup and shutdown circuits. The microphone circuit has a mono-to-stereo programmable gain pre-amp and an optional microphone bias generator. Also integrated is a class A-B mono speaker amplifier which must be powered from a sufficiently high-enough current 4.2V source such as the battery. The speaker amplifier can support up to 2W rms of output assuming a 4.2V supply and a 4 speaker load. These features are described in Chapter 28, "AUDIOIN/ADC," and Chapter 29, "AUDIOOUT/DAC." i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-17 Product Overview AUDIOOUT From DAC DMA 1 FIFO DAC R VAG 8 X HP_VGND 2 LINE1R From DAC DMA X 7 Headphone Right X HPR 1 FIFO DAC L 3 Speaker Amp X X SPEAKERN SPEAKERP 10 2 LINE1L X 7 Headphone Left X HPL LRADC3 /LINE2R LINE1R MIC X X X 7 7 ADC Right Input Mux ADC GAIN AUDIOIN 4 ADC R FIFO To ADC DMA 6 LRADC2 /LINE2L LINE1L LRADC0 LRADC1 X X ADC Left Input Mux 5 7 7 ADC GAIN 4 ADC L FIFO X X 5 Mic Bias 9 To ADC DMA Notes: 1. HW_AUDIOOUT_DACVOLUME: Digital volume control. -100 dB to -0.5 dB in 0.5 dB steps. 2. HW_AUDIOOUT_HPVOL: Analog volume control. -57.5 dB to 6 dB in 0.5 dB steps. 3. HW_AUDIOOUT_PWDN: Enable capless headphone common amplifier. 4. HW_AUDIOOUT_SPEAKERCTRL: Analog control for speaker amplifier, fixed gain of 9.5 dB from each DAC, 15.5dB total. 5. HW_AUDIOIN_ADCVOLUME: Digital volume control. -100 dB to -0.5 dB in 0.5 dB steps. 6. HW_AUDIOIN_ADCVOL: Analog volume control that controls the ADC gain block. 0 dB to 22.5 dB gain in 1.5 dB steps. 7. HW_AUDIOIN_MICLINE_MICGAIN: Analog volume control that controls the microphone amplifier. 0, 20, 30, or 40 dB gain. 8. HW_AUDIOOUT_MICLINE_MIC_BIAS: Mic bias voltage. 1.21V to 2.96V in 0.25V steps. 9. HW_AUDIOOUT_MICLINE_MIC_RESISTOR, HW_AUDIOOUT_MICLINE_MIC_SELECT. 10. HW_AUDIOIN_MICLINE_DIVIDE_LINE1/2. Figure 1-4. Mixed Signal Audio Elements i.MX23 Applications Processor Reference Manual, Rev. 1 1-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Product Overview 1.2.15 Master Digital Control Unit (DIGCTL) The master digital control unit (DIGCTL) provides control registers for a number of blocks that do not have their own AHB or APB slaves, notably the on-chip RAM and on-chip ROM controllers. In addition, it provides control registers for the DRAM controller output clock shifting. It also provides several security features, including an entropy register, as well as the JTAG shield. See Chapter 6, "Digital Control and On-Chip RAM," for more information. 1.2.16 Synchronous Serial Port (SSP) The i.MX23 SOC contains two integrated synchronous serial ports, SSPs. Each SSP supports a wide range of synchronous serial interfaces, including: * * * 1-bit, 4-bit, or 8-bit high-speed MMC/SD/SDIO Motorola (1-bit) and Winbond (1, 2 and 4-bit) SPI with up to 3 slave selects TI SSI Each SSP has a dedicated DMA channel and a dedicated clock divider from the PLL. See Chapter 21, "Synchronous Serial Ports (SSP)," for more information about these features. 1.2.17 I2C Interface The chip contains a two-wire SMB/I2C bus interface. It can act as a master on the SMB interface. The on-chip ROM supports boot operations from I2C EEPROMs. See Chapter 25, "I2C Interface," for more information. 1.2.18 General-Purpose Input/Output (GPIO) The i.MX23 contains 95 GPIO pins in the 169-pin package and 64 GPIO pins in the 128-pin package. Most digital pins (except for EMI pins) that are available for specific functions are also available as GPIO pins if they are not otherwise used in a particular application. See Chapter 37, "Pin Control and GPIO," for more information 1.2.19 Display Processing The i.MX23 display processing and output consists of four distinct modules as shown in Figure 1-5. These are: * * * * Pixel Processing Pipeline - dedicated AXI bus master. Display Controller (LCDIF) - dedicated AXI bus master. PAL/NTSC TV-Encoder - direct feed from LCDIF output 10-bit Video DAC for analog composite output - direct feed from TV-Encoder i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-19 Product Overview This allows for all post video-decode pixel processing to be handled in hardware with minimal CPU intervention. Multiple pixel formats and display configurations are also supported. 8 x Overlays RGB (S1) Video YUV (S0) PXP Block CSC + Scale Colorkey / Alpha-Blend Rotation TV-Out block LCDIF Block TVE NTSC/PAL Encoder (digital) BT.656 Display Out (RGB, System, BT.656) Video DAC (analog) To TV Out Pins To LCD Pins Figure 1-5. Display Processing Sub-System 1.2.19.1 * Display Controller / LCD Interface (LCDIF) The i.MX23 Display Controller (LCDIF) includes: AMBA AXI master mode allows for high-performance operation from external memory. This also includes an increase to a 128x32-bit internal latency buffer which features an under-flow recovery mechanism. Supports 24-bit full color parallel RGB (DOTCK) mode. Able to drive up to VGA (640x480) full color displays at refresh rates up to 60Hz. Supports full 24-bit system mode (8080/6080/VSYNC/WSYNC). Read-mode is not supported. * * i.MX23 Applications Processor Reference Manual, Rev. 1 1-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Product Overview * * ITU-R BT.656 compliant D1 digital video output mode with on-the-fly RGB to YCbCr color-space-conversion. This output also feeds the integrated TV-Encoder Supports wide variety of input and output formats allowing for conversion between input and output (e.g., RGB565 input to RGB888 output). Also supports packed pixel formats. See Chapter 18, "LCD Interface (LCDIF)," for more information. 1.2.19.2 Pixel Processing Pipeline (PXP) The PXP performs all necessary post display frame pre-processing in hardware with minimal memory overhead. In a video-centric system such as the i.MX23, this allows for the CPU to have maximum processing bandwidth for video-decode operation. The PXP operation and features can be described as follows: * The background image (e.g. decoded video frames) is read from external memory into separate Y/U/V buffers as 8x8 pixel macroblocks. These buffers are then fed into a color-space converter (e.g. YUV to RGB) followed by the scaling engine which utilizes an advanced bi-linear weighted scaling algorithm. The scaling operation is defined in terms of the output image (via programmable offsets and cropping registers). The output of the scaler is fed into yet another internal buffer called S0. If the background image is already in the RGB color-space it is assumed to be scaled appropriately for the required output format and can thus be read directly into the internal S0 buffer. In order to maintain efficient use of external memory, only the relevant (visible) portion of the background image is fetched. The scaled RGB image (in the internal S0 buffer) can be blended with up to eight programmable overlays. The co-ordinates of the overlays can once again be described in terms of the resultant output image. Each overlay can have a either a global programmable opacity or a per-pixel resolution if constructed with ARGB color-space. In addition to this, each overlay can have a relative priority level such that when constructing the output image, the PXP only fetches the visible overlay in the current 8x8 macroblock. The overlays are fetched into the internal S1 buffer. Alpha blending is performed on the S0 and S1 buffers to generate the blended output into the internal S3 buffer. Other operations such as BITBLT and color-keying can also be performed at this stage. The final stage of the PXP operation is the rotator which can perform flips and 90, 180 and 270 rotations. The rotator operates on the 8x8 pixel macroblocks in the S3 buffer to maximize external memory fetch efficiency. It writes 8x8 macroblocks to external memory in this final stage. * * It should be noted that the PXP supersedes all pixel operations of the DCP. See Chapter 17, "Pixel Pipeline (PXP)," for more information on the PXP. 1.2.19.3 PAL/NTSC TV-Encoder The PAL/NTSC TV-Encoder is part of the integrated TV-Out functionality of i.MX23. The encoder takes input directly from the LCDIF without intermediate memory access. In order to utilize the TV-Out path, the LCDIF must be configured to output the ITU-R BT.656/BT.601 D1 digital video stream mode. This stream is synchronized to the internal 108MHz clock of the TV-Encoder. After this point, the block i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-21 Product Overview encodes the stream into a format suitable for the Video DAC. Before being sent to the video DAC, the output of the TV-Encoder is passed through a pixel interpolating filter which helps to lessen the requirements for off-chip video filtering. See Chapter 19, "TV-Out NTSC/PAL Encoder." for more information on the TV-Encoder. 1.2.19.4 Video DAC The i.MX23 includes a fully integrated low-power 10-bit Video DAC which takes the direct output from the TV-Encoder to generate a compliant analog composite analog video signal (CVBS). Also supported are optional source termination and automatic jack detection (via interrupt) allowing the Video DAC to be enabled/disabled automatically. See Chapter 20, "Video DAC," for more information. 1.2.20 SPDIF Transmitter The i.MX23 includes a Sony-Philips Digital Interface Format (SPDIF) transmitter. It supports sample rates independently from the A/D and D/A sample rates so that all three can run simultaneously. The SPDIF has a dedicated DMA channel. The SPDIF has its own clock divider from the PLL. See Chapter 30, "SPDIF Transmitter," for more information. 1.2.21 Dual Serial Audio Interfaces The BGA169 package of the i.MX23 includes two serial audio interfaces (SAIF), each with three stereo pairs. The pin multiplexing scheme for i.MX23 allows a stereo transmitter on one device and a stereo receiver to be connected to external devices, either D/A and A/D converters or to a host processor, such as a cell phone or BlueTooth controller. See Chapter 31, "Serial Audio Interface (SAIF) (BGA169 Only)." 1.2.22 Timers and Rotary Decoder An automatic rotary decoder function is integrated into the chip. Two digital inputs are monitored to determine which is leading and by how much. In addition, the hardware automatically determines the period for rotary inputs. There are four timers to provide timer functionality based on different clock inputs. See Chapter 22, "Timers and Rotary Decoder," for more information. 1.2.23 UARTs Three UARTs, similar to a 16550 UART, are provided--two for application use and one for debug use. The application UARTs are a high-speed devices capable of running up to 3.25 Mbits per second with i.MX23 Applications Processor Reference Manual, Rev. 1 1-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Product Overview 16-byte receive and transmit FIFOs. The application UARTs supports DMA and flow control (CTS/RTS). The debug UART does not use DMA channels. See Chapter 26, "Application UART," and Chapter 27, "Debug UART," for more information. 1.2.24 Low-Resolution ADC, Touch-Screen Interface, and Temperature Sensor The LRADC provides 16 "physical" channels of 12-bit resolution analog-to-digital conversion. Only 8 "virtual" channels can be used at one time, but those 8 channels can be mapped to any of the 16 physical channels. Some physical channels have dedicated inputs: * * * * * * * * Channel 15--VDD5V Channel 14--Bandgap reference Channel 13--USB_DN Channel 12--USB_DP Channel 10 and 11--Reserved Channel 8 and 9--Internal temperature sensing Channel 7--Battery Channel 6--VDDIO The USB_DN/DP inputs can only be sampled with the LRADC in non-USB mode (see HW_USBPHY_CTRL_DATA_ON_LRADC). The remaining six channels are available for other uses and can be used for resistive button sense, touch-screens, or other analog input. Channels 0 and 1 have integrated current sources to drive external temperature monitor thermistors. Channels 2-5 have integrated drivers for resistive touch-screens. The LRADC provides typical performance of 12-bit no-missing-codes, 9-bit/~56dB SNR, and 1% absolute accuracy (limited by the bandgap reference). See Chapter 33, "Low-Resolution ADC and Touch-Screen Interface," for more information. 1.2.25 Pulse Width Modulator (PWM) Controller The i.MX23 contains five PWM output controllers that can be used in place of GPIO pins. Applications include LED and backlight brightness control. Independent output control of each phase allows 0, 1, or high impedance to be independently selected for the active and inactive phases. Individual outputs can be run in lock step with guaranteed non-overlapping portions for differential drive applications. See Chapter 24, "Pulse-Width Modulator (PWM) Controller," for more information. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 1-23 Product Overview 1.2.26 Real-Time Clock, Alarm, Watchdog, Persistent Bits The i.MX23 supports real-time clock, alarm clock, watchdog reset, persistent bits and millisecond counter. The RTC system can be powered from the battery 5 V supply. The clock sources for these functions are selectable between 32 kHz, 32.768 kHz or 24 MHz crystals. See Chapter 23, "Real-Time Clock, Alarm, Watchdog, Persistent Bits," for more information. i.MX23 Applications Processor Reference Manual, Rev. 1 1-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 2 Characteristics and Specifications This chapter describes the characteristics and specifications of the i.MX23 and includes sections on absolute maximum ratings, recommended operating conditions, and DC characteristics. 2.1 Absolute Maximum Ratings Table 2-1. Absolute Maximum Ratings Parameter Min Max Units C Storage Temperature -40 125 Battery Pin - BATT, VDD4P2V -0.3 4.242 V 5-Volt Source Pin - VDD5V (transient, t < 30ms, duty cycle < 0.05%) -0.3 7.00 V 5-Volt Source Pin - VDD5V (static) -0.3 6.00 V PSWITCH (Note 1) -0.3 VDDXTAL + 1.575 V Analog Supply Voltage--VDDA -0.3 2.10 V Speaker Amplifier Supply Voltage--VDDS -0.3 4.242 V Digital Core Supply Voltage --VDDD -0.3 1.575 V Non-EMI Digital I/O Supply--VDDIO -0.3 3.63 V EMI Digital I/O Supply--VDDIO.EMI -0.3 3.63 V DC-DC Converter--DCDC_BATT (Note 2) -0.3 BATT V Input Voltage on Any Digital I/O Pin Relative to Ground -0.3 VDDIO+0.3 V Input Voltage on USB_DP and USB_DN Pins Relative to Ground (Note 3) -0.3 3.63 V Input Voltage on Any Analog I/O Pin Relative to Ground -0.3 VDDA+0.3 V 1 VDDIO can be applied to PSWITCH through a 10 k resistor. This is necessary in order to enter the chip's firmware recovery mode. (The on-chip circuitry prevents the actual voltage on the pin from exceeding acceptable levels.) 2 Application should include a Schottky diode between BATT and VDD4P2. 3 USB_DN and USB_DP can tolerate 5V for up to 24 hours. Note that while 5V is applied to USB_DN or USB_DP, LRADC readings can be corrupted. Table 2-2. Electro-Static Discharge Immunity 169-Pin BGA & 128-Pin LQFP Packages Human Body Model (HBM) Charge Device Model (CDM) Tested Level 2 kV 500 V i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 2-1 Characteristics and Specifications 2.2 Recommended Operating Conditions Table 2-3. Recommended Power Supply Operating Conditions Parameter Min Typ Max Units Analog Core Supply Voltage--VDDA 1.62 2.10 V Digital Core Supply Voltage--VDDD 1.00 1.55 V Specification dependent on frequency. (Notes 1, 4) Non-EMI Digital I/O Supply Voltage--VDDIO 2.90 3.575 V EMI Digital I/O Supply Voltage--VDDIO.EMI 1.8 3.25 V Battery / DCDC Input Voltage - BATT, DCDC_BATT (Note 2) 2.6 4.242 V Speaker Supply Voltage - VDDS 2.7 4.242 V VDD5V Supply Voltage (5V current < 100 ma) 4.40 5.00 5.25 V VDD5V Supply Voltage (5V current >= 100 ma) 4.75 5.00 5.25 V Offstate Current (Note 3): * 32-kHz RTC off, BATT = 4.2 V 11 30 A * 32-kHz RTC on, BATT = 4.2 V 13.5 30 A 1 For optimum USB jitter performance, VDDD = 1.35 V or greater. 2 This requires software to program the RTC_PERSIST0_SPARE<31:28> bits. Minimum without the software programming is 2.9V 3 When the real-time clock is enabled, the chip consumes additional current when in the OFF state to keep the crystal oscillator and the real-time clock running. 4 VDDD supply minimum voltage includes 75 mV guardband. Table 2-4. Operating Temperature Conditions Parameter Commercial Ambient Operating Temperature Range, TA (Note 1, 2) Commercial Junction Temperature Range, TJ (Note 1, 2) Industrial Ambient Operating Temperature Range, TA (Note 1, 2) Industrial Junction Temperature Range, TJ (Note 1, 2) Package Thermal Impedance, 128-Pin LQFP, JA (Note 3) Package Thermal Impedance, 169-Pin BGA, JA (Note 3) 1 Min -10 -10 -40 -40 - Typ - Max 70 85 85 105 43 44 Units C C C C C/W C/W 2 * * * * * * * * * 3 In most systems designs, battery and display specifications will limit the operating range to well within these specifications. Most battery manufacturers recommend enabling battery charge only when the ambient temperature is between 0 and 40C. To ensure that battery charging does not occur outside the recommended temperature range, the player ambient temperature may be monitored by connecting a thermistor to the LRADC0 or LRADC1 pin on the i.MX23. Maximum Ambient Operating Temperature may be limited due to on-chip power dissipation. TA (MAX) <= TJ - ( JA x PD ) where: TJ = Maximum Junction Temperature JA = Package Thermal Impedance PD = Total On-chip Power Dissipation = PSpeakerAmp + PVDD4P2 + PBatteryCharger + PDCDC + PLinearRegulators +PInternal. Note that depending on the application, some of these power dissipation terms may not appliy. PSpeakerAmp = Speaker Amp On-Chip Power Dissipation = ~1W (regardless of output amplitude) PVDD4P2 = VDD4P2 On-Chip Power Dissipation = ( VDD5V - VDD4P2 ) x IDD4P2 PBatteryCharger = Battery Charger On-Chip Power Dissipation = (VDD5V - BATT ) x ICHARGE PDCDC = DC-DC Converter On-Chip Power Dissipation = (BATT x DCDC Input Current ) x (1 - efficiency) PLinearRegulators = Linear Regulator On-Chip Power Dissipation = (VDD5V-VDDIO) x (IDDIO + IDDM + IDDA + IDDD) + (VDDIO - VDDM) x IDDM + (VDDIO - VDDA) x (IDDA + IDDD) + (VDDA - VDDD) x IDDD PInternal = Internal Digital On-Chip Power Dissipation = ~VDDD x IDDD Assumes 4-layer PCB and still air. Actual thermal performance may vary based on board and enclosure composition and design. i.MX23 Applications Processor Reference Manual, Rev. 1 2-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Characteristics and Specifications Table 2-5. Recommended Analog Operating Conditions Parameter Min Typ Max Units Low Resolution ADC: * Input Impedance (CH0 - CH5) >1 M * Absolute Accuracy +/- 1.5 % On-Die Temperature Sensor: * Absolute Accuracy +/- 1.5 % Microphone: * Full-Scale Input Voltage (MIC_GAIN=40 dB) (Note 4, 5) 0.0052 0.0055 0.0057 Vrms * Input Resistance 75 100 125 k * Idle SNR (Note 8) 59 66 dB FS * THD+N at -3dBFS -53 -63 dB Line Inputs: * Full-Scale Input Voltage to ADC (Note 1, 4, 5) 0.52 0.54 0.56 Vrms * Full-Scale Input Voltage to HP with 0dB Gain (Note 1, 4) 0.52 0.59 0.61 Vrms * Input Resistance (Line-to-Headphone mode) (Note 2) 37.5 50 62.5 k * Input Resistance (Line-to-ADC mode) (Note 2) 14.1 18.75 23.4 k * LineIn-to-HP SNR Idle Channel (Note 2) 97 100 103 dB FS * ADC SNR Idle Channel (Note 2) 80 87 89 dB FS * ADC -60 dB Dynamic Range (Note 2) 80 87 89 dB FS * ADC THD+N at -3dBFS -73 -80 dB Headphone: 0.46 0.52 0.54 Vrms * Full-Scale Output Voltage (VDDA = 1.8 V, 16 load) (Note 6) * Output Resistance 0.1 0.3 0.5 * Crosstalk between Input Channels (16 load) (Note 7) -65 -70 dB -80 -84 dB * THD+N (16 load) (Note 7, 9) -83 -86 dB * THD+N (10 k load) (Note 7, 9) * DAC SNR Idle Channel (Note 2, 7, 8) 95 97 dB FS * DAC -60 dB Dynamic Range (Note 2, 7, 8) 95 97 dB FS * Output Frequency Response (20Hz - 20kHz, 1 kHz = 0dB) -1 +1 dB FS * Channel Balance (Level Difference between L-ch and R-ch) -0.2 0.04 0.2 dB Speaker Amplifier: 2.6 2.7 2.8 Vrms * Full-Scale Output Voltage (VDDS = 4.2 V, 8 load) * Output Offset Voltage 0 15 45 mV 0.85 0.9 1 W * Maximum Out Power (VDDS = 4.2 V, 8 load, 1% THD) * Maximum Out Power (VDDS = 3.0 V, 8 load, 1% THD) 0.425 0.45 0.55 W 1.6 1.75 1.9 W * Maximum Out Power (VDDS = 4.2 V, 4 load, 10% THD) 1.275 1.45 1.6 W * Maximum Out Power (VDDS = 4.2 V, 4 load, 1% THD) 0.6 0.7 0.8 W * Maximum Out Power (VDDS = 3.0 V, 4 load, 1% THD) 90 95 dB * SNR (VDDS = 4.2 V, A-Weighted, 8 load) 45 mV/ mA * Speaker VDDS Active Current (no signal) (Note 3) 1.3 + Ioffset * Speaker VDDS Leakage Current (VDDS=4.2V, Speaker = OFF) 0.1 0.6 uA -50 -55 dB * THD+N (4 load, -2dB signal) -55 -61 dB * THD+N (8 load, -2dB signal) * PSRR at 217-1000 Hz 60 75 dB 1 1 Vrms requires external resistor divider. 2 Measured "A weighted" over a 20-Hz to a 20-kHz bandwidth, relative to full scale output voltage (when VDDIO = 3.3 V and VDDA = 2.1 V). 3I offset = offset voltage/speaker impedance. 4 Maximum input that achieves -40dB THD+N 5 ADC gain = 0 dB i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 2-3 Characteristics and Specifications 6 7 Maximum output that achieves at least -66dB THD+N into 16 load Measured at -1dB FS, where fullscale achieves at least -66dB THD+N into a 16 load 8 SNR and Dynamic range measurements made in capless headphone mode with DCDC converters running and JTAG disconnected. 9 Applies for both LINE IN and DAC IN sources. 2.3 DC Characteristics Table 2-6. PSWITCH Input Characteristics Parameter HW_PWR_STS _PSWITCH 0x00 0x01 0x11 Min 0.00 0.65 2.1 Max 0.30 1.50 VDDXTAL + 1.575 Units V V V PSWITCH LOW LEVEL (See Note 3) PSWITCH MID LEVEL & STARTUP (See Note 1, 3) PSWITCH HIGH LEVEL (See Note 2, 3) 1 A MID LEVEL PSWITCH state can be generated by connecting the VDDXTAL output of the SOC to PSWITCH through a switch. 2 PSWITCH acts like a high impedance input (>300 k) when the voltage applied to it is less than 1.5V. However, above 1.5V it becomes lower impedance. To simplify design, it is recommended that a 10 k resistor to VDDIO be applied to PSWITCH to set the HIGH LEVEL state. 3 Consult the reference schematics for recommended PSWITCH button circuitry. Table 2-7. Power Supply Characteristics Parameter VDDXTAL Voltage Reference Output Voltage Linear Regulators Output Voltage Accuracy (VDDIO, VDDA, VDDM, VDDD) (See Note 1) VDDIO Maximum Output Current (VDDIO=3.325V, VDD5V=4.75V) (See Note 2, 8) VDDIO Maximum Output Current (VDDIO=3.325V, VDD5V=4.40V) (See Note 2, 8) VDDM Maximum Output Current (VDDM=2.5V, VDD5V=4.75V) (See Note 2, 8) VDDM Maximum Output Current (VDDM=2.5V, VDD5V=4.40V) (See Note 2, 8) VDDA Maximum Output Current (VDDA=1.8V, VDD5V=4.75V) (See Note 2, 8) VDDA Maximum Output Current (VDDA=1.8V, VDD5V=4.75V) (See Note 2, 8) VDDD Maximum Output Current (VDDD=1.2V, VDD5V=4.75V) (See Note 2, 8) VDDD Maximum Output Current (VDDD=1.2V, VDD5V=4.75V) (See Note 2, 8) VDDIO Output Impedance (See Note 9) VDDM Output Impedance (See Note 9) VDDA Output Impedance (See Note 9) VDDD Output Impedance (See Note 9) DCDC Converters Output Voltage Accuracy (DCDC_VDDIO, DCDC_VDDA, DCDC_VDDD) (See Note 1) DCDC Converters (3.0V < BATT < 4.242V) DCDC_VDDD Maximum Output Current (VDDD=1.55V) (See Note 3, 7) DCDC_VDDA Maximum Output Current (VDDA=1.8V) (See Note 3, 7) 1.0 V Min Typ Max Units Min Typ Max Units -1 240 175 240 230 235 225 260 245 115 335 105 175 +3 % mA mA mA mA mA mA mA mA m m m m Min Typ Max Units -1 +3 % Min Typ Max Units 250 200 mA mA i.MX23 Applications Processor Reference Manual, Rev. 1 2-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Characteristics and Specifications Table 2-7. Power Supply Characteristics (continued) DCDC_VDDIO Maximum Output Current (VDDIO=3.30V, VDDD=1.55V) (See Note 3, 4, 7) DCDC_VDDIO Maximum Output Current (VDDIO=3.20V, VDDD=1.55V) (See Note 3, 4, 7) DCDC_VDDIO Maximum Output Current (VDDIO=3.15V, VDDD=1.55V) (See Note 3, 4, 7) DCDC_VDDIO Maximum Output Current (VDDIO=3.15V, VDDD=1.375V) (See Note 3, 4, 7) DCDC Converters (3.3V < BATT < 4.242V) DCDC_VDDD Maximum Output Current (VDDD=1.55V, 3.3V < BATT < 4.242V) (See Note 3, 7) DCDC_VDDA Maximum Output Current (VDDA=1.8V, 3.3V < BATT < 4.242V) (See Note 3, 7) DCDC_VDDIO Maximum Output Current (VDDIO=3.30V, VDDD=1.55V) (See Note 3, 4, 7) DCDC_VDDIO Maximum Output Current (VDDIO=3.20V, VDDD=1.55V) (See Note 3, 4, 7) DCDC_VDDIO Maximum Output Current (VDDIO=3.15V, VDDD=1.55V) (See Note 3, 4, 7) DCDC_VDDIO Maximum Output Current (VDDIO=3.15V, VDDD=1.375V) (See Note 3, 4, 7) DCDC Converters (4.0V < BATT < 4.242V) DCDC_VDDIO Maximum Output Current (VDDIO=3.30V, VDDD=1.55V) (See Note 3, 4, 7) DCDC_VDDIO Maximum Output Current (VDDIO=3.20V, VDDD=1.55V) (See Note 3, 4, 7) DCDC_VDDIO Maximum Output Current (VDDIO=3.15V, VDDD=1.55V) (See Note 3, 4, 7) DCDC_VDDIO Maximum Output Current (VDDIO=3.15V, VDDD=1.375V) (See Note 3, 4, 7) VDD4P2 Regulated Output VDD4P2 Output Voltage Accuracy (TARGET=4.2V) (Note 1) VDD4P2 Maximum Output Current (VDD5V=5.00V, ILIMIT=780mA) (See Note 5) VDD4P2 Maximum Output Current (VDD5V=4.75V, ILIMIT=780mA) (See Note 5) VDD4P2 Maximum Output Current (VDD5V=4.40V, ILIMIT=780mA) (See Note 5) VDD4P2 Output Impedance (See Note 9) VDD4P2 Output Current Limit Accuracy (VDD5V=4.75V, ILIMIT=480mA) (See Note 6) VDD4P2 Output Current Limit Accuracy (VDD5V=4.75V, ILIMIT=100mA) (See Note 6) Battery Charger Final Charge Voltage Accuracy (TARGET=4.2V) 1 2 135 120 95 175 mA mA mA mA Min Typ Max Units 250 200 215 175 135 265 mA mA mA mA mA mA Min Typ Max Units 355 340 325 420 mA mA mA mA Min Typ Max Units -2 725 605 325 90 466 95 480 100 505 105 +1 % mA mA mA m mA mA Min Typ Max Units -2 +1 % No Load. Output regulated within 100 mV of target voltage. 3 DCDC Double FETs Enabled, Inductor Value = 15H. 4 Assumes simultaneous load of IDDD = 250 mA@1.55V and IDDA = 200 mA@1.8V. 5 Output regulated within 300 mV of target voltage. 6 Untuned. 7 The DCDC Converter is a triple output buck converter. The maximum output current capability of each output of the converter is dependent on the loads on the other two outputs. For a given output, it may be possible to achieve a maximum output current higher than that specificed by ensuring the load on the other outputs is well below the maximum. 8 Because the internal linear regulators are cascaded, it is not possible to simultaneously operate the VDDIO, VDDA, VDDM, and VDDD linear regulators at the maximum specified load current. For example, the VDDIO linear regulator provides current to both the VDDIO 3.3 V supply rail as well as the VDDM and VDDA linear regulator inputs. Likewise, the VDDA linear regulator provides current to both the 1.8 V supply rail as well as the VDDD linear regulator input. The application designer should ensure the following two conditions are met: * (VDDIO Load Current + VDDM Load Current + VDDA Load Current) < VDDIO Maximum Output Current * (VDDA Load Current + VDDD Load Current) < VDDA Maximum Output Current 9) The output impedance value is measured on a PCB evaluation board and includes the PCB trace impedance. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 2-5 Characteristics and Specifications Figure 2-1. DCDC Efficiency vs. Battery Voltage (VDDD=1.05V, Low VDDD Load) Figure 2-2. DCDC Efficiency vs. Battery Voltage (VDDD=1.28V, Medium VDDD Load) i.MX23 Applications Processor Reference Manual, Rev. 1 2-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Characteristics and Specifications Figure 2-3. DCDC Efficiency vs. Battery Voltage (VDDD=1.55V, High VDDD Load) Table 2-8. Non-EMI Digital Pin DC Characteristics VDDIO = 3.3 V Parameter Non-EMI Regular & High Drive I/O Input Voltage Non-EMI Regular & High Drive I/O Output Voltage Non-EMI Regular I/O Output Current (see notes 1 and 6 of Table 2-10) VIL VOH VOL IOH - 4mA IOH - 8mA IOH - 12mA IOL - 4mA IOL - 8mA IOL - 12mA Non-EMI High Drive I/O (PWM4) Output Current (see notes 2 and 6 of Table 2-10) IOH - 8mA IOH - 16mA IOH - 24mA IOL - 8mA IOL - 16mA IOL - 24mA External Pull-Up / Pull-Down Resistor Value Required to Overdrive Internal Gate Keeper Internal Pull-Up Resistor Accuracy -20 Name VIH Min 2.00 0.8 * VDDIO 3.60 7.20 10.80 -3.60 -7.20 -10.80 -6.50 -11.00 -16.80 -8.00 -14.50 -19.00 Max VDDIO 0.80 0.40 50 +20 Units V V V V mA mA mA mA mA mA mA mA mA mA mA mA k % i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 2-7 Characteristics and Specifications . Table 2-9. EMI Digital Pin DC Characteristics Unit V V V V mA mA mA mA mA mA mA mA VDDIO.EMI = 2.5 V Parameter EMI I/O Input Voltage EMI I/O Output Voltage EMI I/O Output Current (See notes 1 and 6 of Table 2-10) Name VIH VIL VOH VOL IOH - 4 mA IOH - 8 mA IOH - 12 mA (see note 3 of Table 2-10) IOH - 16 mA (see note 3 of Table 2-10) IOL - 4 mA IOL - 8 mA IOL - 12 mA (see note 3 of Table 2-10) IOL - 16 mA (see note 3 of Table 2-10) Min (VDDIO.EMI / 2) + 0.2 0.7 * VDDIO.EMI 3.00 6.00 Max VDDIO.EMI (VDDIO.EMI / 2) - 0.2 0.40 Min (VDDIO.EMI / 2) + 0.2 0.8 * VDDIO.EMI 3.00 5.00 VDDIO.EMI = 1.8 V Max VDDIO.EMI (VDDIO.EMI / 2) - 0.2 0.2 * VDDIO.EMI - 10.00 - 8.50 - 14.00 - 11.00 - -4.00 -8.00 - -3.50 -7.00 - -12.00 - -10.50 - -16.00 - -13.50 - Table 2-10. External Devices Supported by the EMI DRAM Device DDR mDDR 1 Max Load (see notes 4 and 5) 15 pF 15 pF Pad Voltage 2.5 V 1.8 V The stronger the driver mode, the noisier the on-chip power supply. The use of a stronger drive mode must be limited to only a few pins. The majority of GPIO drivers must be set in 4-mA mode. 2 High-drive I/O has a high current source/sink capability. However, it is not meant as high-speed I/O - the driver turns on slowly to reduce L*di/dt power supply noise. 3 The EMI I/O pad pre-drivers are powered from VDDIO rather than VDDIO.EMI. This causes the higher EMI I/O drive strengths at 2.5 V and 1.8 V to have a dependency on the VDDIO voltage. For 2.5 V and 1.8 V EMI I/O 12 mA & 16 mA drive strengths, VDDIO should equal 3.3 V or higher. i.MX23 Applications Processor Reference Manual, Rev. 1 2-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Characteristics and Specifications 4 5 Max load includes capacitive load due to PCB traces, pad capacitance and driver self-loading. Setting is for worst case. Freescale's EMI interface uses less powerful drivers than those typically used in mDDR devices. A possible transmission-line effect on the PC board must be suppressed by minimizing the trace length combined with Freescale's slower edge-rate drivers. The i.MX23 provides up to 16 mA programmable drive strength. However, the 16-mA mode is an experimental mode. With the 16-mA mode, the EMI function may be impaired by simultaneous switching output (SSO) noise. In general, the stronger the driver mode, the noisier the on-chip power supply. Freescale recommends not using a stronger driver mode than is required. Because on-chip power and ground noise is proportional to the inductance of its return path, users should make their best effort to reduce inductance between the EMI power and ground balls and the PC board power and ground planes. 6 IOH is the maximum output current at which the VOH specification is met. IOL is the maximum input current at which the VOL specification is met. 2.3.1 Recommended Operating Conditions for Specific Clock Targets NOTE At this time, all data is preliminary and subject to change without notice. Table 2-11. System Clocks Name clk_gpmi clk_ssp Min. Freq. (MHz) Max. Freq. (MHz) 102.858 102.858 51.429 Description General Purpose memory interface clock domain Internal SSP Interface clock. External SSP clock. External SSP Clock Table 2-12. Recommended Operating States - 169BGA Package HW_ HW_ HW_ EMICLK AHBCLK CPUCLK HW_ HW_ HW_ CLKCTRL / clk_emi CLKCTRL CLKCTRL / clk_h / clk_p DIGCTRL VDDD SUPPORTED CLKCTRL CLKCTRL Brown-out DRAM FRAC_ FRAC_ EMI_ Frequency Frequency ARMCACHE Frequency (V) HBUS_DIV CPU_DIV_CPU CPUFRC DIV_EMI EMIFRAC (MHz) (MHz) (MHz) (note 1) / PFD VDDD (V) 1.050 1.050 1.275 1.375 1.475 1.550 1.550 0.975 0.975 1.175 1.275 1.375 1.450 1.450 11 00 00 00 00 00 24.00 64.00 261.82 360.00 392.73 454.74 454.74 5 1 1 1 1 1 27 33 24 22 19 19 24.00 64.00 130.91 120.00 196.36 151.58 151.58 1 1 2 3 2 3 3 24.00 64.00 130.91 120.00 130.91 151.58 130.91 5 2 3 2 3 2 27 33 24 33 19 33 DDR, mDDR DDR, mDDR DDR, mDDR DDR, mDDR DDR, mDDR mDDR DDR i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 2-9 Characteristics and Specifications 1 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value. Table 2-13. Recommended Operating States - 128QFP Package HW_ HW_ HW_ EMICLK AHBCLK CPUCLK HW_ HW_ CLKCTRL HW_ / clk_emi CLKCTRL CLKCTRL / clk_h / clk_p DIGCTRL VDDD SUPPORTED CLKCTRL CLKCTRL Brown-out DRAM FRAC_ FRAC_ EMI_ Frequency Frequency ARMCACHE Frequency (V) HBUS_DIV CPU_DIV_CPU CPUFRC DIV_EMI EMIFRAC (MHz) (MHz) (MHz) (note 1) / PFD VDDD (V) 1.050 1.050 1.275 1.375 1.475 1.550 0.975 0.975 1.175 1.275 1.375 1.450 11 00 00 00 00 24.00 64.00 261.82 360.00 392.73 454.74 5 1 1 1 1 27 33 24 22 19 24.00 64.00 130.91 120.00 196.36 151.58 1 1 2 3 2 3 24.00 64.00 130.91 120.00 130.91 130.91 5 2 3 2 2 27 33 24 33 33 mDDR DDR, mDDR DDR, mDDR DDR, mDDR DDR, mDDR DDR, mDDR Table 2-14. Recommended Operating Conditions - CPU Clock (clk_p) Minimum VDDD (V) 1.050 1.225 1.375 1.450 1.550 1 Minimum VDDDBrown-out (V) 0.975 1.125 1.275 1.350 1.450 HW_DIGCTRL ARMCACHE (note 1) 11 00 00 00 00 HW_CLKCTRL CPUCLK / clk_p FRAC_CPUFRC / PFD Frequency max (MHz) 25 - 35 18 - 35 18 - 35 18 - 35 18 - 35 64.00 278.71 360.00 392.73 454.74 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value. Table 2-15. Recommended Operating Conditions - AHB Clock (clk_h) Minimum VDDD (V) 1.050 1.275 1.350 1.475 Minimum VDDDBrown-out (V) 0.975 1.175 1.250 1.375 HW_DIGCTRL ARMCACHE (note 1) 11 00 00 00 HW_CLKCTRL AHBCLK / clk_h FRAC_CPUFRC / PFD Frequency max (MHz) 25 - 35 18 - 35 18 - 35 18 - 35 64.00 130.91 160.00 196.36 205.71 1.525 1.425 00 18 - 35 1 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value. Table 2-16. Frequency vs. Voltage for EMICLK - 169-Pin BGA Package Minimum VDDD (V) 1.55 Minimum VDDDBrownout (V) 1.45 EMICLK Fmax (MHz) DDR (note 1) 130.91 mDDR (note 2) 151.58 i.MX23 Applications Processor Reference Manual, Rev. 1 2-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Characteristics and Specifications Table 2-16. Frequency vs. Voltage for EMICLK - 169-Pin BGA Package (continued) Minimum VDDD (V) 1.45 1.30 1.20 1.05 Minimum VDDDBrownout (V) 1.35 1.20 1.10 0.975 EMICLK Fmax (MHz) DDR (note 1) 130.91 130.91 130.91 96.00 mDDR (note 2) 151.58 151.58 151.58 96.00 1) DDR EMICLK maximum is valid for the following conditions: Temp 105, 2.4V VDDM 2.5V, 3.2V VDDIO 3.3V, Drive Table 2-17. Frequency vs. Voltage for EMICLK - 128-Pin LQFP Package Minimum VDDD (V) 1.55 1.45 1.30 1.20 1.05 Minimum VDDDBrownout (V) 1.45 1.35 1.20 1.10 0.975 EMICLK Fmax (MHz) DDR (note 1) 130.91 130.91 130.91 130.91 96.00 mDDR (note 2) 130.91 130.91 130.91 130.91 96.00 strength 12mA 2) mDDR EMICLK maximum is valid for the following conditions: Temp Drive strength 12mA 105, 1.7V VDDA 1.9V, 3.2V VDDIO 3.3V, i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 2-11 Characteristics and Specifications 2.4 2.4.1 AC Characteristics EMI Electrical Specifications tCK (T) PAD_EMI_CLK PAD_EMI_A*/CMD ADDR/CMD CAS Latency tCK (T) PAD_EMI_DQS* tDIS tDIH tDIS tDIH PAD_EMI_D* DATA DATA DATA Assumptions ========== VDDD PVT : 1.08V, SS, 125C Junction VDDA IO PVT : 1.62V, SS, 125C Junction (1.8V setting, but WCS IO voltage) IO Drive Strength = 4mA, Cap Load = 15pF on all pins DQS has pull-downs on board (never goes high-Z), but DQ has keepers disabled. DQS In Delay chain setting = 4 taps WCS, 13 taps BCS (approx 1/4 cycle, ie approx 0x20) Note that the SoC creates an internal delay on the DQS relative to DQ, so data launched from the DRAM on the rising edge of the DQS will set-up to the rising edge of the DQS, and will hold to the previous edge. Legend ====== tDIS = Data Input Max Setup Time relative to DQS = 0.25T - 0.85 (e.g. at 151.58MHz, tDQSQ cannot exceed 0.25*(1000/151.58) - 0.85 = 0.8ns) tDIH = Data Input Minimum Hold Time relative to DQS = 0.25T + 0.75 (e.g. at 151.58MHz, tQH must be at least 0.25*(1000/151.58) + 0.75 = 2.4ns) Figure 2-4. i.MX23 EMI mDDR DRAM Input AC Timing i.MX23 Applications Processor Reference Manual, Rev. 1 2-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Characteristics and Specifications tCH tCK (T) tCL PAD_EMI_CLK tOS tOH PAD_EMI_A*/CMD ADDR/CMD tDQSS tCK (T) PAD_EMI_DQS* tDOH tDOS PAD_EMI_D* DATA DATA DATA DATA Assumptions ========== VDDD PVT : 1.08V, SS, 125C Junction (unless otherwise noted) VDDA IO PVT : 1.62V, SS, 125C Junction (1.8V setting, but WCS IO voltage) IO Drive Strength = 4mA, Cap Load = 15pF on all pins DQS has pull-downs on board (never goes high-Z), but DQ has keepers disabled. DQS Out Delay chain setting = 0 DQS Write Clock Delay chain setting = 5 taps (approx 1/4 cycle, ie approximately 0x20) Clock Delay line setting = 5 (this also works at BCS PVT and gives best CK/DQS skew) Legend ====== tCK = T = DRAM Clock Cycle Time = @ VDDD=1.55V 6.6ns (min), @ VDDD=1V 7.639ns (min) tCH = DRAM Clock High Pulse = T/2 to T/2 - 0.37ns tCL = DRAM Clock Low Pulse = T/2 to T/2 + 0.37ns tOS = Addr/Cmd output setup to CK rising = T/2 - 0.96ns (min) tOH = Addr/Cmd output hold to CK rising = T/2 - 1.51ns (min) tDQSS = Write command valid to first DQS latching transition = T to T+0.1 tDOS = DQ to DQS setup time = T/4 - 0.485ns (min) tDOH = DQ to DQS hold time = T/4 - 0.365ns (min) Figure 2-5. i.MX23 EMI mDDR DRAM Output AC Timing i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 2-13 Characteristics and Specifications 2.4.2 I2C Electrical Specifications Figure 2-6 depicts the timing for the I2C module. Table 2-18 lists the I2C module timing parameters. I2DAT IC10 IC11 IC9 I2CLK IC2 IC8 IC4 IC7 IC3 START IC10 IC6 IC1 IC5 IC11 START STOP START Figure 2-6. I2C Bus Timing Diagram Table 2-18. I2C Timing Parameters ID Parameter I2C Input Timing IC1 I2CLK cycle time a Min Max Unit 8 1 1 1 4 4 1 1 4 - clk_x cycles clk_x cycles clk_x cycles clk_x cycles clk_x cycles clk_x cycles clk_x cycles clk_x cycles clk_x cycles IC2 Hold time (repeated) START condition IC3 Set-up time for STOP condition IC4 Data hold time IC5 HIGH Period of I2CLK Clock IC6 LOW Period of the I2CLK Clock IC7 Set-up time for a repeated START condition IC8 Data set-up time IC9 Bus free time between a STOP and START condition I2C Output Timing IC1 I2CLK cycle time b high_count + low_count + 6 leadin_count rcv_count + 6 xmit_count high_count low_count bus_free + 7 low_count - xmit_count bus_free + 7 - rcv_count 0.15*Cb 0.17*Cb clk_x cycles clk_x cycles clk_x cycles clk_x cycles clk_x cycles clk_x cycles clk_x cycles clk_x cycles clk_x cycles ns IC2 Hold time (repeated) START condition IC3 Set-up time for STOP condition IC4 Data hold time IC5 HIGH Period of I2CLK Clock IC6 LOW Period of the I2CLK Clock IC7 Set-up time for a repeated START condition IC8 Data set-up time IC9 Bus free time between a STOP and START condition IC10 Rise time of both I2DAT and I2CLK signals i.MX23 Applications Processor Reference Manual, Rev. 1 2-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Characteristics and Specifications Table 2-18. I2C Timing Parameters (continued) ID Parameter Min 0.16*Cb 5 Max 0.17*Cb 100 Unit ns pF IC11 Fall time of both I2DAT and I2CLK signals IC12 Capacitive load for each bus line (Cb) a b c The clk_x period is programmed as a divide with respect to the xtal clock. The divide value can be >= 1. All I2C output timings are determined by PIO register values. These values are multiplied by the programmable clk_x period. c Cb = total capacitance of one bus line in pF. 2.4.3 LCD AC Output Electrical Specifications Figure 2-7 depicts the AC output timing for the LCD module. Table 2-19 lists the LCD module timing parameters. T PAD_LCD_DOTCK Falling edge capture tSF tHF PAD_LCD_DOTCK Rising edge capture tSR tHR tDW PAD_LCD_D[17:0], PAD_LCD_VSYNC, etc DATA/CTRL Notes: T = LCD interface clock period I/O Drive Strength = 4mA I/O Voltage = 3.3V Cck = Capacitance load on DOTCK pad Cd = Capacitance load on DATA/CTRL pad Figure 2-7. LCD AC Output Timing Digram Table 2-19. LCD AC Output Timing Parameters ID tSF tHF tSR tHR tDW Parameter Data setup for falling edge Data hold for falling edge Data setup for rising edge Data hold for rising edge Data valid window DOTCK = T/2 - 1.97ns + 0.15*Cck - 0.19*Cd DOTCK = T/2 + 0.29ns + 0.09*Cd - 0.10*Cck DOTCK = T/2 - 2.09ns + 0.18*Cck - 0.19*Cd DOTCK = T/2 + 0.40ns + 0.09*Cd - 0.10*Cck tDW = T - 1.45ns i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 2-15 Characteristics and Specifications i.MX23 Applications Processor Reference Manual, Rev. 1 2-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 3 ARM CPU Complex This chapter describes the ARM CPU included on the i.MX23 and includes sections on the processor core, the JTAG debugger, and the embedded trace macrocell (ETM) interface. 3.1 ARM 926 Processor Core The on-chip Reduced Instruction Set Computer (RISC) processor core is an ARM, Ltd. 926EJ-S. This CPU implements the ARM v5TE instruction set architecture, which includes enhanced DSP instructions. The ARM9EJ-S has two instruction sets: a 32-bit instruction set used in the ARM state and a 16-bit instruction set used in Thumb state. The core offers the choice of running in the ARM state or the Thumb state or a mix of the two. This enables optimization for both code density and performance. A block diagram of the ARM926EJ-S core is shown in Figure 3-1. See http://www.arm.com/documentation/ARMProcessor_Cores/index.html to download the following ARM documentation on the ARM926EJ-S core: * * ARM926EJ-S Technical Reference Manual, DDI0198D ARM926EJ-S Development Chip Reference Manual, DDI0287A The ARM9 core has a total of 37 programmer-visible registers, including 31 general-purpose 32-bit registers, six 32-bit status registers, and a 32-bit program counter, as shown in Figure 3-2. In ARM state, 16 general-purpose registers and one or two status registers are accessible at any one time. In privileged modes, mode-specific banked registers become available. The ARM state register set contains 16 directly addressable registers, r0 through r15. An additional register, the current program status register (CPSR), contains condition code flags and the current mode bits. Registers r0-r13 are general-purpose registers used to hold data and address values, with R13 being used as a stack pointer. R14 is used as the subroutine link register (lr) to hold the return address. Register r15 holds the program counter (PC). The Thumb state register set is a subset of the ARM register set. The programmer has access to eight general-purpose registers, r0-r7, the PC (ARM r15), the stack pointer (ARM r13), the link register (ARM r14), and the cpsr. Exceptions arise whenever the normal flow of program execution has to be temporarily suspended, for example, to service an interrupt from a peripheral. Before attempting to handle an exception, the ARM i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3-1 ARM CPU Complex core preserves the current processor state, so that the original program can resume when the handler is finished. Unused Unused ARM926EJ-S Instruction TCM Interface Embedded Trace Macrocell (ETM) Interface Data TCM Interface Instruction Cache (16 Kbytes) ARM9EJ-S Core Data Cache (16 Kbytes) MMU MMU Write Buffer Control Logic and Bus Interface Unit Interrupts VINITHI AMBA AHB Interface Integrated Coprocessor AMBA AHB Interface AHB1 IRQ FIQ AHB2 Figure 3-1. ARM926 RISC Processor Core The following exceptions are recognized by the core: * * * * * * * * SWI--Software interrupt UNDEF--Undefined instruction PABT--Instruction prefetch abort FIQ--Fast peripheral interrupt IRQ--Normal peripheral interrupt DABT--Data abort RESET--Reset BKPT--Breakpoint The vector table pointing to these interrupts can be located at physical address 0x00000000 or 0xFFFF0000. The i.MX23 maps its 64-Kbyte on-chip ROM to the address 0xFFFF0000 to 0xFFFFFFFF. The core is hardwired to use the high address vector table at hard reset (core port VINITHI =1). i.MX23 Applications Processor Reference Manual, Rev. 1 3-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor ARM CPU Complex The ARM 926 core includes a 16-Kbyte instruction cache and 16-Kbyte data cache and has two master interfaces to the AMBA AHB, as shown in Figure 3-1. The i.MX23 always operates in little-endian mode. Thumb mode low registers r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr USER FIQ spsr IRQ spsr ABORT spsr SVC spsr undef r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) Thumb mode high registers Figure 3-2. ARM Programmable Registers 3.2 JTAG Debugger The TAP controller of the ARM core in the i.MX23 performs the standard debugger instructions. 3.2.1 JTAG READ ID The TAP controller returns the following 32-bit data value in response to a JTAG READ ID instruction: 0x0792_64F3 3.2.2 JTAG Hardware Reset The JTAG reset instruction can be accomplished by writing 0xDEADC0DE to ETM address 0x70. The ETM is on scan chain 6. The bitstream is 0xF0DEADC0DE. The digital wide reset does not affect the DC-DC converters or the contents of the persistent registers in the analog side of the RTC. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3-3 ARM CPU Complex 3.2.3 JTAG Interaction with CPUCLK Because the JTAG clock is sampled from the processor clock CPUCLK, there are cases in which the behavior of CPUCLK affects the ability to make use of JTAG. Specifically, the JTAG block will not function as expected if: * * * CPUCLK is stalled due to an interrupt CPUCLK is less than 3x the JTAG clock CPUCLK is disabled for any reason 3.3 Embedded Trace Macrocell (ETM) Interface (169BGA-only) The i.MX23 includes a stand-alone ARM CoreSight Embedded Trace Macrocell, ETM9CSSingle, which provides instruction trace and data trace for the ARM9 microprocessor. For more details see the CoreSight ETM9 Technical Reference Manual. Also, see the pin list in Chapter 36, "Pin Descriptions," for pinout information. i.MX23 Applications Processor Reference Manual, Rev. 1 3-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 4 Clock Generation and Control 4.1 Overview The clock control module, or CLKCTRL, generates the clock domains for all components in the i.MX23 system. The crystal clock or PLL clock are the two fundamental sources used to produce all the clock domains. For lower performance and reduced power consumption, the crystal clock is selected. The PLL is selected for higher performance requirements but requires increased power consumption. In most cases, when the PLL is used as the source, a phase fractional divider (PFD) can be programmed to reduce the PLL clock frequency by up to a factor of 2. The PLL and PFD clocks are used as reference clock sources to drive digital clock dividers in the clock control module. These reference clocks, or ref_ 4.2 Clock Structure The reference clocks are used in CLKCTRL as fundamental clock sources to produce clock domains throughout the system. A reference clock can be either the crystal clock, 480Mhz PLL, or PFD output from the analog module. The selected reference clock is used by a digital clock divider to produce the desired clock domain. The table below summarizes all available reference clocks used within the CLKCTRL and all clock domains used in the system. The diagram that follows depicts all clock domains and how they are connected within the CLKCTRL module. This should provide a reference for how clocks are generated within the i.MX23 system. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-1 Clock Generation and Control 4.2.1 Table of System Clocks Table 4-1. System Clocks Table 4-1 summarizes the clocks produced by the clock control module. NAME REFERENCE DIVIDE /FREQ 1 9 phase 9 phase 9 phase 9 phase 9 phase 1 10/6 bits 5 bits 6/6 bits 4/6 bits DESCRIPTION Reference Clocks. ref_xtal ref_cpu ref_emi ref_io ref_pix ref_vid ref_pll clk_p clk_h clk_etm clk_emi xtal_24m /ring_24m PLL PLL PLL PLL PLL PLL ref_xtal /ref_cpu clk_p ref_xtal /ref_cpu ref_xtal /ref_emi /ref_cpu ref_xtal /ref_io ref_xtal /ref_io ref_io /clk_irov ref_xtal /ref_io ref_xtal /ref_pix ref_xtal /ref_pll ref_xtal ref_xtal ref_xtal ref_xtal32k /ref_xtal DDA DDA This is the muxed select between the internal ring oscillator and the external crystal. The 9 phase fractional divider output used as the reference for the CPU clock divider. The 9 phase fractional divider output used as the reference for the EMI clock divider. The 9 phase fractional divider output used as the reference for the GPMI, SSP, and IR clock dividers. The 9 phase fractional divider output used as the reference for the PIX clock divider. The 9 phase fractional divider output used as the reference for the clk_tv108m clock divider. This is the raw PLL output used as the reference for the SAIF clock divider. ARM core clock. AHB/APBH clock domain. clk_h is a gated branch of the clk_p domain. ARM etm clock. External DDR interface clock. Divided clock domains referenced from PLL or Xtal clock. clk_ssp clk_gpmi clk_irov/ir clk_spdif /clk_pcmspdif clk_pix clk_saif 8 bits 8 bits 9/10 bits SSP interface clock. General purpose memory interface clock domain. Over sample IR clock and IR data bit clock. The IROV clock has the ref_io as its reference. The IR clock domain uses the clk_irov domain as its reference. Clk_spdif is an intermediate clock that drives the clk_pcmspdif fractional clock divider. External display interface clock. Its reference is the xtal or fractional divider output that drives a DDA fractional divider. Serial Audio Interface clock domain. Its reference is the PLL clock output which drives a DDA fractional divider. APBX clock domain. UART clock domain. Used for the DRI, filter, and analog 24Mhz clock domains. Fixed 32khz clock domain. The reference is either the 32kHz crystal or the 24Mhz crystal and divides by 768 to produce 32kHhz. Divided clock domains referenced from Xtal clock. clk_x clk_uart clk_xtal24m clk_32k 10 bits 2 bits 24Mhz 32khz Fixed clock domains. i.MX23 Applications Processor Reference Manual, Rev. 1 4-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control Table 4-1. System Clocks (continued) NAME clk_adc clk_tv108m_ng clk_tv54m clk_tv27m clk_tvenc_fifo REFERENCE ref_xtal ref_vid int_108m int_108m Int_108m DIVIDE /FREQ 2khz 108Mhz 54Mhz 27Mhz Fixed 2khz clock domain. Fixed 108Mhz clk domain. Fixed 54Mhz clk domain. The reference is a gated clock on the internal fixed 108Mhz clock. Fixed 27Mhz clk domain. The reference is a gated clock on the internal fixed 108Mhz clock. DESCRIPTION 54Mhz/27Mhz Selectable between 54MHz and 27MHz with control bit from tvenc block. The reference is a gated clock on the internal fixed 108Mhz clock. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-3 Clock Generation and Control 4.2.2 Logical Diagram of Clock Domains ref_xtal 6 bit ICG Int/Frac HW_CLKCTRL_ETM CLK_ETM via OCROM Controller H/W Dynamic Power Adjust HW_CLKCTRL_HBUS EN1 EN2 ICG 5 bit 1 to 31 ICG CLK_OCROM CLK_H HW_CLKCTRL_CPU & INTERRUPT WAIT circuit) Multi-Output PLL Each output configurable for frequency and bypass. ------------------------------------- HW_CLKCTRL_HBUS HW_CLKCTRL_CPU 6 bit HW_CLKCTRL_EMI 6 bit Int ref_xtal PLL ICG ICG ICG ICG ICG Phase Div Phase Div Phase Div Phase Div Phase Div PLL 480M ref_cpu ref_emi ref_io ref_pix ref_vid ref_pll ICG CLK_P CLK_P_NG ICG Int/Frac HW_CLKCTRL_CPU 10 bit HW_CLKCTRL_EMI 4 bit CLK_EMI 6 bit Int ref_xtal Int HW_CLKCTRL_EMI HW_CLKCTRL_EMI_SYNC_MODE_EN ICG 4 bit ref_xtal 9 bit Int/Frac HW_CLKCTRL_SSP ICG CLK_SSP ref_xtal ref_io ref_xtal ICG 10 bit Int/Frac CLK_GPMI HW_CLKCTRL_GPMI 9 bit ICG 4 to 260 HW_CLKCTRL_IR or via IR H/W if AUTO_DIV = 1 CLK_IROV CLK_IR 10 bit 5 to 768 HW_CLKCTRL_IR or via IR H/W if 12 bit AUTO_DIV = 1 ref_xtal ICG Int CLK_PIX HW_CLKCTRL_PIX CLK_TV108M_NG ICG CLK_TV108M 4 Fixed Divider ICG CLK_TV54M ICG CLK_TV27M ICG CLK_TVENC_FIFO ref_xtal HW_CLKCNTL_SPDIF 16 bit ICG Frac HW_CLKCTRL_SAIF CLK_SAIF CLK_PCMSPDIF ICG HW_CLKCTRL_PLLCTRL0 4 Fixed Divider 9 bit Frac via HW_SPDIF_SRR Crystal Clock XTAL_CLK24M 24.000 MHz Ring Oscillator RING_CLK24M 24.000 MHz UTMI_CLK480M CLK_VDAC 0 gl 1 ref_xtal HW_POWER_M INPWR ICG CLK_UART ICG CLK_FILT24M ICG CLK_PWM24M HW_CLKCTRL_XTAL (4 Clock Gate control bits) ICG CLK_DRI24M HW_CLKCNTL_XTAL ICG 750 Fixed Divider CLK_32K CLK_ADC CLK_X CLK_ANA24M 16 Fixed Divider 10 bit 1 to 1023 HW_CLKCTRL_XBUS Crystal Clock XTAL_CLK32K 32.768 kHz / 32.0 kHz HW_CLKCNTL_XTAL ICG 768 Fixed Divider HW_RTC_PERSISTENT0_CLKSOURCE Analog Digital - Xtal Only Digital - Xtal or PLL Digital - PLL Only Legend CLK_RTC32K Unless otherwise shown, all multiplexers are controlled via HW_CLKCTRL_CLKSEQ Within CLKCNTL Figure 4-1. Logical Diagram of Clock Domains i.MX23 Applications Processor Reference Manual, Rev. 1 4-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control 4.2.3 Clock Domain Description All major functional clock domains/branches have trunk level clock gating for power management. The intent is to gate clock domains off when modules for certain applications are not necessary. This clock gating is instantiated using an ICG element from the standard cell library. Software will have to enable the clock domain that drives on chip devices where trunk level clock gating is implemented. The location of ICG elements to gate clock domains is not systematic. Since most of the clock structures throughout the system are unique, the location of ICGs for clock tree power reduction differs from one domain to the next. The location of these ICGs to gate off clock domains is apparent in the clock structure diagram. All clock domains are asynchronous unless noted otherwise. 4.2.3.1 CLK_P, CLK_H The clk_p domain is the used to drive the integrated ARM9 core. The reference for clk_p can be either ref_xtal or ref_cpu. The reference ref_cpu drives a 6 bit clock divider to provide a maximum divide down of the reference clock by 2^6. The reference ref_xtal drives a 10 bit clock divider to provide a maximum divide down of the selected reference clock by 2^10. All of the ARM core and SoC components on the clk_h branch are considered to be on the clk_p domain. clk_h is actually a branch of the clk_p domain. So, clk_h runs synchronous to clk_p. The clk_h domain can be programmed to any divided ratio with respect to the clk_p domain depending on performance and power requirements. A dynamic clock frequency management controller monitors system performance requirements and scales the clk_h frequency to meet performance needs. When the CPU or support components require data transfer to/from system memory, the frequency manager scales the clk_h domain to meet the system performance requirements. Also, when the system is quiesed, the clk_h frequency is reduced to save power. Clk_h has a 5 bit divider that divides the clk_p domain to produce the clk_h domain. The frequency for clk_h can be clk_p/32 <= clk_h <= clk_p. Two divide modes exist for the clk_h branch: * * Integer divide. In this mode, the value programmed in the hw_clkctrl_hbusclkctrl.div field represents an integer divide value. Fractional divide. In this mode, the value programmed in the hw_clkctrl_hbusclkctrl.div field represents a binary fraction. When the accumulation of the current count and the programmed divide value carry out of the most significant bit, a clk_h pulse is generated. For example, to achieve an 8:3 clk_p:clk_h clock ratio, set the div field to 0.01100 which represents (0*1/2) + (1*1/4) + (1*1/8) + (0*1/16) + (0*1/32). Note, fractional divide can not be used when clk_emi is synchronous with clk_h. The clk_h branch can be further divided by the dynamic clock frequency adjustment logic, (hw_clkctrl_emi_sync_mode_en = 0 only). When all the system clk_h components are not busy and their respective busy signals are inactive, the clk_h branch is further divided down by the value in the i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-5 Clock Generation and Control hw_clkctrl_hbusclkctrl register. The frequency reduction of the clk_h branch saves overall power consumption. Note, the dynamic clock frequency adjustment logic should not be enabled when clk_emi is synchronous with clk_h. 4.2.3.2 CLK_EMI The external memory interface domain is called clk_emi. This clock can be asynchronous to clk_h to achieve the highest possible clock rate for the EMI interface, or synchronously to minimize the incurred latency for CPU access to external DRAM. This option is provided to tradeoff the optimization of performace for systems that are dependent on memory access latency or throughput. When the hw_clkctrl_emi_sync_mode_en bit is set to 1, clk_h is synchronous and edge aligned with the emi clock and clk_p. The emi clock dividers will set the frequency of clk_h and clk_emi domains when synchronous mode is selected. In synchronous mode, the dynamic clock frequency adjust logic should be disabled. This is required since DRAM devices cannot operate correctly with changing clock frequencies. 4.2.3.3 System Clocks All reference clock domains used in the CLKCTRL are driven by replicated instances of the PFD pre dividers in the analog module. These PFD reference clocks drive replicated instances of a single digital clock divider design to create all system clocks. The following sections describe the digital clock dividers features and how they can be used to create clocks throughout the system. The CLKCTRL structural diagram should be used with the digital clock divider description to understand how clocks are generated in the i.MX23 system. 4.3 CLKCTRL Digital Clock Divider The digital clock divider that is used to drive all functional clock domains has three modes of operation. These are: * * * integer divide mode fractional divide mode gated clock divide mode These modes are described in the following three sections. 4.3.1 Integer Clock Divide Mode Each divider has the capability to divide an input reference frequency by a fixed integer value. This is the most common mode that will be used to select a particular clock frequency. For a desired clock frequency, first try to select a PFD reference clock frequency AND an integer clock divide value to achieve the desired clock domain frequency. This mode is selected when the respective "frac_en" field in the clock control register is logic 0. The divide value will be in the range of 1 to 2^N. When programming i.MX23 Applications Processor Reference Manual, Rev. 1 4-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control the DIV field to 1, the reference clock for the domain is passed and the clock domain assumes the same frequency as the reference domain. When a value of 2 is programmed, the clock domain frequency will be half the reference clock frequency. The maximum divide value depends on the number of bits each digital clock divider implements. This is different for each digital clock divider. The number of bits implemented for each divider is indicated by each DIV field that controls each clock domain. Divide by zero is NOT a valid programming value for the DIV field of any clock control PIO register. 4.3.2 Fractional Clock Divide Mode This mode is used to divide a reference clock in the range of 2 < div < 2^N. The fractional clock divider in the CLKCTRL module implements a fractional counter to approximate a divided clock with respect to the selected reference frequency. The accuracy of the output clock is dependent on the extent of the bits used to implement the fractional counter. The reference clock frequency and the fractional divide value must both be selected to achieve the desired output frequency. This mode is enabled when setting the FRAC_EN field of the respective clock domain control register to logic 1 AND the most significant bit of the DIV field is logic 0. Do NOT use this mode to divide the reference clock domain by an integer value (such as 4, 8, etc). Use the integer divide mode to achieve the best results for dividing by an integer. NOTE It is important to note that the nearest rising or falling edge of the input reference clock frequency is used to approximate the rising edge of the output clock domain. So, the output clock frequency will jitter based on the input reference clock frequency and the programmed fractional divide value. 4.3.2.1 Fractional Clock Divide Example, Divide by 3.5 As an example, if the desired divide value is 3.5, the digital approximation of 1/3.5 is 0.01001001 using an 8 bit fractional approximation. The most significant bit of the "div" field in this case is logic 0, so the fractional divide mode is selected. The following sequence indicates the first 8 values of the fractional clock divider. Notice the accumulated count is simply the current value incremented by the value programmed in the "div" field on each cycle. 1. 0.01001001 2. 0.10010010 3. 0.11011011 4. 1.00100100 (carry out of MSB initiates an output clock edge) 5. 0.01101101 6. 0.10110110 7. 0.11111111 8. 1.01001000 (output edge initiated) i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-7 Clock Generation and Control When the carry out of the fractional count is one, a rising edge output pulse is initiated and the remainder of the accumulator is preserved. The sub fractional accumulated value is considered to determine if the output edge should occur on the falling edge of the reference clock or the rising edge of the reference clock to minimize output clock jitter 4.3.2.1.1 Fractional ClockDivide Example, Divide by 3/8 This example uses a 3 bit fractional accumulator to divide the reference clock input by 3/8. There are 3 output clock edges produced for every 8 input reference clock edges. An output edge is generated on every cycle that the fractional accumulator carries out of the most significant bit. Notice when the fractional component is .01, the output edge is shifted and generated off the falling edge of the input reference clock. This is done to produce the best output duty cycle that can be achieved based on the input reference clock frequency. 3 output clocks repeats every 8 reference clocks CLK_REF 3 bit divider CLK_OUT 2nd cycle on falling clk_ref 1/2 cycle shift 0.000 0.011 0.110 1.001 0.100 0.111 1.010 0.101 1.000 0.011 Figure 4-2. Fractional Clock divide; 3/8 example 4.3.3 Gated Clock Divide Mode This mode is selected when the reference clock frequency is divided by a range of 1 < div < 2. To select this mode, program the FRAC_EN field to logic 1 and progarm the DIV field with the most significant bit set to logic 1. In this case, the reference clock is enabled/disabled on a cycle by cycle basis to pass to the output clock domain. Essentially, the reference clock is gated on or off depending on the cary out bit of the fractional count accumulator. This option is useful to divide the 24 MHz clock to a range between 12 to 24 MHz. The effective period is equal to the reference period since the output clock is a gated version of the reference clock. For example, a divide value of 4/3 will allow 3 consecutive pulses of the reference clock to propagate and will then gate off a single reference clock cycle. The edge to edge timing is effectively equal to the reference clock. i.MX23 Applications Processor Reference Manual, Rev. 1 4-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control Output clock period equal to reference clock. CLK_REF CLK_OUT 3 output clocks for every 4 reference clocks. Figure 4-3. Divide Range 1 < div < 2 4.4 Clock Frequency Management Clock frequency selection for some domains can be a function of multiple reference clock sources and divide parameters that are set in the CLKCTRL PIO control registers. The most extreme case is using a programmable fractional PLL clock divider, a multiplexer that selects either the xtal clock or fractional PLL clock as a source to drive the CLKCTRL divider, and the divide value for the CLKCTRL divider itself. When programming a selected frequency, the sequence of events to achieve a given frequency must maintain the integrity of the system as a whole. During a clock system context switch, intermediate clock frequencies for selected domains cannot be faster than the sub system or I/O interface is designed to support. It is expected that the sequence of events when a clock domain is tuned to a desired frequency be managed by software using a hardware status polling mechanism. Each parameter has an associated enable bit so that all the divide parameters can be programmed in advance of the parameters taking effect. A single register, hw_clkctrl_clkseq, contains all the enable bits that cause the divide parameters to take effect. The enable bits can be set, the busy bits can be polled for each parameter, and thus the enable/busy sequencing via software control can manage the tuning of clock frequencies throughout the system. 4.5 Analog Clock Control Analog clock control is performed indirectly through PIO accessable registers in the CLKCTRL module. The analog circuits that are controlled via CLKCTRL PIO access are the PLL and all instances of the phase fractional dividers, or PFDs. 4.6 CPU and EMI Clock Programming A defined protocol is necessary for selecting clock frequencies and root sources for driving the clk_p and clk_emi domains. These two clock structures are unique in that they each implement a separate divider, one referenced by xtal clock and a second referenced by a PLL/PFD structure. The "roots" of these clocks must be programmed in order of the sources furthest from the trunk first. Elements in the clock roots should subsequently be configured along the root path up to the desired clock trunk. The programming sequence to go from a clock that is referenced from the xtal clock to the PLL is outlined below. This is the i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-9 Clock Generation and Control case when the device is in low power operation and there exists the need for higher clock rates to meet the demands of a more compute-intensive application. The crystal is the current source for the CPU or EMI clock domain. Enable the PLL. Wait for PLL lock. Program and enable the PFD with the desired configuration. Clear the PFD clock gate to establish the desired reference clock frequency. Program the CLKCTRL clock divider register (EMI or CPU) that uses the PLL/PFD as its reference clock. 7. Switch the bypass to off (select PLL, not crystal). The requirement is that the roots of the clock are configured and stable before elements higher up in the tree are programmed. This will allow the roots to stabilize before selected as a valid source to drive a clock trunk/tree. If this sequence is not honored, unpredictable frequencies can occur which may violate the maximum operating frequency of components on the respective clock trees. Be sure to gate off the clock paths directly downstream from the PLL before powering off the PLL. When clk_emi is operating in synchronous mode, the following requirements must be maintained: * * The clk_p divide value is less than or equal to the clk_emi divide value. The clk_emi divide value must be divisable by the clk_p divide value. An example of possible clk_p:clk_emi divide values would be, but not limited, to 1:1, 1:2, 1:3, 2:2, 2:4, 2:6, 3:3, 3:6, 3:9. 1. 2. 3. 4. 5. 6. 4.7 Chip Reset Two PIO accessible soft reset bits exists to establish the initial state of the device. These bits are called HW_CLKCTRL_RESET_CHIP and HW_CLKCTRL_RESET_DIG. Setting these bits will result in a chip wide reset cycle. When setting the DIG software reset bit, the digital logic is reset with the exception of the power module and the DCDC converter control logic. The CHIP software reset bit also initiates the full reset cycle and the power and DCDC converter logic are also reset. These two soft reset bits are themselves reset during a soft reset sequence. i.MX23 Applications Processor Reference Manual, Rev. 1 4-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control See Figure 4-4 for reference of the functionality of these two reset bits. Chip Chip_reset_n Digital Domain HW_CLKCTRL_RESET_DIG FSM HW_CLKCTRL_RESET_CHIP Reset sequence clock control signals Power_reset_n Power DCDC Figure 4-4. Reset Logic Functional Diagram 4.8 Programmable Registers This section includes the programmable registers supported in the Clock Controller Module. 4.8.1 PLL Control Register 0 Description HW_CLKCTRL_PLLCTRL0 HW_CLKCTRL_PLLCTRL0_SET HW_CLKCTRL_PLLCTRL0_CLR HW_CLKCTRL_PLLCTRL0_TOG Table 4-2. HW_CLKCTRL_PLLCTRL0 0x000 0x004 0x008 0x00C The PLL Control Register 0 programs the 480 MHz PLL and the USB-clock enables. 3 1 3 0 2 9 LFR_SEL 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 DIV_SEL 2 0 1 9 1 8 EN_USB_CLKS 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 Table 4-3. HW_CLKCTRL_PLLCTRL0 Bit Field Descriptions BITS LABEL 31:30 RSRVD6 29:28 LFR_SEL RW RESET RO 0x0 RW 0x0 DEFINITION Always set to zero (0). TEST MODE FOR INTERNAL USE ONLY. Adjusts loop filter resistor. DEFAULT = 0x0 Default loop filter resistor TIMES_2 = 0x1 Doubles the loop filter resistor TIMES_05 = 0x2 Halves the loop filter resistor UNDEFINED = 0x3 Undefined i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-11 RSRVD1 CP_SEL POWER Clock Generation and Control Table 4-3. HW_CLKCTRL_PLLCTRL0 Bit Field Descriptions BITS 27:26 RSRVD5 25:24 CP_SEL LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always set to zero (0). TEST MODE FOR INTERNAL USE ONLY. Adjusts charge pump current DEFAULT = 0x0 Default charge pump current TIMES_2 = 0x1 Doubles charge pump current TIMES_05 = 0x2 Halves the charge pump current UNDEFINED = 0x3 Undefined 23:22 RSRVD4 21:20 DIV_SEL RO 0x0 RW 0x0 Always set to zero (0). TEST MODE FOR INTERNAL USE ONLY. This field is currently NOT supported. DEFAULT = 0x0 PLL frequency is 480 MHz LOWER = 0x1 Lower the PLL fequency from 480MHz to 384MHz LOWEST = 0x2 Lower the PLL fequency from 480MHz to 288MHz UNDEFINED = 0x3 Undefined 19 18 RSRVD3 EN_USB_CLKS RO 0x0 RW 0x0 17 16 RSRVD2 POWER RO 0x0 RW 0x0 15:0 RSRVD1 RO 0x0 Always set to zero (0). 0: 8-phase PLL outputs for USB PHY are powered down. If set to 1, 8-phase PLL outputs for USB PHY are powered up. Additionally, the UTMICLK120_GATE and UTMICLK30_GATE must be deasserted in the UTMI phy to enable USB operation. Always set to zero (0). PLL Power On (0 = PLL off; 1 = PLL On). Allow 10 us after turning the PLL on before using the PLL as a clock source. This is the time the PLL takes to lock to 480 MHz. Always set to zero (0). DESCRIPTION: The PLL Control Register 0 programs the 480 MHz PLL and the USB-clock enables. EXAMPLE: HW_CLKCTRL_PLLCTRL0_WR(BF_CLKCTRL_PLLCTRL0_POWER(1)); // enable PLL wait_10us; // Wait 10 us to let PLL lock before using it 4.8.2 PLL Control Register 1 Description HW_CLKCTRL_PLLCTRL1 Table 4-4. HW_CLKCTRL_PLLCTRL1 0x010 PLL Lock Control Register 3 1 3 0 FORCE_LOCK 2 9 2 8 2 7 2 6 2 5 2 4 2 3 RSRVD1 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 LOCK_COUNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 LOCK i.MX23 Applications Processor Reference Manual, Rev. 1 4-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control Table 4-5. HW_CLKCTRL_PLLCTRL1 Bit Field Descriptions BITS LABEL 31 LOCK 30 FORCE_LOCK 29:16 RSRVD1 15:0 LOCK_COUNT RW RESET RO 0x0 RW 0x0 RO 0x0 RO 0x0 DEFINITION PLL Lock bit. 1=PLL Locked. 0=PLL Unlocked. Force the PLL Lock sequence to start. 1=Enable Force Lock. This bit is not self clearing. Reserved - Always set to zero (0). Status of the PLL lock count. The PLL lock bit will assert when the count reaches 0x4B0. The lock count is driven off of xtal, so the 50us. DESCRIPTION: The lock count is driven off of xtal. So after the PLL is powered on, the PLL Lock should be asserted after 50us. EXAMPLE: HW_CLKCTRL_PLLCTRL1_WR(BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(1)); // force pll lock sequence HW_CLKCTRL_PLLCTRL1_WR(BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(0)); // clear force pll lock 4.8.3 CPU Clock Control Register Description HW_CLKCTRL_CPU HW_CLKCTRL_CPU_SET HW_CLKCTRL_CPU_CLR HW_CLKCTRL_CPU_TOG Table 4-6. HW_CLKCTRL_CPU 0x020 0x024 0x028 0x02c The CPUCLK Clock Control Register provides controls for generating the ARM CPUCLK. 3 1 3 0 2 9 BUSY_REF_XTAL 2 8 BUSY_REF_CPU 2 7 2 6 DIV_XTAL_FRAC_EN 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 INTERRUPT_WAIT 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DIV_XTAL Table 4-7. HW_CLKCTRL_CPU Bit Field Descriptions BITS LABEL 31:30 RSVD6 29 BUSY_REF_XTAL RW RESET RO 0x0 RO 0x0 DEFINITION Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). 1 = Enable fractional divide. 0 = Enable integer divide. 28 BUSY_REF_CPU RO 0x0 27 26 RSVD5 DIV_XTAL_FRAC_EN RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-13 DIV_CPU RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 Clock Generation and Control Table 4-7. HW_CLKCTRL_CPU Bit Field Descriptions BITS LABEL 25:16 DIV_XTAL RW RESET RW 0x001 DEFINITION This field controls the divider connected to the crystal reference clock that drives the CLK_P domain when bypass is selected. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. Always set to zero (0). Gate off CLK_P while waiting for an interrupt. Always set to zero (0). Program this field to 0x0. Always set to zero (0). This field controls the divider connected to the ref_cpu reference clock that drives the CLK_P domain when bypass is NOT selected. For changes to this field to take effect, the ref_cpu reference clock must be running. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 15:13 12 11 10 9:6 5:0 RSVD4 INTERRUPT_WAIT RSVD3 RSVD2 RSVD1 DIV_CPU RO RW RO RW RO RW 0x0 0x0 0x0 0x0 0x0 0x01 DESCRIPTION: Controls for the ARM 926 clock divider. Note: Do not write register space when busy bit(s) are high. EXAMPLE: HW_CLKCTRL_CPU_WR(BF_CLKCTRL_DIV_CPU(12)); // 480 MHz / 12 = 40 MHz 4.8.4 AHB, APBH Bus Clock Control Register Description The AHB, APBH Bus Clock Control Register provides controls for CLK_H generation when HW_CLKCTRL_EMI_SYNC_MODE_EN = 0. HW_CLKCTRL_HBUS HW_CLKCTRL_HBUS_SET HW_CLKCTRL_HBUS_CLR HW_CLKCTRL_HBUS_TOG Table 4-8. HW_CLKCTRL_HBUS 3 1 3 0 2 9 2 8 2 7 2 6 APBHDMA_AS_ENABLE 2 5 APBXDMA_AS_ENABLE 2 4 TRAFFIC_JAM_AS_ENABLE 2 3 TRAFFIC_AS_ENABLE 2 2 CPU_DATA_AS_ENABLE 2 1 CPU_INSTR_AS_ENABLE 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x030 0x034 0x038 0x03c AUTO_SLOW_MODE DCP_AS_ENABLE PXP_AS_ENABLE DIV_FRAC_EN SLOW_DIV RSRVD2 RSRVD4 RSRVD1 BUSY i.MX23 Applications Processor Reference Manual, Rev. 1 4-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor DIV Clock Generation and Control Table 4-9. HW_CLKCTRL_HBUS Bit Field Descriptions BITS 31:30 RSRVD4 29 BUSY LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Enable auto-slow mode based on DCP activity. 0 = Run at the programmed CLK_H frequency. Enable auto-slow mode based on PXP activity. 0 = Run at the programmed CLK_H frequency. Enable auto-slow mode based on APBH DMA activity. 0 = Run at the programmed CLK_H frequency. Enable auto-slow mode based on APBX DMA activity. 0 = Run at the programmed CLK_H frequency. Enable auto-slow mode when less than three masters are trying to use the AHB. More than three active masters will engage the default mode. 0 = Run at the programmed CLK_H frequency. Enable auto-slow mode based on AHB master activity. 0 = Run at the programmed CLK_H frequency. Enable auto-slow mode based on with CPU Data access to AHB. 0 = Run at the programmed CLK_H frequency. Enable auto-slow mode based on with CPU Instruction access to AHB. 0 = Run at the programmed CLK_H frequency. Enable CLK_H auto-slow mode. When this is set, then CLK_H will run at the slow rate until one of the fast mode events has occurred. Note: The AUTO_SLOW_MODE bit must be cleared before writing to the SLOW_DIV bitfield. Reserved Slow mode divide ratio. Sets the ratio of CLK_H fast rate to the slow rate. Note: The AUTO_SLOW_MODE bit must be cleared before writing to the SLOW_DIV bitfield. BY1 = 0x0 Slow mode divide ratio = 1 BY2 = 0x1 Slow mode divide ratio = 2 BY4 = 0x2 Slow mode divide ratio = 4 BY8 = 0x3 Slow mode divide ratio = 8 BY16 = 0x4 Slow mode divide ratio = 16 BY32 = 0x5 Slow mode divide ratio = 32 28 27 26 25 24 DCP_AS_ENABLE PXP_AS_ENABLE APBHDMA_AS_ENABLE APBXDMA_AS_ENABLE TRAFFIC_JAM_AS_ENABLE RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 23 22 TRAFFIC_AS_ENABLE CPU_DATA_AS_ENABLE RW 0x0 RW 0x0 21 CPU_INSTR_AS_ENABLE RW 0x0 20 AUTO_SLOW_MODE RW 0x0 19 RSRVD2 18:16 SLOW_DIV RO 0x0 RW 0x0 15:6 5 4:0 RSRVD1 DIV_FRAC_EN DIV RO 0x0 RW 0x0 RW 0x01 Reserved 1 = Enable fractional divide. 0 = Enable integer divide. CLK_P-to-CLK_H divide ratio. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. DESCRIPTION: This register controls the clock divider that generates the CLK_H, the clock used by the AHB and APBH buses, when HW_CLKCTRL_EMI_SYNC_MODE_EN = 0. Note: Do not write register space when busy bit(s) are high. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-15 Clock Generation and Control EXAMPLE: HW_CLKCTRL_HBUS_WR(BF_CLKCTRL_HBUS_DIV(2)); // set CLK_H to half the ARM clock (CLK_P) frequency 4.8.5 APBX Clock Control Register Description HW_CLKCTRL_XBUS Table 4-10. HW_CLKCTRL_XBUS 0x040 The APBX Clock Control Register provides control of the CLK_X clock divider. 3 1 BUSY 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 RSVD2 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD1 0 9 0 8 0 7 0 6 0 5 DIV 0 4 0 3 0 2 0 1 0 0 Table 4-11. HW_CLKCTRL_XBUS Bit Field Descriptions BITS 31 BUSY LABEL RW RESET RO 0x0 DEFINITION This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). Program this field to 0x0. This field controls the CLK_X divide ratio. CLK_X is sourced from the 24-MHz XTAL through this divider. Do NOT divide by 0. 30:11 RSVD2 10 RSVD1 9:0 DIV RO 0x0 RW 0x0 RW 0x001 DESCRIPTION: This register controls the clock divider that generates the CLK_X, the clock used by the APBX bus. Note: Do not write register space when busy bit(s) are high. EXAMPLE: HW_CLKCTRL_XBUS_WR(BF_CLKCTRL_XBUS_DIV(4)); // set apbx xbus clock to 1/4 the 24.0MHz crystal clock frequency 4.8.6 XTAL Clock Control Register Description The XTAL control register provides gating control for clocks sourced from the 24-MHz XTAL clock domain. HW_CLKCTRL_XTAL HW_CLKCTRL_XTAL_SET HW_CLKCTRL_XTAL_CLR HW_CLKCTRL_XTAL_TOG 0x050 0x054 0x058 0x05C i.MX23 Applications Processor Reference Manual, Rev. 1 4-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control Table 4-12. HW_CLKCTRL_XTAL 3 1 UART_CLK_GATE 3 0 FILT_CLK24M_GATE 2 9 PWM_CLK24M_GATE 2 8 DRI_CLK24M_GATE 2 7 DIGCTRL_CLK1M_GATE 2 6 TIMROT_CLK32K_GATE 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 4-13. HW_CLKCTRL_XTAL Bit Field Descriptions BITS LABEL 31 UART_CLK_GATE 30 29 28 27 26 25:2 1:0 FILT_CLK24M_GATE PWM_CLK24M_GATE DRI_CLK24M_GATE DIGCTRL_CLK1M_GATE TIMROT_CLK32K_GATE RSRVD1 DIV_UART RW RESET RW 0x0 RW 0x1 RW 0x1 RW 0x1 RW 0x0 RW 0x0 RO 0x0 RW 0x1 DEFINITION If set to 1, fixed 24-MHz clock for the UART, CLK_UART, is gated off. If set to 1, fixed 24-MHz clock for the Digital Filter, CLK_FILT24M, is gated off. If set to 1, fixed 24-MHz clock for the PWM, CLK_PWM24M, is gated off. If set to 1, fixed 24-MHz clock for the Digital Radio Interface (DRI), CLK_DRI24M, is gated off. If set to 1, fixed 1-MHz clock for DIGCTRL, CLK_1M, is gated off. If set to 1, fixed 32-kHz clock for the TIMROT block, CLK_32K, is gated off. Always set to zero (0). Reserved - Always set to one (1) DESCRIPTION: This register controls various fixed-rate divider clocks working off the 24.0-MHz crystal clock. EXAMPLE: HW_CLKCTRL_XTAL_WR(BF_CLKCTRL_XTAL_UART_CLK_GATE(0)|BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(1)); 4.8.7 PIX (LCDIF) Clock Control Register Description HW_CLKCTRL_PIX 0x060 The PIX control register provides control for LCDIF clock generation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-17 DIV_UART RSRVD1 Clock Generation and Control Table 4-14. HW_CLKCTRL_PIX 3 1 CLKGATE 3 0 RSRVD2 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 RSRVD1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 DIV_FRAC_EN 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BUSY Table 4-15. HW_CLKCTRL_PIX Bit Field Descriptions BITS LABEL 31 CLKGATE RW RESET RW 0x1 DEFINITION CLK_PIX Gate. If set to 1, CLK_PIX is gated off. 0: CLK_PIX is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). Reserved - Always set to zero (0). The Pixel clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_pix) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. Do not divide by more than 255. 30 29 RSRVD2 BUSY RO 0x0 RO 0x0 28:13 RSRVD1 12 DIV_FRAC_EN 11:0 DIV RO 0x0 RW 0x0 RW 0x1 DESCRIPTION: This register controls the divider that generates the PIX (LCDIF) clock. Note: Do not write register space when busy bit(s) are high. EXAMPLE: HW_CLKCTRL_PIX_WR(BF_CLKCTRL_PIX_DIV(40)); 4.8.8 Synchronous Serial Port Clock Control Register Description HW_CLKCTRL_SSP 0x070 The SSP control register provides control for SSP clock generation. i.MX23 Applications Processor Reference Manual, Rev. 1 4-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor DIV Clock Generation and Control Table 4-16. HW_CLKCTRL_SSP 3 1 CLKGATE 3 0 RSVD3 2 9 BUSY 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 RSVD2 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 RSVD1 0 8 0 7 0 6 0 5 0 4 DIV 0 3 0 2 0 1 0 0 Table 4-17. HW_CLKCTRL_SSP Bit Field Descriptions BITS LABEL 31 CLKGATE RW RESET RW 0x1 DEFINITION CLK_SSP Gate. If set to 1, CLK_SSP is gated off. 0: CLK_SSP is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). Program this field to 0x0. The synchronous serial port clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_io) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 30 29 RSVD3 BUSY RO 0x0 RO 0x0 28:10 RSVD2 9 RSVD1 8:0 DIV RO 0x0 RW 0x0 RW 0x1 DESCRIPTION: This register controls the clock divider that generates the clock for the synchronous serial port (SSP), CLK_SSP. Note: Do not write register space when busy bit(s) are high. EXAMPLE: HW_CLKCTRL_SSP_WR(BF_CLKCTRL_SSP_DIV(40)); 4.8.9 General-Purpose Media Interface Clock Control Register Description HW_CLKCTRL_GPMI 0x080 The GPMI control register provides control for GPMI clock generation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-19 Clock Generation and Control Table 4-18. HW_CLKCTRL_GPMI 3 1 CLKGATE 3 0 RSVD3 2 9 BUSY 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 RSVD2 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD1 0 9 0 8 0 7 0 6 0 5 DIV 0 4 0 3 0 2 0 1 0 0 Table 4-19. HW_CLKCTRL_GPMI Bit Field Descriptions BITS LABEL 31 CLKGATE RW RESET RW 0x1 DEFINITION CLK_GPMI Gate. If set to 1, CLK_GPMI is gated off. 0: CLK_GPMI is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). Program this field to 0x0. The GPMI clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_io) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 30 29 RSVD3 BUSY RO 0x0 RO 0x0 28:11 RSVD2 10 RSVD1 9:0 DIV RO 0x0 RW 0x0 RW 0x1 DESCRIPTION: This register controls the divider that generates the General-Purpose Media Interface (GPMI) clock, CLK_GPMI. Note: Do not write register space when busy bit(s) are high. EXAMPLE: HW_CLKCTRL_GPMI_WR(BF_CLKCTRL_GPMI_DIV(40)); 4.8.10 SPDIF Clock Control Register Description HW_CLKCTRL_SPDIF 0x090 The SPDIF control register provides control for SPDIF clock generation. i.MX23 Applications Processor Reference Manual, Rev. 1 4-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control Table 4-20. HW_CLKCTRL_SPDIF 3 1 CLKGATE 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSRVD 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 4-21. HW_CLKCTRL_SPDIF Bit Field Descriptions BITS LABEL 31 CLKGATE RW RESET RW 0x1 DEFINITION CLK_PCMSPDIF Gate. If set to 1, CLK_PCMSPDIF is gated off. 0: CLK_PCMSPDIF is not gated. When this bit is modified, or when it is high, the SPDIF rate change field should not change its value. The SPDIF rate change field can change ONLY when this clock gate bit field is low. Always set to zero (0). 30:0 RSRVD RO 0x0 DESCRIPTION: This register controls the clock gate on the SPDIF clock, CLK_PCMSPDIF. EXAMPLE: HW_CLKCTRL_SPDIF_WR(BF_CLKCTRL_SPDIF_CLKGATE(1)); 4.8.11 EMI Clock Control Register Description HW_CLKCTRL_EMI Table 4-22. HW_CLKCTRL_EMI 0x0a0 The EMi control register provides control for External Memory Interface clock generation. 3 1 3 0 SYNC_MODE_EN 2 9 BUSY_REF_XTAL 2 8 BUSY_REF_EMI 2 7 BUSY_REF_CPU 2 6 BUSY_SYNC_MODE 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CLKGATE DIV_XTAL i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-21 DIV_EMI RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 Clock Generation and Control Table 4-23. HW_CLKCTRL_EMI Bit Field Descriptions BITS LABEL 31 CLKGATE RW RESET RW 0x1 DEFINITION CLK_EMI crystal divider Gate. If set to 1, the EMI_CLK divider that is sourced by the crystal reference clock, ref_xtal, is gated off. 0: CLK_EMI crystal divider is not gated If set to 1, EMI_CLK is synchronous with the APBH clock. If set to 0, EMI_CLK is aysnchronous. In synchronous operation, the EMI clock dividers control both EMI_CLK and APBH clock. Both xtal and ref_cpu must be active to switch between asynchronous/synchronous operation. This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. This bit is valid when HW_CLKCTRL_EMI_SYNC_MODE_EN = 0. This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. This bit is valid when HW_CLKCTRL_EMI_SYNC_MODE_EN = 1. This read-only bit field returns a one when there is a change in HW_CLKCTRL_EMI_SYNCE_MODE_EN or when there is a change in HW_CLKCTRL_CLKSEQ_BYPASS_CPU and HW_CLKCTRL_EMI_SYNCE_MODE_EN is set. When this bit returns a one, do not change the CPU or EMI divider values. Always set to zero (0). Program this field to 0x0. Program this field to 0x0. Always set to zero (0). This field controls the divider connected to the crystal reference clock, ref_xtal, that drives the CLK_EMI domain when bypass IS selected. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. Always set to zero (0). This field controls the divider connected to the ref_emi reference clock that drives the CLK_EMI domain when bypass IS NOT selected. For changes to this field to take effect, the ref_emi reference clock must be running. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 30 SYNC_MODE_EN RW 0x0 29 BUSY_REF_XTAL RO 0x0 28 BUSY_REF_EMI RO 0x0 27 BUSY_REF_CPU RO 0x0 26 BUSY_SYNC_MODE RO 0x0 25:18 17 16 15:12 11:8 RSVD5 RSVD4 RSVD3 RSVD2 DIV_XTAL RO RO RW RO RW 0x0 0x0 0x0 0x0 0x1 7:6 5:0 RSVD1 DIV_EMI RO 0x0 RW 0x1 DESCRIPTION: This register controls the clock dividers that generate the External Memory Interface (EMI) clock. Note: Do not write register space when busy bit(s) are high. i.MX23 Applications Processor Reference Manual, Rev. 1 4-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control EXAMPLE: HW_CLKCTRL_EMI_WR(BF_CLKCTRL_EMI_DIV_XTAL(1)); 4.8.12 SAIF Clock Control Register Description HW_CLKCTRL_SAIF Table 4-24. HW_CLKCTRL_SAIF 0x0c0 The SAIF control register provides control for SAIF clock generation. 3 1 CLKGATE 3 0 RSRVD2 2 9 2 8 2 7 2 6 2 5 2 4 2 3 RSRVD1 2 2 2 1 2 0 1 9 1 8 1 7 1 6 DIV_FRAC_EN 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BUSY Table 4-25. HW_CLKCTRL_SAIF Bit Field Descriptions BITS LABEL 31 CLKGATE RW RESET RW 0x1 DEFINITION CLK_SAIF Gate. If set to 1, CLK_SAIF is gated off. 0: CLK_SAIF is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). Reserved - Always set to one (1) - Notice this is not the reset value. The SAIF clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_pll) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 30 29 RSRVD2 BUSY RO 0x0 RO 0x0 28:17 RSRVD1 16 DIV_FRAC_EN 15:0 DIV RO 0x0 RW 0x0 RW 0x1 DESCRIPTION: This register controls the divider that generates the Serial Audio Interface (SAIF) clock. Note: Do not write register space when busy bit(s) are high. EXAMPLE: HW_CLKCTRL_SAIF_WR(BF_CLKCTRL_SAIF_DIV(40)); 4.8.13 TV Encode Clock Control Register Description The TV control register provides control for TV Encoder clock generation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-23 DIV Clock Generation and Control HW_CLKCTRL_TV Table 4-26. HW_CLKCTRL_TV 3 1 CLK_TV108M_GATE 3 0 CLK_TV_GATE 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0x0d0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 4-27. HW_CLKCTRL_TV Bit Field Descriptions BITS LABEL 31 CLK_TV108M_GATE 30 CLK_TV_GATE RW RESET RW 0x1 RW 0x1 DEFINITION If set to 1, fixed 108-MHz clock for the TV Component Video is gated off. 0: CLK_TV108M, is not gated. If set to 1, fixed 54-MHz and 27-MHz clocks for the TV Encoder are gated off. 0: CLK_TV54M and CLK_TV27M, are not gated. Always set to zero (0). 29:0 RSRVD RO 0x0 DESCRIPTION: This register controls various video divider clocks. EXAMPLE: HW_CLKCTRL_CLK_TV108M_GATE_WR(BF_CLKCTRL_CLK_TV108M_GATE(0)); 4.8.14 ETM Clock Control Register Description HW_CLKCTRL_ETM Table 4-28. HW_CLKCTRL_ETM 0x0e0 The ETM control register provides control for ETM clock generation. 3 1 CLKGATE 3 0 RSRVD2 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 RSRVD 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DIV_FRAC_EN 0 5 0 4 0 3 0 2 0 1 0 0 BUSY i.MX23 Applications Processor Reference Manual, Rev. 1 4-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor DIV Clock Generation and Control Table 4-29. HW_CLKCTRL_ETM Bit Field Descriptions BITS LABEL 31 CLKGATE RW RESET RW 0x1 DEFINITION CLK_ETM Gate. If set to 1, CLK_ETM is gated off. 0: CLK_ETM is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). Reserved - Always set to zero (0). The Pixel clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_cpu) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 30 29 RSRVD2 BUSY RO 0x0 RO 0x0 28:7 6 5:0 RSRVD1 DIV_FRAC_EN DIV RO 0x00000 RW 0x0 RW 0x01 DESCRIPTION: This register controls the divider that generates the ETM clock. Note: Do not write register space when busy bit(s) are high. EXAMPLE: HW_CLKCTRL_ETM_WR(BF_CLKCTRL_ETM_DIV(4)); 4.8.15 Fractional Clock Control Register Description The FRAC control register provides control for PFD clock generation. NOTE: Only byte accesses are supported. When using DWORD accesses to this regiester, the PFD update sequence will commence for all four PFDs controlled by this register. This may be undersirable if only one of the PFD divide values need to be updated. Only access individual bytes within this register in a single PIO access. HW_CLKCTRL_FRAC HW_CLKCTRL_FRAC_SET HW_CLKCTRL_FRAC_CLR HW_CLKCTRL_FRAC_TOG Table 4-30. HW_CLKCTRL_FRAC 3 1 CLKGATEIO 3 0 IO_STABLE 2 9 2 8 2 7 IOFRAC 2 6 2 5 2 4 2 3 CLKGATEPIX 2 2 PIX_STABLE 2 1 2 0 1 9 PIXFRAC 1 8 1 7 1 6 1 5 CLKGATEEMI 1 4 EMI_STABLE 1 3 1 2 1 1 EMIFRAC 1 0 0 9 0 8 0 7 CLKGATECPU 0 6 CPU_STABLE 0 5 0 4 0 3 CPUFRAC 0 2 0 1 0 0 0x0f0 0x0f4 0x0f8 0x0fC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-25 Clock Generation and Control Table 4-31. HW_CLKCTRL_FRAC Bit Field Descriptions BITS LABEL 31 CLKGATEIO RW RESET RW 0x1 DEFINITION IO Clock Gate. If set to 1, the IO fractional divider clock (reference PLL ref_io) is off (power savings). 0: IO fractional divider clock is enabled. This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. This field controls the IO clocks fractional divider. The resulting frequency shall be 480 * (18/IOFRAC) where IOFRAC = 1-35. PIX Clock Gate. If set to 1, the PIX fractional divider clock (reference PLL ref_pix) is off (power savings). 0: PIX fractional divider clock is enabled. This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. This field controls the pixel clock fractional divider. The resulting frequency shall be 480 * (18/PIXFRAC) where PIXFRAC = 1-35. EMI Clock Gate. If set to 1, the EMI fractional divider clock (reference PLL ref_emi) is off (power savings). 0: EMI fractional divider clock is enabled. This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divide should become stable quickly enough that this field will never need to be used by either device driver or application code. This value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. This field controls the EMI clock fractional divider. The resulting frequency shall be 480 * (18/EMIFRAC) where EMIFRAC = 1-35. CPU Clock Gate. If set to 1, the CPU fractional divider clock (reference PLL ref_cpu) is off (power savings). 0: CPU fractional divider clock is enabled. 30 IO_STABLE RO 0x0 29:24 IOFRAC RW 0x12 23 CLKGATEPIX RW 0x1 22 PIX_STABLE RO 0x0 21:16 PIXFRAC RW 0x12 15 CLKGATEEMI RW 0x1 14 EMI_STABLE RO 0x0 13:8 EMIFRAC RW 0x12 7 CLKGATECPU RW 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 4-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control Table 4-31. HW_CLKCTRL_FRAC Bit Field Descriptions BITS LABEL 6 CPU_STABLE RW RESET RO 0x0 DEFINITION This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divide should become stable quickly enough that this field will never need to be used by either device driver or application code. The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. This field controls the CPU clock fractional divider. The resulting frequency shall be 480 * (18/CPUFRAC) where CPUFRAC = 1-35. 5:0 CPUFRAC RW 0x12 DESCRIPTION: This register controls the 9-phase fractional clock dividers. The fractional clock frequencies are a product of the values in these registers. EXAMPLE: HW_CLKCTRL_FRAC_WR(BF_CLKCTRL_FRAC_CPUFRAC(4)); 4.8.16 Fractional Clock Control Register 1 Description HW_CLKCTRL_FRAC1 HW_CLKCTRL_FRAC1_SET HW_CLKCTRL_FRAC1_CLR HW_CLKCTRL_FRAC1_TOG Table 4-32. HW_CLKCTRL_FRAC1 0x100 0x104 0x108 0x10C The FRAC1 control register provides control for PFD clock generation. 3 1 CLKGATEVID 3 0 VID_STABLE 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSRVD1 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-27 Clock Generation and Control Table 4-33. HW_CLKCTRL_FRAC1 Bit Field Descriptions BITS LABEL 31 CLKGATEVID RW RESET RW 0x1 DEFINITION 432 MHz PLL Clock Gate. If set to 1, the 432 MHz fractional divider clock (reference PLL ref_vid) is off (power savings). 0: IO fractional divider clock is enabled. This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. Always set to zero (0). 30 VID_STABLE RO 0x0 29:0 RSRVD1 RO 0x0 DESCRIPTION: This register controls the 9-phase fractional clock dividers. The fractional clock frequencies are a product of the values in these registers. EXAMPLE: HW_CLKCTRL_FRAC1_WR(BF_CLKCTRL_FRAC1_CLKGATEVID(0)); 4.8.17 Clock Frequency Sequence Control Register Description HW_CLKCTRL_CLKSEQ HW_CLKCTRL_CLKSEQ_SET HW_CLKCTRL_CLKSEQ_CLR HW_CLKCTRL_CLKSEQ_TOG Table 4-34. HW_CLKCTRL_CLKSEQ 0x110 0x114 0x118 0x11c The CLKSEQ control register provides control for switching between XTAL and PLL clock generation. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 RSRVD1 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 BYPASS_ETM 0 7 BYPASS_CPU 0 6 BYPASS_EMI 0 5 BYPASS_SSP 0 4 BYPASS_GPMI 0 3 BYPASS_IR 0 2 RSRVD0 0 1 BYPASS_PIX 0 0 BYPASS_SAIF i.MX23 Applications Processor Reference Manual, Rev. 1 4-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control Table 4-35. HW_CLKCTRL_CLKSEQ Bit Field Descriptions BITS LABEL 31:9 RSRVD1 8 BYPASS_ETM RW RESET RO 0x0 RW 0x1 DEFINITION Always set to zero (0). ETM bypass select. 1 = Select ref_xtal path to generate the ETM clock domain. 0 = Select ref_cpu path to generate the ETM clock domain. PLL and 9-phase fractional divider must be configured when this bit is cleared. CPU bypass select. 1 = Select ref_xtal path to generate the CPU and APBH clock domains. 0 = Select ref_cpu path to generate the CPU and APBH clock domains. PLL and 9-phase fractional divider must be configured when this bit is cleared. EMI bypass select. 1 = Select ref_xtal path to generate the EMI clock domain. 0 = Select ref_emi path to generate the EMI clock domain. PLL and 9-phase fractional divider must be configured when this bit is cleared. SSP bypass select. 1 = Select ref_xtal path to generate the SSP clock domain. 0 = Select ref_io path to generate the SSP clock domain. PLL and 9-phase fractional divider must be configured when this bit is cleared. GPMI bypass select. 1 = Select ref_xtal path to generate the GPMI clock domain. 0 = Select ref_io path to generate the GPMI clock domain. PLL and 9-phase fractional divider must be configured when this bit is cleared. IR bypass select. 1 = Select ref_xtal path to generate the IR clock domain. 0 = Select ref_io path to generate the IR clock domain. PLL and 9-phase fractional divider must be configured when this bit is cleared. Always set to zero (0). PIX bypass select. 1 = Select ref_xtal path to generate the PIX clock domain. 0 = Select ref_pix path to generate the PIX clock domain. PLL and 9-phase fractional divider must be configured when this bit is cleared. Reserved - Always set to zero (0) - Notice this is not the reset value. 7 BYPASS_CPU RW 0x1 6 BYPASS_EMI RW 0x1 5 BYPASS_SSP RW 0x1 4 BYPASS_GPMI RW 0x1 3 BYPASS_IR RW 0x1 2 1 RSRVD0 BYPASS_PIX RO 0x0 RW 0x1 0 BYPASS_SAIF RW 0x1 DESCRIPTION: This register controls the selection of clock sources (ref_xtal or ref_*) for various clock dividers. EXAMPLE: HW_CLKCTRL_CLKSEQ_WR(BF_CLKCTRL_CLKSEQ_BYPASS_IR(1)); 4.8.18 System Software Reset Register Description HW_CLKCTRL_RESET 0x120 The RESET control register provides control for soft reset. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-29 Clock Generation and Control Table 4-36. HW_CLKCTRL_RESET 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 RSRVD 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 CHIP 0 0 DIG 0 0 Table 4-37. HW_CLKCTRL_RESET Bit Field Descriptions BITS 31:2 RSRVD 1 CHIP LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always set to zero (0). Setting this bit to a logic one will reset the ENTIRE chip, no exceptions. This bit will also be reset after the full chip reset cycle completes. Setting this bit to a logic one will reset the digital sections of the chip. The DCDC and power module will not be reset. This bit will also be reset after the reset cycle completes. 0 DIG RW 0x0 DESCRIPTION: This register controls full chip reset generation. EXAMPLE: HW_CLKCTRL_RESET_WR(BF_CLKCTRL_RESET_ALL(1)); 4.8.19 ClkCtrl Status Description HW_CLKCTRL_STATUS Table 4-38. HW_CLKCTRL_STATUS 0x130 The STATUS control register provides read only status of the CPU frequecy limits. 3 1 CPU_LIMIT 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSRVD 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 Table 4-39. HW_CLKCTRL_STATUS Bit Field Descriptions BITS LABEL 31:30 CPU_LIMIT RW RESET RO 0x00 DEFINITION CPU Limiting. 00: full cpu frequency, 01: limit cpu frequency to 411.43 MHz, 10: limit cpu frequency to 360 MHz, 11: limit cpu frequency to 320 MHz Always set to zero (0). 29:0 RSRVD RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 4-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor Clock Generation and Control DESCRIPTION: This register indicates the CPU Frequency limit. EXAMPLE: HW_CLKCTRL_STATUS_RD(BF_CLKCTRL_STATUS_CPU_LIMIT()); 4.8.20 ClkCtrl Version Description HW_CLKCTRL_VERSION Table 4-40. HW_CLKCTRL_VERSION 0x140 The VERSION control register is a read only status of the clkctrl block version. 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 4-41. HW_CLKCTRL_VERSION Bit Field Descriptions BITS 31:24 MAJOR 23:16 MINOR 15:0 STEP LABEL RW RESET RO 0x4 RO 0x0 RO 0x0 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: HW_CLKCTRL_VERSION_RD(BF_CLKCTRL_VERSION_MAJOR()); CLKCTRL Block v4.0, Revision 1.48 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 4-31 Clock Generation and Control i.MX23 Applications Processor Reference Manual, Rev. 1 4-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 5 Interrupt Collector This chapter describes the interrupt control features of the i.MX23 and includes sections on interrupt nesting, FIQ generation, and CPU wait-for-interrupt mode. Table 5-1 lists all of the interrupt sources available on the i.MX23. Programmable registers for interrupt generation and control are described in Section 5.4, "Programmable Registers." 5.1 Overview The ARM9 CPU core has two interrupt input lines, IRQ and FIQ. As shown in Figure 5-1, the Interrupt Collector (ICOLL) can steer any of 128 interrupt sources to either the the FIQn or IRQn lines of the ARM9 CPU. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-1 Interrupt Collector HW Int Sources HW_ICOLL_INTERRUPT0-127[ENFIQ] HW_ICOLL_INTERRUPT0-127[ENABLE] 128 HW_ICOLL_RAW0-3 HW_ICOLL_RAW0-3 HW_ICOLL_RAW0-3 HW_ICOLL_RAW0-3 128 0 . . . 127 HW_ICOLL_INTERRUPT0-127[SOFTIRQ] 128 128 128 128 HW_ICOLL_INTERRUPT0-127[PRIORITY] 128 128 OR x128 Priority Encoder Vector Address = Vector Base Address + 4 * Source Bit Number FIQ HW_ICOLL_VECTOR IRQ ARM9 Figure 5-1. Interrupt Collector System Diagram 5.2 Operation Within an individual interrupt request line (IRQ only), the ICOLL offers four-level priority (above base level) for each of its interrupt sources. Preemption of a lower priority interrupt by a higher priority is supported (interrupt nesting). Interrupts assigned to the same level are serviced in a strict linear priority order within level from lowest to highest interrupt source bit number. FIQ interrupts are not prioritized, nor are they vectorized. All interrupt lines can be configured as a FIQ. If more than one is routed to the FIQ, then they must be discriminated by software. It is highly recommended to reserve FIQ assignment to time critical events such as voltage brownouts or timers. i.MX23 Applications Processor Reference Manual, Rev. 1 5-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector HW_ICOLL_VBASE (Vector Table Base Addr) Vector Address = Vector Base Address + 4 * Source Bit Number HW_ICOLL_INTERRUPT33[PRIORITY] HW_ICOLL_VECTOR APBH HW_ICOLL_INTERRUPT33[SOFTIRQ] INT Sources 1:4 HW_ICOLL_INTERRUPT33[ENABLE] 32 . . . 63 HW_ICOLL_RAW1 (Read-Only) IRQ FIQ ARM 926 HW_ICOLL_INTERRUPT33[ENFIQ] Other sources Figure 5-2. Interrupt Collector IRQ/FIQ Logic for Source 33 For a single interrupt source bit, there is an enable bit that gates it to the priority logic (HW_ICOLL_INTERRUPTn[ENABLE]). A software interrupt bit per source bit can be used to force an interrupt at the appropriate priority level directed to the corresponding vector address. Each source can be applied to one of four interrupt levels. The enable bit, FIQ-enable, the software interrupt bit, and the two-bit priority level specification for each interrupt source bit are contained with a single programmable register for each interrupt. The path from any interrupt source to the FIQ or IRQ logic is shown in Figure 5-2 using HW_ICOLL_INTERRUPT33 as an example. The data path for generating the vector address (readable by software) for the IRQ generation portion of the interrupt collector is implemented as a multicycle path, as shown in Figure 5-3. The interrupt sources are continuously sampled in the holding register until one or more arrive. The FSM causes the holding register to stop sampling while a vector address is computed. Each interrupt source bit is applied to one of four levels based on the two-bit priority specification of each source bit. When the holding register "closes," there can be more than one newly arrived source bit. Thus, the source bits could be assigned such that more than one interrupt level is requesting an interrupt. The pipeline first determines the highest level requesting interrupt service. All interrupt requests on that level are presented to the linear priority encoder. The result of this stage is a six-bit number corresponding to the source bit number of the highest priority requesting an interrupt. This six-bit source number is used to compute the vector address as follows: i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-3 AHB Interrupt Collector VectorAddress = VectorBase + (Pitch * SourceBitNumber) Pitch = 4,8, 12,16,20,24, or 28 as desired, see HW_CTRL_VECTOR_PITCH. Multicycle Path 3x INTERRUPT37[PRIORITY] Compute vector address INTERRUPT37[SOFTIRQ] Linear Priority INTERRUPT37[ENABLE] HW_ICOLL_VECTOR Pick Hghest Level Holding Register APBH AHB 1:4 (1x) FIQ HW_ICOLL_RAW1 (Read-Only) 32 . . . 63 FSM IRQ [37] APB PIO Cycles ARM9 INT Sources Figure 5-3. IRQ Control Flow 5.2.1 Nesting of Multi-Level IRQ Interrupts There are a number of very important interactions between the interrupt collector's FSM and the interrupt service routine (ISR) running on the CPU. See Figure 5-4 for the following discussion. As soon as the interrupt source is recognized in the holding register, the FSM delays two clocks, then grabs the vector address and asserts IRQ to the CPU. As soon as possible after the CPU enters the interrupt service routine, it must notify the interrupt collector. Software indicates the in-service state by writing to the HW_ICOLL_VECTOR register. The contents of the data bus on this write do not matter. Optionally, firmware can enable the ARM read side-effect mode. In this case, the in-service state is indicated as a side effect of having read the HW_ICOLL_VECTOR register at the exception vector (0xFFFF0018). At this point, the FSM reopens the holding register and scans for new interrupt sources. Any such IRQ sources are presented to the CPU, provided that they are at a level higher than any currently in-service level. Whenever the ARM CPU takes an IRQ exception, it turns off the IRQ enable in the CPU status register (CSR), as shown in Figure 5-4. If a higher priority interrupt is pending at this point, then another IRQ exception is taken. i.MX23 Applications Processor Reference Manual, Rev. 1 5-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Critical section Critical section CSR IRQ IRQ IRQ LEVEL 3 IRQ LEVEL 2 IRQ LEVEL 1 IRQ LEVEL 0 INSERVICE Re-enable IRQ INSERVICE INSERVICE ACKLEVEL2 Re-enable IRQ Base Figure 5-4. Nesting of Multi-Level IRQ Interrupts The example in Figure 5-4 shows going from the base to a level 0 ISR. When the ISR at level 0 was ready, it enabled IRQ interrupts. At this point, it nests IRQ interrupts up to a level 3 interrupt. The level 3 ISR marks its in-service state, which causes the interrupt collector to open the holding register to search for new interrupt sources. In this example, none comes in, so the level 3 ISR completes. As part of the return process, the ISR disables IRQ interrupts, then acknowledges the level 3 service state. This is accomplished by writing the level number (3 in this case) to the interrupt collector's Level Acknowledge register. The interrupt collector resets the in-service bit for level 3. If this enables an IRQ at level 3, then it asserts IRQ and goes through the nesting process again. Since IRQ exceptions are masked in the level 3 ISR, this nesting does not take place until the level 3 ISR returns from interrupt. This return automatically re-enables IRQ exceptions. At this point, another exception could occur. Figure 5-4 shows a second nesting of the IRQ interrupt by the arrival of a level 2 interrupt source bit. Finally, the figure shows the point at which the level 0 ISR enters its critical section (masks IRQ) and acknowledges level 0 to the interrupt collector and returns from interrupt. The FSM reverts to its "BASE" level state waiting for an interrupt request to arrive in the holding register. The waveform for the IRQ mask in the CPU status register (CSR) and the waveform for the IRQ input to the CPU as they relate to the interrupt collector action are shown in Figure 5-4. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-5 Re-enable IRQ ACKLEVEL3 ACKLEVEL0 Critical section Interrupt Collector WARNING: There is an inherent race condition between notifying the interrupt collector that an ISR has been entered and having that ISR re-enable IRQ exceptions in the CSR. The in-service notification can take a number of cycles to percolate through the write buffer, through the AHB and APB bridge and into the interrupt collector where it removes the IRQ assertion to the CPU. This ICOLL IRQ must be deasserted before the CSR IRQ on the CPU is re-enabled or the CPU will see a phantom interrupt. This is why the ARM vectored interrupt controller provides this in service notification as a read side effect of the vector address read. Alternatively, the ISR can read the interrupt collector's CSR. The value received is unimportant, but the time required to do the read ensures that the write data has arrived at the interrupt collector. If firmware uses this method, it should allow clocks after the read for the FSM and for the CPU to recognize that the IRQ has been deasserted. 5.2.2 FIQ Generation On i.MX23, all interrupt sources can be configured as FIQ. This is controlled via the HW_ICOLL_INTERRUPTn[ENFIQ] register bit as shown in Figure 5-2. When enabled to the FIQ, the software interrupt associated with these bits can be used to generate the FIQ from these sources for test purposes. When an interrupt source is programmed as an FIQ, and IRQ cannot be generated from that source. 5.2.3 Interrupt Sources Table 5-1 lists all of the interrupt sources on the i.MX23. Use hw_irq.h to access these bits. Table 5-1. i.MX23 Interrupt Sources INTERRUPT SOURCE DEBUG_UART COMMS_RX,COMMS_TX SSP2_ERROR VDD5V HEADPHONE_SHORT DAC_DMA DAC_ERROR ADC_DMA ADC_ERROR SPDIF_DMA,SAIF2_DMA SPDIF_ERROR, SAIF1_IRQ, SAIF2_IRQ SRC 0 1 2 3 4 5 6 7 8 9 10 VECTOR 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 DESCRIPTION Non DMA on the debug UART JTAG debug communications port SSP2 device-level error and status IRQ on 5V connect or disconnect. Shared with DCDC status, Linear Regulator status, PSWITCH, and Host 4.2V HEADPHONE_SHORT DAC DMA channel DAC FIFO buffer underflow ADC DMA channel ADC FIFO buffer overflow SPDIF DMA channel, SAIF2 DMA channel SPDIF, SAIF1, SAIF2 FIFO underflow/overflow i.MX23 Applications Processor Reference Manual, Rev. 1 5-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-1. i.MX23 Interrupt Sources (continued) INTERRUPT SOURCE USB_CTRL USB_WAKEUP GPMI_DMA SSP1_DMA SSP_ERROR GPIO0 GPIO1 GPIO2 SAIF1_DMA SSP2_DMA ECC8_IRQ RTC_ALARM UARTAPP_TX_DMA UARTAPP_INTERNAL UARTAPP_RX_DMA I2C_DMA I2C_ERROR TIMER0 TIMER1 TIMER2 TIMER3 BATT_BRNOUT VDDD_BRNOUT VDDIO_BRNOUT VDD18_BRNOUT TOUCH_DETECT LRADC_CH0 LRADC_CH1 LRADC_CH2 LRADC_CH3 LRADC_CH4 SRC 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 VECTOR 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4 USB controller USB wakeup. Also ARC core to remain suspended. From DMA channel for GPMI From DMA channel for SSP1 SSP1 device-level error and status GPIO bank 0 interrupt GPIO bank 1 interrupt GPIO bank 2 interrupt SAIF1 DMA channel From DMA channel for SSP2 ECC8 completion interrupt RTC alarm event Application UART1 transmitter DMA Application UART1 internal error Application UART1 receiver DMA From DMA channel for I2C From I2C device detected errors and line conditions TIMROT Timer0, recommend to set as FIQ. TIMROT Timer1, recommend to set as FIQ. TIMROT Timer2, recommend to set as FIQ. TIMROT Timer3, recommend to set as FIQ. Power module battery brownout detect, recommend to set as FIQ. Power module VDDD brownout detect, recommend to set as FIQ. Power module VDDIO brownout detect, recommend to set as FIQ. Power module VDD18 brownout detect, recommend to set as FIQ. Touch detection. Channel 0 complete. Channel 1 complete. Channel 2 complete. Channel 3 complete. Channel 4 complete. DESCRIPTION i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-7 Interrupt Collector Table 5-1. i.MX23 Interrupt Sources (continued) INTERRUPT SOURCE LRADC_CH5 LRADC_CH6 LRADC_CH7 LCDIF_DMA LCDIF_ERROR DIGCTL_DEBUG_TRAP RTC_1MSEC RSVD RSVD GPMI RSVD DCP_VMI DCP RSVD BCH PXP UARTAPP2_TX_DMA UARTAPP2_INTERNAL UARTAPP2_RX_DMA VDAC_DETECT RSVD RSVD VDD5V_DROOP DCDC4P2_BO RSVD SRC 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66-1278 VECTOR 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x00D8 0x00DC 0x00E0 0x00E4 0x00E8 0x00EC 0x00F0 0x00F4 0x00F8 0x00FC 0x0100 0x0104 0x0108-01FC Channel 5 complete. Channel 6 complete. Channel 7 complete. From DMA channel for LCDIF. LCDIF error. AHB arbiter debug trap. RTC 1 ms tick interrupt. Reserved Reserved From GPMI internal error and status IRQ. Reserved DCP Channel 0 virtual memory page copy. DCP Reserved. BCH consolidated Interrupt Pixel Pipeline consolidated Interrupt Application UART2 transmitter DMA Application UART2 internal error Application UART2 receiver DMA Video dac, jack presence auto-detect Reserved. Reserved. 5V Droop, recommend to be set as FIQ. 4.2V regulated supply brown-out, recommend to be set as FIQ. Reserved. DESCRIPTION i.MX23 Applications Processor Reference Manual, Rev. 1 5-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector 5.2.4 CPU Wait-for-Interrupt Mode To enable wait-for-interrupt mode, two distinct actions are required by the programmer: Set the INTERRUPT_WAIT bit in the HW_CLKCTRL_CPUCLKCTRL register. This must be done via a RMW operation. For example: uclkctrl = HW_CLKCTRL_CPUCLKCTRL_RD(); uclkctrl |= BM_CLKCTRL_CPUCLKCTRL_INTERRUPT_WAIT; HW_CLKCTRL_CPUCLKCTRL_WR(uclkctrl); 8. After setting the INTERRUPT_WAIT bit, a coprocessor instruction is required. asm ( // Note: R0 is used in the following example, but any usual // The coprocessor instruction sequence above enables an internal gating signal. This internal signal guarantees that write buffers are drained and ensures that the processor is in an idle state. On execution of the MCR coprocessor instruction, the CPU clock is stopped and the processor halts on the instruction--waiting for an interrupt to occur. The INTERRUPT_WAIT bit can be thought of as a Wait-for-Interrupt enable bit. Therefore, it must be set prior to execution of the MCR instruction. It is recommended that, when the Wait-for-Interrupt mode is to be used, the INTERRUPT_WAIT bit be set at initialization time and left on. With the INTERRUPT_WAIT bit set, after execution of the MCR WFI command, the processor halts on the MCR instruction. When an interrupt or FIQ occurs, the MCR instruction completes and the IRQ or FIQ handler is entered normally. The return link that is passed to the handler is automatically adjusted by the above MCR instruction, such that a normal return from interrupt results in continuing execution at the instruction immediately following the MCR. That is, the LR will contain the address of the MCR instruction plus eight, such that a typical return from interrupt instruction (e.g., subs pc, LR, 4) will return to the instruction immediately following the MCR (the NOP in the example above). Whenever the CPU is stopped because the clock control HW_CLKCTRL_ CPUCLKCTRL_INTERRUPT_WAIT bit is set and the MCR WFI instruction is executed, the CPU stops until an interrupt occurs. The actual condition that wakes up the CPU is determined by ORing together all enabled interrupt requests including those that are directed to the FIQ CPU input. The ICOLL_BUSY output signal from the ICOLL communicates this information to the clock control. This function does not pass through the normal ICOLL state machine. It starts the CPU clock as soon as an enabled interrupt arrives. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-9 Interrupt Collector 5.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block, for additional information on using the SFTRST and CLKGATE bit fields. 5.4 Programmable Registers The following registers provide interrupt generation and control for the i.MX23. 5.4.1 Interrupt Collector Interrupt Vector Address Register Description This register is can be read by the Interrupt Service Routine using a load PC instruction. The priority logic presents the vector address of the next IRQ interrupt to be processed by the CPU. The vector address is held until a new ISR is entered.. HW_ICOLL_VECTOR HW_ICOLL_VECTOR_SET HW_ICOLL_VECTOR_CLR HW_ICOLL_VECTOR_TOG Table 5-2. HW_ICOLL_VECTOR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 IRQVECTOR 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 RSRVD1 DEFINITION This register presents the vector address for the interrupt currently active on the CPU IRQ input. Writing to this register notifies the interrupt collector that the interrupt service routine for the current interrupt has been entered (alternatively when ARM_RSE_MODE is set, reading this register is required). Always write zeroes to this field. Freescale Semiconductor Preliminary--Subject to Change Without Notice 0 0 0x000 0x004 0x008 0x00C Table 5-3. HW_ICOLL_VECTOR Bit Field Descriptions BITS LABEL 31:2 IRQVECTOR RW RESET RW 0x0 1:0 RSRVD1 RO 0x0 DESCRIPTION: This register mediates the vectored interrupt collectors interface with the CPU when it enteres the IRQ exception trap. The exception trap should have a LDPC instruction from this address. EXAMPLE: LDPC HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018 i.MX23 Applications Processor Reference Manual, Rev. 1 5-10 Interrupt Collector 5.4.2 Interrupt Collector Level Acknowledge Register Description The Interrupt Collector Level Acknowledge Register is used by software to indicate the completion of an interrupt on a specific level. HW_ICOLL_LEVELACK Table 5-4. HW_ICOLL_LEVELACK 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 IRQLEVELACK DEFINITION Any value can be written to this bitfield. Writes are ignored. This bitfield is written by the processor to acknowledge the completion of an interrupt. The value written must correspond to the priority level of the completed interrupt LEVEL0 = 0x1 level 0 LEVEL1 = 0x2 level 1 LEVEL2 = 0x4 level 2 LEVEL3 = 0x8 level 3 0x010 0 1 0 0 Table 5-5. HW_ICOLL_LEVELACK Bit Field Descriptions BITS 31:4 RSRVD1 3:0 LABEL RW RESET RO 0x0 RW 0x0 IRQLEVELACK DESCRIPTION: This register is written to advance the ICOLL internal irq state machine. It advances from an in-service on a level state to the next pending interrupt level or to the idle state. This register is written at the very end of an interrupt service routine. If nesting is used then the CPU irq must be turned on before writing to this register to avoid a race condition in the CPU interrupt hardware. WARNING: the value written to the level ack register is decoded not binary, i.e. 8, 4, 2, 1. EXAMPLE: HW_ICOLL_LEVELACK_WR(HW_ICOLL_LEVELACK__LEVEL3); 5.4.3 Interrupt Collector Control Register Description The Interrupt Collector Control Register provides overall control of interrupts being routed to the CPU. This register is not at offset zero from the block base because that location is needed for single 32 bit instructions to be placed in the exception vector location. HW_ICOLL_CTRL HW_ICOLL_CTRL_SET HW_ICOLL_CTRL_CLR HW_ICOLL_CTRL_TOG 0x020 0x024 0x028 0x02C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-11 Interrupt Collector Table 5-6. HW_ICOLL_CTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 VECTOR_PITCH 2 1 2 0 1 9 1 8 ARM_RSE_MODE 1 7 FIQ_FINAL_ENABLE 1 6 IRQ_FINAL_ENABLE 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BYPASS_FSM NO_NESTING CLKGATE RSRVD3 Table 5-7. HW_ICOLL_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION When set to one, this bit causes a soft reset to the entire interrupt collector. This bit must be turned off for normal operation. RUN = 0x0 Allow the interrupt collector to operate normally. IN_RESET = 0x1 Hold the interrupt collector in its reset state. 30 CLKGATE RW 0x1 When set to one, this bit causes all clocks within the interrupt collector to be gated off. WARNING: Do not set this bit at the same time as SFTRST. Doing so, causes the softreset to have no effect. Setting SFTRST will cause the CLKGATE bit to set automatically four clocks later. RUN = 0x0 Enable clocks for normal operation of interrupt collector. NO_CLOCKS = 0x1 disable clocking within the interrupt collector. 29:24 RSRVD3 23:21 VECTOR_PITCH RO 0x0 RW 0x0 Always write zeroes to this bitfield. When an interrupt occurs one of the 128 input requests becomes the winning bit number, i.e. 0 to 127. This bit field selects one of eight constant multiplier values to multiply the winning bit number. The multiplied bit number is added to the vector table base to become the vector address. 0x0 and 0x1 yield a multiplier of 4 bytes. 0x2 yields a multiplier of 8 bytes while 0x3 yields a multiplier of 12 bytes, i.e. (8 + 4) bytes per step. DEFAULT_BY4 = 0x0 one word pitch BY4 = 0x1 one word pitch BY8 = 0x2 two word pitch BY12 = 0x3 three word pitch BY16 = 0x4 four word pitch BY20 = 0x5 five word pitch BY24 = 0x6 six word pitch BY28 = 0x7 seven word pitch 20 BYPASS_FSM RW 0x0 Set this bit to one to bypass the FSM control of the request holding register and the vector address. With this bit set to one, the vector address register is continuously updated as interrupt requests come in. Turn off all enable bits and walk a one through the software interrupts, observing the vector address changes. Set to zero for normal operation. This control is included as a test mode, and is not intended for use by a real application. NORMAL = 0x0 Normal BYPASS = 0x1 no FSM handshake with CPU i.MX23 Applications Processor Reference Manual, Rev. 1 5-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD1 SFTRST Interrupt Collector Table 5-7. HW_ICOLL_CTRL Bit Field Descriptions BITS LABEL 19 NO_NESTING RW RESET RW 0x0 DEFINITION Set this bit to one disable interrupt level nesting, i.e. higher priority interrupt interrupting lower priority. For normal operation, set this bit to zero. NORMAL = 0x0 Normal NO_NEST = 0x1 no support for interrupt nesting 18 ARM_RSE_MODE RW 0x0 17 FIQ_FINAL_ENABLE RW 0x1 Set this bit to one enable the ARM-style read side effect associated with the vector address register. In this mode, interrupt inservice is signalled by the read of the HW_ICOLL_VECTOR register to acquire the interrupt vector address. Set this bit to zero for normal operation, in which the ISR signals inservice explicitly by means of a write to the HW_ICOLL_VECTOR register. Set this bit to one to enable the final FIQ output to the CPU. Set this bit to zero for testing the interrupt collector without causing actual CPU interrupts. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 16 IRQ_FINAL_ENABLE RW 0x1 Set this bit to one to enable the final IRQ output to the CPU. Set this bit to zero for testing the interrupt collector without causing actual CPU interrupts. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 15:0 RSRVD1 RO 0x0 Always write zeroes to this bitfield. DESCRIPTION: This register handles the overall control of the interrupt collector, including soft reset and clock gate. In addition, it handles state machine variations like NO_NESTING and ARM read side effect processing on the vector address register. EXAMPLE: HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST | BM_ICOLL_CTRL_SFTRST ); 5.4.4 Interrupt Collector Interrupt Vector Base Address Register Description This register is used by the priority logic to generate a unique vector address for each of the 80 interrupt request lines coming into the interrupt collector. The vector address is formed by multiply the interrupt bit number by 4 and adding it to the vector base address. HW_ICOLL_VBASE HW_ICOLL_VBASE_SET HW_ICOLL_VBASE_CLR HW_ICOLL_VBASE_TOG 0x040 0x044 0x048 0x04C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-13 Interrupt Collector Table 5-8. HW_ICOLL_VBASE 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 TABLE_ADDRESS 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 5-9. HW_ICOLL_VBASE Bit Field Descriptions BITS LABEL 31:2 TABLE_ADDRESS 1:0 RSRVD1 RW RESET RW 0x0 RO 0x0 DEFINITION This bitfield holds the upper 30 bits of the base address of the vector table. Always write zeroes to this bitfield. DESCRIPTION: This register provides a mechanism to specify the base address of the interrupt vector table. It is used in the compuation of the value supplied in HW_ICOLL_VECTOR register. EXAMPLE: HW_ICOLL_VBASE_WR(pInterruptVectorTable); 5.4.5 Interrupt Collector Status Register Description HW_ICOLL_STAT Table 5-10. HW_ICOLL_STAT 0x070 Read only view into various internal states, including the Vector number of the current interupt. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 VECTOR_NUMBER 0 2 0 1 RSRVD1 0 0 Freescale Semiconductor i.MX23 Applications Processor Reference Manual, Rev. 1 5-14 Preliminary--Subject to Change Without Notice RSRVD1 Interrupt Collector Table 5-11. HW_ICOLL_STAT Bit Field Descriptions BITS LABEL 31:7 RSRVD1 6:0 VECTOR_NUMBER RW RESET RO 0x0 RO 0x7F DEFINITION Always write zeroes to this bitfield. Vector number of current interrupt. Multiply by 4 * HW_ICOLL_CTRL[VECTOR_PITCH] and add to vector base address to obtain the value in HW_ICOLL_VECTOR. DESCRIPTION: This register is used to test interrupt collector state machine and its associated request holding register. EXAMPLE: if(HW_ICOLL_STAT_VECTOR_NUMBER_READ() == 0x00000017) ISR_vector_23(); // ISR for vector 23 decimal, 17 hex 5.4.6 Interrupt Collector Raw Interrupt Input Register 0 Description HW_ICOLL_RAW0 HW_ICOLL_RAW0_SET HW_ICOLL_RAW0_CLR HW_ICOLL_RAW0_TOG Table 5-12. HW_ICOLL_RAW0 0x0A0 0x0A4 0x0A8 0x0AC The lower 32 interrupt hardware-source states are visible in this read-only register. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RAW_IRQS Table 5-13. HW_ICOLL_RAW0 Bit Field Descriptions BITS LABEL 31:0 RAW_IRQS RW RESET RO 0x0 DEFINITION read-only view of the lower 32 hardware interrupt request bits. DESCRIPTION: This register provides a read-only view of the raw interrupt request lines coming from various parts of the chip. Its purpose is to improve diagnostic observability. Note that these only capture the state of hardware interrupt sources. EXAMPLE: ulTest = HW_ICOLL_RAW0.RAW_IRQS; 5.4.7 Interrupt Collector Raw Interrupt Input Register 1 Description HW_ICOLL_RAW1 HW_ICOLL_RAW1_SET HW_ICOLL_RAW1_CLR 0x0B0 0x0B4 0x0B8 Interrupt hardware-source states 32-63 are visible in this read-only register. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-15 Interrupt Collector HW_ICOLL_RAW1_TOG Table 5-14. HW_ICOLL_RAW1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0x0BC 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RAW_IRQS Table 5-15. HW_ICOLL_RAW1 Bit Field Descriptions BITS LABEL 31:0 RAW_IRQS RW RESET RO 0x0 DEFINITION read-only view of hardware interrupt request bits 32-63. DESCRIPTION: This register provides a read-only view of the raw interrupt request lines coming from various parts of the chip. The purpose is to improve diagnostic observability. Note that these only capture the state of hardware interrupt sources. EXAMPLE: ulTest = HW_ICOLL_RAW0.RAW_IRQS; 5.4.8 Interrupt Collector Raw Interrupt Input Register 2 Description HW_ICOLL_RAW2 HW_ICOLL_RAW2_SET HW_ICOLL_RAW2_CLR HW_ICOLL_RAW2_TOG Table 5-16. HW_ICOLL_RAW2 0x0C0 0x0C4 0x0C8 0x0CC Interrupt hardware-source states 64-95 are visible in this read-only register. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RAW_IRQS Table 5-17. HW_ICOLL_RAW2 Bit Field Descriptions BITS LABEL 31:0 RAW_IRQS RW RESET RO 0x0 DEFINITION read-only view of hardware interrupt request bits 64-95. DESCRIPTION: This register provides a read-only view of the raw interrupt request lines coming from various parts of the chip. The purpose is to improve diagnostic observability. Note that these only capture the state of hardware interrupt sources. EXAMPLE: ulTest = HW_ICOLL_RAW0.RAW_IRQS; i.MX23 Applications Processor Reference Manual, Rev. 1 5-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector 5.4.9 Interrupt Collector Raw Interrupt Input Register 3 Description HW_ICOLL_RAW3 HW_ICOLL_RAW3_SET HW_ICOLL_RAW3_CLR HW_ICOLL_RAW3_TOG Table 5-18. HW_ICOLL_RAW3 0x0D0 0x0D4 0x0D8 0x0DC Interrupt hardware-source states 96-127 are visible in this read-only register. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RAW_IRQS Table 5-19. HW_ICOLL_RAW3 Bit Field Descriptions BITS LABEL 31:0 RAW_IRQS RW RESET RO 0x0 DEFINITION read-only view of hardware interrupt request bits 96-127. DESCRIPTION: This register provides a read-only view of the raw interrupt request lines coming from various parts of the chip. The purpose is to improve diagnostic observability. Note that these only capture the state of hardware interrupt sources. EXAMPLE: ulTest = HW_ICOLL_RAW0.RAW_IRQS; 5.4.10 Interrupt Collector Interrupt Register 0 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT0 HW_ICOLL_INTERRUPT0_SET HW_ICOLL_INTERRUPT0_CLR HW_ICOLL_INTERRUPT0_TOG Table 5-20. HW_ICOLL_INTERRUPT0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x120 0x124 0x128 0x12C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-17 Interrupt Collector Table 5-21. HW_ICOLL_INTERRUPT0 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT0_SET(0,0x00000001); 5.4.11 Interrupt Collector Interrupt Register 1 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT1 HW_ICOLL_INTERRUPT1_SET HW_ICOLL_INTERRUPT1_CLR HW_ICOLL_INTERRUPT1_TOG Table 5-22. HW_ICOLL_INTERRUPT1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x130 0x134 0x138 0x13C i.MX23 Applications Processor Reference Manual, Rev. 1 5-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-23. HW_ICOLL_INTERRUPT1 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT1_SET(0,0x00000001); 5.4.12 Interrupt Collector Interrupt Register 2 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT2 HW_ICOLL_INTERRUPT2_SET HW_ICOLL_INTERRUPT2_CLR HW_ICOLL_INTERRUPT2_TOG Table 5-24. HW_ICOLL_INTERRUPT2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x140 0x144 0x148 0x14C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-19 Interrupt Collector Table 5-25. HW_ICOLL_INTERRUPT2 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT2_SET(0,0x00000001); 5.4.13 Interrupt Collector Interrupt Register 3 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT3 HW_ICOLL_INTERRUPT3_SET HW_ICOLL_INTERRUPT3_CLR HW_ICOLL_INTERRUPT3_TOG Table 5-26. HW_ICOLL_INTERRUPT3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x150 0x154 0x158 0x15C i.MX23 Applications Processor Reference Manual, Rev. 1 5-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-27. HW_ICOLL_INTERRUPT3 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT3_SET(0,0x00000001); 5.4.14 Interrupt Collector Interrupt Register 4 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT4 HW_ICOLL_INTERRUPT4_SET HW_ICOLL_INTERRUPT4_CLR HW_ICOLL_INTERRUPT4_TOG Table 5-28. HW_ICOLL_INTERRUPT4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x160 0x164 0x168 0x16C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-21 Interrupt Collector Table 5-29. HW_ICOLL_INTERRUPT4 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT4_SET(0,0x00000001); 5.4.15 Interrupt Collector Interrupt Register 5 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT5 HW_ICOLL_INTERRUPT5_SET HW_ICOLL_INTERRUPT5_CLR HW_ICOLL_INTERRUPT5_TOG Table 5-30. HW_ICOLL_INTERRUPT5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x170 0x174 0x178 0x17C i.MX23 Applications Processor Reference Manual, Rev. 1 5-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-31. HW_ICOLL_INTERRUPT5 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT5_SET(0,0x00000001); 5.4.16 Interrupt Collector Interrupt Register 6 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT6 HW_ICOLL_INTERRUPT6_SET HW_ICOLL_INTERRUPT6_CLR HW_ICOLL_INTERRUPT6_TOG Table 5-32. HW_ICOLL_INTERRUPT6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x180 0x184 0x188 0x18C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-23 Interrupt Collector Table 5-33. HW_ICOLL_INTERRUPT6 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT6_SET(0,0x00000001); 5.4.17 Interrupt Collector Interrupt Register 7 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT7 HW_ICOLL_INTERRUPT7_SET HW_ICOLL_INTERRUPT7_CLR HW_ICOLL_INTERRUPT7_TOG Table 5-34. HW_ICOLL_INTERRUPT7 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x190 0x194 0x198 0x19C i.MX23 Applications Processor Reference Manual, Rev. 1 5-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-35. HW_ICOLL_INTERRUPT7 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT7_SET(0,0x00000001); 5.4.18 Interrupt Collector Interrupt Register 8 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT8 HW_ICOLL_INTERRUPT8_SET HW_ICOLL_INTERRUPT8_CLR HW_ICOLL_INTERRUPT8_TOG Table 5-36. HW_ICOLL_INTERRUPT8 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x1A0 0x1A4 0x1A8 0x1AC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-25 Interrupt Collector Table 5-37. HW_ICOLL_INTERRUPT8 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT8_SET(0,0x00000001); 5.4.19 Interrupt Collector Interrupt Register 9 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT9 HW_ICOLL_INTERRUPT9_SET HW_ICOLL_INTERRUPT9_CLR HW_ICOLL_INTERRUPT9_TOG Table 5-38. HW_ICOLL_INTERRUPT9 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x1B0 0x1B4 0x1B8 0x1BC i.MX23 Applications Processor Reference Manual, Rev. 1 5-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-39. HW_ICOLL_INTERRUPT9 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT9_SET(0,0x00000001); 5.4.20 Interrupt Collector Interrupt Register 10 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT10 HW_ICOLL_INTERRUPT10_SET HW_ICOLL_INTERRUPT10_CLR HW_ICOLL_INTERRUPT10_TOG Table 5-40. HW_ICOLL_INTERRUPT10 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x1C0 0x1C4 0x1C8 0x1CC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-27 Interrupt Collector Table 5-41. HW_ICOLL_INTERRUPT10 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT10_SET(0,0x00000001); 5.4.21 Interrupt Collector Interrupt Register 11 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT11 HW_ICOLL_INTERRUPT11_SET HW_ICOLL_INTERRUPT11_CLR HW_ICOLL_INTERRUPT11_TOG Table 5-42. HW_ICOLL_INTERRUPT11 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x1D0 0x1D4 0x1D8 0x1DC i.MX23 Applications Processor Reference Manual, Rev. 1 5-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-43. HW_ICOLL_INTERRUPT11 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT11_SET(0,0x00000001); 5.4.22 Interrupt Collector Interrupt Register 12 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT12 HW_ICOLL_INTERRUPT12_SET HW_ICOLL_INTERRUPT12_CLR HW_ICOLL_INTERRUPT12_TOG Table 5-44. HW_ICOLL_INTERRUPT12 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x1E0 0x1E4 0x1E8 0x1EC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-29 Interrupt Collector Table 5-45. HW_ICOLL_INTERRUPT12 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT12_SET(0,0x00000001); 5.4.23 Interrupt Collector Interrupt Register 13 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT13 HW_ICOLL_INTERRUPT13_SET HW_ICOLL_INTERRUPT13_CLR HW_ICOLL_INTERRUPT13_TOG Table 5-46. HW_ICOLL_INTERRUPT13 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x1F0 0x1F4 0x1F8 0x1FC i.MX23 Applications Processor Reference Manual, Rev. 1 5-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-47. HW_ICOLL_INTERRUPT13 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT13_SET(0,0x00000001); 5.4.24 Interrupt Collector Interrupt Register 14 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT14 HW_ICOLL_INTERRUPT14_SET HW_ICOLL_INTERRUPT14_CLR HW_ICOLL_INTERRUPT14_TOG Table 5-48. HW_ICOLL_INTERRUPT14 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x200 0x204 0x208 0x20C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-31 Interrupt Collector Table 5-49. HW_ICOLL_INTERRUPT14 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT14_SET(0,0x00000001); 5.4.25 Interrupt Collector Interrupt Register 15 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT15 HW_ICOLL_INTERRUPT15_SET HW_ICOLL_INTERRUPT15_CLR HW_ICOLL_INTERRUPT15_TOG Table 5-50. HW_ICOLL_INTERRUPT15 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x210 0x214 0x218 0x21C i.MX23 Applications Processor Reference Manual, Rev. 1 5-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-51. HW_ICOLL_INTERRUPT15 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT15_SET(0,0x00000001); 5.4.26 Interrupt Collector Interrupt Register 16 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT16 HW_ICOLL_INTERRUPT16_SET HW_ICOLL_INTERRUPT16_CLR HW_ICOLL_INTERRUPT16_TOG Table 5-52. HW_ICOLL_INTERRUPT16 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x220 0x224 0x228 0x22C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-33 Interrupt Collector Table 5-53. HW_ICOLL_INTERRUPT16 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT16_SET(0,0x00000001); 5.4.27 Interrupt Collector Interrupt Register 17 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT17 HW_ICOLL_INTERRUPT17_SET HW_ICOLL_INTERRUPT17_CLR HW_ICOLL_INTERRUPT17_TOG Table 5-54. HW_ICOLL_INTERRUPT17 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x230 0x234 0x238 0x23C i.MX23 Applications Processor Reference Manual, Rev. 1 5-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-55. HW_ICOLL_INTERRUPT17 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT17_SET(0,0x00000001); 5.4.28 Interrupt Collector Interrupt Register 18 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT18 HW_ICOLL_INTERRUPT18_SET HW_ICOLL_INTERRUPT18_CLR HW_ICOLL_INTERRUPT18_TOG Table 5-56. HW_ICOLL_INTERRUPT18 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x240 0x244 0x248 0x24C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-35 Interrupt Collector Table 5-57. HW_ICOLL_INTERRUPT18 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT18_SET(0,0x00000001); 5.4.29 Interrupt Collector Interrupt Register 19 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT19 HW_ICOLL_INTERRUPT19_SET HW_ICOLL_INTERRUPT19_CLR HW_ICOLL_INTERRUPT19_TOG Table 5-58. HW_ICOLL_INTERRUPT19 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x250 0x254 0x258 0x25C i.MX23 Applications Processor Reference Manual, Rev. 1 5-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-59. HW_ICOLL_INTERRUPT19 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT19_SET(0,0x00000001); 5.4.30 Interrupt Collector Interrupt Register 20 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT20 HW_ICOLL_INTERRUPT20_SET HW_ICOLL_INTERRUPT20_CLR HW_ICOLL_INTERRUPT20_TOG Table 5-60. HW_ICOLL_INTERRUPT20 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x260 0x264 0x268 0x26C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-37 Interrupt Collector Table 5-61. HW_ICOLL_INTERRUPT20 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT20_SET(0,0x00000001); 5.4.31 Interrupt Collector Interrupt Register 21 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT21 HW_ICOLL_INTERRUPT21_SET HW_ICOLL_INTERRUPT21_CLR HW_ICOLL_INTERRUPT21_TOG Table 5-62. HW_ICOLL_INTERRUPT21 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x270 0x274 0x278 0x27C i.MX23 Applications Processor Reference Manual, Rev. 1 5-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-63. HW_ICOLL_INTERRUPT21 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT21_SET(0,0x00000001); 5.4.32 Interrupt Collector Interrupt Register 22 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT22 HW_ICOLL_INTERRUPT22_SET HW_ICOLL_INTERRUPT22_CLR HW_ICOLL_INTERRUPT22_TOG Table 5-64. HW_ICOLL_INTERRUPT22 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x280 0x284 0x288 0x28C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-39 Interrupt Collector Table 5-65. HW_ICOLL_INTERRUPT22 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT22_SET(0,0x00000001); 5.4.33 Interrupt Collector Interrupt Register 23 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT23 HW_ICOLL_INTERRUPT23_SET HW_ICOLL_INTERRUPT23_CLR HW_ICOLL_INTERRUPT23_TOG Table 5-66. HW_ICOLL_INTERRUPT23 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x290 0x294 0x298 0x29C i.MX23 Applications Processor Reference Manual, Rev. 1 5-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-67. HW_ICOLL_INTERRUPT23 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT23_SET(0,0x00000001); 5.4.34 Interrupt Collector Interrupt Register 24 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT24 HW_ICOLL_INTERRUPT24_SET HW_ICOLL_INTERRUPT24_CLR HW_ICOLL_INTERRUPT24_TOG Table 5-68. HW_ICOLL_INTERRUPT24 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x2A0 0x2A4 0x2A8 0x2AC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-41 Interrupt Collector Table 5-69. HW_ICOLL_INTERRUPT24 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT24_SET(0,0x00000001); 5.4.35 Interrupt Collector Interrupt Register 25 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT25 HW_ICOLL_INTERRUPT25_SET HW_ICOLL_INTERRUPT25_CLR HW_ICOLL_INTERRUPT25_TOG Table 5-70. HW_ICOLL_INTERRUPT25 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x2B0 0x2B4 0x2B8 0x2BC i.MX23 Applications Processor Reference Manual, Rev. 1 5-42 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-71. HW_ICOLL_INTERRUPT25 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT25_SET(0,0x00000001); 5.4.36 Interrupt Collector Interrupt Register 26 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT26 HW_ICOLL_INTERRUPT26_SET HW_ICOLL_INTERRUPT26_CLR HW_ICOLL_INTERRUPT26_TOG Table 5-72. HW_ICOLL_INTERRUPT26 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x2C0 0x2C4 0x2C8 0x2CC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-43 Interrupt Collector Table 5-73. HW_ICOLL_INTERRUPT26 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT26_SET(0,0x00000001); 5.4.37 Interrupt Collector Interrupt Register 27 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT27 HW_ICOLL_INTERRUPT27_SET HW_ICOLL_INTERRUPT27_CLR HW_ICOLL_INTERRUPT27_TOG Table 5-74. HW_ICOLL_INTERRUPT27 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x2D0 0x2D4 0x2D8 0x2DC i.MX23 Applications Processor Reference Manual, Rev. 1 5-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-75. HW_ICOLL_INTERRUPT27 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT27_SET(0,0x00000001); 5.4.38 Interrupt Collector Interrupt Register 28 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT28 HW_ICOLL_INTERRUPT28_SET HW_ICOLL_INTERRUPT28_CLR HW_ICOLL_INTERRUPT28_TOG Table 5-76. HW_ICOLL_INTERRUPT28 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x2E0 0x2E4 0x2E8 0x2EC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-45 Interrupt Collector Table 5-77. HW_ICOLL_INTERRUPT28 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT28_SET(0,0x00000001); 5.4.39 Interrupt Collector Interrupt Register 29 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT29 HW_ICOLL_INTERRUPT29_SET HW_ICOLL_INTERRUPT29_CLR HW_ICOLL_INTERRUPT29_TOG Table 5-78. HW_ICOLL_INTERRUPT29 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x2F0 0x2F4 0x2F8 0x2FC i.MX23 Applications Processor Reference Manual, Rev. 1 5-46 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-79. HW_ICOLL_INTERRUPT29 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT29_SET(0,0x00000001); 5.4.40 Interrupt Collector Interrupt Register 30 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT30 HW_ICOLL_INTERRUPT30_SET HW_ICOLL_INTERRUPT30_CLR HW_ICOLL_INTERRUPT30_TOG Table 5-80. HW_ICOLL_INTERRUPT30 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x300 0x304 0x308 0x30C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-47 Interrupt Collector Table 5-81. HW_ICOLL_INTERRUPT30 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT30_SET(0,0x00000001); 5.4.41 Interrupt Collector Interrupt Register 31 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT31 HW_ICOLL_INTERRUPT31_SET HW_ICOLL_INTERRUPT31_CLR HW_ICOLL_INTERRUPT31_TOG Table 5-82. HW_ICOLL_INTERRUPT31 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x310 0x314 0x318 0x31C i.MX23 Applications Processor Reference Manual, Rev. 1 5-48 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-83. HW_ICOLL_INTERRUPT31 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT31_SET(0,0x00000001); 5.4.42 Interrupt Collector Interrupt Register 32 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT32 HW_ICOLL_INTERRUPT32_SET HW_ICOLL_INTERRUPT32_CLR HW_ICOLL_INTERRUPT32_TOG Table 5-84. HW_ICOLL_INTERRUPT32 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x320 0x324 0x328 0x32C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-49 Interrupt Collector Table 5-85. HW_ICOLL_INTERRUPT32 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT32_SET(0,0x00000001); 5.4.43 Interrupt Collector Interrupt Register 33 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT33 HW_ICOLL_INTERRUPT33_SET HW_ICOLL_INTERRUPT33_CLR HW_ICOLL_INTERRUPT33_TOG Table 5-86. HW_ICOLL_INTERRUPT33 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x330 0x334 0x338 0x33C i.MX23 Applications Processor Reference Manual, Rev. 1 5-50 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-87. HW_ICOLL_INTERRUPT33 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT33_SET(0,0x00000001); 5.4.44 Interrupt Collector Interrupt Register 34 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT34 HW_ICOLL_INTERRUPT34_SET HW_ICOLL_INTERRUPT34_CLR HW_ICOLL_INTERRUPT34_TOG Table 5-88. HW_ICOLL_INTERRUPT34 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x340 0x344 0x348 0x34C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-51 Interrupt Collector Table 5-89. HW_ICOLL_INTERRUPT34 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT34_SET(0,0x00000001); 5.4.45 Interrupt Collector Interrupt Register 35 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT35 HW_ICOLL_INTERRUPT35_SET HW_ICOLL_INTERRUPT35_CLR HW_ICOLL_INTERRUPT35_TOG Table 5-90. HW_ICOLL_INTERRUPT35 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x350 0x354 0x358 0x35C i.MX23 Applications Processor Reference Manual, Rev. 1 5-52 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-91. HW_ICOLL_INTERRUPT35 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT35_SET(0,0x00000001); 5.4.46 Interrupt Collector Interrupt Register 36 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT36 HW_ICOLL_INTERRUPT36_SET HW_ICOLL_INTERRUPT36_CLR HW_ICOLL_INTERRUPT36_TOG Table 5-92. HW_ICOLL_INTERRUPT36 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x360 0x364 0x368 0x36C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-53 Interrupt Collector Table 5-93. HW_ICOLL_INTERRUPT36 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT36_SET(0,0x00000001); 5.4.47 Interrupt Collector Interrupt Register 37 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT37 HW_ICOLL_INTERRUPT37_SET HW_ICOLL_INTERRUPT37_CLR HW_ICOLL_INTERRUPT37_TOG Table 5-94. HW_ICOLL_INTERRUPT37 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x370 0x374 0x378 0x37C i.MX23 Applications Processor Reference Manual, Rev. 1 5-54 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-95. HW_ICOLL_INTERRUPT37 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT37_SET(0,0x00000001); 5.4.48 Interrupt Collector Interrupt Register 38 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT38 HW_ICOLL_INTERRUPT38_SET HW_ICOLL_INTERRUPT38_CLR HW_ICOLL_INTERRUPT38_TOG Table 5-96. HW_ICOLL_INTERRUPT38 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x380 0x384 0x388 0x38C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-55 Interrupt Collector Table 5-97. HW_ICOLL_INTERRUPT38 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT38_SET(0,0x00000001); 5.4.49 Interrupt Collector Interrupt Register 39 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT39 HW_ICOLL_INTERRUPT39_SET HW_ICOLL_INTERRUPT39_CLR HW_ICOLL_INTERRUPT39_TOG Table 5-98. HW_ICOLL_INTERRUPT39 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 0x390 0x394 0x398 0x39C i.MX23 Applications Processor Reference Manual, Rev. 1 5-56 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-99. HW_ICOLL_INTERRUPT39 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT39_SET(0,0x00000001); 5.4.50 Interrupt Collector Interrupt Register 40 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT40 HW_ICOLL_INTERRUPT40_SET HW_ICOLL_INTERRUPT40_CLR HW_ICOLL_INTERRUPT40_TOG 0x3A0 0x3A4 0x3A8 0x3AC Table 5-100. HW_ICOLL_INTERRUPT40 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-57 Interrupt Collector Table 5-101. HW_ICOLL_INTERRUPT40 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT40_SET(0,0x00000001); 5.4.51 Interrupt Collector Interrupt Register 41 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT41 HW_ICOLL_INTERRUPT41_SET HW_ICOLL_INTERRUPT41_CLR HW_ICOLL_INTERRUPT41_TOG 0x3B0 0x3B4 0x3B8 0x3BC Table 5-102. HW_ICOLL_INTERRUPT41 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-58 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-103. HW_ICOLL_INTERRUPT41 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT41_SET(0,0x00000001); 5.4.52 Interrupt Collector Interrupt Register 42 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT42 HW_ICOLL_INTERRUPT42_SET HW_ICOLL_INTERRUPT42_CLR HW_ICOLL_INTERRUPT42_TOG 0x3C0 0x3C4 0x3C8 0x3CC Table 5-104. HW_ICOLL_INTERRUPT42 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-59 Interrupt Collector Table 5-105. HW_ICOLL_INTERRUPT42 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT42_SET(0,0x00000001); 5.4.53 Interrupt Collector Interrupt Register 43 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT43 HW_ICOLL_INTERRUPT43_SET HW_ICOLL_INTERRUPT43_CLR HW_ICOLL_INTERRUPT43_TOG 0x3D0 0x3D4 0x3D8 0x3DC Table 5-106. HW_ICOLL_INTERRUPT43 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-60 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-107. HW_ICOLL_INTERRUPT43 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT43_SET(0,0x00000001); 5.4.54 Interrupt Collector Interrupt Register 44 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT44 HW_ICOLL_INTERRUPT44_SET HW_ICOLL_INTERRUPT44_CLR HW_ICOLL_INTERRUPT44_TOG 0x3E0 0x3E4 0x3E8 0x3EC Table 5-108. HW_ICOLL_INTERRUPT44 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-61 Interrupt Collector Table 5-109. HW_ICOLL_INTERRUPT44 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT44_SET(0,0x00000001); 5.4.55 Interrupt Collector Interrupt Register 45 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT45 HW_ICOLL_INTERRUPT45_SET HW_ICOLL_INTERRUPT45_CLR HW_ICOLL_INTERRUPT45_TOG 0x3F0 0x3F4 0x3F8 0x3FC Table 5-110. HW_ICOLL_INTERRUPT45 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-62 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-111. HW_ICOLL_INTERRUPT45 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT45_SET(0,0x00000001); 5.4.56 Interrupt Collector Interrupt Register 46 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT46 HW_ICOLL_INTERRUPT46_SET HW_ICOLL_INTERRUPT46_CLR HW_ICOLL_INTERRUPT46_TOG 0x400 0x404 0x408 0x40C Table 5-112. HW_ICOLL_INTERRUPT46 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-63 Interrupt Collector Table 5-113. HW_ICOLL_INTERRUPT46 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT46_SET(0,0x00000001); 5.4.57 Interrupt Collector Interrupt Register 47 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT47 HW_ICOLL_INTERRUPT47_SET HW_ICOLL_INTERRUPT47_CLR HW_ICOLL_INTERRUPT47_TOG 0x410 0x414 0x418 0x41C Table 5-114. HW_ICOLL_INTERRUPT47 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-64 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-115. HW_ICOLL_INTERRUPT47 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT47_SET(0,0x00000001); 5.4.58 Interrupt Collector Interrupt Register 48 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT48 HW_ICOLL_INTERRUPT48_SET HW_ICOLL_INTERRUPT48_CLR HW_ICOLL_INTERRUPT48_TOG 0x420 0x424 0x428 0x42C Table 5-116. HW_ICOLL_INTERRUPT48 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-65 Interrupt Collector Table 5-117. HW_ICOLL_INTERRUPT48 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT48_SET(0,0x00000001); 5.4.59 Interrupt Collector Interrupt Register 49 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT49 HW_ICOLL_INTERRUPT49_SET HW_ICOLL_INTERRUPT49_CLR HW_ICOLL_INTERRUPT49_TOG 0x430 0x434 0x438 0x43C Table 5-118. HW_ICOLL_INTERRUPT49 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-66 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-119. HW_ICOLL_INTERRUPT49 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT49_SET(0,0x00000001); 5.4.60 Interrupt Collector Interrupt Register 50 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT50 HW_ICOLL_INTERRUPT50_SET HW_ICOLL_INTERRUPT50_CLR HW_ICOLL_INTERRUPT50_TOG 0x440 0x444 0x448 0x44C Table 5-120. HW_ICOLL_INTERRUPT50 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-67 Interrupt Collector Table 5-121. HW_ICOLL_INTERRUPT50 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT50_SET(0,0x00000001); 5.4.61 Interrupt Collector Interrupt Register 51 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT51 HW_ICOLL_INTERRUPT51_SET HW_ICOLL_INTERRUPT51_CLR HW_ICOLL_INTERRUPT51_TOG 0x450 0x454 0x458 0x45C Table 5-122. HW_ICOLL_INTERRUPT51 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-68 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-123. HW_ICOLL_INTERRUPT51 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT51_SET(0,0x00000001); 5.4.62 Interrupt Collector Interrupt Register 52 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT52 HW_ICOLL_INTERRUPT52_SET HW_ICOLL_INTERRUPT52_CLR HW_ICOLL_INTERRUPT52_TOG 0x460 0x464 0x468 0x46C Table 5-124. HW_ICOLL_INTERRUPT52 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-69 Interrupt Collector Table 5-125. HW_ICOLL_INTERRUPT52 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT52_SET(0,0x00000001); 5.4.63 Interrupt Collector Interrupt Register 53 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT53 HW_ICOLL_INTERRUPT53_SET HW_ICOLL_INTERRUPT53_CLR HW_ICOLL_INTERRUPT53_TOG 0x470 0x474 0x478 0x47C Table 5-126. HW_ICOLL_INTERRUPT53 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-70 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-127. HW_ICOLL_INTERRUPT53 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT53_SET(0,0x00000001); 5.4.64 Interrupt Collector Interrupt Register 54 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT54 HW_ICOLL_INTERRUPT54_SET HW_ICOLL_INTERRUPT54_CLR HW_ICOLL_INTERRUPT54_TOG 0x480 0x484 0x488 0x48C Table 5-128. HW_ICOLL_INTERRUPT54 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-71 Interrupt Collector Table 5-129. HW_ICOLL_INTERRUPT54 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT54_SET(0,0x00000001); 5.4.65 Interrupt Collector Interrupt Register 55 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT55 HW_ICOLL_INTERRUPT55_SET HW_ICOLL_INTERRUPT55_CLR HW_ICOLL_INTERRUPT55_TOG 0x490 0x494 0x498 0x49C Table 5-130. HW_ICOLL_INTERRUPT55 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-72 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-131. HW_ICOLL_INTERRUPT55 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT55_SET(0,0x00000001); 5.4.66 Interrupt Collector Interrupt Register 56 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT56 HW_ICOLL_INTERRUPT56_SET HW_ICOLL_INTERRUPT56_CLR HW_ICOLL_INTERRUPT56_TOG 0x4A0 0x4A4 0x4A8 0x4AC Table 5-132. HW_ICOLL_INTERRUPT56 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-73 Interrupt Collector Table 5-133. HW_ICOLL_INTERRUPT56 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT56_SET(0,0x00000001); 5.4.67 Interrupt Collector Interrupt Register 57 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT57 HW_ICOLL_INTERRUPT57_SET HW_ICOLL_INTERRUPT57_CLR HW_ICOLL_INTERRUPT57_TOG 0x4B0 0x4B4 0x4B8 0x4BC Table 5-134. HW_ICOLL_INTERRUPT57 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-74 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-135. HW_ICOLL_INTERRUPT57 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT57_SET(0,0x00000001); 5.4.68 Interrupt Collector Interrupt Register 58 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT58 HW_ICOLL_INTERRUPT58_SET HW_ICOLL_INTERRUPT58_CLR HW_ICOLL_INTERRUPT58_TOG 0x4C0 0x4C4 0x4C8 0x4CC Table 5-136. HW_ICOLL_INTERRUPT58 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-75 Interrupt Collector Table 5-137. HW_ICOLL_INTERRUPT58 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT58_SET(0,0x00000001); 5.4.69 Interrupt Collector Interrupt Register 59 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT59 HW_ICOLL_INTERRUPT59_SET HW_ICOLL_INTERRUPT59_CLR HW_ICOLL_INTERRUPT59_TOG 0x4D0 0x4D4 0x4D8 0x4DC Table 5-138. HW_ICOLL_INTERRUPT59 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-76 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-139. HW_ICOLL_INTERRUPT59 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT59_SET(0,0x00000001); 5.4.70 Interrupt Collector Interrupt Register 60 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT60 HW_ICOLL_INTERRUPT60_SET HW_ICOLL_INTERRUPT60_CLR HW_ICOLL_INTERRUPT60_TOG 0x4E0 0x4E4 0x4E8 0x4EC Table 5-140. HW_ICOLL_INTERRUPT60 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-77 Interrupt Collector Table 5-141. HW_ICOLL_INTERRUPT60 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT60_SET(0,0x00000001); 5.4.71 Interrupt Collector Interrupt Register 61 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT61 HW_ICOLL_INTERRUPT61_SET HW_ICOLL_INTERRUPT61_CLR HW_ICOLL_INTERRUPT61_TOG 0x4F0 0x4F4 0x4F8 0x4FC Table 5-142. HW_ICOLL_INTERRUPT61 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-78 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-143. HW_ICOLL_INTERRUPT61 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT61_SET(0,0x00000001); 5.4.72 Interrupt Collector Interrupt Register 62 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT62 HW_ICOLL_INTERRUPT62_SET HW_ICOLL_INTERRUPT62_CLR HW_ICOLL_INTERRUPT62_TOG 0x500 0x504 0x508 0x50C Table 5-144. HW_ICOLL_INTERRUPT62 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-79 Interrupt Collector Table 5-145. HW_ICOLL_INTERRUPT62 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT62_SET(0,0x00000001); 5.4.73 Interrupt Collector Interrupt Register 63 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT63 HW_ICOLL_INTERRUPT63_SET HW_ICOLL_INTERRUPT63_CLR HW_ICOLL_INTERRUPT63_TOG 0x510 0x514 0x518 0x51C Table 5-146. HW_ICOLL_INTERRUPT63 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-80 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-147. HW_ICOLL_INTERRUPT63 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT63_SET(0,0x00000001); 5.4.74 Interrupt Collector Interrupt Register 64 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT64 HW_ICOLL_INTERRUPT64_SET HW_ICOLL_INTERRUPT64_CLR HW_ICOLL_INTERRUPT64_TOG 0x520 0x524 0x528 0x52C Table 5-148. HW_ICOLL_INTERRUPT64 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-81 Interrupt Collector Table 5-149. HW_ICOLL_INTERRUPT64 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT64_SET(0,0x00000001); 5.4.75 Interrupt Collector Interrupt Register 65 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT65 HW_ICOLL_INTERRUPT65_SET HW_ICOLL_INTERRUPT65_CLR HW_ICOLL_INTERRUPT65_TOG 0x530 0x534 0x538 0x53C Table 5-150. HW_ICOLL_INTERRUPT65 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-82 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-151. HW_ICOLL_INTERRUPT65 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT65_SET(0,0x00000001); 5.4.76 Interrupt Collector Interrupt Register 66 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT66 HW_ICOLL_INTERRUPT66_SET HW_ICOLL_INTERRUPT66_CLR HW_ICOLL_INTERRUPT66_TOG 0x540 0x544 0x548 0x54C Table 5-152. HW_ICOLL_INTERRUPT66 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-83 Interrupt Collector Table 5-153. HW_ICOLL_INTERRUPT66 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT66_SET(0,0x00000001); 5.4.77 Interrupt Collector Interrupt Register 67 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT67 HW_ICOLL_INTERRUPT67_SET HW_ICOLL_INTERRUPT67_CLR HW_ICOLL_INTERRUPT67_TOG 0x550 0x554 0x558 0x55C Table 5-154. HW_ICOLL_INTERRUPT67 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-84 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-155. HW_ICOLL_INTERRUPT67 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT67_SET(0,0x00000001); 5.4.78 Interrupt Collector Interrupt Register 68 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT68 HW_ICOLL_INTERRUPT68_SET HW_ICOLL_INTERRUPT68_CLR HW_ICOLL_INTERRUPT68_TOG 0x560 0x564 0x568 0x56C Table 5-156. HW_ICOLL_INTERRUPT68 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-85 Interrupt Collector Table 5-157. HW_ICOLL_INTERRUPT68 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT68_SET(0,0x00000001); 5.4.79 Interrupt Collector Interrupt Register 69 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT69 HW_ICOLL_INTERRUPT69_SET HW_ICOLL_INTERRUPT69_CLR HW_ICOLL_INTERRUPT69_TOG 0x570 0x574 0x578 0x57C Table 5-158. HW_ICOLL_INTERRUPT69 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-86 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-159. HW_ICOLL_INTERRUPT69 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT69_SET(0,0x00000001); 5.4.80 Interrupt Collector Interrupt Register 70 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT70 HW_ICOLL_INTERRUPT70_SET HW_ICOLL_INTERRUPT70_CLR HW_ICOLL_INTERRUPT70_TOG 0x580 0x584 0x588 0x58C Table 5-160. HW_ICOLL_INTERRUPT70 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-87 Interrupt Collector Table 5-161. HW_ICOLL_INTERRUPT70 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT70_SET(0,0x00000001); 5.4.81 Interrupt Collector Interrupt Register 71 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT71 HW_ICOLL_INTERRUPT71_SET HW_ICOLL_INTERRUPT71_CLR HW_ICOLL_INTERRUPT71_TOG 0x590 0x594 0x598 0x59C Table 5-162. HW_ICOLL_INTERRUPT71 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-88 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-163. HW_ICOLL_INTERRUPT71 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT71_SET(0,0x00000001); 5.4.82 Interrupt Collector Interrupt Register 72 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT72 HW_ICOLL_INTERRUPT72_SET HW_ICOLL_INTERRUPT72_CLR HW_ICOLL_INTERRUPT72_TOG 0x5A0 0x5A4 0x5A8 0x5AC Table 5-164. HW_ICOLL_INTERRUPT72 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-89 Interrupt Collector Table 5-165. HW_ICOLL_INTERRUPT72 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT72_SET(0,0x00000001); 5.4.83 Interrupt Collector Interrupt Register 73 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT73 HW_ICOLL_INTERRUPT73_SET HW_ICOLL_INTERRUPT73_CLR HW_ICOLL_INTERRUPT73_TOG 0x5B0 0x5B4 0x5B8 0x5BC Table 5-166. HW_ICOLL_INTERRUPT73 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-90 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-167. HW_ICOLL_INTERRUPT73 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT73_SET(0,0x00000001); 5.4.84 Interrupt Collector Interrupt Register 74 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT74 HW_ICOLL_INTERRUPT74_SET HW_ICOLL_INTERRUPT74_CLR HW_ICOLL_INTERRUPT74_TOG 0x5C0 0x5C4 0x5C8 0x5CC Table 5-168. HW_ICOLL_INTERRUPT74 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-91 Interrupt Collector Table 5-169. HW_ICOLL_INTERRUPT74 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT74_SET(0,0x00000001); 5.4.85 Interrupt Collector Interrupt Register 75 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT75 HW_ICOLL_INTERRUPT75_SET HW_ICOLL_INTERRUPT75_CLR HW_ICOLL_INTERRUPT75_TOG 0x5D0 0x5D4 0x5D8 0x5DC Table 5-170. HW_ICOLL_INTERRUPT75 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-92 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-171. HW_ICOLL_INTERRUPT75 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT75_SET(0,0x00000001); 5.4.86 Interrupt Collector Interrupt Register 76 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT76 HW_ICOLL_INTERRUPT76_SET HW_ICOLL_INTERRUPT76_CLR HW_ICOLL_INTERRUPT76_TOG 0x5E0 0x5E4 0x5E8 0x5EC Table 5-172. HW_ICOLL_INTERRUPT76 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-93 Interrupt Collector Table 5-173. HW_ICOLL_INTERRUPT76 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT76_SET(0,0x00000001); 5.4.87 Interrupt Collector Interrupt Register 77 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT77 HW_ICOLL_INTERRUPT77_SET HW_ICOLL_INTERRUPT77_CLR HW_ICOLL_INTERRUPT77_TOG 0x5F0 0x5F4 0x5F8 0x5FC Table 5-174. HW_ICOLL_INTERRUPT77 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-94 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-175. HW_ICOLL_INTERRUPT77 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT77_SET(0,0x00000001); 5.4.88 Interrupt Collector Interrupt Register 78 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT78 HW_ICOLL_INTERRUPT78_SET HW_ICOLL_INTERRUPT78_CLR HW_ICOLL_INTERRUPT78_TOG 0x600 0x604 0x608 0x60C Table 5-176. HW_ICOLL_INTERRUPT78 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-95 Interrupt Collector Table 5-177. HW_ICOLL_INTERRUPT78 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT78_SET(0,0x00000001); 5.4.89 Interrupt Collector Interrupt Register 79 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT79 HW_ICOLL_INTERRUPT79_SET HW_ICOLL_INTERRUPT79_CLR HW_ICOLL_INTERRUPT79_TOG 0x610 0x614 0x618 0x61C Table 5-178. HW_ICOLL_INTERRUPT79 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-96 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-179. HW_ICOLL_INTERRUPT79 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT79_SET(0,0x00000001); 5.4.90 Interrupt Collector Interrupt Register 80 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT80 HW_ICOLL_INTERRUPT80_SET HW_ICOLL_INTERRUPT80_CLR HW_ICOLL_INTERRUPT80_TOG 0x620 0x624 0x628 0x62C Table 5-180. HW_ICOLL_INTERRUPT80 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-97 Interrupt Collector Table 5-181. HW_ICOLL_INTERRUPT80 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT80_SET(0,0x00000001); 5.4.91 Interrupt Collector Interrupt Register 81 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT81 HW_ICOLL_INTERRUPT81_SET HW_ICOLL_INTERRUPT81_CLR HW_ICOLL_INTERRUPT81_TOG 0x630 0x634 0x638 0x63C Table 5-182. HW_ICOLL_INTERRUPT81 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-98 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-183. HW_ICOLL_INTERRUPT81 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT81_SET(0,0x00000001); 5.4.92 Interrupt Collector Interrupt Register 82 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT82 HW_ICOLL_INTERRUPT82_SET HW_ICOLL_INTERRUPT82_CLR HW_ICOLL_INTERRUPT82_TOG 0x640 0x644 0x648 0x64C Table 5-184. HW_ICOLL_INTERRUPT82 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-99 Interrupt Collector Table 5-185. HW_ICOLL_INTERRUPT82 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT82_SET(0,0x00000001); 5.4.93 Interrupt Collector Interrupt Register 83 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT83 HW_ICOLL_INTERRUPT83_SET HW_ICOLL_INTERRUPT83_CLR HW_ICOLL_INTERRUPT83_TOG 0x650 0x654 0x658 0x65C Table 5-186. HW_ICOLL_INTERRUPT83 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-100 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-187. HW_ICOLL_INTERRUPT83 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT83_SET(0,0x00000001); 5.4.94 Interrupt Collector Interrupt Register 84 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT84 HW_ICOLL_INTERRUPT84_SET HW_ICOLL_INTERRUPT84_CLR HW_ICOLL_INTERRUPT84_TOG 0x660 0x664 0x668 0x66C Table 5-188. HW_ICOLL_INTERRUPT84 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-101 Interrupt Collector Table 5-189. HW_ICOLL_INTERRUPT84 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT84_SET(0,0x00000001); 5.4.95 Interrupt Collector Interrupt Register 85 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT85 HW_ICOLL_INTERRUPT85_SET HW_ICOLL_INTERRUPT85_CLR HW_ICOLL_INTERRUPT85_TOG 0x670 0x674 0x678 0x67C Table 5-190. HW_ICOLL_INTERRUPT85 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-102 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-191. HW_ICOLL_INTERRUPT85 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT85_SET(0,0x00000001); 5.4.96 Interrupt Collector Interrupt Register 86 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT86 HW_ICOLL_INTERRUPT86_SET HW_ICOLL_INTERRUPT86_CLR HW_ICOLL_INTERRUPT86_TOG 0x680 0x684 0x688 0x68C Table 5-192. HW_ICOLL_INTERRUPT86 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-103 Interrupt Collector Table 5-193. HW_ICOLL_INTERRUPT86 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT86_SET(0,0x00000001); 5.4.97 Interrupt Collector Interrupt Register 87 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT87 HW_ICOLL_INTERRUPT87_SET HW_ICOLL_INTERRUPT87_CLR HW_ICOLL_INTERRUPT87_TOG 0x690 0x694 0x698 0x69C Table 5-194. HW_ICOLL_INTERRUPT87 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-104 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-195. HW_ICOLL_INTERRUPT87 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT87_SET(0,0x00000001); 5.4.98 Interrupt Collector Interrupt Register 88 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT88 HW_ICOLL_INTERRUPT88_SET HW_ICOLL_INTERRUPT88_CLR HW_ICOLL_INTERRUPT88_TOG 0x6A0 0x6A4 0x6A8 0x6AC Table 5-196. HW_ICOLL_INTERRUPT88 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-105 Interrupt Collector Table 5-197. HW_ICOLL_INTERRUPT88 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT88_SET(0,0x00000001); 5.4.99 Interrupt Collector Interrupt Register 89 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT89 HW_ICOLL_INTERRUPT89_SET HW_ICOLL_INTERRUPT89_CLR HW_ICOLL_INTERRUPT89_TOG 0x6B0 0x6B4 0x6B8 0x6BC Table 5-198. HW_ICOLL_INTERRUPT89 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-106 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-199. HW_ICOLL_INTERRUPT89 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT89_SET(0,0x00000001); 5.4.100 Interrupt Collector Interrupt Register 90 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT90 HW_ICOLL_INTERRUPT90_SET HW_ICOLL_INTERRUPT90_CLR HW_ICOLL_INTERRUPT90_TOG 0x6C0 0x6C4 0x6C8 0x6CC Table 5-200. HW_ICOLL_INTERRUPT90 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-107 Interrupt Collector Table 5-201. HW_ICOLL_INTERRUPT90 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT90_SET(0,0x00000001); 5.4.101 Interrupt Collector Interrupt Register 91 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT91 HW_ICOLL_INTERRUPT91_SET HW_ICOLL_INTERRUPT91_CLR HW_ICOLL_INTERRUPT91_TOG 0x6D0 0x6D4 0x6D8 0x6DC Table 5-202. HW_ICOLL_INTERRUPT91 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-108 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-203. HW_ICOLL_INTERRUPT91 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT91_SET(0,0x00000001); 5.4.102 Interrupt Collector Interrupt Register 92 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT92 HW_ICOLL_INTERRUPT92_SET HW_ICOLL_INTERRUPT92_CLR HW_ICOLL_INTERRUPT92_TOG 0x6E0 0x6E4 0x6E8 0x6EC Table 5-204. HW_ICOLL_INTERRUPT92 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-109 Interrupt Collector Table 5-205. HW_ICOLL_INTERRUPT92 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT92_SET(0,0x00000001); 5.4.103 Interrupt Collector Interrupt Register 93 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT93 HW_ICOLL_INTERRUPT93_SET HW_ICOLL_INTERRUPT93_CLR HW_ICOLL_INTERRUPT93_TOG 0x6F0 0x6F4 0x6F8 0x6FC Table 5-206. HW_ICOLL_INTERRUPT93 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-110 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-207. HW_ICOLL_INTERRUPT93 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT93_SET(0,0x00000001); 5.4.104 Interrupt Collector Interrupt Register 94 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT94 HW_ICOLL_INTERRUPT94_SET HW_ICOLL_INTERRUPT94_CLR HW_ICOLL_INTERRUPT94_TOG 0x700 0x704 0x708 0x70C Table 5-208. HW_ICOLL_INTERRUPT94 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-111 Interrupt Collector Table 5-209. HW_ICOLL_INTERRUPT94 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT94_SET(0,0x00000001); 5.4.105 Interrupt Collector Interrupt Register 95 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT95 HW_ICOLL_INTERRUPT95_SET HW_ICOLL_INTERRUPT95_CLR HW_ICOLL_INTERRUPT95_TOG 0x710 0x714 0x718 0x71C Table 5-210. HW_ICOLL_INTERRUPT95 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-112 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-211. HW_ICOLL_INTERRUPT95 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT95_SET(0,0x00000001); 5.4.106 Interrupt Collector Interrupt Register 96 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT96 HW_ICOLL_INTERRUPT96_SET HW_ICOLL_INTERRUPT96_CLR HW_ICOLL_INTERRUPT96_TOG 0x720 0x724 0x728 0x72C Table 5-212. HW_ICOLL_INTERRUPT96 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-113 Interrupt Collector Table 5-213. HW_ICOLL_INTERRUPT96 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT96_SET(0,0x00000001); 5.4.107 Interrupt Collector Interrupt Register 97 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT97 HW_ICOLL_INTERRUPT97_SET HW_ICOLL_INTERRUPT97_CLR HW_ICOLL_INTERRUPT97_TOG 0x730 0x734 0x738 0x73C Table 5-214. HW_ICOLL_INTERRUPT97 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-114 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-215. HW_ICOLL_INTERRUPT97 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT97_SET(0,0x00000001); 5.4.108 Interrupt Collector Interrupt Register 98 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT98 HW_ICOLL_INTERRUPT98_SET HW_ICOLL_INTERRUPT98_CLR HW_ICOLL_INTERRUPT98_TOG 0x740 0x744 0x748 0x74C Table 5-216. HW_ICOLL_INTERRUPT98 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-115 Interrupt Collector Table 5-217. HW_ICOLL_INTERRUPT98 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT98_SET(0,0x00000001); 5.4.109 Interrupt Collector Interrupt Register 99 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT99 HW_ICOLL_INTERRUPT99_SET HW_ICOLL_INTERRUPT99_CLR HW_ICOLL_INTERRUPT99_TOG 0x750 0x754 0x758 0x75C Table 5-218. HW_ICOLL_INTERRUPT99 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-116 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-219. HW_ICOLL_INTERRUPT99 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT99_SET(0,0x00000001); 5.4.110 Interrupt Collector Interrupt Register 100 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT100 HW_ICOLL_INTERRUPT100_SET HW_ICOLL_INTERRUPT100_CLR HW_ICOLL_INTERRUPT100_TOG 0x760 0x764 0x768 0x76C Table 5-220. HW_ICOLL_INTERRUPT100 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-117 Interrupt Collector Table 5-221. HW_ICOLL_INTERRUPT100 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT100_SET(0,0x00000001); 5.4.111 Interrupt Collector Interrupt Register 101 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT101 HW_ICOLL_INTERRUPT101_SET HW_ICOLL_INTERRUPT101_CLR HW_ICOLL_INTERRUPT101_TOG 0x770 0x774 0x778 0x77C Table 5-222. HW_ICOLL_INTERRUPT101 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-118 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-223. HW_ICOLL_INTERRUPT101 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT101_SET(0,0x00000001); 5.4.112 Interrupt Collector Interrupt Register 102 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT102 HW_ICOLL_INTERRUPT102_SET HW_ICOLL_INTERRUPT102_CLR HW_ICOLL_INTERRUPT102_TOG 0x780 0x784 0x788 0x78C Table 5-224. HW_ICOLL_INTERRUPT102 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-119 Interrupt Collector Table 5-225. HW_ICOLL_INTERRUPT102 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT102_SET(0,0x00000001); 5.4.113 Interrupt Collector Interrupt Register 103 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT103 HW_ICOLL_INTERRUPT103_SET HW_ICOLL_INTERRUPT103_CLR HW_ICOLL_INTERRUPT103_TOG 0x790 0x794 0x798 0x79C Table 5-226. HW_ICOLL_INTERRUPT103 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-120 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-227. HW_ICOLL_INTERRUPT103 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT103_SET(0,0x00000001); 5.4.114 Interrupt Collector Interrupt Register 104 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT104 HW_ICOLL_INTERRUPT104_SET HW_ICOLL_INTERRUPT104_CLR HW_ICOLL_INTERRUPT104_TOG 0x7A0 0x7A4 0x7A8 0x7AC Table 5-228. HW_ICOLL_INTERRUPT104 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-121 Interrupt Collector Table 5-229. HW_ICOLL_INTERRUPT104 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT104_SET(0,0x00000001); 5.4.115 Interrupt Collector Interrupt Register 105 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT105 HW_ICOLL_INTERRUPT105_SET HW_ICOLL_INTERRUPT105_CLR HW_ICOLL_INTERRUPT105_TOG 0x7B0 0x7B4 0x7B8 0x7BC Table 5-230. HW_ICOLL_INTERRUPT105 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-122 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-231. HW_ICOLL_INTERRUPT105 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT105_SET(0,0x00000001); 5.4.116 Interrupt Collector Interrupt Register 106 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT106 HW_ICOLL_INTERRUPT106_SET HW_ICOLL_INTERRUPT106_CLR HW_ICOLL_INTERRUPT106_TOG 0x7C0 0x7C4 0x7C8 0x7CC Table 5-232. HW_ICOLL_INTERRUPT106 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-123 Interrupt Collector Table 5-233. HW_ICOLL_INTERRUPT106 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT106_SET(0,0x00000001); 5.4.117 Interrupt Collector Interrupt Register 107 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT107 HW_ICOLL_INTERRUPT107_SET HW_ICOLL_INTERRUPT107_CLR HW_ICOLL_INTERRUPT107_TOG 0x7D0 0x7D4 0x7D8 0x7DC Table 5-234. HW_ICOLL_INTERRUPT107 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-124 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-235. HW_ICOLL_INTERRUPT107 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT107_SET(0,0x00000001); 5.4.118 Interrupt Collector Interrupt Register 108 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT108 HW_ICOLL_INTERRUPT108_SET HW_ICOLL_INTERRUPT108_CLR HW_ICOLL_INTERRUPT108_TOG 0x7E0 0x7E4 0x7E8 0x7EC Table 5-236. HW_ICOLL_INTERRUPT108 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-125 Interrupt Collector Table 5-237. HW_ICOLL_INTERRUPT108 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT108_SET(0,0x00000001); 5.4.119 Interrupt Collector Interrupt Register 109 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT109 HW_ICOLL_INTERRUPT109_SET HW_ICOLL_INTERRUPT109_CLR HW_ICOLL_INTERRUPT109_TOG 0x7F0 0x7F4 0x7F8 0x7FC Table 5-238. HW_ICOLL_INTERRUPT109 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-126 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-239. HW_ICOLL_INTERRUPT109 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT109_SET(0,0x00000001); 5.4.120 Interrupt Collector Interrupt Register 110 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT110 HW_ICOLL_INTERRUPT110_SET HW_ICOLL_INTERRUPT110_CLR HW_ICOLL_INTERRUPT110_TOG 0x800 0x804 0x808 0x80C Table 5-240. HW_ICOLL_INTERRUPT110 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-127 Interrupt Collector Table 5-241. HW_ICOLL_INTERRUPT110 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT110_SET(0,0x00000001); 5.4.121 Interrupt Collector Interrupt Register 111 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT111 HW_ICOLL_INTERRUPT111_SET HW_ICOLL_INTERRUPT111_CLR HW_ICOLL_INTERRUPT111_TOG 0x810 0x814 0x818 0x81C Table 5-242. HW_ICOLL_INTERRUPT111 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-128 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-243. HW_ICOLL_INTERRUPT111 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT111_SET(0,0x00000001); 5.4.122 Interrupt Collector Interrupt Register 112 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT112 HW_ICOLL_INTERRUPT112_SET HW_ICOLL_INTERRUPT112_CLR HW_ICOLL_INTERRUPT112_TOG 0x820 0x824 0x828 0x82C Table 5-244. HW_ICOLL_INTERRUPT112 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-129 Interrupt Collector Table 5-245. HW_ICOLL_INTERRUPT112 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT112_SET(0,0x00000001); 5.4.123 Interrupt Collector Interrupt Register 113 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT113 HW_ICOLL_INTERRUPT113_SET HW_ICOLL_INTERRUPT113_CLR HW_ICOLL_INTERRUPT113_TOG 0x830 0x834 0x838 0x83C Table 5-246. HW_ICOLL_INTERRUPT113 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-130 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-247. HW_ICOLL_INTERRUPT113 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT113_SET(0,0x00000001); 5.4.124 Interrupt Collector Interrupt Register 114 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT114 HW_ICOLL_INTERRUPT114_SET HW_ICOLL_INTERRUPT114_CLR HW_ICOLL_INTERRUPT114_TOG 0x840 0x844 0x848 0x84C Table 5-248. HW_ICOLL_INTERRUPT114 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-131 Interrupt Collector Table 5-249. HW_ICOLL_INTERRUPT114 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT114_SET(0,0x00000001); 5.4.125 Interrupt Collector Interrupt Register 115 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT115 HW_ICOLL_INTERRUPT115_SET HW_ICOLL_INTERRUPT115_CLR HW_ICOLL_INTERRUPT115_TOG 0x850 0x854 0x858 0x85C Table 5-250. HW_ICOLL_INTERRUPT115 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-132 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-251. HW_ICOLL_INTERRUPT115 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT115_SET(0,0x00000001); 5.4.126 Interrupt Collector Interrupt Register 116 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT116 HW_ICOLL_INTERRUPT116_SET HW_ICOLL_INTERRUPT116_CLR HW_ICOLL_INTERRUPT116_TOG 0x860 0x864 0x868 0x86C Table 5-252. HW_ICOLL_INTERRUPT116 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-133 Interrupt Collector Table 5-253. HW_ICOLL_INTERRUPT116 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT116_SET(0,0x00000001); 5.4.127 Interrupt Collector Interrupt Register 117 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT117 HW_ICOLL_INTERRUPT117_SET HW_ICOLL_INTERRUPT117_CLR HW_ICOLL_INTERRUPT117_TOG 0x870 0x874 0x878 0x87C Table 5-254. HW_ICOLL_INTERRUPT117 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-134 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-255. HW_ICOLL_INTERRUPT117 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT117_SET(0,0x00000001); 5.4.128 Interrupt Collector Interrupt Register 118 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT118 HW_ICOLL_INTERRUPT118_SET HW_ICOLL_INTERRUPT118_CLR HW_ICOLL_INTERRUPT118_TOG 0x880 0x884 0x888 0x88C Table 5-256. HW_ICOLL_INTERRUPT118 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-135 Interrupt Collector Table 5-257. HW_ICOLL_INTERRUPT118 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT118_SET(0,0x00000001); 5.4.129 Interrupt Collector Interrupt Register 119 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT119 HW_ICOLL_INTERRUPT119_SET HW_ICOLL_INTERRUPT119_CLR HW_ICOLL_INTERRUPT119_TOG 0x890 0x894 0x898 0x89C Table 5-258. HW_ICOLL_INTERRUPT119 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-136 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-259. HW_ICOLL_INTERRUPT119 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT119_SET(0,0x00000001); 5.4.130 Interrupt Collector Interrupt Register 120 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT120 HW_ICOLL_INTERRUPT120_SET HW_ICOLL_INTERRUPT120_CLR HW_ICOLL_INTERRUPT120_TOG 0x8A0 0x8A4 0x8A8 0x8AC Table 5-260. HW_ICOLL_INTERRUPT120 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-137 Interrupt Collector Table 5-261. HW_ICOLL_INTERRUPT120 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT120_SET(0,0x00000001); 5.4.131 Interrupt Collector Interrupt Register 121 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT121 HW_ICOLL_INTERRUPT121_SET HW_ICOLL_INTERRUPT121_CLR HW_ICOLL_INTERRUPT121_TOG 0x8B0 0x8B4 0x8B8 0x8BC Table 5-262. HW_ICOLL_INTERRUPT121 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-138 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-263. HW_ICOLL_INTERRUPT121 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT121_SET(0,0x00000001); 5.4.132 Interrupt Collector Interrupt Register 122 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT122 HW_ICOLL_INTERRUPT122_SET HW_ICOLL_INTERRUPT122_CLR HW_ICOLL_INTERRUPT122_TOG 0x8C0 0x8C4 0x8C8 0x8CC Table 5-264. HW_ICOLL_INTERRUPT122 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-139 Interrupt Collector Table 5-265. HW_ICOLL_INTERRUPT122 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT122_SET(0,0x00000001); 5.4.133 Interrupt Collector Interrupt Register 123 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT123 HW_ICOLL_INTERRUPT123_SET HW_ICOLL_INTERRUPT123_CLR HW_ICOLL_INTERRUPT123_TOG 0x8D0 0x8D4 0x8D8 0x8DC Table 5-266. HW_ICOLL_INTERRUPT123 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-140 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-267. HW_ICOLL_INTERRUPT123 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT123_SET(0,0x00000001); 5.4.134 Interrupt Collector Interrupt Register 124 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT124 HW_ICOLL_INTERRUPT124_SET HW_ICOLL_INTERRUPT124_CLR HW_ICOLL_INTERRUPT124_TOG 0x8E0 0x8E4 0x8E8 0x8EC Table 5-268. HW_ICOLL_INTERRUPT124 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-141 Interrupt Collector Table 5-269. HW_ICOLL_INTERRUPT124 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT124_SET(0,0x00000001); 5.4.135 Interrupt Collector Interrupt Register 125 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT125 HW_ICOLL_INTERRUPT125_SET HW_ICOLL_INTERRUPT125_CLR HW_ICOLL_INTERRUPT125_TOG 0x8F0 0x8F4 0x8F8 0x8FC Table 5-270. HW_ICOLL_INTERRUPT125 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-142 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-271. HW_ICOLL_INTERRUPT125 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT125_SET(0,0x00000001); 5.4.136 Interrupt Collector Interrupt Register 126 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT126 HW_ICOLL_INTERRUPT126_SET HW_ICOLL_INTERRUPT126_CLR HW_ICOLL_INTERRUPT126_TOG 0x900 0x904 0x908 0x90C Table 5-272. HW_ICOLL_INTERRUPT126 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-143 Interrupt Collector Table 5-273. HW_ICOLL_INTERRUPT126 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT126_SET(0,0x00000001); 5.4.137 Interrupt Collector Interrupt Register 127 Description This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT127 HW_ICOLL_INTERRUPT127_SET HW_ICOLL_INTERRUPT127_CLR HW_ICOLL_INTERRUPT127_TOG 0x910 0x914 0x918 0x91C Table 5-274. HW_ICOLL_INTERRUPT127 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENFIQ 0 3 SOFTIRQ 0 2 ENABLE 0 1 PRIORITY 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-144 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-275. HW_ICOLL_INTERRUPT127 Bit Field Descriptions BITS 31:5 RSRVD1 4 ENFIQ LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. DISABLE = 0x0 Disable ENABLE = 0x1 Enable 3 2 1:0 SOFTIRQ ENABLE PRIORITY RW 0x0 RW 0x0 RW 0x0 Set this bit to one to force a software interrupt. NO_INTERRUPT = 0x0 turn off the software interrupt request. FORCE_INTERRUPT = 0x1 force a software interrupt Enable the interrupt bit through the collector. DISABLE = 0x0 Disable ENABLE = 0x1 Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). LEVEL0 = 0x0 level 0, lowest or weakest priority LEVEL1 = 0x1 level 1 LEVEL2 = 0x2 level 2 LEVEL3 = 0x3 level 3, highest or strongest priority DESCRIPTION: This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE: HW_ICOLL_INTERRUPT127_SET(0,0x00000001); 5.4.138 Interrupt Collector Debug Register 0 Description The contents of this register will be defined as the hardware is developed. HW_ICOLL_DEBUG HW_ICOLL_DEBUG_SET HW_ICOLL_DEBUG_CLR HW_ICOLL_DEBUG_TOG Table 5-276. HW_ICOLL_DEBUG 3 1 3 0 2 9 2 8 2 7 2 6 LEVEL_REQUESTS 2 5 2 4 2 3 2 2 REQUESTS_BY_LEVEL 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x1120 0x1124 0x1128 0x112C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-145 VECTOR_FSM INSERVICE RSRVD2 RSRVD1 IRQ FIQ Interrupt Collector Table 5-277. HW_ICOLL_DEBUG Bit Field Descriptions BITS LABEL 31:28 INSERVICE RW RESET RO 0x0 DEFINITION read-only view of the Inservice bits used for nesting IRQs. LEVEL0 = 0x1 LEVEL0 LEVEL1 = 0x2 LEVEL1 LEVEL2 = 0x4 LEVEL2 LEVEL3 = 0x8 LEVEL3 27:24 LEVEL_REQUESTS RO 0x0 read-only view of the requsts by priority level for the current IRQ. LEVEL0 = 0x1 LEVEL0 LEVEL1 = 0x2 LEVEL1 LEVEL2 = 0x4 LEVEL2 LEVEL3 = 0x8 LEVEL3 23:20 REQUESTS_BY_LEVEL RO 0x0 read-only view of the requsts by priority level for the current IRQ. LEVEL0 = 0x1 LEVEL0 LEVEL1 = 0x2 LEVEL1 LEVEL2 = 0x4 LEVEL2 LEVEL3 = 0x8 LEVEL3 19:18 RSRVD2 17 FIQ 16 IRQ RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 Always write zeroes to this bitfield. Read-Only View of the FIQ output to the CPU. NO_FIQ_REQUESTED = 0x0 No FIQ Requested FIQ_REQUESTED = 0x1 FIQ Requested Read-Only View of the FIQ output to the CPU. NO_IRQ_REQUESTED = 0x0 No IRQ Requested IRQ_REQUESTED = 0x1 IRQ Requested 15:10 RSRVD1 9:0 VECTOR_FSM Always write zeroes to this bitfield. Empty description. FSM_IDLE = 0x000 FSM_IDLE FSM_MULTICYCLE1 = 0x001 FSM_MULTICYCLE1 FSM_MULTICYCLE2 = 0x002 FSM_MULTICYCLE2 FSM_PENDING = 0x004 FSM_PENDING FSM_MULTICYCLE3 = 0x008 FSM_MULTICYCLE3 FSM_MULTICYCLE4 = 0x010 FSM_MULTICYCLE4 FSM_ISR_RUNNING1 = 0x020 FSM_ISR_RUNNING1 FSM_ISR_RUNNING2 = 0x040 FSM_ISR_RUNNING2 FSM_ISR_RUNNING3 = 0x080 FSM_ISR_RUNNING3 FSM_MULTICYCLE5 = 0x100 FSM_MULTICYCLE5 FSM_MULTICYCLE6 = 0x200 FSM_MULTICYCLE6 DESCRIPTION: This register provides diagnostic visibility into the IRQ request state machine and its various inputs. EXAMPLE: if (BF_RD(ICOLL_DEBUG, LEVEL_REQUESTS) != HW_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3) Error(); TPRINTF(TP_MED, ("ICOLL INSERVICE = 0x%x BF_RD(ICOLL_DEBUG, INSERVICE))); TPRINTF(TP_MED, ("ICOLL STATE = 0x%x VECTOR_FSM))); 5.4.139 Interrupt Collector Debug Read Register 0 Description This register always returns a known read value for debug purposes. HW_ICOLL_DBGREAD0 HW_ICOLL_DBGREAD0_SET HW_ICOLL_DBGREAD0_CLR HW_ICOLL_DBGREAD0_TOG 0x1130 0x1134 0x1138 0x113C i.MX23 Applications Processor Reference Manual, Rev. 1 5-146 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-278. HW_ICOLL_DBGREAD0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUE Table 5-279. HW_ICOLL_DBGREAD0 Bit Field Descriptions BITS 31:0 VALUE LABEL RW RESET RO 0xECA94567 DEFINITION Fixed read-only value. DESCRIPTION: This register is used to test the read mux paths on the APBH. EXAMPLE: if (HW_ICOLL_DBGREAD0_RD != 0xECA94567) Error(); 5.4.140 Interrupt Collector Debug Read Register 1 Description This register always returns a known read value for debug purposes. HW_ICOLL_DBGREAD1 HW_ICOLL_DBGREAD1_SET HW_ICOLL_DBGREAD1_CLR HW_ICOLL_DBGREAD1_TOG Table 5-280. HW_ICOLL_DBGREAD1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x1140 0x1144 0x1148 0x114C VALUE Table 5-281. HW_ICOLL_DBGREAD1 Bit Field Descriptions BITS 31:0 VALUE LABEL RW RESET RO 0x1356DA98 DEFINITION Fixed read-only value. DESCRIPTION: This register is used to test the read mux paths on the APBH. EXAMPLE: if (HW_ICOLL_DBGREAD1_RD != 0x1356DA98) Error(); 5.4.141 Interrupt Collector Debug Flag Register Description The Interrupt Collector debug flag register is used to post diagnostic state into simulation. HW_ICOLL_DBGFLAG HW_ICOLL_DBGFLAG_SET 0x1150 0x1154 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-147 Interrupt Collector HW_ICOLL_DBGFLAG_CLR HW_ICOLL_DBGFLAG_TOG Table 5-282. HW_ICOLL_DBGFLAG 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RSRVD1 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0x1158 0x115C 0 9 0 8 FLAG 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 5-283. HW_ICOLL_DBGFLAG Bit Field Descriptions BITS 31:16 RSRVD1 15:0 FLAG LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bitfield. This debug facility is probably temporary. DESCRIPTION: This register provides a posting register to synchronize C program execution and the internal simulation environment. EXAMPLE: BF_WR(ICOLL_DBGFLAG, FLAG, 3); // ... do some diagnostic action BF_WR(ICOLL_DBGFLAG, FLAG, 4); // ... do some more diagnostic actions BF_WR(ICOLL_DBGFLAG, FLAG, 5); 5.4.142 Interrupt Collector Debug Read Request Register 0 Description read-only view into the low 32 bits of the request holding register. HW_ICOLL_DBGREQUEST0 HW_ICOLL_DBGREQUEST0_SET HW_ICOLL_DBGREQUEST0_CLR HW_ICOLL_DBGREQUEST0_TOG 0x1160 0x1164 0x1168 0x116C Table 5-284. HW_ICOLL_DBGREQUEST0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BITS Table 5-285. HW_ICOLL_DBGREQUEST0 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Low 32 bits of the request holding register. DESCRIPTION: This register is used to test interrupt collector state machine and its associated request holding register. i.MX23 Applications Processor Reference Manual, Rev. 1 5-148 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector EXAMPLE: if (HW_ICOLL_DBGREQUESTn_RD(0) != 0x00000000) Error(); 5.4.143 Interrupt Collector Debug Read Request Register 1 Description read-only view into bits 32-63 of the request holding register. HW_ICOLL_DBGREQUEST1 HW_ICOLL_DBGREQUEST1_SET HW_ICOLL_DBGREQUEST1_CLR HW_ICOLL_DBGREQUEST1_TOG 0x1170 0x1174 0x1178 0x117C Table 5-286. HW_ICOLL_DBGREQUEST1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BITS Table 5-287. HW_ICOLL_DBGREQUEST1 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Bits 32-63 of the request holding register. DESCRIPTION: This register is used to test interrupt collector state machine and its associated request holding register. EXAMPLE: if (HW_ICOLL_DBGREQUESTn_RD(n) != 0x00000000) Error(); 5.4.144 Interrupt Collector Debug Read Request Register 2 Description read-only view into bits 64-95 of the request holding register. HW_ICOLL_DBGREQUEST2 HW_ICOLL_DBGREQUEST2_SET HW_ICOLL_DBGREQUEST2_CLR HW_ICOLL_DBGREQUEST2_TOG 0x1180 0x1184 0x1188 0x118C Table 5-288. HW_ICOLL_DBGREQUEST2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BITS Table 5-289. HW_ICOLL_DBGREQUEST2 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Bits 64-95 of the request holding register. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-149 Interrupt Collector DESCRIPTION: This register is used to test interrupt collector state machine and its associated request holding register. EXAMPLE: if (HW_ICOLL_DBGREQUESTn_RD(n) != 0x00000000) Error(); 5.4.145 Interrupt Collector Debug Read Request Register 3 Description read-only view into bits 96-127 of the request holding register. HW_ICOLL_DBGREQUEST3 HW_ICOLL_DBGREQUEST3_SET HW_ICOLL_DBGREQUEST3_CLR HW_ICOLL_DBGREQUEST3_TOG 0x1190 0x1194 0x1198 0x119C Table 5-290. HW_ICOLL_DBGREQUEST3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BITS Table 5-291. HW_ICOLL_DBGREQUEST3 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Bits 96-127 of the request holding register. DESCRIPTION: This register is used to test interrupt collector state machine and its associated request holding register. EXAMPLE: if (HW_ICOLL_DBGREQUESTn_RD(n) != 0x00000000) Error(); 5.4.146 Interrupt Collector Version Register Description This register always returns a known read value for debug purposes it indicates the version of the block. HW_ICOLL_VERSION Table 5-292. HW_ICOLL_VERSION 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x11E0 i.MX23 Applications Processor Reference Manual, Rev. 1 5-150 Preliminary--Subject to Change Without Notice Freescale Semiconductor Interrupt Collector Table 5-293. HW_ICOLL_VERSION Bit Field Descriptions BITS 31:24 MAJOR 23:16 MINOR 15:0 STEP LABEL RW RESET RO 0x03 RO 0x01 RO 0x0000 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_ICOLL_VERSION.B.MAJOR != 3) Error(); ICOLL Block v3.1, Revision 1.50 5.4.147 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5-151 Interrupt Collector i.MX23 Applications Processor Reference Manual, Rev. 1 5-152 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 6 Digital Control and On-Chip RAM This chapter describes the digital control block and the on-chip RAM features of the i.MX23. It includes sections on controlling the SRAM, performance monitors, high-entropy pseudo-random number seed, and free-running microseconds counter. Programmable registers for the block are described in Section 6.4, "Programmable Registers." 6.1 Overview The digital control block provides overall control of various items within the top digital block of the chip, including the on-chip RAM controls and HCLK performance counter, as shown in Figure 6-1. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-1 Digital Control and On-Chip RAM ARM Core D M I M SRAM S S S S AHB0 AHB1 HCLK AHB2 AHB3 S AHB SLAVE AHB MASTER SHARED DMA APBH MASTER AHB-to-APBH Bridge APBH PIO Programmable Registers On-Chip OTP Controller Default FirstLevel Page Table Revision Performance Monitors Entropy DIGCTL PSWITCH SRAM 0 1 3 2 AHB Arbiter Figure 6-1. Digital Control (DIGCTL) Block Diagram The on-chip RAM is constructed from an array of six-transistor dynamic RAM bit cells. The repair functions of this SRAM are controlled by registers in the DIGCTL block. 6.2 SRAM Controls The on-chip RAM is a compiled RAM cell. It is implemented in one segment of 32 Kbytes. The memory is addressed as shown in Figure 6-2. 31 0x0000_0000 0x0000_0004 0x0000_0008 0x0000_000C 0 Bank 0 a . . . . Figure 6-2. On-Chip RAM Partitioning i.MX23 Applications Processor Reference Manual, Rev. 1 6-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM A 32-bit AHB address is arranged as shown in Table 6-1. Table 6-1. On-Chip RAM Address Bits AHB ADDR BITS 29:2 1:0 Address Bank Address Byte Address USAGE Tied 2'b00. Selects/masks out specific bytes within a word. DESCRIPTION Selects one of 32K words in a bank. Accessing on-chip RAM requires only one initial wait state for arbitration. There is a single cycle access for writes, and two cycle (one wait state) for reads. Other wait states happen whenever there is a read immediately following a write and also when a master is waiting to access a bank because some other master is accessing the same bank on a cycle. The i.MX23 contains a simple 32-bit word RAM repair scheme. The purpose of this scheme is to address single-bit errors in the on-chip RAM. To enable the repair, HW_DIGCTL_RAMCTRL_RAM_REPAIR_EN must be set. Once this bit is set, the RAM controller replaces any access to the word address specified in HW_DIGCTL_RAMREPAIR_ADDR with a 32-bit redundant hardware memory. The actual repair enable and address must be read from OTP. Because these registers must be loaded by software, ROM boot code reads the OTP to see if the repair enable bit is set. If the repair enable bit is set, the ROM boot code sets HW_DIGCTL_RAMCTRL_RAM_REPAIR_EN and copies the 16-bit word address from OTP to HW_DIGCTL_RAMREPAIR_ADDR. 6.3 Miscellaneous Controls The digital control block also contains a number of other miscellaneous functions, as detailed in this section. 6.3.1 Performance Monitoring The digital control block contains several registers for system bus performance monitoring, including HW_DIGCTL_HCLKCOUNT, which counts HCLK rising edges. This register counts at a variable rate as HW_CLKCTRL_HBUS_AUTO_SLOW_ MODE is enabled. In addition, there exists a performance monitoring register for each AHB layer (L0-L3). The HW_DIGCTL_L(n)_AHB_DATA_STALLED and HW_DIGCTL_L(n)_AHB_ACTIVE_CYCLES registers can be used to measure AHB bus utilization. The Stalled register counts all cycles in which any device has an outstanding and unfulfilled bus operation in flight. The Active Cycles register counts the number of data transfer cycles. Subtract cycles from stalls to determine under utilized bus cycles. These counters can be used to tune the performance of the HCLK frequency for specific activities. In addition, these monitors can be forced to focus on specific masters (which connect to that layer). See the HW_DIGCTL_AHB_STATS_SELECT bit description for details. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-3 Digital Control and On-Chip RAM 6.3.2 High-Entropy PRN Seed A 32-bit entropy register begins running a pseudo-random number algorithm from the time reset is removed until the PSWITCH is released by the user. This high-entropy value can be used as the seed for other pseudo-random number generators. 6.3.3 Write-Once Register A 32-bit write-once register holds a runtime-derived locked seed. Once written, it cannot be changed until the next chip wide reset event. The contents of this register are frequently derived from the entropy register. 6.3.4 Microseconds Counter A 32-bit free-running microseconds counter provides fine-grain real-time control. Its period is determined by dividing the 24.0-MHz crystal oscillator by 24. Thus, its frequency does not change as HCLK, XCLK, and the processor clock frequency are changed. 6.4 Programmable Registers The following registers provide control of all programmable elements of the digital control block. 6.4.1 DIGCTL Control Register Description The DIGCTL Control Register provides overall control of various functions throughout the digital portion of the chip. HW_DIGCTL_CTRL HW_DIGCTL_CTRL_SET HW_DIGCTL_CTRL_CLR HW_DIGCTL_CTRL_TOG Table 6-2. HW_DIGCTL_CTRL 3 1 3 0 2 9 2 8 2 7 2 6 CACHE_BIST_TMODE 2 5 LCD_BIST_CLKEN 2 4 LCD_BIST_START 2 3 DCP_BIST_CLKEN 2 2 DCP_BIST_START 2 1 ARM_BIST_CLKEN 2 0 USB_TESTMODE 1 9 ANALOG_TESTMODE 1 8 DIGITAL_TESTMODE 1 7 ARM_BIST_START 1 6 UART_LOOPBACK 1 5 SAIF_LOOPBACK 1 4 SAIF_CLKMUX_SEL 1 3 1 2 SAIF_CLKMST_SEL 1 1 SAIF_ALT_BITCLK_SEL 1 0 0 9 0 8 0 7 0 6 USE_SERIAL_JTAG 0 5 TRAP_IN_RANGE 0 4 0 3 DEBUG_DISABLE 0 2 0 1 0 0 LATCH_ENTROPY 0x000 0x004 0x008 0x00C XTAL24M_GATE USB_CLKGATE TRAP_ENABLE i.MX23 Applications Processor Reference Manual, Rev. 1 6-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor JTAG_SHIELD SY_CLKGATE SY_SFTRST SY_ENDIAN TRAP_IRQ RSVD3 RSVD2 RSVD1 Digital Control and On-Chip RAM Table 6-3. HW_DIGCTL_CTRL Bit Field Descriptions BITS LABEL 31 RSVD3 30 XTAL24M_GATE RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. If set to 1, disable the Digital Control Microseconds counter, STRB1MHZ. If set to 0, enable the Digital Control Microseconds counter.. This bit is set when an AHB access occurs to the range defined by the TRAP_ADDR registers below and the trap function is enabled with the TRAP_ENABLE bit. Reserved. Set this bit to enable the Cache BIST test mode. Set this bit to enable the LCD memory BIST clock. Set this bit to start the LCD memory BIST. Set this bit to enable the DCP memory BIST clock. Set this bit to start the DCP memory BIST. Set this bit to enable the ARM BIST clock. Set this bit to get into USB test mode. Set this bit to get into analog test mode. Set this bit to get into digital test mode. Set this bit to start the ARM cache BIST controller. Set this bit to loop the two AUARTs back on themselves in a null modem configuration (as well as connect AUART1 to DUART). NORMAL = 0x0 No loopback. LOOPIT = 0x1 Internally connect AUART1 TX to AUART2 RX and DUART RX, also connect AUART2 TX to AUART1 RX (note that DUART TX is unaffected). 29 TRAP_IRQ RW 0x0 28:27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 CACHE_BIST_TMODE LCD_BIST_CLKEN LCD_BIST_START DCP_BIST_CLKEN DCP_BIST_START ARM_BIST_CLKEN USB_TESTMODE ANALOG_TESTMODE DIGITAL_TESTMODE ARM_BIST_START UART_LOOPBACK RO RW RW RW RW RW RW RW RW RW RW RW 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 15 SAIF_LOOPBACK RW 0x0 Set this bit to loop SAIF1 to SAIF2 and SAIF2 to SAIF1. To use SAIF loopback, configure one SAIF for transmit and the other for receive. Because this bit connects SAIF1 output to SAIF2 input and SAIF2 output to SAIF1 input, it does not matter which of the two ports is configured for TX and the other for RX. Either configuration will produce an internal TX to RX loopback. Note that SAIF_CLKMST_SEL is ignored when loopback is enabled. NORMAL = 0x0 No loopback. LOOPIT = 0x1 Loop SAIF1 and SAIF2 back to each other. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-5 Digital Control and On-Chip RAM Table 6-3. HW_DIGCTL_CTRL Bit Field Descriptions BITS LABEL 14:13 SAIF_CLKMUX_SEL RW RESET RW 0x0 DEFINITION Selects the muxed pins and directions for the SAIF1 and SAIF2 master clock (MCLK), bit clock (BITCLK), and left/right sample clock (LRCLK). MCLK is an optional output and when used, is connected to the SAIF_MCLK_BITCLK muxed pin output. BITCLK can be either an input or output and can be connected to either the SAIF_MCLK_BITCLK muxed pin or the SAIF_ALT_BITCLK muxed pin. LRCLK can also be either an input or output and is connected to the SAIF_LRCLK muxed pin. When either MCLK, MCLK/BITCLK, or MCLK/BITCLK/LRCLK are configured to be outputs, the SAIF_CLKMST_SEL bit is used to determine which of the two SAIFs drives these clocks. Note that only one of the two SAIFs can be clock master at a time (READ_MODE=0 and/or SLAVE_MODE=0). When MCLK is not used and BITCLK/LRCLK are both inputs, one or both SAIFs must be configured as RX clock slaves (READ_MODE=1 and SLAVE_MODE=1). Valid configurations for SAIF_CLKMUX_SEL, as well as SAIF1 and SAIF2 SLAVE_MODE and READ_MODE bits, are: 1) one SAIF port is TX or RX master and controls BITCLK/LRCLK (both to the pins and to the other SAIF), and MCLK can optionally be an output while the other SAIF is an RX slave; 2) both ports are in RX slave mode and are driven by the BITCLK/LRCLK pin inputs, and MCLK can optionally be an output; 3) only one SAIF port is used as a TX or RX master during a given time, and SAIF_CLKMST_SEL is configured to give control of MCLK/BITCLK/LRCLK to the active port; or 4) only one of the two ports is used as an RX slave. See the table earlier in this chapter for a complete list of SAIF_CLKMUX_SEL/SAIF_CLKMST_SEL options, as well as SAIF1 and SAIF2 SLAVE_MODE/READ_MODE configurations. Note that SAIF_CLKMUX_SEL is ignored when SAIF_LOOPBACK=1. Also note that when the SAIF_ALT_BITCLK pinmux is selected to input/output BITCLK, 6-channel mode cannot be used since the SAIF2_SDATA2 pin is used for the alternate BITCLK. MBL_CLK_OUT = 0x0 MCLK output to SAIF_MCLK_BITCLK, BITCLK output to SAIF_ALT_BITCLK, LRCLK output to SAIF_LRCLK. BL_CLK_OUT = 0x1 BITCLK output to SAIF_MCLK_BITCLK, LRCLK output to SAIF_LRCLK. M_CLK_OUT_BL_CLK_IN = 0x2 MCLK output to SAIF_MCLK_BITCLK, BITCLK input to SAIF_ALT_BITCLK, LRCLK input to SAIF_LRCLK. BL_CLK_IN = 0x3 BITCLK input to SAIF_MCLK_BITCLK, LRCLK input to SAIF_LRCLK. i.MX23 Applications Processor Reference Manual, Rev. 1 6-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM Table 6-3. HW_DIGCTL_CTRL Bit Field Descriptions BITS LABEL 12 SAIF_CLKMST_SEL RW RESET RW 0x0 DEFINITION Selects whether SAIF1 or SAIF2 drives MCLK/BITCLK/LRCLK when they are configured as outputs via SAIF_CLKMUX_SEL. Note that the selected SAIF must be configured in clock master mode (READ_MODE=0 and/or SLAVE_MODE=0). This bit must also be configured when SAIF_LOOPBACK=1 to determine the clock master. SAIF1_MST = 0x0 SAIF1 clocks are used to output MCLK/BITCLK/LRCLK. SAIF2_MST = 0x1 SAIF2 clocks are used to output MCLK/BITCLK/LRCLK. 11 SAIF_ALT_BITCLK_SEL RW 0x0 10 9 RSVD1 SY_ENDIAN RO 0x0 RW 0x1 8 SY_SFTRST RW 0x1 7 SY_CLKGATE RW 0x1 6 USE_SERIAL_JTAG RW 0x0 When the master SAIF (as selected by SAIF_CLKMST_SEL) requires all three clocks (MCLK/BITCLK/LRCLK), which is selected by programming SAIF_CLKMUX_SEL = 00 or 10, this bit selects whether SAIF2_SDATA2 or LCD_D16 is used to input/output BITCLK. 0 = SAIF2_SDATA2 pinmux pin selected for BITCLK. 1 = LCD_D16 pin selected for BITCLK. Note that this bit is ignored when SAIF_CLKMUX_SEL=01 or 11. Also note that the corresponding pin selected for BITCLK must have its MUXXEL bit field correctly programmed in the pin control block. Reserved. Setting this bit to 1 configures the SY to run in big endian mode, clearing this bit to 0 configures the SY to run in little endian mode. Setting this bit to 1 forces a reset to the entire SY. SY_SFTRST has no effect on SY_CLKGATE. Also, the SY_SFTRST bit may be written when SY_CLKGATE=1. This bit must be cleared to 0 for normal SY operation. This bit gates the clocks to the SY to save power when the clocks are not in use. When set to 1, this bit gates off the clocks to the block. When this bit is cleared to 0, the block receives its clock for normal operation. Selects whether the one-wire serial JTAG interface or the alternative six-wire parallel JTAG interface is used. 0 = Parallel six-wire JTAG is enabled and is mapped to a collection of module pins that must be enabled by programming their MUXSEL bits in the pin control block. 1 = Serial JTAG is enabled and uses the dedicated DEBUG pin. The ROM bootcode writes this field prior to enabling JTAG, selecting which type of JTAG pin signaling to use. OLD_JTAG = 0x0 Use six-wire parallel JTAG mode. SERIAL_JTAG = 0x1 Use one-wire serial JTAG mode. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-7 Digital Control and On-Chip RAM Table 6-3. HW_DIGCTL_CTRL Bit Field Descriptions BITS LABEL 5 TRAP_IN_RANGE RW RESET RW 0x0 DEFINITION Determines whether the debug trap function causes a match when the master address is inside (low-address <= current-address <= high-address) the specified range. 0 = The trap occurs when the master address falls outside of the range. 1 = The check is inside the range. Enables the AHB arbiter debug trap functions. When a trap occurs and this bit is set, an interrupt is sent to the ARM core. Set this bit to disable the ARM core's debug logic (for power savings). This bit must remain 0 following power-on reset for normal JTAG debugger operation of the ARM core. When set to 1, it gates off the clocks to the ARM core's debug logic. Once this bit is set, the part must undergo a power-on reset to re-enable debug operation. Manually clearing this bit via a write after it has been set produces unknown results. This bit must be cleared to 0 for normal operation of the USB controller. When set to 1, it gates off the clocks to the USB controller. USB_CLKGATE can be set during suspend to gate the USB clock during suspend. If this is gated, then the USB controller Reset Received bit (HW_USBCTRL_USBSTS_URI) should be not be polled for reset during suspend; use the HW_USBPHY_CTRL_RESUME_IRQ bit instead. RUN = 0x0 Allow USB to operate normally. NO_CLKS = 0x1 Do not clock USB gates in order to minimize power consumption. 4 TRAP_ENABLE RW 0x0 3 DEBUG_DISABLE RW 0x0 2 USB_CLKGATE RW 0x1 1 JTAG_SHIELD RW 0x0 0 = The JTAG debugger is enabled. 1 = The JTAG debugger is disabled. NORMAL = 0x0 JTAG debugger enabled. SHIELDS_UP = 0x1 JTAG debugger disabled. 0 LATCH_ENTROPY RW 0x0 Setting this bit latches the current value of the entropy register into HW_DIGCTL_ENTROPY_VALUE. This can be used get a stable value on players that do not deassert the PSWITCH while powered up. DESCRIPTION: This register controls various functions throughout the digital portion of the chip. EXAMPLE: HW_DIGCTL_CTRL_CLR(BM_DIGCTL_CTRL_USB_CLKGATE); // enable USB clock 6.4.2 DIGCTL Status Register Description HW_DIGCTL_STATUS HW_DIGCTL_STATUS_SET HW_DIGCTL_STATUS_CLR HW_DIGCTL_STATUS_TOG 0x010 0x014 0x018 0x01C The DIGCTL Status Register reports status for the digital control block. i.MX23 Applications Processor Reference Manual, Rev. 1 6-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM Table 6-4. HW_DIGCTL_STATUS 3 1 USB_HS_PRESENT 3 0 USB_OTG_PRESENT 2 9 USB_HOST_PRESENT 2 8 USB_DEVICE_PRESENT 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DCP_BIST_DONE LCD_BIST_DONE DCP_BIST_PASS LCD_BIST_PASS PACKAGE_TYPE DCP_BIST_FAIL LCD_BIST_FAIL JTAG_IN_USE Table 6-5. HW_DIGCTL_STATUS Bit Field Descriptions BITS LABEL 31 USB_HS_PRESENT 30 29 28 USB_OTG_PRESENT USB_HOST_PRESENT USB_DEVICE_PRESENT RW RESET RO 0x1 RO 0x1 RO 0x1 RO 0x1 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 DEFINITION This read-only bit returns a 1 when USB high-speed mode is present. This read-only bit returns a 1 when USB on-the-go (OTG) functionality is present. This read-only bit returns a 1 when USB host functionality is present. This read-only bit returns a 1 when USB device functionality is present. Reserved. This read-only bit is a 1 if the DCP memory BIST returns a failure. This read-only bit is a 1 if the DCP memory BIST returns a pass. This read-only bit is a 1 if the DCP memory BIST has completed. This read-only bit is a 1 if the LCD memory BIST returns a failure. This read-only bit is a 1 if the LCD memory BIST returns a pass. This read-only bit is a 1 if the LCD memory BIST has completed. This read-only bit is a 1 if JTAG debugger usage has been detected. This read-only bit field returns the pin count and package type. 000=169BGA, 011=128TQFP, all others=Reserved. Set to 1 by any successful write to the HW_DIGCTL_WRITEONCE register. 27:11 RSVD2 10 DCP_BIST_FAIL 9 8 7 6 5 4 3:1 DCP_BIST_PASS DCP_BIST_DONE LCD_BIST_FAIL LCD_BIST_PASS LCD_BIST_DONE JTAG_IN_USE PACKAGE_TYPE 0 WRITTEN RO 0x0 DESCRIPTION: The DIGCTL Status Register provides a read-only view to various input conditions and internal states. EXAMPLE: if(HW_DIGCTL_STATUS.PACKAGE_TYPE) { i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-9 WRITTEN RSVD2 Digital Control and On-Chip RAM // do 100-pin package things } 6.4.3 Free-Running HCLK Counter Register Description HW_DIGCTL_HCLKCOUNT HW_DIGCTL_HCLKCOUNT_SET HW_DIGCTL_HCLKCOUNT_CLR HW_DIGCTL_HCLKCOUNT_TOG Table 6-6. HW_DIGCTL_HCLKCOUNT 0x020 0x024 0x028 0x02C The Free-Running HCLK Counter Register is available for performance metrics. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-7. HW_DIGCTL_HCLKCOUNT Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RO 0x0 DEFINITION This counter counts up from reset using HCLK. The count is valid for HCLK frequencies greater than 2 MHz. DESCRIPTION: This counter increments once per HCLK rising edge. EXAMPLE: StartTime = HW_DIGCTL_HCLKCOUNT; // Do something you want timed here EndTime = HW_DIGCTL_HCLKCOUNT; Duration = EndTime - StartTime; // make sure to handle rollover in a real application 6.4.4 On-Chip RAM Control Register Description HW_DIGCTL_RAMCTRL HW_DIGCTL_RAMCTRL_SET HW_DIGCTL_RAMCTRL_CLR HW_DIGCTL_RAMCTRL_TOG 0x030 0x034 0x038 0x03C The On-Chip RAM Control Register holds on-chip SRAM control bit fields. i.MX23 Applications Processor Reference Manual, Rev. 1 6-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM Table 6-8. HW_DIGCTL_RAMCTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 SPEED_SELECT 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RAM_REPAIR_EN 0 3 0 2 0 1 0 0 RSVD1 Table 6-9. HW_DIGCTL_RAMCTRL Bit Field Descriptions BITS LABEL 31:12 RSVD1 11:8 SPEED_SELECT RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Speed select for 16Kx32 OCRAM instances. Recommended value is 0x0. To be used for characterization. This value may have to be modified to allow lower voltage operation. Reserved. Enable word repair for OCRAM, using the address specified in HW_DIGCTL_RAMREPAIR. 7:1 0 RSVD0 RAM_REPAIR_EN RO 0x0 RW 0x0 DESCRIPTION: This register controls various parts of the on-chip RAM, including the repair state machine that shifts the repair configuration data into the SRAM macro-cell. EXAMPLE: HW_DIGCTL_RAMCTRL_SET(BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT); // Start the efuse state machine 6.4.5 On-Chip RAM Repair Address Register Description HW_DIGCTL_RAMREPAIR HW_DIGCTL_RAMREPAIR_SET HW_DIGCTL_RAMREPAIR_CLR HW_DIGCTL_RAMREPAIR_TOG Table 6-10. HW_DIGCTL_RAMREPAIR 0x040 0x044 0x048 0x04C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RSVD1 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 ADDR 0 7 0 6 0 5 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-11 RSVD0 0 4 Digital Control and On-Chip RAM Table 6-11. HW_DIGCTL_RAMREPAIR Bit Field Descriptions BITS 31:16 RSVD1 15:0 ADDR LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Word repair address for OCRAM. Must be read from OTP and copied to this register. The repair is enabled when HW_DIGCTL_RAMCTRL_RAM_REPAIR_EN is set. DESCRIPTION: The On-Chip RAM Repair Address Register holds repair address for the on-chip SRAM. The value must be read from the OTP and copied here. EXAMPLE: HW_DIGCTL_RAMREPAIR.ADDR= 0xBADA; // read modify write is ok 6.4.6 On-Chip ROM Control Register Description HW_DIGCTL_ROMCTRL HW_DIGCTL_ROMCTRL_SET HW_DIGCTL_ROMCTRL_CLR HW_DIGCTL_ROMCTRL_TOG Table 6-12. HW_DIGCTL_ROMCTRL 0x050 0x054 0x058 0x05C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSVD0 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 RD_MARGIN 0 1 0 0 Table 6-13. HW_DIGCTL_ROMCTRL Bit Field Descriptions BITS LABEL 31:4 RSVD0 3:0 RD_MARGIN RW RESET RO 0x0 RW 0x2 DEFINITION Reserved. This field is used for setting the read margin for the on-chip ROM. It programs the sense amp differential setting and allows the trade-off between speed and robustness. This field should not be changed unless instructed by Freescale. DESCRIPTION: The On-Chip ROM Control Register provides settings for the OCROM. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 6-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM 6.4.7 Software Write-Once Register Description HW_DIGCTL_WRITEONCE Table 6-14. HW_DIGCTL_WRITEONCE 0x060 The Software Write-Once Register hold the value used in software certification management. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BITS Table 6-15. HW_DIGCTL_WRITEONCE Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RW 0xA5A5A5A5 DEFINITION This field can be written only one time. The contents are not used by hardware. DESCRIPTION: This register is used to hold a portion of a certificate that is not mutable after software initialization. EXAMPLE: HW_DIGCTL_WRITEONCE.U = my_certificate; 6.4.8 Entropy Register Description HW_DIGCTL_ENTROPY Table 6-16. HW_DIGCTL_ENTROPY 0x090 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUE Table 6-17. HW_DIGCTL_ENTROPY Bit Field Descriptions BITS 31:0 VALUE LABEL RW RESET RO 0x0 DEFINITION This read-only bit field always reads back the results of an entropy calculation. It is used to randomize the seeds for random number generators. DESCRIPTION: The Entropy register is a read-only test value register. EXAMPLE: while(HW_DIGCTL_STATUS.PSWITCH != 0) { //wait for pswitch to go away } HW_DIGCTL_WRITEONCE.BITS = rand(HW_DIGCTL_ENTROPY.VALUE); i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-13 Digital Control and On-Chip RAM 6.4.9 Entropy Latched Register Description HW_DIGCTL_ENTROPY_LATCHED 0x0A0 Table 6-18. HW_DIGCTL_ENTROPY_LATCHED 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUE Table 6-19. HW_DIGCTL_ENTROPY_LATCHED Bit Field Descriptions BITS 31:0 VALUE LABEL RW RESET RO 0x0 DEFINITION When the LATCH_ENTROPY bit in the HW_DIGCTL_CTRL register is set to 1, the value of the HW_DIGCTL_ENTROPY register is latched into this register. This can be used to latch a stable random value on players where the PSWITCH is not deasserted after power-up. DESCRIPTION: The Entropy Latched Register is a read-only test value register. EXAMPLE: Empty Example. 6.4.10 SJTAG Debug Register Description The SJTAG Debug Register controls various debug points within the SJTAG block and provides read-only views into the SJTAG state machines. HW_DIGCTL_SJTAGDBG HW_DIGCTL_SJTAGDBG_SET HW_DIGCTL_SJTAGDBG_CLR HW_DIGCTL_SJTAGDBG_TOG Table 6-20. HW_DIGCTL_SJTAGDBG 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DELAYED_ACTIVE 0 5 0 4 0 3 0 2 SJTAG_PIN_STATE 0 1 SJTAG_DEBUG_DATA 0 0 SJTAG_DEBUG_OE 0x0B0 0x0B4 0x0B8 0x0BC SJTAG_STATE SJTAG_MODE SJTAG_TDO SJTAG_TDI i.MX23 Applications Processor Reference Manual, Rev. 1 6-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor ACTIVE RSVD2 RSVD1 Digital Control and On-Chip RAM Table 6-21. HW_DIGCTL_SJTAGDBG Bit Field Descriptions BITS LABEL 31:27 RSVD2 26:16 SJTAG_STATE RW RESET RO 0x0 RO 0x2 DEFINITION Reserved. This bitfield shows the state of the sjtag_state flip-flops inside the SJTAG controller. These bits implement the second state machine in the SJTAG block. Reserved. This bit shows the state of the ARM JTAG TDO signal as seen inside the SJTAG controller. This bit shows the state of the JTAG TDI capture FF inside the SJTAG controller. This bit shows the state of the JTAG mode capture FF inside the SJTAG controller. This bitfield shows the state of the delay_onewire_active_reg FF inside the SJTAG controller. These bits implement the first state machine in the SJTAG block. This bit shows the state of the onewire_active_reg FF inside the SJTAG controller. This bit reflects the state of the input driver sampling the SJTAG pin. When HW_DIGCTL_CTRL_USE_SERIAL_JTAG is cleared to 0, external source can pull the SJTAG pin high without starting the SJTAG state machines. In this mode, the SJTAG_PIN_STATE bit is used to confirm continuity from the pad to the SJTAG block. When HW_DIGCTL_CTRL_USE_SERIAL_JTAG is cleared to 0, then the SJTAG pin is placed in a diagnostic mode. In that case, this bit controls the input to the pad data drive signal. If HW_DIGCTL_CTRL_SJTAG_DEBUG_OE is set to 1, then this bit also controls the state of the SJTAG pin itself. When HW_DIGCTL_CTRL_USE_SERIAL_JTAG is cleared to 0, then the SJTAG pin is placed in a diagnostic mode. In that case, this bit controls the input to the pad data output enable signal. Setting this bit to 1 turns on the SJTAG pad and drives it to the state indicated by HW_DIGCTL_CTRL_SJTAG_DEBUG_DATA. 15:11 RSVD1 10 SJTAG_TDO 9 8 7:4 SJTAG_TDI SJTAG_MODE DELAYED_ACTIVE RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 3 2 ACTIVE SJTAG_PIN_STATE RO 0x0 RO 0x0 1 SJTAG_DEBUG_DATA RW 0x0 0 SJTAG_DEBUG_OE RW 0x0 6.4.11 Digital Control Microseconds Counter Register Description HW_DIGCTL_MICROSECONDS HW_DIGCTL_MICROSECONDS_SET HW_DIGCTL_MICROSECONDS_CLR HW_DIGCTL_MICROSECONDS_TOG 0x0C0 0x0C4 0x0C8 0x0CC The Digital Control Microseconds Counter Register is a read-only test value register. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-15 Digital Control and On-Chip RAM Table 6-22. HW_DIGCTL_MICROSECONDS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUE Table 6-23. HW_DIGCTL_MICROSECONDS Bit Field Descriptions BITS 31:0 VALUE LABEL RW RESET RW 0x0 DEFINITION This register maintains a 32-bit counter that increments at a 1-microsecond rate. The 1-MHz clock driving this counter is derived from the 24.0-MHz crystal oscillator. The count value is not preserved over power-downs. The 32-bit value wraps in less than two hours. DESCRIPTION: This fixed-rate timer always increments at 24.0 MHz divided by 24 or 1.0 MHz. It does not generate an interrupt. EXAMPLE: StartTime = HW_DIGCTL_MICROSECONDS_RD(); EndTime = HW_DIGCTL_MICROSECONDS_RD(); ElapsedTime = StartTime - EndTime; // WARNING, handle rollover in real software 6.4.12 Digital Control Debug Read Test Register Description HW_DIGCTL_DBGRD Table 6-24. HW_DIGCTL_DBGRD 0x0D0 The Digital Control Debug Read Test Register is a read-only test value register. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COMPLEMENT Table 6-25. HW_DIGCTL_DBGRD Bit Field Descriptions BITS LABEL 31:0 COMPLEMENT RW RESET DEFINITION RO 0x789ABCDE This read-only bit field always reads back the one's complement of the value in HW_DIGCTL_DBG. DESCRIPTION: This register is used for debugging purposes. EXAMPLE: debug_value = HW_DIGCTL_DBGRD_RD(); 6.4.13 Digital Control Debug Register Description The Digital Control Debug Register is a read-only test value register. i.MX23 Applications Processor Reference Manual, Rev. 1 6-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM HW_DIGCTL_DBG Table 6-26. HW_DIGCTL_DBG 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0x0E0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUE Table 6-27. HW_DIGCTL_DBG Bit Field Descriptions BITS 31:0 VALUE LABEL RW RESET RO 0x87654321 DEFINITION This read-only bit field always reads back the fixed value 0x87654321. DESCRIPTION: This register is used for debugging purposes. EXAMPLE: debug_value = HW_DIGCTL_DBG_RD(); 6.4.14 SRAM BIST Control and Status Register Description HW_DIGCTL_OCRAM_BIST_CSR HW_DIGCTL_OCRAM_BIST_CSR_SET HW_DIGCTL_OCRAM_BIST_CSR_CLR HW_DIGCTL_OCRAM_BIST_CSR_TOG 0x0F0 0x0F4 0x0F8 0x0FC The SRAM BIST Control and Status Register provides overall control of the integrated BIST engine. Table 6-28. HW_DIGCTL_OCRAM_BIST_CSR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 BIST_DEBUG_MODE 0 9 BIST_DATA_CHANGE 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BIST_CLKEN RSVD1 RSVD0 Table 6-29. HW_DIGCTL_OCRAM_BIST_CSR Bit Field Descriptions BITS 31:11 10 9 8 7:4 3 LABEL RSVD1 BIST_DEBUG_MODE BIST_DATA_CHANGE BIST_CLKEN RSVD0 FAIL RW RO RW RW RW RO RO RESET 0x0 0x0 0x0 0x0 0x0 0x0 DEFINITION Reserved. OCRAM BIST debug mode select OCRAM BIST data background select. Enable clock gate for OCRAM BIST. Reserved. BIST has failed. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-17 START DONE PASS FAIL Digital Control and On-Chip RAM Table 6-29. HW_DIGCTL_OCRAM_BIST_CSR Bit Field Descriptions BITS 2 PASS 1 DONE 0 START LABEL RW RESET RO 0x0 RO 0x0 RW 0x0 DEFINITION BIST has passed. BIST has completed. Initiate BIST of internal memory when high. DESCRIPTION: This register is used to start off the BIST operation on two RAMS in the DMA block. The status signals are returned after the BIST operation is completed to this register. EXAMPLE: To start the BIST operation, set HW_DIGCTL_1TRAM_BIST_CSR = 0x00000001. After the BIST is completed and the test passes, the contents of HW_DIGCTL_1TRAM_BIST_CSR will be 0x00000007, as the DONE and PASS flags will be set. 6.4.15 SRAM Status Register 0 Description HW_DIGCTL_OCRAM_STATUS0 HW_DIGCTL_OCRAM_STATUS0_SET HW_DIGCTL_OCRAM_STATUS0_CLR HW_DIGCTL_OCRAM_STATUS0_TOG 0x110 0x114 0x118 0x11C The SRAM Status Register 0 is a read-only fail data register. Table 6-30. HW_DIGCTL_OCRAM_STATUS0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FAILDATA00 Table 6-31. HW_DIGCTL_OCRAM_STATUS0 Bit Field Descriptions BITS LABEL 31:0 FAILDATA00 RW RESET RO 0x0 DEFINITION This read-only bit field contains the fail data for the first fail in block 0. DESCRIPTION: This register contains fail data for the first fail in block 0. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS0_RD(); 6.4.16 SRAM Status Register 1 Description HW_DIGCTL_OCRAM_STATUS1 HW_DIGCTL_OCRAM_STATUS1_SET HW_DIGCTL_OCRAM_STATUS1_CLR HW_DIGCTL_OCRAM_STATUS1_TOG 0x120 0x124 0x128 0x12C The SRAM Status Register 1 is a read-only fail data register. i.MX23 Applications Processor Reference Manual, Rev. 1 6-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM Table 6-32. HW_DIGCTL_OCRAM_STATUS1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FAILDATA01 Table 6-33. HW_DIGCTL_OCRAM_STATUS1 Bit Field Descriptions BITS LABEL 31:0 FAILDATA01 RW RESET RO 0x0 DEFINITION This read-only bit field contains the fail data for the second fail in block 0. DESCRIPTION: This register contains fail data for the second fail in block 0. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS1_RD(); 6.4.17 SRAM Status Register 2 Description HW_DIGCTL_OCRAM_STATUS2 HW_DIGCTL_OCRAM_STATUS2_SET HW_DIGCTL_OCRAM_STATUS2_CLR HW_DIGCTL_OCRAM_STATUS2_TOG 0x130 0x134 0x138 0x13C SRAM Status Register 2 is a read-only fail data register. Table 6-34. HW_DIGCTL_OCRAM_STATUS2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FAILDATA10 Table 6-35. HW_DIGCTL_OCRAM_STATUS2 Bit Field Descriptions BITS LABEL 31:0 FAILDATA10 RW RESET RO 0x0 DEFINITION This read-only bit field contains the fail data for the first fail in block 1. DESCRIPTION: This register contains fail data for the first fail in block 1. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS2_RD(); 6.4.18 SRAM Status Register 3 Description HW_DIGCTL_OCRAM_STATUS3 HW_DIGCTL_OCRAM_STATUS3_SET 0x140 0x144 RAM Status Register 3 is a read-only fail data register. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-19 Digital Control and On-Chip RAM HW_DIGCTL_OCRAM_STATUS3_CLR HW_DIGCTL_OCRAM_STATUS3_TOG 0x148 0x14C Table 6-36. HW_DIGCTL_OCRAM_STATUS3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FAILDATA11 Table 6-37. HW_DIGCTL_OCRAM_STATUS3 Bit Field Descriptions BITS LABEL 31:0 FAILDATA11 RW RESET RO 0x0 DEFINITION This read-only bit field contains the fail data for the second fail in block 1. DESCRIPTION: This register contains fail data for the second fail in block 1. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS3_RD(); 6.4.19 SRAM Status Register 4 Description HW_DIGCTL_OCRAM_STATUS4 HW_DIGCTL_OCRAM_STATUS4_SET HW_DIGCTL_OCRAM_STATUS4_CLR HW_DIGCTL_OCRAM_STATUS4_TOG 0x150 0x154 0x158 0x15C SRAM Status Register 4 is a read-only fail data register. Table 6-38. HW_DIGCTL_OCRAM_STATUS4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FAILDATA20 Table 6-39. HW_DIGCTL_OCRAM_STATUS4 Bit Field Descriptions BITS LABEL 31:0 FAILDATA20 RW RESET RO 0x0 DEFINITION This read-only bit field contains the fail data for the first fail in block 2. DESCRIPTION: This register contains fail data for the first fail in block 2. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS4_RD(); i.MX23 Applications Processor Reference Manual, Rev. 1 6-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM 6.4.20 SRAM Status Register 5 Description HW_DIGCTL_OCRAM_STATUS5 HW_DIGCTL_OCRAM_STATUS5_SET HW_DIGCTL_OCRAM_STATUS5_CLR HW_DIGCTL_OCRAM_STATUS5_TOG 0x160 0x164 0x168 0x16C SRAM Status Register 5 is a read-only fail data register. Table 6-40. HW_DIGCTL_OCRAM_STATUS5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FAILDATA21 Table 6-41. HW_DIGCTL_OCRAM_STATUS5 Bit Field Descriptions BITS LABEL 31:0 FAILDATA21 RW RESET RO 0x0 DEFINITION This read-only bit field contains the fail data for the second fail in block 2. DESCRIPTION: This register contains fail data for the second fail in block 2. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS5_RD(); 6.4.21 SRAM Status Register 6 Description HW_DIGCTL_OCRAM_STATUS6 HW_DIGCTL_OCRAM_STATUS6_SET HW_DIGCTL_OCRAM_STATUS6_CLR HW_DIGCTL_OCRAM_STATUS6_TOG 0x170 0x174 0x178 0x17C SRAM Status Register 6 is a read-only fail data register. Table 6-42. HW_DIGCTL_OCRAM_STATUS6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FAILDATA30 Table 6-43. HW_DIGCTL_OCRAM_STATUS6 Bit Field Descriptions BITS LABEL 31:0 FAILDATA30 RW RESET RO 0x0 DEFINITION This read-only bit field contains the fail data for the first fail in block 3. DESCRIPTION: This register contains fail data for the first fail in block 3. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-21 Digital Control and On-Chip RAM EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS6_RD(); 6.4.22 SRAM Status Register 7 Description HW_DIGCTL_OCRAM_STATUS7 HW_DIGCTL_OCRAM_STATUS7_SET HW_DIGCTL_OCRAM_STATUS7_CLR HW_DIGCTL_OCRAM_STATUS7_TOG 0x180 0x184 0x188 0x18C SRAM Status Register 7 is a read-only fail data register. Table 6-44. HW_DIGCTL_OCRAM_STATUS7 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 FAILDATA31 Table 6-45. HW_DIGCTL_OCRAM_STATUS7 Bit Field Descriptions BITS LABEL 31:0 FAILDATA31 RW RESET RO 0x0 DEFINITION This read-only bit field contains the fail data for the second fail in block 3. DESCRIPTION: This register contains fail data for the second fail in block 3. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS7_RD(); 6.4.23 SRAM Status Register 8 Description HW_DIGCTL_OCRAM_STATUS8 HW_DIGCTL_OCRAM_STATUS8_SET HW_DIGCTL_OCRAM_STATUS8_CLR HW_DIGCTL_OCRAM_STATUS8_TOG 0x190 0x194 0x198 0x19C SRAM Status Register 8 is a read-only fail address register. Table 6-46. HW_DIGCTL_OCRAM_STATUS8 3 1 3 0 RSVD3 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 FAILADDR01 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 RSVD2 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 FAILADDR00 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 6-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM Table 6-47. HW_DIGCTL_OCRAM_STATUS8 Bit Field Descriptions BITS LABEL 31:29 RSVD3 28:16 FAILADDR01 15:13 RSVD2 12:0 FAILADDR00 RW RESET RO 0x0 RO 0x0 RO 0x0 RO 0x0 DEFINITION This field is unused. This read-only bit field contains the failing address for the second fail in block 0. This field is unused. This read-only bit field contains the failing address for the first fail in block 0. DESCRIPTION: This register contains fail data for the first and second failures in block 0. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS8_RD(); 6.4.24 SRAM Status Register 9 Description HW_DIGCTL_OCRAM_STATUS9 HW_DIGCTL_OCRAM_STATUS9_SET HW_DIGCTL_OCRAM_STATUS9_CLR HW_DIGCTL_OCRAM_STATUS9_TOG 0x1A0 0x1A4 0x1A8 0x1AC SRAM Status Register 9 is a read-only fail address register. Table 6-48. HW_DIGCTL_OCRAM_STATUS9 3 1 3 0 RSVD3 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 FAILADDR11 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 RSVD2 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 FAILADDR10 0 5 0 4 0 3 0 2 0 1 0 0 Table 6-49. HW_DIGCTL_OCRAM_STATUS9 Bit Field Descriptions BITS LABEL 31:29 RSVD3 28:16 FAILADDR11 15:13 RSVD2 12:0 FAILADDR10 RW RESET RO 0x0 RO 0x0 RO 0x0 RO 0x0 DEFINITION This field is unused. This read-only bit field contains the failing address for the second fail in block 1. This field is unused. This read-only bit field contains the failing address for the first fail in block 1. DESCRIPTION: This register contains fail data for the first second failures in block 1. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS9_RD(); i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-23 Digital Control and On-Chip RAM 6.4.25 SRAM Status Register 10 Description HW_DIGCTL_OCRAM_STATUS10 HW_DIGCTL_OCRAM_STATUS10_SET HW_DIGCTL_OCRAM_STATUS10_CLR HW_DIGCTL_OCRAM_STATUS10_TOG 0x1B0 0x1B4 0x1B8 0x1BC SRAM Status Register 10 is a read-only fail address register. Table 6-50. HW_DIGCTL_OCRAM_STATUS10 3 1 3 0 RSVD3 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 FAILADDR21 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 RSVD2 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 FAILADDR20 0 5 0 4 0 3 0 2 0 1 0 0 Table 6-51. HW_DIGCTL_OCRAM_STATUS10 Bit Field Descriptions BITS LABEL 31:29 RSVD3 28:16 FAILADDR21 15:13 RSVD2 12:0 FAILADDR20 RW RESET RO 0x0 RO 0x0 RO 0x0 RO 0x0 DEFINITION This field is unused. This read-only bit field contains the failing address for the second fail in block 2. This field is unused. This read-only bit field contains the failing address for the first fail in block 2. DESCRIPTION: This register contains fail data for the first and second failures in block 2. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS10_RD(); 6.4.26 SRAM Status Register 11 Description HW_DIGCTL_OCRAM_STATUS11 HW_DIGCTL_OCRAM_STATUS11_SET HW_DIGCTL_OCRAM_STATUS11_CLR HW_DIGCTL_OCRAM_STATUS11_TOG 0x1C0 0x1C4 0x1C8 0x1CC SRAM Status Register 11 is a read-only fail address register. i.MX23 Applications Processor Reference Manual, Rev. 1 6-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM Table 6-52. HW_DIGCTL_OCRAM_STATUS11 3 1 3 0 RSVD3 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 FAILADDR31 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 RSVD2 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 FAILADDR30 0 5 0 4 0 3 0 2 0 1 0 0 Table 6-53. HW_DIGCTL_OCRAM_STATUS11 Bit Field Descriptions BITS LABEL 31:29 RSVD3 28:16 FAILADDR31 15:13 RSVD2 12:0 FAILADDR30 RW RESET RO 0x0 RO 0x0 RO 0x0 RO 0x0 DEFINITION This field is unused. This read-only bit field contains the failing address for the second fail in block 3. This field is unused. This read-only bit field contains the failing address for the first fail in block 3. DESCRIPTION: This register contains fail data for the first and second failures in block 3. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS11_RD(); 6.4.27 SRAM Status Register 12 Description HW_DIGCTL_OCRAM_STATUS12 HW_DIGCTL_OCRAM_STATUS12_SET HW_DIGCTL_OCRAM_STATUS12_CLR HW_DIGCTL_OCRAM_STATUS12_TOG 0x1D0 0x1D4 0x1D8 0x1DC SRAM Status Register 12 is a read-only fail state register. Table 6-54. HW_DIGCTL_OCRAM_STATUS12 3 1 3 0 RSVD3 2 9 2 8 2 7 2 6 FAILSTATE11 2 5 2 4 2 3 2 2 RSVD2 2 1 2 0 1 9 1 8 FAILSTATE10 1 7 1 6 1 5 1 4 RSVD1 1 3 1 2 1 1 1 0 FAILSTATE01 0 9 0 8 0 7 0 6 RSVD0 0 5 0 4 0 3 0 2 FAILSTATE00 0 1 0 0 Table 6-55. HW_DIGCTL_OCRAM_STATUS12 Bit Field Descriptions BITS LABEL 31:28 RSVD3 27:24 FAILSTATE11 RW RESET RO 0x0 RO 0x0 DEFINITION This field is unused. This read-only bit field contains the failing state for the second fail in block 1. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-25 Digital Control and On-Chip RAM Table 6-55. HW_DIGCTL_OCRAM_STATUS12 Bit Field Descriptions BITS LABEL 23:20 RSVD2 19:16 FAILSTATE10 15:12 RSVD1 11:8 FAILSTATE01 7:4 3:0 RSVD0 FAILSTATE00 RW RESET RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 DEFINITION This field is unused. This read-only bit field contains the failing state for the first fail in block 1. This field is unused. This read-only bit field contains the failing state for the second fail in block 0. This field is unused. This read-only bit field contains the failing state for the first fail in block 0. DESCRIPTION: This register contains fail data for the first and second failures in blocks 0 and 1. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS12_RD(); 6.4.28 SRAM Status Register 13 Description HW_DIGCTL_OCRAM_STATUS13 HW_DIGCTL_OCRAM_STATUS13_SET HW_DIGCTL_OCRAM_STATUS13_CLR HW_DIGCTL_OCRAM_STATUS13_TOG 0x1E0 0x1E4 0x1E8 0x1EC SRAM Status Register 13 is a read-only fail state register. Table 6-56. HW_DIGCTL_OCRAM_STATUS13 3 1 3 0 RSVD3 2 9 2 8 2 7 2 6 FAILSTATE31 2 5 2 4 2 3 2 2 RSVD2 2 1 2 0 1 9 1 8 FAILSTATE30 1 7 1 6 1 5 1 4 RSVD1 1 3 1 2 1 1 1 0 FAILSTATE21 0 9 0 8 0 7 0 6 RSVD0 0 5 0 4 0 3 0 2 FAILSTATE20 Freescale Semiconductor Preliminary--Subject to Change Without Notice 0 1 0 0 Table 6-57. HW_DIGCTL_OCRAM_STATUS13 Bit Field Descriptions BITS LABEL 31:28 RSVD3 27:24 FAILSTATE31 23:20 RSVD2 19:16 FAILSTATE30 15:12 RSVD1 11:8 FAILSTATE21 RW RESET RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 DEFINITION This field is unused. This read-only bit field contains the failing state for the second fail in block 3. This field is unused. This read-only bit field contains the failing state for the first fail in block 3. This field is unused. This read-only bit field contains the failing state for the second fail in block 2. i.MX23 Applications Processor Reference Manual, Rev. 1 6-26 Digital Control and On-Chip RAM Table 6-57. HW_DIGCTL_OCRAM_STATUS13 Bit Field Descriptions BITS LABEL 7:4 RSVD0 3:0 FAILSTATE20 RW RESET RO 0x0 RO 0x0 DEFINITION This field is unused. This read-only bit field contains the failing state for the first fail in block 2. DESCRIPTION: This register contains fail data for the first and second failures in blocks 2 and 3. EXAMPLE: fail_data = HW_DIGCTL_OCRAM_STATUS0_RD(); 6.4.29 Digital Control Scratch Register 0 Description HW_DIGCTL_SCRATCH0 Table 6-58. HW_DIGCTL_SCRATCH0 0x290 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PTR Table 6-59. HW_DIGCTL_SCRATCH0 Bit Field Descriptions BITS 31:0 PTR LABEL RW RESET RW 0x0 DEFINITION DESCRIPTION: Scratch Pad Register 0. EXAMPLE: scratch_pad = (*void)HW_DIGCTL_SCRATCH0.PTR; 6.4.30 Digital Control Scratch Register 1 Description HW_DIGCTL_SCRATCH1 Table 6-60. HW_DIGCTL_SCRATCH1 0x2A0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PTR Table 6-61. HW_DIGCTL_SCRATCH1 Bit Field Descriptions BITS 31:0 PTR LABEL RW RESET RW 0x0 DEFINITION i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-27 Digital Control and On-Chip RAM DESCRIPTION: Scratch Pad Register 1. EXAMPLE: scratch_pad = (*void)HW_DIGCTL_SCRATCH1.PTR; 6.4.31 Digital Control ARM Cache Register Description HW_DIGCTL_ARMCACHE Table 6-62. HW_DIGCTL_ARMCACHE 0x2B0 This register provides the ARM cache RAM controls. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 RSVD4 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 VALID_SS 1 6 1 5 RSVD3 1 4 1 3 DRTY_SS 1 2 1 1 RSVD2 1 0 0 9 CACHE_SS 0 8 0 7 RSVD1 0 6 0 5 DTAG_SS 0 4 0 3 RSVD0 0 2 0 1 ITAG_SS 0 0 Table 6-63. HW_DIGCTL_ARMCACHE Bit Field Descriptions BITS LABEL 31:18 RSVD4 17:16 VALID_SS 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 RSVD3 DRTY_SS RSVD2 CACHE_SS RSVD1 DTAG_SS RSVD0 ITAG_SS RW RESET RO 0x0 RW 0x0 RO RW RO RW RO RW RO RW 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 DEFINITION Reserved. Timing Control for 64x24x1 RAMs (both instruction and data cache_valid arrays). Reserved. Timing Control for 128x8x1 RAM (DDRTY). Reserved. Timing Control for 1024x32x4 RAMs (both instruction and data cache arrays). Reserved. Timing Control for 256x22x4 RAM (DTAG). Reserved. Timing Control for 128x22x4 RAM (ITAG). DESCRIPTION: ARM Cache Control Register. EXAMPLE: cache_timing = HW_DIGCTL_ARMCACHE.CACHE_SS; 6.4.32 Debug Trap Range Low Address Description The Debug Trap Range Low Address Register defines the lower bound for an address range that can be enabled to trigger an interrupt to the ARM core when an AHB cycle occurs within this range. HW_DIGCTL_DEBUG_TRAP_ADDR_LOW 0x2C0 i.MX23 Applications Processor Reference Manual, Rev. 1 6-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM Table 6-64. HW_DIGCTL_DEBUG_TRAP_ADDR_LOW 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ADDR Table 6-65. HW_DIGCTL_DEBUG_TRAP_ADDR_LOW Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION This field contains the 32-bit lower address for the debug trap range. DESCRIPTION: This register sets the lower address that defines the debug trap function. When this function is enabled, any active AHB cycle on either Layer 0 or Layer 3 which accesses this range will trigger an interrupt to the ARM core. 6.4.33 Debug Trap Range High Address Description The Debug Trap Range High Address Register defines the upper bound for an address range that can be enabled to trigger an interrupt to the ARM core when an AHB cycle occurs within this range. HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH 0x2D0 Table 6-66. HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ADDR Table 6-67. HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION This field contains the 32-bit upper address for the debug trap range. DESCRIPTION: This register sets the upper address that defines the debug trap function. When this function is enabled, any active AHB cycle on either Layer 0 or Layer 3 which accesses this range will trigger an interrupt to the ARM core. 6.4.34 Freescale Copyright Identifier Register Description HW_DIGCTL_SGTL 0x300 Read-only Freescale Copyright Identifier Register. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-29 Digital Control and On-Chip RAM Table 6-68. HW_DIGCTL_SGTL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COPYRIGHT Table 6-69. HW_DIGCTL_SGTL Bit Field Descriptions BITS LABEL 31:0 COPYRIGHT RW RESET RO 0x6d676953 DEFINITION This read-only bit field contains the four bytes of the Freescale Copyright Identification String. DESCRIPTION: This register provides read-only access to the zero-terminated twelve-byte Freescale copyright identification string. This register behaves somewhat differently from all other APB registers in that it provides different read-back values at its three successive SCT bus addresses. The following binary values are read back at 0x300, 0x304, and 0x308 respectively: 0x6d676953 m,g,i,S at 0x300 0x6c655461 l,e,T,a at 0x304 0x00AEA92d 0x00, Registered Trademark (AE), Copyright ((c)), hyphen (-) at 0x308 The debugger does a string compare on these 12 successive little endian bytes. Any chip that reads back these values is either a Freescale chip or it is a competitors chip that is violating Freescale registered trademarks and or copyrights. EXAMPLE: printf("%s", (char *)HW_DIGCTL_SGTL_ADDR); 6.4.35 Digital Control Chip Revision Register Description HW_DIGCTL_CHIPID Table 6-70. HW_DIGCTL_CHIPID 0x310 Read-only chip revision register. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 PRODUCT_CODE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 6-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor REVISION RSVD0 Digital Control and On-Chip RAM Table 6-71. HW_DIGCTL_CHIPID Bit Field Descriptions BITS LABEL 31:16 PRODUCT_CODE 15:8 7:0 RSVD0 REVISION RW RESET RO 0x3780 RO 0x0 RO 0x00 DEFINITION This read-only bit field returns 0x3780, which identifies the generation from which the part is derived. Reserved. This read-only bit field always reads back the mask revision level of the chip. 0x0 = TA1 0x1 = TA2 0x2 = TA3 0x3 = TA4 EXAMPLE: FormatAndPrintChipID(HW_DIGCTL_CHIPID_PRODUCT_CODE,HW_DIGCTL_CHIPID_REVISION ); 6.4.36 AHB Statistics Control Register Description The AHB Statistics Control Register selects which AHB masters on each layer of the AHB subsystem are enabled to contribute to the statistics calculations. HW_DIGCTL_AHB_STATS_SELECT 0x330 Table 6-72. HW_DIGCTL_AHB_STATS_SELECT 3 1 3 0 2 9 2 8 2 7 2 6 L3_MASTER_SELECT 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 L2_MASTER_SELECT 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 L1_MASTER_SELECT 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 L0_MASTER_SELECT 0 1 0 0 RSVD3 RSVD2 RSVD1 Table 6-73. HW_DIGCTL_AHB_STATS_SELECT Bit Field Descriptions BITS LABEL 31:28 RSVD3 27:24 L3_MASTER_SELECT RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Set various bits of this bit field to one to enable performance monitoring in the AHB Layer 3 arbiter for the corresponding AHB master. APBH = 0x1 Select APBH DMA Master. APBX = 0x2 Select APBX DMA Master. USB = 0x4 Select USB Master. 23:20 RSVD2 19:16 L2_MASTER_SELECT RO 0x0 RW 0x0 Reserved. Set various bits of this bit field to one to enable performance monitoring in the AHB Layer 2 arbiter for the corresponding AHB master. ARM_D = 0x1 Select ARM D Master. 15:12 RSVD1 RO 0x0 Reserved. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-31 RSVD0 Digital Control and On-Chip RAM Table 6-73. HW_DIGCTL_AHB_STATS_SELECT Bit Field Descriptions BITS LABEL 11:8 L1_MASTER_SELECT RW RESET RW 0x0 DEFINITION Set various bits of this bit field to one to enable performance monitoring in the AHB Layer 1 arbiter for the corresponding AHB master. ARM_I = 0x1 Select ARM I Master. 7:4 3:0 RSVD0 L0_MASTER_SELECT RO 0x0 RW 0x0 Reserved. Set various bits of this bit field to one to enable performance monitoring in the AHB Layer 0 arbiter for the corresponding AHB master. ECC8 = 0x1 Select ECC8 Master. CRYPTO = 0x2 Select Crypto Master. 6.4.37 AHB Layer 0 Transfer Count Register Description The AHB Layer 0 Transfer Count Register counts the number of AHB bus cycles during which a transfer is active on AHB Layer 0. HW_DIGCTL_L0_AHB_ACTIVE_CYCLES 0x340 Table 6-74. HW_DIGCTL_L0_AHB_ACTIVE_CYCLES 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-75. HW_DIGCTL_L0_AHB_ACTIVE_CYCLES Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field contains the count of AHB bus cycles during which a master was active on the AHB Layer 0. DESCRIPTION: This field counts the number of AHB cycles in which a master was requesting a transfer, and the slave had not responded. This includes cycles in which it was requesting transfers but was not granted them, as well as cycles in which it was granted and driving the bus but the targeted slave was not ready. The master selects in HW_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT are used in the arbiter to mask which master's cycles are actually recorded here. EXAMPLE: NumberCycles = HW_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT_RD(); 6.4.38 AHB Layer 0 Performance Metric for Stalled Bus Cycles Register Description Used for AHB bus utilization measurements, the AHB Performance Metric for Stalled Bus Cycles Register counts the number of stalled AHB cycles. HW_DIGCTL_L0_AHB_DATA_STALLED 0x350 i.MX23 Applications Processor Reference Manual, Rev. 1 6-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM Table 6-76. HW_DIGCTL_L0_AHB_DATA_STALLED 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-77. HW_DIGCTL_L0_AHB_DATA_STALLED Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field counts the number of AHB cycles in which a master was stalled. DESCRIPTION: This counter increments on a data-phase of the AHB in which the HREADY signal is low, indicating a stalled data transfer. EXAMPLE: NumberStalledCycles = HW_DIGCTL_L0_AHB_DATA_STALLED_COUNT_RD(); 6.4.39 AHB Layer 0 Performance Metric for Valid Bus Cycles Register Description Used for AHB bus utilization measurements, the AHB Performance Metric for Valid Bus Cycles Register counts the number of actual AHB cycles in which a data transfer is completed. HW_DIGCTL_L0_AHB_DATA_CYCLES 0x360 Table 6-78. HW_DIGCTL_L0_AHB_DATA_CYCLES 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-79. HW_DIGCTL_L0_AHB_DATA_CYCLES Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field contains the count of AHB bus cycles during which data was actually transferred from a master to a slave or from a slave to a master. DESCRIPTION: This field counts the number of AHB cycles in which a master completed a data transfer (a data-phase in which HREADY is high). EXAMPLE: StartTime = HW_DIGCTL_HCLKCOUNT_RD(); while(HW_DIGCTL_L0_AHB_DATA_CYCLES.COUNT less than 1000000) { // wait for a specific number of xfers } ElapsedTime = HW_DIGCTL_HCLKCOUNT_RD() - StartTime; i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-33 Digital Control and On-Chip RAM 6.4.40 AHB Layer 1 Transfer Count Register Description The AHB Layer 1 Transfer Count Register counts the number of AHB bus cycles during which a transfer is active on AHB Layer 1. HW_DIGCTL_L1_AHB_ACTIVE_CYCLES 0x370 Table 6-80. HW_DIGCTL_L1_AHB_ACTIVE_CYCLES 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-81. HW_DIGCTL_L1_AHB_ACTIVE_CYCLES Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field contains the count of AHB bus cycles during which a master was active on the AHB Layer 1. DESCRIPTION: This field counts the number of AHB cycles in which a master was requesting a transfer, and the slave had not responded. This includes cycles in which it was requesting transfers but was not granted them, as well as cycles in which it was granted and driving the bus but the targeted slave was not ready. The master selects in HW_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT are used in the arbiter to mask which master's cycles are actually recorded here. EXAMPLE: NumberCycles = HW_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_RD(); 6.4.41 AHB Layer 1 Performance Metric for Stalled Bus Cycles Register Description Used for AHB bus utilization measurements, the AHB Performance Metric for Stalled Bus Cycles Register counts the number of stalled AHB cycles. HW_DIGCTL_L1_AHB_DATA_STALLED 0x380 Table 6-82. HW_DIGCTL_L1_AHB_DATA_STALLED 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-83. HW_DIGCTL_L1_AHB_DATA_STALLED Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field counts the number of AHB cycles in which a master was stalled. i.MX23 Applications Processor Reference Manual, Rev. 1 6-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM DESCRIPTION: This counter increments on a data-phase of the AHB in which the HREADY signal is low, indicating a stalled data transfer. EXAMPLE: NumberStalledCycles = HW_DIGCTL_L1_AHB_DATA_STALLED_COUNT_RD(); 6.4.42 AHB Layer 1 Performance Metric for Valid Bus Cycles Register Description Used for AHB bus utilization measurements, the AHB Performance Metric for Valid Bus Cycles Register counts the number of actual AHB cycles in which a data transfer is completed. HW_DIGCTL_L1_AHB_DATA_CYCLES 0x390 Table 6-84. HW_DIGCTL_L1_AHB_DATA_CYCLES 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-85. HW_DIGCTL_L1_AHB_DATA_CYCLES Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field contains the count of AHB bus cycles during which data was actually transferred from a master to a slave or from a slave to a master. DESCRIPTION: This field counts the number of AHB cycles in which a master completed a data transfer (a data-phase in which HREADY is high). EXAMPLE: StartTime = HW_DIGCTL_HCLKCOUNT_RD(); while(HW_DIGCTL_L1_AHB_DATA_CYCLES.COUNT less than 1000000) { // wait for a specific number of xfers } ElapsedTime = HW_DIGCTL_HCLKCOUNT_RD() - StartTime; 6.4.43 AHB Layer 2 Transfer Count Register Description The AHB Layer 2 Transfer Count Register counts the number of AHB bus cycles during which a transfer is active on AHB Layer 2. HW_DIGCTL_L2_AHB_ACTIVE_CYCLES 0x3A0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-35 Digital Control and On-Chip RAM Table 6-86. HW_DIGCTL_L2_AHB_ACTIVE_CYCLES 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-87. HW_DIGCTL_L2_AHB_ACTIVE_CYCLES Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field contains the count of AHB bus cycles during which a master was active on the AHB Layer 2. DESCRIPTION: This field counts the number of AHB cycles in which a master was requesting a transfer, and the slave had not responded. This includes cycles in which it was requesting transfers but was not granted them, as well as cycles in which it was granted and driving the bus but the targeted slave was not ready. The master selects in HW_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT are used in the arbiter to mask which master's cycles are actually recorded here. EXAMPLE: NumberCycles = HW_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT_RD(); 6.4.44 AHB Layer 2 Performance Metric for Stalled Bus Cycles Register Description Used for AHB bus utilization measurements, the AHB Performance Metric for Stalled Bus Cycles Register counts the number of stalled AHB cycles. HW_DIGCTL_L2_AHB_DATA_STALLED 0x3B0 Table 6-88. HW_DIGCTL_L2_AHB_DATA_STALLED 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-89. HW_DIGCTL_L2_AHB_DATA_STALLED Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field counts the number of AHB cycles in which a master was stalled. DESCRIPTION: This counter increments on a data-phase of the AHB in which the HREADY signal is low, indicating a stalled data transfer. EXAMPLE: NumberStalledCycles = HW_DIGCTL_L2_AHB_DATA_STALLED_COUNT_RD(); i.MX23 Applications Processor Reference Manual, Rev. 1 6-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM 6.4.45 AHB Layer 2 Performance Metric for Valid Bus Cycles Register Description Used for AHB bus utilization measurements, the AHB Performance Metric for Valid Bus Cycles Register counts the number of actual AHB cycles in which a data transfer is completed. HW_DIGCTL_L2_AHB_DATA_CYCLES 0x3C0 Table 6-90. HW_DIGCTL_L2_AHB_DATA_CYCLES 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-91. HW_DIGCTL_L2_AHB_DATA_CYCLES Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field contains the count of AHB bus cycles during which data was actually transferred from a master to a slave or from a slave to a master. DESCRIPTION: This field counts the number of AHB cycles in which a master completed a data transfer (a data-phase in which HREADY is high). EXAMPLE: StartTime = HW_DIGCTL_HCLKCOUNT_RD(); while(HW_DIGCTL_L2_AHB_DATA_CYCLES.COUNT less than 1000000) { // wait for a specific number of xfers } ElapsedTime = HW_DIGCTL_HCLKCOUNT_RD() - StartTime; 6.4.46 AHB Layer 3 Transfer Count Register Description The AHB Layer 3 Transfer Count Register counts the number of AHB bus cycles during which a transfer is active on AHB Layer 3. HW_DIGCTL_L3_AHB_ACTIVE_CYCLES 0x3D0 Table 6-92. HW_DIGCTL_L3_AHB_ACTIVE_CYCLES 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-93. HW_DIGCTL_L3_AHB_ACTIVE_CYCLES Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field contains the count of AHB bus cycles during which a master was active on the AHB Layer 3. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-37 Digital Control and On-Chip RAM DESCRIPTION: This field counts the number of AHB cycles in which a master was requesting a transfer, and the slave had not responded. This includes cycles in which it was requesting transfers but was not granted them, as well as cycles in which it was granted and driving the bus but the targeted slave was not ready. The master selects in HW_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT are used in the arbiter to mask which master's cycles are actually recorded here. EXAMPLE: NumberCycles = HW_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT_RD(); 6.4.47 AHB Layer 3 Performance Metric for Stalled Bus Cycles Register Description Used for AHB bus utilization measurements, the AHB Performance Metric for Stalled Bus Cycles Register counts the number of stalled AHB cycles. HW_DIGCTL_L3_AHB_DATA_STALLED 0x3E0 Table 6-94. HW_DIGCTL_L3_AHB_DATA_STALLED 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-95. HW_DIGCTL_L3_AHB_DATA_STALLED Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field counts the number of AHB cycles in which a master was stalled. DESCRIPTION: This counter increments on a data-phase of the AHB in which the HREADY signal is low, indicating a stalled data transfer. EXAMPLE: NumberStalledCycles = HW_DIGCTL_L3_AHB_DATA_STALLED_COUNT_RD(); 6.4.48 AHB Layer 3 Performance Metric for Valid Bus Cycles Register Description Used for AHB bus utilization measurements, the AHB Performance Metric for Valid Bus Cycles Register counts the number of actual AHB cycles in which a data transfer is completed. HW_DIGCTL_L3_AHB_DATA_CYCLES 0x3F0 i.MX23 Applications Processor Reference Manual, Rev. 1 6-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Control and On-Chip RAM Table 6-96. HW_DIGCTL_L3_AHB_DATA_CYCLES 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 6-97. HW_DIGCTL_L3_AHB_DATA_CYCLES Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x0 DEFINITION This field contains the count of AHB bus cycles during which data was actually transferred from a master to a slave or from a slave to a master. DESCRIPTION: This field counts the number of AHB cycles in which a master completed a data transfer (a data-phase in which HREADY is high). EXAMPLE: StartTime = HW_DIGCTL_HCLKCOUNT_RD(); while(HW_DIGCTL_L3_AHB_DATA_CYCLES.COUNT less than 1000000) { // wait for a specific number of xfers } ElapsedTime = HW_DIGCTL_HCLKCOUNT_RD() - StartTime; 6.4.49 EMI CLK/CLKN Delay Adjustment Description HW_DIGCTL_EMICLK_DELAY 0x500 Used to adjust delay of the EMI_CLK and EMI_CLKN. Table 6-98. HW_DIGCTL_EMICLK_DELAY 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSVD0 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 NUM_TAPS DEFINITION Reserved. Select one of 32 delay line taps to delay the EMI_CLK and EMI_CLKN pins 0 1 0 0 Table 6-99. HW_DIGCTL_EMICLK_DELAY Bit Field Descriptions BITS LABEL 31:5 RSVD0 4:0 NUM_TAPS RW RESET RO 0x0 RW 0x0 DESCRIPTION: This register setting is useful in cases where additional setup time is required (at the expense of hold) for EMI Address/Command signals in SDRAM and mDDR modes. It can also be used to give additional write data setup time in SDRAM modes. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 6-39 Digital Control and On-Chip RAM EXAMPLE: Empty Example. DIGCTL Block digctl, Revision 1.0 i.MX23 Applications Processor Reference Manual, Rev. 1 6-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 7 On-Chip OTP (OCOTP) Controller This chapter describes the on-chip OTP (OCOTP) controller included on the i.MX23. Programmable registers are described in Section 7.4, "Programmable Registers." 7.1 * * * * Overview Full memory-mapped (restricted) read access of 1 Kbit of on-chip OTP ROM. Data-register programming interface for the 1 Kbit of OTP. Generation of the chip hardware capability bus. Chip-level pin access to nonrestricted portions of OTP. The on-chip OTP controller (OCOTP) provides the following functions: The OCOTP is connected to the APBH system peripheral bus and is accessible via the ARM core Data-AHB layer (Layer 2). Read accesses can be done at maximum HCLK frequency. Programming/writes can be performed at 24 MHz. The system diagram for the OCOTP is shown in Figure 7-1. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-1 On-Chip OTP (OCOTP) Controller APBS S OCO TP A P B In te rfa c e HW _O CO TP_CTR L S A P B 3 - to -A P B 2 B r id g e M H W _O CO TP _DATA H W /S W C a p a b ilit y , LO CK and RO M Shadow Regs APBH H W C a p a b ility B u s A ll B lo c k s O T P C o n tro lle r /S ta te M a c h in e C ry p to K e y + E n a b le To DCP T e s t/P in In te r fa c e 256x1 OTP 256x1 OTP 256x1 OTP Figure 7-1. On-Chip OTP (OCOTP) Controller Block Diagram 7.2 * Operation Programmer-model access to registers (see Section 7.4, "Programmable Registers," for register details). These operations require a bank opening sequence via HW_OCOTP_CTRL_RD_BANK_OPEN. Restricted 32-bit word write/program access to the 1-Kbit OTP The APB interface of the OCOTP provides two functions: * The OTP is divided into 32-bit words (32 in total). All the 32 words are memory-mapped to APBH addresses (for reads only). Writes require the use of HW_OCOTP_CTRL_ADDR. The customer view of the high-level OTP allocation is shown in Figure 7-2. i.MX23 Applications Processor Reference Manual, Rev. 1 7-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor 256x1 OTP On-Chip OTP (OCOTP) Controller HW_OCOTP_CTRL_ADDR 0x1F 0x1E 0x1D Shadow Regs 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 Pin Access 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E Shadow Regs 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Freescale Internal Freescale Internal Freescale Internal Freescale Internal Freescale Internal Freescale ROM Use Freescale ROM Use Freescale ROM Use Freescale Internal Freescale Internal Freescale Internal Freescale Internal Freescale Internal Freescale Internal Freescale Internal LOCK CUSTCAP Freescale Internal Freescale Internal Freescale Internal Freescale Internal Freescale Internal Freescale Internal Freescale Internal CRYPTO KEY CRYPTO KEY CRYPTO KEY CRYPTO KEY Customer Customer Customer Customer OTP Bank 0 OTP Bank 1 OTP Bank 2 OTP Bank 3 Figure 7-2. OCOTP Allocation OTP reads and writes can be performed on 32-bit words only. For writes, the 32-bit word reflects the "write-mask", such that bit fields with 0 will not be programmed and bit fields with 1 will be programmed. For OTP random access, the programming interface consists of: * * * * * HW_OCOTP_DATA--Data register (32- bit) for OTP programming (writes). HW_OCOTP_CTRL_ADDR--Address register (5-bit) for OTP programming (writes). HW_OCOTP_CTRL_BUSY--Programming/write request/status handshake bit. HW_OCOTP_CTRL_ERROR--Read/write access error status. HW_OCOTP_CTRL_RD_BANK_OPEN--Status of OTP read availability (reads). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-3 On-Chip OTP (OCOTP) Controller 7.2.1 Software Read Sequence Reading OTP contents is relatively simple, because all OTP words are memory-mapped on the APB space (see Section 7.4, "Programmable Registers," for details). These registers are read-only, except for the HW/SW capability shadow registers, which are writable until the appropriate LOCK bit in OTP is set. Due to the fuse-read architecture, the OTP banks must be open before they can be read. This is accomplished as follows (the following does not apply to shadow registers, which can be read at any time). 1. Program the HCLK to a frequency up to the maximum allowable HCLK frequency. Note that this cannot exceed 200 MHz. 2. Check that HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_ERROR are clear. 3. Set HW_OCOTP_CTRL_RD_BANK_OPEN. This will kick the controller to put the fuses into read mode. The controller will set HW_OCOTP_CTRL_BUSY until the OTP contents are readable. Note that if there was a pending write (holding HW_OCOTP_CTRL_BUSY) and HW_OCOTP_CTRL_RD_BANK_OPEN was set, the controller would complete the write and immediately move into read operation (keeping HW_OCOTP_CTRL_BUSY set while the banks are being opened). 4. Poll for HW_OCOTP_CTRL_BUSY clear. When HW_OCOTP_CTRL_BUSY is clear and HW_OCOTP_CTRL_RD_BANK_OPEN is set, read the data from the appropriate memory-mapped address. Note that this is not necessary for registers that are shadowed. Reading before HW_OCOTP_CTRL_BUSY is cleared by the controller, will return 0xBADA_BADA and will result in the setting of HW_OCOTP_CTRL_ERROR. Because opening banks takes approximately 33 HCLK cycles, immediate polling for BUSY is not recommended. 5. Once accesses are complete, clear HW_OCOTP_CTRL_RD_BANK_OPEN. Leaving the banks open will cause current drain. If data is accessed from a protected region (such as the crypto key, once a read LOCK bit has been set), the controller returns 0xBADA_BADA. In addition HW_OCOTP_CTRL_ERROR is set. It must be cleared by software before any new write access can be issued. Subsequent reads to unrestricted mapped OTP locations will still work successfully assuming that HW_OCOTP_CTRL_RD_BANK_OPEN is set and HW_OCOTP_CTRL_BUSY is clear. It should be noted that after opening the banks, read latencies to OTP are "instant" (meaning they behave like regular reads from hardware registers), since parallel loading is used. It should also be noted that setting HW_OCOTP_CTRL_RELOAD_SHADOWS to reload shadow registers does not set HW_OCOTP_CTRL_RD_BANK_OPEN. HW_OCOTP_CTRL_RD_BANK_OPEN can only be set and cleared by software. Forced reloading of shadows is covered in Section 7.2.4, "Shadow Registers and Hardware Capability Bus." i.MX23 Applications Processor Reference Manual, Rev. 1 7-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller 7.2.2 Software Write Sequence In order to avoid erroneous code performing erroneous writes to OTP, a special unlocking sequence is required for writes. 1. Program HCLK to 24 MHz. OTP writes do not work at frequencies above 24 MHz. 2. Set the VDDIO voltage to 2.8 V (using HW_POWER_VDDIOCTRL_TRG). The VDDIO voltage is used to program OTP. Incorrect voltage and frequency settings will result in the OTP being programmed with incorrect values. 3. Check that HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_ERROR are clear. Overlapped accesses are not supported by the controller. Any pending write must be completed before a write access can be requested. In addition, the banks cannot be open for reading, so HW_OCOTP_CTRL_RD_BANK_OPEN must also be clear. If the write is done following a previous write, the postamble wait period of 2 s must be followed after the clearing of HW_OCOTP_CTRL_BUSY (see Section 7.2.3, "Write Postamble,"). 4. Write the requested address to HW_OCOTP_CTRL_ADDR and program the unlock code into HW_OCOTP_CTRL_WR_UNLOCK. This must be programmed for each write access. The lock code is documented in the register description. Both the unlock code and address can be written in the same operation. 5. Write the data to HW_OCOTP_DATA. This automatically sets HW_OCOTP_CTRL_BUSY and clears HW_OCOTP_CTRL_WR_UNLOCK. In this case, the data is a programming mask. Bit fields with ones will result in that OTP bit being set. Only the controller can clear HW_OCOTP_CTRL_BUSY. The controller will use the mask to program a 32-bit word in the OTP per the address in ADDR. At the same time that the write is accepted, the controller makes an internal copy of HW_OCOTP_CTRL_ADDR that cannot be updated until the next write sequence is initiated. This copy guarantees that erroneous writes to HW_OCOTP_CTRL_ADDR will not affect an active write operation. It should also be noted that, during the programming, HW_OCOTP_DATA will shift right (with zero fill). This shifting is required to program the OTP serially. During the write operation, HW_OCOTP_DATA cannot be modified. 6. Once complete, the controller clears BUSY. Beyond this, the 2-s postamble requirement must be met before submitting any further OTP operations (see Section 7.2.3, "Write Postamble,"). A write request to a protected region will result in no OTP access and no setting of HW_OCOTP_CTRL_BUSY. In addition, HW_OCOTP_CTRL_ERROR will be set. It must be cleared by software before any new write access can be issued. It should be noted that write latencies to OTP are in the order of 10s to 100s of microseconds per word. Write latencies will vary based on the location of the word within the OTP bank. Once a write is initiated, HW_OCOTP_DATA is shifted one bit per every 32 HCLK cycles. Given: 8 words per OTP bank 32 bits per word tHCLK is the HCLK clock period n word locations (where 0 n 7) i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-5 On-Chip OTP (OCOTP) Controller Then, the approximate write latency for a given word is: tHCLK * 32 * 32 * n In addition to this latency, software must allow for the 2-s postamble (using HW_DIGCTL_MICROSECONDS), as described in Section 7.2.3, "Write Postamble," 7.2.3 Write Postamble Due to internal electrical characteristics of the OTP during writes, all OTP operations following a write must be separated by 2 s after the clearing of HW_OCOTP_CTRL_BUSY following the write. This guarantees programming voltages on-chip to reach a steady state when exiting a write sequence. This includes reads, shadow reloads, or other writes. A recommended software sequence to meet the postamble requirements is as follows: 1. Issue the write and poll for BUSY (as per Section 7.2.2, "Software Write Sequence,"). 2. Once BUSY is clear, use HW_DIGCTL_MICROSECONDS to wait 2 s. 3. Perform the next OTP operation. 7.2.4 Shadow Registers and Hardware Capability Bus The on-chip customer hardware capability bus is generated using a direct connection to the HW_OCOTP_CUSTCAP shadow register. The bits are copied from the OTP on reset. They can be modified until HW_OCOTP_LOCK_CUSTCAP_SHADOW is set. The user can force a reload of the shadow registers (including HW_OCOTP_LOCK) without having to reset the device, which is useful for debugging code. To force a reload: * * * Set HW_OCOTP_CTRL_RELOAD_SHADOWS. Wait for HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_RELOAD_SHADOWS to be cleared by the controller. Attempting to write to the shadow registers while the shadows are being reloaded will result in the setting of HW_OCOTP_CTRL_ERROR. In addition, the register will not take the attempted write (yielding to the reload instead). Attempting to write to a shadow register that is locked will result in the setting of HW_OCOTP_CTRL_ERROR. * HW_OCOTP_CTRL_RELOAD_SHADOWS can be set at any time. There is no need to wait for HW_OCOTP_CTRL_BUSY or HW_OCOTP_CTRL_ERROR to be clear. * * In the case of HW_OCOTP_CTRL_BUSY being set due to an active write, the controller will perform the bank opening and shadow reloading immediately after the completion of the write. In the case where HW_OCOTP_CTRL_RD_BANK_OPEN is set, the shadow reload will be performed immediately after the banks are closed by software (by clearing HW_OCOTP_CTRL_RD_BANK_OPEN). It should be noted that BUSY will take approximately 33 HCLK cycles to clear, so polling for HW_OCOTP_CTRL_BUSY immediately after clearing HW_OCOTP_CTRL_RD_BANK_OPEN is not recommended. i.MX23 Applications Processor Reference Manual, Rev. 1 7-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller * In all cases, the controller will clear HW_OCOTP_CTRL_RELOAD_SHADOWS after the successful completion of the operation. 7.3 Behavior During Reset The OCOTP is always active. The shadow registers described in Section 7.4, "Programmable Registers," automatically load the appropriate OTP contents after reset is deasserted. During this load-time HW_OCOTP_CTRL_BUSY is set. The load time is approximately 32 HCLK cycles after the deassertion of reset. These shadow registers can be reloaded as described in Section 7.2.4, "Shadow Registers and Hardware Capability Bus." 7.4 Programmable Registers The following registers are available for programmer access and control of the OCOTP. 7.4.1 OTP Controller Control Register Description The OCOTP Control and Status Register specifies the copy state, as well as the control required for random access of the OTP memory HW_OCOTP_CTRL HW_OCOTP_CTRL_SET HW_OCOTP_CTRL_CLR HW_OCOTP_CTRL_TOG Table 7-1. HW_OCOTP_CTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RELOAD_SHADOWS 1 2 RD_BANK_OPEN 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x000 0x004 0x008 0x00C WR_UNLOCK RSRVD1 RSRVD2 RSRVD0 ERROR i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-7 ADDR BUSY On-Chip OTP (OCOTP) Controller Table 7-2. HW_OCOTP_CTRL Bit Field Descriptions BITS LABEL 31:16 WR_UNLOCK RW RESET RW 0x0 DEFINITION Write 0x3E77 to enable OTP write accesses. NOTE: This register must be unlocked on a write-by-write basis (a write is initiated when HW_OCOTP_DATA is written), so the UNLOCK bitfield must contain the correct key value during all writes to HW_OCOTP_DATA, otherwise a write shall not be initiated. This field is automatically cleared after a successful write completion (clearing of BUSY). KEY = 0x3E77 Key needed to unlock HW_OCOTP_DATA register. 15:14 RSRVD2 13 RELOAD_SHADOWS RO 0x0 RW 0x0 12 RD_BANK_OPEN RW 0x0 11:10 RSRVD1 9 ERROR RO 0x0 RW 0x0 These bits always read back zero. Set to force re-loading the shadow registers (HW/SW capability and LOCK). This operation will automatically open banks (but will not set RD_BANK_OPEN) and set BUSY. Once the shadow registers have been re-loaded, BUSY and RELOAD_SHADOWS are automatically cleared by the controller. There is no need to set RD_BANK_OPEN to force the reload. If RD_BANK_OPEN is already set, its still possible to set RELOAD_SHADOWS. In this case, the shadow registers will only be updated upon the clearing of RD_BANK_OPEN. Set to open the all the OTP banks for reading. When set, the controller sets BUSY to allow time for the banks to become available (approximatly 32 HCLK cycles later at which time the controller will clear BUSY). Once BUSY is clear, the various OTP words are accessible via their memory mapped address. Note that OTP words which are shadowed, can be read at anytime and will not be affected by RD_BANK_OPEN. This bit must be cleared after reading is complete. Keeping the OTP banks open causes additional current draw. BUSY must be clear before this setting will take affect. If there is a write transaction pending (holding BUSY), then the bank opening sequence will begin automatically upon the previous transaction clears BUSY. Note that if a read is performed from non-shadowed locations without RD_BANK_OPEN, ERROR will be set These bits always read back zero. Set by the controller when either an access to a locked region is requested or a read is requested from non-shadowed efuse locations without the banks being open. Must be cleared before any further write access can be performed. This bit can only be set by the controller. This bit is also set if the Pin interface is active and software requests an access to the OTP. In this instance, the ERROR bit cannot be cleared until the Pin interface access has completed. Reset this bit by writing a one to the SCT clear address space and not by a general write. i.MX23 Applications Processor Reference Manual, Rev. 1 7-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller Table 7-2. HW_OCOTP_CTRL Bit Field Descriptions BITS 8 BUSY LABEL RW RESET RO 0x0 DEFINITION OTP controller status bit. When active, no new write access or bank open operations (including RELOAD_SHADOWS) can be performed. Cleared by controller when access complete (for writes), or the banks are open (for reads). After reset (or after setting RELOAD_SHADOWS), this bit is set by the controller until the HW/SW and LOCK registers are successfully copied, after which time it is automatically cleared by the controller. These bits always read back zero. OTP write access address register. Specifies one of 32 word address locations (0x00 - 0x1F). If a valid write is accepted by the controller (see HW_OCOTP_DATA for details on what constitutes a valid write), the controller makes an internal copy of this value (to avoid the OTP programming being corrupted). This internal copy will not update until the write access is complete. 7:5 4:0 RSRVD0 ADDR RO 0x0 RW 0x0 DESCRIPTION: The OCOTP Control and Status Register provides the necessary software interface for performing read and write operations to the On-Chip OTP (One-Time Programmable ROM). The control fields such as WR_UNLOCK, ADDR and BUSY/ERROR may be used in conjuction with the HW_OCOTP_DATA register to perform write operations. Read operations are performed via the direct memory mapped registers. In the cases where OTP values are shadowed into local memory storage, the memory mapped location can be read directly. In the cases where the OTP values are not shadowed into local memory, the read-preparation sequence involving RD_BANK_OPEN and BUSY/ERROR fields must be used before performing the read. EXAMPLE: Empty Example. 7.4.2 OTP Controller Write Data Register Description HW_OCOTP_DATA Table 7-3. HW_OCOTP_DATA 0x010 The OCOTP Data Register is used for OTP Programming 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DATA Table 7-4. HW_OCOTP_DATA Bit Field Descriptions BITS 31:0 DATA LABEL RW RESET RW 0x0 DEFINITION Used to initiate a write to OTP. Please see the "Software Write Sequence" section for operating details. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-9 On-Chip OTP (OCOTP) Controller DESCRIPTION: This register is used in conjuction with HW_OCOTP_CTRL to perform one-time writes to the OTP. Please see the "Software Write Sequence" section for operating details. EXAMPLE: Empty Example. 7.4.3 Value of OTP Bank0 Word0 (Customer) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_CUST0 Table 7-5. HW_OCOTP_CUST0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x020 BITS Table 7-6. HW_OCOTP_CUST0 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 0, word 0 (ADDR = 0x00) DESCRIPTION: Non-shadowed memory mapped access to OTP Bank 0, word 0 (ADDR = 0x00). EXAMPLE: Empty Example. 7.4.4 Value of OTP Bank0 Word1 (Customer) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_CUST1 Table 7-7. HW_OCOTP_CUST1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x030 BITS i.MX23 Applications Processor Reference Manual, Rev. 1 7-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller Table 7-8. HW_OCOTP_CUST1 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 0, word 1 (ADDR = 0x01) DESCRIPTION: Non-shadowed memory mapped access to OTP Bank 0, word 1 (ADDR = 0x01). EXAMPLE: Empty Example. 7.4.5 Value of OTP Bank0 Word2 (Customer) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_CUST2 Table 7-9. HW_OCOTP_CUST2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x040 BITS Table 7-10. HW_OCOTP_CUST2 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 0, word 2 (ADDR = 0x02) DESCRIPTION: Non-shadowed memory mapped access to OTP Bank 0, word 2 (ADDR = 0x02). EXAMPLE: Empty Example. 7.4.6 Value of OTP Bank0 Word3 (Customer) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_CUST3 0x050 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-11 On-Chip OTP (OCOTP) Controller Table 7-11. HW_OCOTP_CUST3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BITS Table 7-12. HW_OCOTP_CUST3 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 0, word 3 (ADDR = 0x03) DESCRIPTION: Non-shadowed memory mapped access to OTP Bank 0, word 3 (ADDR = 0x03). EXAMPLE: Empty Example. 7.4.7 Value of OTP Bank0 Word4 (Crypto Key) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_CRYPTO0 Table 7-13. HW_OCOTP_CRYPTO0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x060 BITS Table 7-14. HW_OCOTP_CRYPTO0 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 0, word 4 (ADDR = 0x04). If LOCK[CRYPTOKEY] is set, returns 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR] DESCRIPTION: Non-shadowed memory mapped access to OTP Bank 0, word 4 (ADDR = 0x04). EXAMPLE: Empty Example. 7.4.8 Value of OTP Bank0 Word5 (Crypto Key) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and i.MX23 Applications Processor Reference Manual, Rev. 1 7-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_CRYPTO1 Table 7-15. HW_OCOTP_CRYPTO1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x070 BITS Table 7-16. HW_OCOTP_CRYPTO1 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 0, word 5 (ADDR = 0x05). If LOCK[CRYPTOKEY] is set, returns 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR] DESCRIPTION: Non-shadowed memory mapped access to OTP Bank 0, word 5 (ADDR = 0x05). EXAMPLE: Empty Example. 7.4.9 Value of OTP Bank0 Word6 (Crypto Key) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_CRYPTO2 Table 7-17. HW_OCOTP_CRYPTO2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x080 BITS Table 7-18. HW_OCOTP_CRYPTO2 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 0, word 6 (ADDR = 0x06). If LOCK[CRYPTOKEY] is set, returns 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR] DESCRIPTION: Non-shadowed memory mapped access to OTP Bank 0, word 6 (ADDR = 0x06). EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-13 On-Chip OTP (OCOTP) Controller 7.4.10 Value of OTP Bank0 Word7 (Crypto Key) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_CRYPTO3 Table 7-19. HW_OCOTP_CRYPTO3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x090 BITS Table 7-20. HW_OCOTP_CRYPTO3 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 0, word 7 (ADDR = 0x07). If LOCK[CRYPTOKEY] is set, returns 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR] DESCRIPTION: Non-shadowed memory mapped access to OTP Bank 0, word 7 (ADDR = 0x07). EXAMPLE: Empty Example. 7.4.11 HW Capability Shadow Register 0 Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] HW_OCOTP_HWCAP0 Table 7-21. HW_OCOTP_HWCAP0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0A0 BITS Table 7-22. HW_OCOTP_HWCAP0 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RW 0x0 DEFINITION Shadow register for HW capability bits 31:0 (copy of OTP bank 1, word 0 (ADDR = 0x08)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. i.MX23 Applications Processor Reference Manual, Rev. 1 7-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller DESCRIPTION: Shadowed memory mapped access to OTP bank 1, word 0 (ADDR = 0x08). EXAMPLE: Empty Example. 7.4.12 HW Capability Shadow Register 1 Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] HW_OCOTP_HWCAP1 Table 7-23. HW_OCOTP_HWCAP1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0B0 BITS Table 7-24. HW_OCOTP_HWCAP1 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RW 0x0 DEFINITION Shadow register for HW capability bits 63:32 (copy of OTP bank 1, word 1 (ADDR = 0x09)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. DESCRIPTION: Shadowed memory mapped access to OTP bank 1, word 1 (ADDR = 0x09). EXAMPLE: Empty Example. 7.4.13 HW Capability Shadow Register 2 Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] HW_OCOTP_HWCAP2 Table 7-25. HW_OCOTP_HWCAP2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0C0 BITS i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-15 On-Chip OTP (OCOTP) Controller Table 7-26. HW_OCOTP_HWCAP2 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RW 0x0 DEFINITION Shadow register for HW capability bits 95:64 (copy of OTP bank 1, word 2 (ADDR = 0x0A)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. DESCRIPTION: Shadowed memory mapped access to OTP bank 1, word 2 (ADDR = 0x0A). EXAMPLE: Empty Example. 7.4.14 HW Capability Shadow Register 3 Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] HW_OCOTP_HWCAP3 Table 7-27. HW_OCOTP_HWCAP3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0D0 BITS Table 7-28. HW_OCOTP_HWCAP3 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RW 0x0 DEFINITION Shadow register for HW capability bits 127:96 (copy of OTP bank 1, word 3 (ADDR = 0x0B)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. DESCRIPTION: Shadowed memory mapped access to OTP bank 1, word 3 (ADDR = 0x0B). EXAMPLE: Empty Example. 7.4.15 HW Capability Shadow Register 4 Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] HW_OCOTP_HWCAP4 0x0E0 i.MX23 Applications Processor Reference Manual, Rev. 1 7-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller Table 7-29. HW_OCOTP_HWCAP4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BITS Table 7-30. HW_OCOTP_HWCAP4 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RW 0x0 DEFINITION Shadow register for HW capability bits 159:128 (copy of OTP bank 1, word 4 (ADDR = 0x0C)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. DESCRIPTION: Shadowed memory mapped access to OTP bank 1, word 4 (ADDR = 0x0C). EXAMPLE: Empty Example. 7.4.16 HW Capability Shadow Register 5 Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] HW_OCOTP_HWCAP5 Table 7-31. HW_OCOTP_HWCAP5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0F0 BITS Table 7-32. HW_OCOTP_HWCAP5 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RW 0x0 DEFINITION Shadow register for HW capability bits 191:160 (copy of OTP bank 1, word 5 (ADDR = 0x0D)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. DESCRIPTION: Shadowed memory mapped access to OTP bank 1, word 5 (ADDR = 0x0D). EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-17 On-Chip OTP (OCOTP) Controller 7.4.17 SW Capability Shadow Register Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] HW_OCOTP_SWCAP Table 7-33. HW_OCOTP_SWCAP 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x100 BITS Table 7-34. HW_OCOTP_SWCAP Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RW 0x0 DEFINITION Shadow register for SW capability bits 31:0 (copy of OTP bank 1, word 6 (ADDR = 0x0E)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. DESCRIPTION: Shadowed memory mapped access to OTP bank 1, word 6 (ADDR = 0x0E). EXAMPLE: Empty Example. 7.4.18 Customer Capability Shadow Register Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] HW_OCOTP_CUSTCAP Table 7-35. HW_OCOTP_CUSTCAP 3 1 CUST_DISABLE_WMADRM9 3 0 CUST_DISABLE_JANUSDRM10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ENABLE_SJTAG_12MA_DRIVE 0 3 0 2 RTC_XTAL_32768_PRESENT 0 1 RTC_XTAL_32000_PRESENT 0 0 0x110 USE_PARALLEL_JTAG RSRVD1 i.MX23 Applications Processor Reference Manual, Rev. 1 7-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD0 On-Chip OTP (OCOTP) Controller Table 7-36. HW_OCOTP_CUSTCAP Bit Field Descriptions BITS LABEL 31 CUST_DISABLE_WMADRM9 30 CUST_DISABLE_JANUSDRM 10 29:5 RSRVD1 4 ENABLE_SJTAG_12MA_DRI VE RW RESET RW 0x0 RW 0x0 RW 0x0 RW 0x0 DEFINITION Blow to disable WMA DRM9. Blow to disable WMA Janus DRM10. Reserved - do not blow these bits. Blow to force the 1-wire DEBUG (serial JTAG) pin to drive 12mA, the default is 8mA (see ENABLE_PJTAG_12MA_DRIVE in the ROM0 register for 6-wire parallel JTAG). This is a hardware override which will cause the drive select bits in the PINCTRL block to reset to the 12mA drive settings rather than the normal default of 8mA. The user is still free to reprogram these bits to other drive levels. During JTAG boot mode, the ROM reads this bit, then inverts it, and writes the value to the HW_DIGCTL_CTRL_USE_SERIAL_JTAG bit. If this bit is one, indicating parallel JTAG mode is selected, a zero is written to the DIGCTL USE_SERIAL_JTAG bit which places the device into 6-wire JTAG mode, and if this bit is zero, a one instead is written causing the SJTAG block to switch to the 1-wire serial JTAG mode. Blow to indicate the presence of an optional 32.768KHz crystal off-chip. Blow to indicate the presence of an optional 32.000KHz crystal off-chip. Reserved - do not blow these bits. 3 USE_PARALLEL_JTAG RW 0x0 2 1 0 RTC_XTAL_32768_PRESENT RW 0x0 RTC_XTAL_32000_PRESENT RW 0x0 RSRVD0 RW 0x0 DESCRIPTION: Shadowed memory mapped access to OTP bank 1, word 7 (ADDR = 0x0F). EXAMPLE: Empty Example. 7.4.19 LOCK Shadow Register OTP Bank 2 Word 0 Description Shadow register for OCOTP Lock Status Value (ADDR = 0x10). Copy of the state of the OTP lock regions. Copied from the OTP upon reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] HW_OCOTP_LOCK 0x120 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-19 On-Chip OTP (OCOTP) Controller Table 7-37. HW_OCOTP_LOCK 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 HWSW_SHADOW_ALT 2 2 CRYPTODCP_ALT 2 1 CRYPTOKEY_ALT 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 CUSTCAP_SHADOW 0 6 HWSW_SHADOW 0 5 0 4 0 3 0 2 0 1 0 0 UNALLOCATED ROM_SHADOW CRYPTODCP CRYPTOKEY CUSTCAP HWSW CUST3 CUST2 CUST1 Table 7-38. HW_OCOTP_LOCK Bit Field Descriptions BITS 31 ROM7 LABEL RW RESET RO 0x0 DEFINITION Status of ROM use region write lock bits (ADDR = 0x1F). When set, word 0x1F in the ROM region is locked. Status of ROM use region write lock bits (ADDR = 0x1E). When set, word 0x1E in the ROM region is locked. Status of ROM use region write lock bits (ADDR = 0x1D). When set, word 0x1D in the ROM region is locked. Status of ROM use region write lock bits (ADDR = 0x1C). When set, word 0x1C in the ROM region is locked. Status of ROM use region write lock bits (ADDR = 0x1B). When set, word 0x1B in the ROM region is locked. Status of ROM use region write lock bits (ADDR = 0x1A). When set, word 0x1A in the ROM region is locked. Status of ROM use region write lock bits (ADDR = 0x19). When set, word 0x19 in the ROM region is locked. Status of ROM use region write lock bits (ADDR = 0x18). When set, word 0x18 in the ROM region is locked. Status of alternate bit for HWSW_SHADOW lock Status of alternate bit for CRYPTODCP lock Status of alternate bit for CRYPTOKEY lock Status of Pin access lock bit. When set, pin access is disabled. Status of SGTL-OPS region (ADDR = 0x11-0x14) write lock bit. When set, region is locked. Status of un-assigned (ADDR = 0x17) write-lock bit. When set, un-asigned word at OTP address 0x17 is locked. Status of un-assigned (ADDR = 0x16) write-lock bit. When set, un-asigned word at OTP address 0x16 is locked. 30 ROM6 RO 0x0 29 ROM5 RO 0x0 28 ROM4 RO 0x0 27 ROM3 RO 0x0 26 ROM2 RO 0x0 25 ROM1 RO 0x0 24 ROM0 RO 0x0 23 22 21 20 19 18 HWSW_SHADOW_ALT CRYPTODCP_ALT CRYPTOKEY_ALT PIN OPS UN2 RO RO RO RO 0x0 0x0 0x0 0x0 RO 0x0 RO 0x0 17 UN1 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 7-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor CUST0 ROM7 ROM6 ROM5 ROM4 ROM3 ROM2 ROM1 ROM0 OPS UN2 UN1 UN0 PIN On-Chip OTP (OCOTP) Controller Table 7-38. HW_OCOTP_LOCK Bit Field Descriptions BITS 16 UN0 LABEL RW RESET RO 0x0 DEFINITION Status of un-assigned (ADDR = 0x15) write-lock bit. When set, un-asigned word at OTP address 0x15 is locked. Value of un-used portion of LOCK word Status of ROM region shadow register lock. When set, over-ride of ROM-region shadow bits is blocked. Status of Customer Capability region (ADDR = 0x0F) write lock bit. When set, region is locked. Status of HW/SW region (ADDR = 0x08-0x0E) write lock bit. When set, region is locked. Status of Customer Capability shadow register lock. When set, over-ride of customer capabality shadow bits is blocked. Status of HW/SW Capability shadow register lock. When set, over-ride of HW/SW capabality shadow bits is blocked. Status of read lock bit for DCP APB crypto access. When set, the DCP will disallow reads of its crypto keys via its APB interface. Status of crypto key region (ADDR = 0x04-0x07) read/write lock bit. When set, region is locked. Status of customer region word (ADDR = 0x03) write lock bit. When set, the region is locked. Status of customer region word (ADDR = 0x02) write lock bit. When set, the region is locked. Status of customer region word (ADDR = 0x01) write lock bit. When set, the region is locked. Status of customer region word (ADDR = 0x00) write lock bit. When set, the region is locked. 15:11 UNALLOCATED 10 ROM_SHADOW 9 8 7 CUSTCAP HWSW CUSTCAP_SHADOW RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 6 HWSW_SHADOW RO 0x0 5 CRYPTODCP RO 0x0 4 3 2 1 0 CRYPTOKEY CUST3 CUST2 CUST1 CUST0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 DESCRIPTION: Shadowed memory mapped access to OTP bank 2, word 0 (ADDR = 0x10). EXAMPLE: Empty Example. 7.4.20 Value of OTP Bank2 Word1 (Freescale OPS0) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_OPS0 Table 7-39. HW_OCOTP_OPS0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x130 BITS i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-21 On-Chip OTP (OCOTP) Controller Table 7-40. HW_OCOTP_OPS0 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 2, word 1 (ADDR = 0x11) DESCRIPTION: Shadowed memory mapped access to OTP Bank 2, word 1 (ADDR = 0x11). EXAMPLE: Empty Example. 7.4.21 Value of OTP Bank2 Word2 (Freescale OPS1) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_OPS1 Table 7-41. HW_OCOTP_OPS1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x140 BITS Table 7-42. HW_OCOTP_OPS1 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 2, word 2 (ADDR = 0x12) DESCRIPTION: Shadowed memory mapped access to OTP Bank 2, word 2 (ADDR = 0x12). EXAMPLE: Empty Example. 7.4.22 Value of OTP Bank2 Word3 (Freescale OPS2) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_OPS2 0x150 i.MX23 Applications Processor Reference Manual, Rev. 1 7-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller Table 7-43. HW_OCOTP_OPS2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BITS Table 7-44. HW_OCOTP_OPS2 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 2, word 3 (ADDR = 0x13) DESCRIPTION: Shadowed memory mapped access to OTP Bank 2, word 3 (ADDR = 0x13). EXAMPLE: Empty Example. 7.4.23 Value of OTP Bank2 Word4 (Freescale OPS3) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_OPS3 Table 7-45. HW_OCOTP_OPS3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x160 BITS Table 7-46. HW_OCOTP_OPS3 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 2, word 4 (ADDR = 0x14) DESCRIPTION: Shadowed memory mapped access to OTP Bank 2, word 4 (ADDR = 0x14). EXAMPLE: Empty Example. 7.4.24 Value of OTP Bank2 Word5 (Unassigned0) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-23 On-Chip OTP (OCOTP) Controller HW_OCOTP_UN0 Table 7-47. HW_OCOTP_UN0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0x170 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BITS Table 7-48. HW_OCOTP_UN0 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 2, word 5 (ADDR = 0x15) DESCRIPTION: Non-shadowed memory mapped access to OTP Bank 2, word 5 (ADDR = 0x15). EXAMPLE: Empty Example. 7.4.25 Value of OTP Bank2 Word6 (Unassigned1) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_UN1 Table 7-49. HW_OCOTP_UN1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x180 BITS Table 7-50. HW_OCOTP_UN1 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 2, word 6 (ADDR = 0x16) DESCRIPTION: Non-shadowed memory mapped access to OTP Bank 2, word 6 (ADDR = 0x16). EXAMPLE: Empty Example. 7.4.26 Value of OTP Bank2 Word7 (Unassigned2) Description OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and i.MX23 Applications Processor Reference Manual, Rev. 1 7-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. HW_OCOTP_UN2 Table 7-51. HW_OCOTP_UN2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x190 BITS Table 7-52. HW_OCOTP_UN2 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RO 0x0 DEFINITION Reflects value of OTP Bank 2, word 7 (ADDR = 0x17) DESCRIPTION: Non-shadowed memory mapped access to OTP Bank 2, word 7 (ADDR = 0x17). EXAMPLE: Empty Example. 7.4.27 Shadow Register for OTP Bank3 Word0 (ROM Use 0) Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. HW_OCOTP_ROM0 Table 7-53. HW_OCOTP_ROM0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 ENABLE_PJTAG_12MA_DRIVE 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DISABLE_SPI_NOR_FAST_ READ 0 5 ENABLE_USB_BOOT_SERIAL_NUM 0 4 ENABLE_UNENCRYPTED_ BOOT 0 3 0 2 0 1 0 0 0x1A0 SD_POWER_GATE_GPIO SD_POWER_UP_DELAY USE_PARALLEL_JTAG SSP_SCK_INDEX SD_BUS_WIDTH SD_MBR_BOOT BOOT_MODE RSRVD3 RSRVD2 RSRVD1 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-25 RSRVD0 On-Chip OTP (OCOTP) Controller Table 7-54. HW_OCOTP_ROM0 Bit Field Descriptions BITS LABEL 31:24 BOOT_MODE 23 ENABLE_PJTAG_12MA_DRI VE RW RESET RW 0x0 RW 0x0 DEFINITION Encoded boot mode. Blow to force the 6-wire PJTAG pins to drive 12mA, default is 4mA (note that SJTAG is fixed at 8mA). Blowing this bit causes the ROM to program all six parallel JTAG pins to drive 12mA via the pin control registers. During JTAG boot mode, the ROM reads this bit, then inverts it, and writes the value to the HW_DIGCTL_CTRL_USE_SERIAL_JTAG bit. If this bit is one, indicating parallel JTAG mode is selected, a zero is written to the DIGCTL USE_SERIAL_JTAG bit which places the device into 6-wire JTAG mode, and if this bit is zero, a one instead is written causing the SJTAG block to switch to the 1-wire serial JTAG mode. SD card power gate GPIO pin select: 00 - PWM0, 01 LCD_DOTCLK, 10 - PWM3, 11 - NO_GATE. SD card power up delay required after enabling GPIO power gate: 000000 - 0 ms, 000001 - 10 ms, 000010 20 ms, 111111 - 630 ms. SD card bus width: 00 - 4-bit, 01 - 1-bit, 10 - 8-bit, 11 reserved. Index to the SSP clock speed Reserved - do not blow this bit. Blow to disable SPI NOR fast reads which are used by default. Blow to enable USB boot serial number. Blow to enable unencrypted boot modes. Blow to enable master boot record (MBR) boot mode for SD boot. Reserved - do not blow this bit. Reserved - do not blow this bit. Reserved - do not blow this bit. 22 USE_PARALLEL_JTAG RW 0x0 21:20 SD_POWER_GATE_GPIO 19:14 SD_POWER_UP_DELAY RW 0x0 RW 0x0 13:12 SD_BUS_WIDTH 11:8 7 6 5 4 3 2 1 0 SSP_SCK_INDEX RSRVD3 DISABLE_SPI_NOR_FAST_ READ ENABLE_USB_BOOT_SERIA L_NUM ENABLE_UNENCRYPTED_ BOOT SD_MBR_BOOT RSRVD2 RSRVD1 RSRVD0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 DESCRIPTION: Shadowed memory mapped access to OTP Bank 3, word 0 (ADDR = 0x18). EXAMPLE: Empty Example. 7.4.28 Shadow Register for OTP Bank3 Word1 (ROM Use 1) Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. HW_OCOTP_ROM1 0x1B0 i.MX23 Applications Processor Reference Manual, Rev. 1 7-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller Table 7-55. HW_OCOTP_ROM1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 ENABLE_NAND3_CE_RDY_PULLUP 2 2 ENABLE_NAND2_CE_RDY_PULLUP 2 1 ENABLE_NAND1_CE_RDY_PULLUP 2 0 ENABLE_NAND0_CE_RDY_PULLUP 1 9 UNTOUCH_INTERNAL_SSP_PULLUP 1 8 1 7 1 6 SD_INCREASE_INIT_SEQ_TIME 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SD_INIT_SEQ_1_DISABLE SD_INIT_SEQ_2_ENABLE USE_ALT_SSP1_DATA4-7 BOOT_SEARCH_COUNT USE_ALT_GPMI_RDY3 USE_ALT_GPMI_RDY2 Table 7-56. HW_OCOTP_ROM1 Bit Field Descriptions BITS LABEL 31:30 RSRVD1 29:28 USE_ALT_GPMI_RDY3 RW RESET RW 0x0 RW 0x0 DEFINITION Reserved - do not blow this bit. These bits are used by ROM NAND driver to enable one of 3 alternate pins for GPMI_RDY3. 00-GPMI_RDY3, 01-PWM2 and 10-LCD_DOTCK. These bits are used by ROM NAND driver to enable one of 4 alternate pins for GPMI_CE3. 00-GPMI_D15, 01-LCD_RESET, 10-SSP_DETECT and 11-ROTARYB. If the bit is blown then ROM NAND driver will enable alternate pins for GPMI_RDY2. If the bit is blown then ROM NAND driver will enable alternate pins for GPMI_CE2. If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE3 and GPMI_RDY3 pins. If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE2 and GPMI_RDY2 pins. If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE1 and GPMI_RDY1 pins. If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE0 and GPMI_RDY0 pins. If this bit is blown then internal pull-ups for SSP are neither enabled nor disabled. This bit is used only if external pull-ups are implemented and ROM1:18 and/or ROM1:17 are blown. Blow to indicate external pull-ups implemented for SSP2. Blow to indicate external pull-ups implemented for SSP1. Blow to increase the SD card initialization sequence time from 1ms (default) to 4ms. Blow to enable the second initialization sequence for SD boot. 27:26 USE_ALT_GPMI_CE3 RW 0x0 25 24 23 22 21 20 19 USE_ALT_GPMI_RDY2 USE_ALT_GPMI_CE2 ENABLE_NAND3_CE_RDY_P ULLUP ENABLE_NAND2_CE_RDY_P ULLUP ENABLE_NAND1_CE_RDY_P ULLUP ENABLE_NAND0_CE_RDY_P ULLUP UNTOUCH_INTERNAL_SSP_ PULLUP RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 18 17 16 15 SSP2_EXT_PULLUP SSP1_EXT_PULLUP SD_INCREASE_INIT_SEQ_TI ME SD_INIT_SEQ_2_ENABLE RW 0x0 RW 0x0 RW 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-27 NUMBER_OF_NANDS USE_ALT_GPMI_CE3 USE_ALT_GPMI_CE2 SD_CMD0_DISABLE SSP2_EXT_PULLUP SSP1_EXT_PULLUP RSRVD1 RSRVD0 On-Chip OTP (OCOTP) Controller Table 7-56. HW_OCOTP_ROM1 Bit Field Descriptions BITS LABEL 14 SD_CMD0_DISABLE RW RESET RW 0x0 DEFINITION Cmd0 (reset cmd) is called by default to reset the SD card during startup. Blow this bit to not reset the card during SD boot. Blow to disable the first initialization sequence for SD. This bit is blown to enable alternate pin use for SSP1 data lines 4-7. Number of 64 page blocks that should be read by the boot loader. Reserved - do not blow these bits. Encoded value indicates number of external NAND devices (0 to 7). Zero indicates ROM will probe for the number of NAND devices connected in the system. 13 12 11:8 7:3 2:0 SD_INIT_SEQ_1_DISABLE USE_ALT_SSP1_DATA4-7 BOOT_SEARCH_COUNT RSRVD0 NUMBER_OF_NANDS RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 DESCRIPTION: Shadowed memory mapped access to OTP Bank 3, word 1 (ADDR = 0x19). EXAMPLE: Empty Example. 7.4.29 Shadow Register for OTP Bank3 Word2 (ROM Use 2) Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. HW_OCOTP_ROM2 Table 7-57. HW_OCOTP_ROM2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 USB_VID 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 USB_PID 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x1C0 Table 7-58. HW_OCOTP_ROM2 Bit Field Descriptions BITS 31:16 USB_VID 15:0 USB_PID LABEL RW RESET RW 0x0 RW 0x0 DEFINITION USB Vendor ID. USB Product ID DESCRIPTION: Shadowed memory mapped access to OTP Bank 3, word 2 (ADDR = 0x1A). EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 7-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller 7.4.30 Shadow Register for OTP Bank3 Word3 (ROM Use 3) Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. HW_OCOTP_ROM3 Table 7-59. HW_OCOTP_ROM3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 RSRVD1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 RSRVD0 0 4 0 3 0 2 0 1 0 0 0x1D0 Table 7-60. HW_OCOTP_ROM3 Bit Field Descriptions BITS 31:10 RSRVD1 9:0 RSRVD0 LABEL RW RESET RW 0x0 RW 0x0 DEFINITION Reserved - do not blow these bits. SDK reserved bits. DESCRIPTION: Shadowed memory mapped access to OTP Bank 3, word 3 (ADDR = 0x1B). EXAMPLE: Empty Example. 7.4.31 Shadow Register for OTP Bank3 Word4 (ROM Use 4) Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. HW_OCOTP_ROM4 Table 7-61. HW_OCOTP_ROM4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x1E0 BITS Table 7-62. HW_OCOTP_ROM4 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RW 0x0 DEFINITION Shadow register for ROM-use word4 (Copy of OTP Bank 3, word 4 (ADDR = 0x1C)). These bits become read-only after the HW_OCOTP_LOCK[ROM_SHADOW] bit is set. DESCRIPTION: Shadowed memory mapped access to OTP Bank 3, word 4 (ADDR = 0x1C). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-29 On-Chip OTP (OCOTP) Controller EXAMPLE: Empty Example. 7.4.32 Shadow Register for OTP Bank3 Word5 (ROM Use 5) Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. HW_OCOTP_ROM5 Table 7-63. HW_OCOTP_ROM5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x1F0 BITS Table 7-64. HW_OCOTP_ROM5 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RW 0x0 DEFINITION Shadow register for ROM-use word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x1D)). These bits become read-only after the HW_OCOTP_LOCK[ROM_SHADOW] bit is set. DESCRIPTION: Shadowed memory mapped access to OTP Bank 3, word 5 (ADDR = 0x1D). EXAMPLE: Empty Example. 7.4.33 Shadow Register for OTP Bank3 Word6 (ROM Use 6) Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. HW_OCOTP_ROM6 Table 7-65. HW_OCOTP_ROM6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x200 BITS Table 7-66. HW_OCOTP_ROM6 Bit Field Descriptions BITS 31:0 BITS LABEL RW RESET RW 0x0 DEFINITION Shadow register for ROM-use word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x1E)). These bits become read-only after the HW_OCOTP_LOCK[ROM_SHADOW] bit is set. i.MX23 Applications Processor Reference Manual, Rev. 1 7-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor On-Chip OTP (OCOTP) Controller DESCRIPTION: Shadowed memory mapped access to OTP Bank 3, word 6 (ADDR = 0x1E). EXAMPLE: Empty Example. 7.4.34 Shadow Register for OTP Bank3 Word7 (ROM Use 7) Description Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. HW_OCOTP_ROM7 Table 7-67. HW_OCOTP_ROM7 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 ENABLE_SSP_12MA_DRIVE 0 7 0 6 0 5 0 4 0 3 0 2 ENABLE_ARM_ICACHE 0 1 0 0 ENABLE_PIN_BOOT_CHECK 0x210 I2C_USE_400KHZ RSRVD2 RSRVD1 Table 7-68. HW_OCOTP_ROM7 Bit Field Descriptions BITS 31:9 8 7:4 3 2 1 0 LABEL RSRVD2 ENABLE_SSP_12MA_DRIVE RSRVD1 I2C_USE_400KHZ RW RW RW RW RW RESET 0x0 0x0 0x0 0x0 DEFINITION Reserved - do not blow these bits. Blow to force SSP pins to drive 12mA (default is 4mA) Reserved - do not blow these bits. Blow to force the I2C to be programmed by the boot loader to run at 400KHz (100KHz is the default) Blow to enable the ARM 926 ICache during boot Reserved - do not blow this bit. Blow to enable boot loader to first test the LCD_RS pin to determine if pin boot mode is enabled. If this bit is blown, and LCD_RS is pulled high, then boot mode is determined by the state of LCD_D[6:0] pins. If this bit is not blown, skip testing the LCD_RS pin and go directly to determining boot mode by reading the state of LCD_D[6:0]. ENABLE_ARM_ICACHE RW 0x0 RSRVD0 RW 0x0 ENABLE_PIN_BOOT_CHECK RW 0x1 DESCRIPTION: Shadowed memory mapped access to OTP Bank 3, word 7 (ADDR = 0x1F). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7-31 RSRVD0 On-Chip OTP (OCOTP) Controller EXAMPLE: Empty Example. 7.4.35 OTP Controller Version Register Description HW_OCOTP_VERSION Table 7-69. HW_OCOTP_VERSION 0x220 This register always returns a known read value for debug purposes it indicates the version of the block. 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 7-70. HW_OCOTP_VERSION Bit Field Descriptions BITS 31:24 MAJOR 23:16 MINOR 15:0 STEP LABEL RW RESET RO 0x01 RO 0x04 RO 0x0000 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: Empty Example. OCOTP Block v1.4, Revision 1.21 i.MX23 Applications Processor Reference Manual, Rev. 1 7-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 8 USB High-Speed Host/Device Controller This chapter describes the USB high-speed controller included on the i.MX23. It includes sections on the PIO, DMA, and UTMI interfaces, along with USB controller flowcharts. Programmable USB controller registers are described in Section 8.6, "Programmable Registers." Descriptions for additional programmable registers mentioned in this chapter can be found in Section 4.8, "Programmable Registers," Section 6.4, "Programmable Registers," Section 9.4, "Programmable Registers, and Section 32.11, "Programmable Registers." 8.1 Overview The i.MX23 includes a Universal Serial Bus (USB) version 2.0 controller capable of operating as either a USB device or a USB host, as shown in Figure 8-1. The USB controller is used to download digital music data or program code into external memory and to upload voice recordings from memory to the PC. Program updates can also be loaded into the flash memory area using the USB interface. The USB device controller included on the i.MX23 supports five bi-directional endpoints: one control (for the default pipe) and four general purpose endpoints, each capable of operating in either IN, OUT, or both directions simultaneously. A typical portable device application defines 1 bulk-in, 1 bulk-out, and 1 interrupt in pipe. As a USB host controller, it can enumerate and control USB devices attached to it. Using the USB Host Capability features, the USB controller can negotiate with another USB Host Capable system to be either the host or the device in a peer connection. The USB controller operates either in full-speed mode or high-speed mode. Refer to the USB Implementer's Forum website www.usb.org for detailed specifications and information on the USB protocol, timing and electrical characteristics. The USB 2.0 controller comprises both a programmed I/O (PIO) interface and a DMA interface. Both of these interfaces are designed to meet an ARM Ltd. AMBA Hardware Bus (AHB). The AHB is used by the USB controller as a slave (PIO register accesses) and as a master (DMA memory accesses). The USB 2.0 PHY is fully integrated on-chip and is described in Chapter 9, "Integrated USB 2.0 PHY," The PHY is controlled over the APBX peripheral bus. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-1 USB High-Speed Host/Device Controller ARM Core On-Chip RAM AHB AHB Slave AHB Slave AHB Master AHB-to-APBX Bridge APBX Master USB PIO Interface USB DMA Interface APBX Programmed I/O Target Inteface DMA Engine * Bus Interface * Endpoint Priming State Machine * Data Movement Dual Port RAM Controller * Bus Interface * Control and Status * Interrupts * Virtual FIFO Channels * DMA Contexts On-Chip Dual Port Synchronous SRAM Protocol Engine * Interval Timers * Error Handling * CRC Handling Port Controller USB 2.0 Device/ Host Controller * Asynchronous Clock Domain Crossing * Transceiver Interface Logic USB Interface Block PHY Registers USB UTM Interface USB Xcvr Integrated USB 2.0 PHY 480-MHz PLL Figure 8-1. USB 2.0 Device Controller Block Diagram i.MX23 Applications Processor Reference Manual, Rev. 1 8-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller 8.2 USB Programmed I/O (PIO) Target Interface The PIO interface is on an AHB slave of the USB controller. It allows the ARM processor to access the configuration, control, and status registers. There are identification registers for hardware configuration parameters and operational registers for control and status. 8.3 USB DMA Interface The DMA is a master AHB interface that allows USB data to be transferred to/from the system memory. The data in memory is structured to implement a software framework supported by the controller. For a device controller, this structure is a linked-list interface that consists of queue heads and pointers that are transfer descriptors. The queue head is where transfers are managed. It has status information and location of the data buffers. The hardware controller's PIO registers enable the entire data structure, and once USB data is transferred between the host, the status of the transfer is updated in the queue head, with minimal latency to the system. For a host controller, there is also a linked-list interface. It consists of a periodic frame list and pointers to transfer descriptors. The period frame list is a schedule of transfers. The frame list points to the data buffers through the transfer descriptors. The hardware controller's PIO registers enable the data structure and manage the transfers within a USB frame. The period frame list works as a sliding window of host transfers over time. As each transfer is completed, the status information is updated in the frame list. The i.MX23 has the bandwidth to handle the data buffers in DRAM for both high-speed and full-speed USB transmissions. However, the queue heads (dQH) must be placed in on-chip RAM. A design limitation on burst size does not allow the queue heads to be placed in DRAM. 8.4 USB UTM Interface The USB UTM interface on the i.MX23 implements the specification that allows USB controllers to interface with the USB PHY. Please refer to the USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.05 and UTMI+ Specification, Version 1.0 for additional details: http://www.intel.com/technology/usb/spec.htm 8.4.1 Digital/Analog Loopback Test Mode Since the UTM has to operate at high frequencies (480 MHz), it has a capacity to self-test. A pseudo-random number generator transmits data to the receive path, and data is compared for validity. In the digital loopback, the data transfer only resides in the UTM. It checks for sync, EOP, and bit-stuffing generation and data integrity. The analog loopback is the same as the digital loopback, but involves the analog PHY. This allows for checking of the and full-speed (FS) comparators and transmitters. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-3 USB High-Speed Host/Device Controller 8.5 USB Controller Flowcharts Start NO HW_POWER_STS_ VDD5V_GT_VDDIO Check for 5-V input YES NO HW_USBPHY_CTRL_ SFTRST YES Phy_Startup Set HW_USBPHY_DEBUG_ENHSTPULLDOWN Clear HW_USBPHY_DEBUG_HSTPULLDOWN Set HW_USBPHY_CTRL_ENDEVPLUGINDETECT Wait for 1 microsecond NO HW_USBPHY_ STATUS_DEVPLUGIN _STATUS DONE Figure 8-2. USB 2.0 Check_USB_Plugged_In Flowchart i.MX23 Applications Processor Reference Manual, Rev. 1 8-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller PHY Startup Clear HW_USBPHY_CTRL_SFTRST Clear HW_USBPHY_CTRL_CLKGATE Clear HW_USBPHY_PWD Clear HW_POWER_CTRL_CLKGATE Set HW_POWER_DEBUG_VBUSVALIDPIOLOCK Set HW_POWER_DEBUG_AVALIDPIOLOCK Set HW_POWER_DEBUG_BVALIDPIOLOCK Device and Host operation not OTG Set HW_POWER_STS_BVALID Set HW_POWER_STS_AVALID Set HW_POWER_STS_VBUSVALID Set CPU Clock to 1.2 MHz Set HW_CLKCTRL_CPU_DIV_CPU=400 Set GPMI Clock to 1.2 MHz Set HW_CLKCTRL_GPMI_DIV=400 Make sure XBUS is lower than HBUS Set HW_CLKCTRL_XBUS_DIV=20 Power on PLL Set HW_CLKCTRL_PLLCTRL0_POWER NO HW_CLKCTRL_ PLLCTRL1_ LOCK==1 YES Clear HW_CLKCTRL_CLKSEQ_BYPASS_CPU Switch to PLL from Crystal Set HW_CLKCTRL_XBUS_DIV=1 Set HW_CLKCTRL_PLLCTRL0_EN_USB_CLKS Figure 8-3. USB 2.0 USB PHY Startup Flowchart i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-5 USB High-Speed Host/Device Controller ARC IRQ To Other ARC ISR NO ARC Suspend Interrupt? YES Set HW_USBPHY_CTRL_ENIRQRESUMEDETECT PHY Shut Down Set all power-down bits in HW_USBPHY_PWD Set HW_DIGCTRL_CTRL_USB_CLKGATE PLL Bypass, switches to XTAL Set HW_CLKCTRL_CLKSEQ BYPASS bits Clear HW_CLKCTRL_PLLCTRL0_POWER Figure 8-4. USB 2.0 PHY PLL Suspend Flowchart Clear HW_DIGCTL_CTRL_USB_CLKGATE Clear HW _USBPHY_CTRL_SFTRST Clear HW_USBPHY_CTRL_CLKGATE Prepare USB controller to deassert UTMI_RESET Set HW_DIGCTL_CTRL_USB_CLKGATE Set all power-down bits in HW_USBPHY_PWD Figure 8-5. UTMI Powerdown i.MX23 Applications Processor Reference Manual, Rev. 1 8-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller 8.5.1 * References USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.05, March 2001, Jon Lueker, Steve McGowan (Editor) Ken Oliver, Dean Warren. http://www.intel.com VSI Alliance Virtual Component Interface Standard, Version 2 (OCB 2 2.0), April 2001, On-Chip Bus Development Working Group. http://www.vsi.org Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips. http://www.usb.org On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0, Dec 2001, On-The-Go Working Group of the USB-IF. http://www.usb.org Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95, November 2000, Intel Corporation. http://www.intel.com Universal Serial Bus Specification, Revision 1.1, September 1998, Compaq, Intel, Microsoft, NEC. http://www.usb.org AMBA Specification, Revision 2.0, May 1999, ARM Limited. http://www.arm.com UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.0 February 2004, ULPI Specification Organization. http://www.ulpi.org * * * * * * * 8.6 Programmable Registers This section includes the programmable registers supported in the USB high-speed Host controller core. 8.6.1 Identification Register Description The Identification Register provides a simple way to determine if the USB-HS USB 2.0 core is provided in the system. The HW_USBCTRL_ID register identifies the USB-HS USB 2.0 core and its revision. The default value of this register is 0xE241FA05. HW_USBCTRL_ID Table 8-1. HW_USBCTRL_ID 3 1 3 0 CIVERSION 2 9 2 8 2 7 VERSION 2 6 2 5 2 4 2 3 REVISION 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSVD1 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 RSVD0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x000 TAG NID i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-7 ID USB High-Speed Host/Device Controller Table 8-2. HW_USBCTRL_ID Bit Field Descriptions BITS LABEL 31:29 CIVERSION 28:25 VERSION 24:21 REVISION 20:16 TAG 15:14 13:8 7:6 5:0 RSVD1 NID RSVD0 ID RW RESET RO 0x7 RO 0x1 RO 0x2 RO 0x1 RO RO RO RO 0x3 0x3a 0x0 0x05 DEFINITION Identifies the Chip Idea product version of the USB-HS USB 2.0 core. Identifies the version of the USB-HS USB 2.0 core release. ( DESCRIPTION: REV/ID EXAMPLE: Empty Example. 8.6.2 General Hardware Parameters Register Description HW_USBCTRL_HWGENERAL 0x004 The default value of this register is 0x00000015. Table 8-3. HW_USBCTRL_HWGENERAL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 RSVD 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 SM 0 9 0 8 0 7 PHYM 0 6 0 5 PHYW 0 4 0 3 BWT 0 2 CLKC 0 1 0 0 RT Table 8-4. HW_USBCTRL_HWGENERAL Bit Field Descriptions BITS 31:11 RSVD 10:9 SM 8:6 5:4 3 PHYM PHYW BWT LABEL RW RESET RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 DEFINITION Reserved. PHY Serial Engine Type. Always 0 = Serial engine not present. PHY Type. Always 1 = UTMI. Data Interface Width to PHY. Always 1 = 16 bits. Reserved for internal testing. Always 0. i.MX23 Applications Processor Reference Manual, Rev. 1 8-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-4. HW_USBCTRL_HWGENERAL Bit Field Descriptions BITS 2:1 CLKC 0 RT LABEL RW RESET RO 0x2 RO 0x1 DEFINITION USB Controller Clocking Method. Always 2 = Mixed clocked. Reset Type. Always 1 = Synchronous DESCRIPTION: General Hardware Parameters EXAMPLE: Empty Example. 8.6.3 Host Hardware Parameters Register Description HW_USBCTRL_HWHOST Table 8-5. HW_USBCTRL_HWHOST 0x008 The default value of this register is 0x10020001. 3 1 3 0 2 9 2 8 TTPER 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 TTASY 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 NPORT 0 1 0 0 HC Table 8-6. HW_USBCTRL_HWHOST Bit Field Descriptions BITS 31:24 23:16 15:4 3:1 0 LABEL TTPER TTASY RSVD NPORT HC RW RO RO RO RO RO RESET 0x10 0x02 0x0 0x0 0x1 DEFINITION Periodic contexts for hub TT. Asynch contexts for hub TT. Reserved. Maximum downstream ports minus 1. Host Capable. Always 0x1. DESCRIPTION: Host hardware params as defined in sys-level/core-config EXAMPLE: Empty Example. 8.6.4 Device Hardware Parameters Register Description HW_USBCTRL_HWDEVICE 0x00c The default value of this register is 0x0000000B. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-9 USB High-Speed Host/Device Controller Table 8-7. HW_USBCTRL_HWDEVICE 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 RSVD 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 DEVEP 0 2 0 1 0 0 DC 0 2 0 1 0 0 Table 8-8. HW_USBCTRL_HWDEVICE Bit Field Descriptions BITS 31:6 RSVD 5:1 DEVEP 0 DC LABEL RW RESET RO 0x0 RO 0x5 RO 0x1 DEFINITION Reserved. Maximum number of endpoints, which is 5. Device Capable. Always 0x1. DESCRIPTION: device hardware params as defined in sys-level/core-config EXAMPLE: Empty Example. 8.6.5 TX Buffer Hardware Parameters Register Description HW_USBCTRL_HWTXBUF Table 8-9. HW_USBCTRL_HWTXBUF 0x010 The default value of this register is 0x40060910. 3 1 TXLCR 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 TXCHANADD 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 TXADD 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 TXBURST 0 3 RSVD Table 8-10. HW_USBCTRL_HWTXBUF Bit Field Descriptions BITS 31 30:24 23:16 15:8 7:0 LABEL TXLCR RSVD TXCHANADD TXADD TXBURST RW RO RO RO RO RO RESET 0x1 0x0 0x06 0x09 0x10 DEFINITION Always 0x1. Reserved. Number of address bits for the TX buffer. Always 0x9. Burst size for memory-to-TX-buffer transfers. DESCRIPTION: tx hardware buf params i.MX23 Applications Processor Reference Manual, Rev. 1 8-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller EXAMPLE: Empty Example. 8.6.6 RX Buffer Hardware Parameters Register Description HW_USBCTRL_HWRXBUF Table 8-11. HW_USBCTRL_HWRXBUF 0x014 The default value of this register is 0x00000710. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RSVD 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RXADD 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 RXBURST 0 3 0 2 0 1 0 0 Table 8-12. HW_USBCTRL_HWRXBUF Bit Field Descriptions BITS LABEL 31:16 RSVD 15:8 RXADD 7:0 RXBURST RW RESET RO 0x0 RO 0x07 RO 0x10 DEFINITION Reserved. Always 0x07. Burst size for RX buffer-to-memory transfers. DESCRIPTION: rx hardware buf params EXAMPLE: Empty Example. 8.6.7 General-Purpose Timer 0 Load (Non-EHCI-Compliant) Register Description The host/device controller driver can measure time-related activities using this timer register. This register is not part of the standard EHCI controller. This register contains the timer duration or load value. See the GPTIMER0CTRL (Non-EHCI) for a description of the timer functions. HW_USBCTRL_GPTIMER0LD 0x080 Table 8-13. HW_USBCTRL_GPTIMER0LD 3 1 3 0 2 9 2 8 RSVD0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 GPTLD 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-11 USB High-Speed Host/Device Controller Table 8-14. HW_USBCTRL_GPTIMER0LD Bit Field Descriptions BITS 31:24 RSVD0 23:0 GPTLD LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. General-Purpose Timer Load Value. This field is the value to be loaded into the GPTCNT countdown timer on a reset action. This value in this register represents the time in microseconds minus 1 for the timer duration. Example: for a one-millisecond timer, load 1000 Note: Max value is 0xFFFFFF or 16.777215 seconds. DESCRIPTION: General Purpose Timer #0 Load Register EXAMPLE: Empty Example. 8.6.8 General-Purpose Timer 0 Control (Non-EHCI-Compliant) Register Description The host/device controller driver can measure time-related activities using this timer register. This register is not part of the standard EHCI controller. This register contains the control for the timer and a data field can be queried to determine the running count value. This timer has granularity on 1 us and can be programmed to a little over 16 seconds. There are two modes supported by this timer, the first is a one-shot and the second is a looped count that is described in the register table below. When the timer counter value transitions to 0, an interrupt can be generated through the use of the timer interrupts in the USBTS and USBINTR registers. HW_USBCTRL_GPTIMER0CTRL 0x084 Table 8-15. HW_USBCTRL_GPTIMER0CTRL 3 1 GPTRUN 3 0 GPTRST 2 9 2 8 2 7 RSVD0 2 6 2 5 2 4 GPTMODE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 GPTCNT 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-16. HW_USBCTRL_GPTIMER0CTRL Bit Field Descriptions BITS 31 GPTRUN LABEL RW RESET RW 0x0 DEFINITION General-Purpose Timer Run. This bit enables the general-purpose timer to run. Setting or clearing this bit will not have an effect on the GPTCNT except if it stops or starts counting. STOP = 0 Timer stop. RUN = 1 Timer run. 30 GPTRST W O 0x0 General-Purpose Timer Reset. Writing a 1 to this bit will reload the GPTCNT with the value in GPTLD. NOACTION = 0 No action. LOADCOUNTER = 1 Load counter value. 29:25 RSVD0 24 GPTMODE RO 0x0 RW 0x0 Reserved. General-Purpose Timer Mode. This bit selects between a single timer countdown and a looped count down. In one-shot mode, the timer will count down to 0, generate an interrupt, and stop until the counter is reset by software. In repeat mode, the timer will count down to 0, generate an interrupt, and automatically reload the counter to begin again. ONESHOT = 0 One shot. REPEAT = 1 Repeat. 23:0 GPTCNT RO 0x0 General-Purpose Timer Counter. This field is the value of the running timer. DESCRIPTION: General Purpose Timer #0 Control Register EXAMPLE: Empty Example. 8.6.9 General-Purpose Timer 1 Load (Non-EHCI-Compliant) Register Description HW_USBCTRL_GPTIMER1LD 0x088 Same as GPTIMER0LD description. Table 8-17. HW_USBCTRL_GPTIMER1LD 3 1 3 0 2 9 2 8 RSVD0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 GPTLD 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-13 USB High-Speed Host/Device Controller Table 8-18. HW_USBCTRL_GPTIMER1LD Bit Field Descriptions BITS 31:24 RSVD0 23:0 GPTLD LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. General-Purpose Timer Load Value. This field is the value to be loaded into the GPTCNT countdown timer on a reset action. This value in this register represents the time in microseconds minus 1 for the timer duration. Example: for a one-millisecond timer, load 1000 Note: Max value is 0xFFFFFF or 16.777215 seconds. DESCRIPTION: General Purpose Timer #1 Load Register EXAMPLE: Empty Example. 8.6.10 General-Purpose Timer 1 Control (Non-EHCI-Compliant) Register Description HW_USBCTRL_GPTIMER1CTRL 0x08c Same as GPTIMER0CTRL description. Table 8-19. HW_USBCTRL_GPTIMER1CTRL 3 1 GPTRUN 3 0 GPTRST 2 9 2 8 2 7 RSVD0 2 6 2 5 2 4 GPTMODE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 GPTCNT 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 8-20. HW_USBCTRL_GPTIMER1CTRL Bit Field Descriptions BITS 31 GPTRUN LABEL RW RESET RW 0x0 DEFINITION General-Purpose Timer Run. This bit enables the general-purpose timer to run. Setting or clearing this bit will not have an effect on the GPTCNT except if it stops or starts counting. STOP = 0 Timer stop. RUN = 1 Timer run. 30 GPTRST W O 0x0 General-Purpose Timer Reset. Writing a 1 to this bit will reload the GPTCNT with the value in GPTLD. NOACTION = 0 No action. LOADCOUNTER = 1 Load counter value. 29:25 RSVD0 RO 0x0 Reserved. i.MX23 Applications Processor Reference Manual, Rev. 1 8-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-20. HW_USBCTRL_GPTIMER1CTRL Bit Field Descriptions BITS LABEL 24 GPTMODE RW RESET RW 0x0 DEFINITION General-Purpose Timer Mode. This bit selects between a single timer countdown and a looped count down. In one-shot mode, the timer will count down to 0, generate an interrupt, and stop until the counter is reset by software. In repeat mode, the timer will count down to 0, generate an interrupt, and automatically reload the counter to begin again. ONESHOT = 0 One shot. REPEAT = 1 Repeat. 23:0 GPTCNT RO 0x0 General-Purpose Timer Counter. This field is the value of the running timer. DESCRIPTION: General Purpose Timer #1 Control Register EXAMPLE: Empty Example. 8.6.11 System Bus Configuration (Non-EHCI-Compliant) Register Description HW_USBCTRL_SBUSCFG Table 8-21. HW_USBCTRL_SBUSCFG 0x090 This register controls the AMBA system bus Master/Slave interfaces. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 RSVD 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 AHBBRST 0 0 Table 8-22. HW_USBCTRL_SBUSCFG Bit Field Descriptions BITS LABEL 31:3 RSVD 2:0 AHBBRST RW RESET RO 0x00 RW 0x0 DEFINITION Reserved. AMBA AHB BURST. This field selects the following options for the m_hburst signal of the AMBA master interface: U_INCR = 0x0 INCR burst of unspecified length. S_INCR4 = 0x1 INCR4, non-multiple transfers of INCR4 will be decomposed into singles. S_INCR8 = 0x2 INCR8, non-multiple transfers of INCR8 will be decomposed into INCR4 or singles. S_INCR16 = 0x3 INCR16, non-multiple transfers of INCR16 will be decomposed into INCR8, INCR4 or singles. RESERVED = 0x4 This value is reserved and should not be used. U_INCR4 = 0x5 INCR4, non-multiple transfers of INCR4 will be decomposed into smaller unspecified length bursts. U_INCR8 = 0x6 INCR8, non-multiple transfers of INCR8 will be decomposed into smaller unspecified length bursts. U_INCR16 = 0x7 INCR16, non-multiple transfers of INCR16 will be decomposed into smaller unspecified length bursts. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-15 USB High-Speed Host/Device Controller DESCRIPTION: AHB System Bus Configuration Register EXAMPLE: Empty Example. 8.6.12 Capability Length and HCI Version (EHCI-Compliant) Register Description HW_USBCTRL_CAPLENGTH 0x100 This register contains the Capability Length and HCI Version Register. Table 8-23. HW_USBCTRL_CAPLENGTH 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 HCIVERSION 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 CAPLENGTH 0 3 0 2 0 1 0 0 Table 8-24. HW_USBCTRL_CAPLENGTH Bit Field Descriptions BITS LABEL 31:16 HCIVERSION RW RESET RO 0x0100 DEFINITION Contains a BCD encoding of the EHCI revision number supported by the host controller. The most significant byte of this register represents a major revision and the least significant byte is the minor revision. Reserved. Offset to add to register base address at beginning of the Operational Register. 15:8 7:0 RSVD CAPLENGTH RO 0x00 RO 0x40 DESCRIPTION: Capability Length and HCI Version register EXAMPLE: Empty Example. 8.6.13 Host Control Structural Parameters (EHCI-Compliant with Extensions) Register Description Port-steering logic capabilities are described in this register. The default value of this register is 0x00010011. HW_USBCTRL_HCSPARAMS 0x104 i.MX23 Applications Processor Reference Manual, Rev. 1 8-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSVD USB High-Speed Host/Device Controller Table 8-25. HW_USBCTRL_HCSPARAMS 3 1 3 0 RSVD2 2 9 2 8 2 7 2 6 N_TT 2 5 2 4 2 3 2 2 N_PTT 2 1 2 0 1 9 1 8 RSVD1 1 7 1 6 1 5 1 4 N_CC 1 3 1 2 1 1 1 0 N_PCC 0 9 0 8 0 7 0 6 RSVD0 0 5 0 4 PPC 0 3 0 2 N_PORTS 0 1 0 0 Table 8-26. HW_USBCTRL_HCSPARAMS Bit Field Descriptions BITS 31:28 RSVD2 27:24 N_TT LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved. Number of Transaction Translators (N_TT). Indicates the number of embedded transaction translators associated with the USB2.0 host controller. This in a non-EHCI field to support embedded TT. Number of Ports per Transaction Translator (N_PTT). Indicates the number of ports assigned to each transaction translator within the USB2.0 host controller. This in a non-EHCI field to support embedded TT. Reserved. Port Indicators (P INDICATOR). Indicates whether the ports support port indicator control. When set to 1, the port status and control registers include a read/writable field for controlling the state of the port indicator. Number of Companion Controller (N_CC). Indicates the number of companion controllers associated with this USB2.0 host controller. A 0 in this field indicates there are no internal Companion Controllers. Port-ownership hand-off is not supported. A value larger than 0 in this field indicates there are companion USB host controller(s). Port-ownership hand-offs are supported. High- and Full-speed devices are supported on the host controller root ports. Number of Ports per Companion Controller. Indicates the number of ports supported per internal Companion Controller. It is used to indicate the port routing configuration to the system software. For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3. The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc. In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2. The number in this field must be consistent with N_PORTS and N_CC. Reserved. 23:20 N_PTT RO 0x0 19:17 RSVD1 16 PI RO 0x0 RO 0x1 15:12 N_CC RO 0x0 11:8 N_PCC RO 0x0 7:5 RSVD0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-17 PI USB High-Speed Host/Device Controller Table 8-26. HW_USBCTRL_HCSPARAMS Bit Field Descriptions BITS 4 PPC LABEL RW RESET RO 0x1 DEFINITION Port Power Control. Indicates whether the host controller implementation includes port power control. A 1 indicates the ports have port power switches. A 0 indicates the ports do not have port power switches. The value of this field affects the functionality of the Port Power field in each port status and control register. Number of downstream ports. Specifies the number of physical downstream ports implemented on this host controller. The value of this field determines how many port registers are addressable in the Operational Register. Valid values are in the range of 0x11-0xF. A 0 in this field is undefined. 3:0 N_PORTS RO 0x1 DESCRIPTION: host controller structural params EXAMPLE: Empty Example. 8.6.14 Host Control Capability Parameters (EHCI-Compliant) Register Description This register identifies multiple mode control (time-base bit functionality) addressing capability. The default value of this register is 0x00000006. HW_USBCTRL_HCCPARAMS 0x108 Table 8-27. HW_USBCTRL_HCCPARAMS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RSVD2 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 EECP 1 1 1 0 0 9 0 8 0 7 0 6 IST 0 5 0 4 0 3 RSVD0 0 2 ASP 0 1 PFL 0 0 ADC i.MX23 Applications Processor Reference Manual, Rev. 1 8-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-28. HW_USBCTRL_HCCPARAMS Bit Field Descriptions BITS 31:16 RSVD2 15:8 EECP LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved. EHCI Extended Capabilities Pointer. Default = 0. This optional field indicates the existence of a capabilities list. A value of 0x00 indicates no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI configuration space of the first EHCI extended capability. The pointer value must be 0x40 or greater if implemented to maintain the consistency of the PCI header defined for this class of device. Isochronous Scheduling Threshold. Indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit 7 is 0, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. When bit 7 is a 1, then host software assumes the host controller may cache an isochronous data structure for an entire frame. Reserved. Asynchronous Schedule Park Capability. Default = 1. If this bit is set to a 1, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. Programmable Frame List Flag. If this bit is set to 0, then the system software must use a frame list length of 1024 elements with this host controller. The USBCMD register Frame List Size field is a read-only register and must be set to 0. If set to a 1, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K page boundary. This requirement ensures that the frame list is always physically contiguous. 64-bit Addressing Capability. No 64-bit addressing capability is supported. 7:4 IST RO 0x0 3 2 RSVD0 ASP RO 0x0 RO 0x1 1 PFL RO 0x1 0 ADC RO 0x0 DESCRIPTION: host controller capability params EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-19 USB High-Speed Host/Device Controller 8.6.15 Device Interface Version Number (Non-EHCI-Compliant) Register Description The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register. HW_USBCTRL_DCIVERSION 0x120 Table 8-29. HW_USBCTRL_DCIVERSION 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 DCIVERSION 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 8-30. HW_USBCTRL_DCIVERSION Bit Field Descriptions BITS LABEL 31:16 RSVD 15:0 DCIVERSION RW RESET RO 0x0 RW 0x1 DEFINITION Reserved. Two-byte BCD encoding of the interface version number. DESCRIPTION: device interface version EXAMPLE: Empty Example. 8.6.16 Device Control Capability Parameters (Non-EHCI-Compliant) Register Description These fields describe the overall host/device capability of the controller. The default value of this register is 0x00000185. HW_USBCTRL_DCCPARAMS 0x124 RSVD Table 8-31. HW_USBCTRL_DCCPARAMS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 RSVD1 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HC 0 7 DC 0 6 RSVD2 0 5 0 4 0 3 0 2 DEN Freescale Semiconductor Preliminary--Subject to Change Without Notice 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-20 USB High-Speed Host/Device Controller Table 8-32. HW_USBCTRL_DCCPARAMS Bit Field Descriptions BITS 31:9 RSVD1 8 HC LABEL RW RESET RO 0x0 RO 0x1 DEFINITION Reserved. Host Capable. When this bit is 1, this controller is capable of operating as an EHCI-compatible USB 2.0 host controller. Device Capable. When this bit is 1, this controller is capable of operating as a USB 2.0 device. Reserved. Device Endpoint Number. This field indicates the number of endpoints built into the device controller, which is 5. 7 DC RO 0x1 6:5 4:0 RSVD2 DEN RO 0x0 RO 0x5 DESCRIPTION: device controller capability params EXAMPLE: Empty Example. 8.6.17 USB Command Register Description The serial bus host/device controller executes the command indicated in this register. * Default Value:0x00080B00 (Host mode), 0x00080000 (Device mode) HW_USBCTRL_USBCMD Table 8-33. HW_USBCTRL_USBCMD 3 1 3 0 2 9 2 8 RSVD3 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ITC 1 9 1 8 1 7 1 6 1 5 FS2 1 4 ATDTW 1 3 SUTW 1 2 RSVD2 1 1 ASPE 1 0 RSVD1 0 9 ASP 0 8 0 7 LR 0 6 IAA 0 5 ASE 0 4 PSE 0 3 FS1 0 2 FS0 0 1 RST 0 0 RS 0x140 Table 8-34. HW_USBCTRL_USBCMD Bit Field Descriptions BITS 31:24 RSVD3 23:16 ITC LABEL RW RESET RO 0x0 RW 0x8 DEFINITION Reserved. Interrupt Threshold Control. Default 0x08. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are: IMM = 0x0 Immediate (no threshold). 1_MICROFRAME = 0x1 1_MICROFRAME. 2_MICROFRAME = 0x2 2_MICROFRAME. 4_MICROFRAME = 0x4 4_MICROFRAME. 8_MICROFRAME = 0x8 8_MICROFRAME. 16_MICROFRAME = 0x10 16_MICROFRAME. 32_MICROFRAME = 0x20 32_MICROFRAME. 64_MICROFRAME = 0x40 64_MICROFRAME. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-21 USB High-Speed Host/Device Controller Table 8-34. HW_USBCTRL_USBCMD Bit Field Descriptions BITS 15 FS2 14 ATDTW LABEL RW RESET RW 0x0 RW 0x0 DEFINITION Bit 2 of Frame List Size field. See definition of bit FS0 for the complete definition. Add dTD TripWire (device mode only). This bit is used as a semaphore to ensure the proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software. This bit shall also be cleared by hardware when is state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized. Setup TripWire (device mode only). This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (See USBMODE) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. Reserved. Asynchronous Schedule Park Mode Enable (OPTIONAL). This bit defaults to 0x1. Software uses this bit to enable or disable Park mode. When this bit is 1, Park mode is enabled. When this bit is a 0, Park mode is disabled. This field is set to 1 in host mode; 0 in device mode. Reserved. Asynchronous Schedule Park Mode Count (OPTIONAL). This field defaults to 0x3 and is R/W. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. See Section 4.10.3.2 of the EHCI specification for full operational details. Valid values are 0x1-0x3. Software must not write a 0 to this bit as this will result in undefined behavior. This field is set to 0x3 in host mode; 0x0 in device mode. Light Host/Device Controller Reset (OPTIONAL). Not Implemented. This field will always be 0. 13 SUTW RW 0x0 12 11 RSVD2 ASPE RO 0x0 RW 0x0 10 9:8 RSVD1 ASP RO 0x0 RW 0x0 7 LR RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-34. HW_USBCTRL_USBCMD Bit Field Descriptions BITS 6 IAA LABEL RW RESET RW 0x0 DEFINITION Interrupt on Async Advance Doorbell. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is 1, then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to 0 after it has set the Interrupt on Sync Advance status bit in the USBSTS register to 1. Software should not write a 1 to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. This bit is only used in host mode. Writing a 1 to this bit when device mode is selected will have undefined results. Asynchronous Schedule Enable. Default 0. This bit controls whether the host controller skips processing the Asynchronous Schedule. 0 = Do not process the Asynchronous Schedule. 1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule. Only the host controller uses this bit. Periodic Schedule Enable. Default Ob. This bit controls whether the host controller skips processing the Periodic Schedule. 0 = Do not process the Periodic Schedule 1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. Only the host controller uses this bit. Bit 1 of Frame List Size field. See definition of bit FS0 for the complete definition. Bit 0 of Frame List Size field. The Frame List Size field (FS2, FS1, FS0) specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3 and 2. Default is 000b. 000b = 1024 ELEMENTS (4096 bytes) Default value. 001b = 512_ELEMENTS (2048 bytes). 010b = 256_ELEMENTS (1024 bytes). 011b = 128_ELEMENTS (512 bytes). 100b = 64_ELEMENTS (256 bytes). 101b = 32_ELEMENTS (128 bytes). 110b = 16_ELEMENTS (64 bytes). 111b = 8_ELEMENTS (32 bytes). Only the host controller uses this field. 5 ASE RW 0x0 4 PSE RW 0x0 3 2 FS1 FS0 RW 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-23 USB High-Speed Host/Device Controller Table 8-34. HW_USBCTRL_USBCMD Bit Field Descriptions BITS 1 RST LABEL RW RESET RW 0x0 DEFINITION Controller Reset (RESET). Software uses this bit to reset the controller. This bit is set to 0 by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a 0 to this register. Host Controller: When software writes a 1 to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a 1 when the HCHalted bit in the USBSTS register is a 0. Attempting to reset an actively running host controller will result in undefined behavior. Device Controller: When software writes a 1 to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Writing a 1 to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. Run/Stop (RS). Default 0. 1 = Run. 0 = Stop. Host Controller: When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a 1. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a 1 to this field unless the host controller is in the Halted state (i.e., HCHalted in the USBSTS register is a 1). Device Controller: Writing a 1 to this bit will cause the device controller to enable a pullup on D+ and initiate an attach event. This control bit is not directly connected to the pullup enable, as the pullup will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized. Writing a 0 to this will cause a detach event. 0 RS RW 0x0 DESCRIPTION: command EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 8-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller 8.6.18 USB Status Register Description This register indicates various states of the Host/Device Controller and any pending interrupts. This register does not indicate status resulting from a transaction on the serial bus. Software clears certain bits in this register by writing a 1 to them. * Default Value:0x00001000 (Host mode), 0x00000000 (Device mode) HW_USBCTRL_USBSTS Table 8-35. HW_USBCTRL_USBSTS 3 1 3 0 2 9 RSVD5 2 8 2 7 2 6 2 5 TI1 2 4 TI0 2 3 2 2 RSVD4 2 1 2 0 1 9 UPI 1 8 UAI 1 7 RSVD3 1 6 NAKI 1 5 AS 1 4 PS 1 3 RCL 1 2 HCH 1 1 RSVD2 1 0 ULPII 0 9 RSVD1 0 8 SLI 0 7 SRI 0 6 URI 0 5 AAI 0 4 SEI 0 3 FRI 0 2 PCI 0 1 UEI 0 0 UI 0x144 Table 8-36. HW_USBCTRL_USBSTS Bit Field Descriptions BITS 31:26 RSVD5 25 TI1 LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. General-Purpose Timer Interrupt 1 (GPTINT1). This bit is set when the counter in the GPTIMER1CTRL (Non-EHCI) register transitions to 0. Writing a 1 to this bit will clear it. General-Purpose Timer Interrupt 0 (GPTINT0). This bit is set when the counter in the GPTIMER0CTRL (Non-EHCI) register transitions to 0. Writing a 1 to this bit will clear it. Reserved. USB Host Periodic Interrupt (USBHSTPERINT). This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected AND the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. This bit is not used by the device controller and will always be 0. 24 TI0 RW 0x0 23:20 RSVD4 19 UPI RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-25 USB High-Speed Host/Device Controller Table 8-36. HW_USBCTRL_USBSTS Bit Field Descriptions BITS 18 UAI LABEL RW RESET RW 0x0 DEFINITION USB Host Asynchronous Interrupt (USBHSTASYNCINT). This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected AND the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. This bit is not used by the device controller and will always be 0. Reserved. NAK Interrupt Bit. It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared. Asynchronous Schedule Status. This bit reports the current real status of the Asynchronous Schedule. When set to 0 the asynchronous schedule status is disabled and if set to 1 the status is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). Only used by the host controller. Periodic Schedule Status. 0 = Default. This bit reports the current real status of the Periodic Schedule. When set to 0 the periodic schedule is disabled, and if set to 1 the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). Only used by the host controller. Reclamation. 0 = Default. This is a read-only status bit used to detect an empty asynchronous schedule. Only used by the host controller; 0 in device mode. 17 16 RSVD3 NAKI RO 0x0 RO 0x0 15 AS RO 0x0 14 PS RO 0x0 13 RCL RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-36. HW_USBCTRL_USBSTS Bit Field Descriptions BITS 12 HCH LABEL RW RESET RW 0x0 DEFINITION HC Halted. 1 = Default. This bit is a 0 whenever the Run/Stop bit is a 1. The Host Controller sets this bit to 1 after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. internal error). Only used by the host controller; 0 in device mode. Reserved. Not present in this implementation. Reserved. DC Suspend. 0 = Default. When a device controller enters a suspend state from an active state, this bit will be set to a 1. The device controller clears the bit upon exiting from a suspend state. Only used by the device controller. SOF Received. 0 = Default. When the device controller detects a Start Of (micro) Frame, this bit will be set to a 1. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. Software writes a 1 to this bit to clear it. This is a non-EHCI status bit. USB Reset Received. 0 = Default. When the device controller detects a USB Reset and enters the default state, this bit will be set to a 1. Software can write a 1 to this bit to clear the USB Reset Received status bit. Only used by the device controller. NOTE: This bit should not normally be used to detect reset during suspend, as this block will normally be clock-gated during that time. Use HW_USBPHY_CTRL_RESUME_IRQ, instead. Interrupt on Async Advance. 0 = Default. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. Only used by the host controller. 11 10 9 8 RSVD2 ULPII RSVD1 SLI RO RW RO RW 0x0 0x0 0x0 0x0 7 SRI RW 0x0 6 URI RW 0x0 5 AAI RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-27 USB High-Speed Host/Device Controller Table 8-36. HW_USBCTRL_USBSTS Bit Field Descriptions BITS 4 SEI LABEL RW RESET RW 0x0 DEFINITION System Error. This bit is not used in this implementation and will always be set to 0. Frame List Rollover. The Host Controller sets this bit to a 1 when the Frame List Index rolls over from its maximum value to 0. The exact value at which the rollover occurs depends on the frame list size. For example. If the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a 1 every time FHINDEX [12] toggles. Only used by the host controller. Port Change Detect. The Host Controller sets this bit to a 1 when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. The Device Controller sets this bit to a 1 when the port controller enters the full or high-speed operational state. When the port controller exits the full or highspeed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits respectively. This bit is not EHCI compatible. USB Error Interrupt (USBERRINT). When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. See Section 4.15.1 in the EHCI specification for a complete list of host error interrupt conditions. The device controller detects resume signaling only. USB Interrupt (USBINT). This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. 3 FRI RW 0x0 2 PCI RW 0x0 1 UEI RW 0x0 0 UI RW 0x0 DESCRIPTION: status EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 8-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller 8.6.19 USB Interrupt Enable Register Description The interrupts to software are enabled with this register. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing polling of interrupt events by the software. HW_USBCTRL_USBINTR Table 8-37. HW_USBCTRL_USBINTR 3 1 3 0 2 9 RSVD5 2 8 2 7 2 6 2 5 TIE1 2 4 TIE0 2 3 2 2 RSVD4 2 1 2 0 1 9 UPIE 1 8 UAIE 1 7 RSVD3 1 6 NAKE 1 5 1 4 1 3 RSVD2 1 2 1 1 1 0 ULPIE 0 9 RSVD1 0 8 SLE 0 7 SRE 0 6 URE 0 5 AAE 0 4 SEE 0 3 FRE 0 2 PCE 0 1 UEE 0 0 UE 0x148 Table 8-38. HW_USBCTRL_USBINTR Bit Field Descriptions BITS 31:26 RSVD5 25 TIE1 LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. General-Purpose Timer Interrupt Enable 1. When this bit is a 1, and the GPTINT1 bit in the USBSTS register is a 1, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the GPTINT1 bit. General-Purpose Timer Interrupt Enable 0. When this bit is a 1, and the GPTINT0 bit in the USBSTS register is a 1, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the GPTINT0 bit. Reserved. USB Host Periodic Interrupt Enable. When this bit is a 1, and the USBHSTPERINT bit in the USBSTS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit. USB Host Asynchronous Interrupt Enable. RW 0x0 When this bit is a 1, and the USBHSTASYNCINT bit in the USBSTS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit. Reserved. NAK Interrupt Enable. This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated. Reserved. ULPI Enable. Not used in this implementation. Reserved. 24 TIE0 RW 0x0 23:20 RSVD4 19 UPIE RO 0x0 RW 0x0 18 UAIE RW 0x0 17 16 RSVD3 NAKE RO 0x0 RW 0x0 15:11 RSVD2 10 ULPIE 9 RSVD1 RO 0x0 RW 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-29 USB High-Speed Host/Device Controller Table 8-38. HW_USBCTRL_USBINTR Bit Field Descriptions BITS 8 SLE LABEL RW RESET RW 0x0 DEFINITION Sleep Enable. When this bit is a 1, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a 1 to the DCSuspend bit. Only used by the device controller. SOF Received Enable. When this bit is a 1, and the SOF Received bit in the USBSTS register is a 1, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit. USB Reset Enable. When this bit is a 1, and the USB Reset Received bit in the USBSTS register is a 1, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit. Only used by the device controller. Interrupt on Async Advance Enable. When this bit is a 1, and the Interrupt on Async Advance bit in the USBSTS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit. Only used by the host controller. System Error Enable. When this bit is a 1, and the System Error bit in the USBSTS register is a 1, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the System Error bit. Frame List Rollover Enable. When this bit is a 1, and the Frame List Rollover bit in the USBSTS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. Only used by the host controller. Port Change Detect Enable. When this bit is a 1, and the Port Change Detect bit in the USBSTS register is a 1, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit. USB Error Interrupt Enable. When this bit is a 1, and the USBERRINT bit in the USBSTS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register. USB Interrupt Enable. When this bit is a 1, and the USBINT bit in the USBSTS register is a 1, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit. 7 SRE RW 0x0 6 URE RW 0x0 5 AAE RW 0x0 4 SEE RW 0x0 3 FRE RW 0x0 2 PCE RW 0x0 1 UEE RW 0x0 0 UE RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller DESCRIPTION: interrupt enables EXAMPLE: Empty Example. 8.6.20 USB Frame Index Register Description This register is used by the host controller to index the periodic frame list. The register updates every 125 microseconds (once each micro-frame). Bits [N: 3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by system software in the Frame List Size field in the USBCMD register. This register must be written as a DWord. Byte writes produce-undefined results. This register cannot be written unless the Host Controller is in the 'Halted' state as indicated by the HCHalted bit. A write to this register while the Run/Stop bit is set to a 1 produces undefined results. Writes to this register also affect the SOF value. In device mode this register is Read-Only and, the device controller updates the FRINDEX [13:3] register from the frame number indicated by the SOF marker. Whenever a SOF is received by the USB bus, FRINDEX [13:3] will be checked against the SOF marker. If FRINDEX [13:3] is different from the SOF marker, FRINDEX [13:3] will be set to the SOF value and FRINDEX [2:0] will be set to 0 (i.e., SOF for 1 ms frame). If FRINDEX [13:3] is equal to the SOF value, FRINDEX [2:0] will be incremented (i.e., SOF for 125 us micro-frame.) * The default value of this register is undefined (free-running counter). HW_USBCTRL_FRINDEX Table 8-39. HW_USBCTRL_FRINDEX 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 RSVD 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 FRINDEX 0 7 0 6 0 5 0 4 0 3 0 2 0 1 UINDEX 0 0 0x14c i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-31 USB High-Speed Host/Device Controller Table 8-40. HW_USBCTRL_FRINDEX Bit Field Descriptions BITS 31:14 RSVD 13:3 FRINDEX LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved. Frame List Current Index. Read/write in host mode. Read in device mode. The value in this register increments at the end of each time frame (e.g., micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. In device mode, the value is the current frame number of the last frame transmitted. It is not used as an index. N_12 = 12 FRAME LIST SIZE = 1024, USBCMD = 3'b000. N_11 = 11 FRAME LIST SIZE = 512, USBCMD = 3'b001. N_10 = 10 FRAME LIST SIZE = 256, USBCMD = 3'b010. N_9 = 9 FRAME LIST SIZE = 128, USBCMD = 3'b011. N_8 = 8 FRAME LIST SIZE = 64, USBCMD = 3'b100. N_7 = 7 FRAME LIST SIZE = 32, USBCMD = 3'b101. N_6 = 6 FRAME LIST SIZE = 16, USBCMD = 3'b110. N_5 = 5 FRAME LIST SIZE = 8, USBCMD = 3'b111. 2:0 UINDEX RW 0x0 Current Microframe. DESCRIPTION: frame index EXAMPLE: Empty Example. 8.6.21 Frame List Base Address Register (Host Controller mode) Description In Host Controller mode, this 32-bit register contains the beginning address of the Periodic Frame List in the system memory. HCD loads this register prior to starting the schedule execution by the Host Controller. The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence. This is a read/write register. Writes must be DWORD writes. HW_USBCTRL_PERIODICLISTBASE 0x154 Table 8-41. HW_USBCTRL_PERIODICLISTBASE 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 PERBASE 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 RSVD 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-42. HW_USBCTRL_PERIODICLISTBASE Bit Field Descriptions BITS LABEL 31:12 PERBASE RW RESET RW 0x0 DEFINITION Base Address (Low). These bits correspond to memory address signals [31:12], respectively. Only used by the host controller. Reserved. Must be written as zeros. During runtime, the values of these bits are undefined. 11:0 RSVD RO 0x0 DESCRIPTION: PERIODIC LIST BASE (host-controller) EXAMPLE: Empty Example. 8.6.22 USB Device Address Register (Device Controller mode) Description In Device Controller mode, the upper seven bits of this register represent the device address. After any controller reset or a USB reset, the device address is set to the default address (0). The default address will match all incoming addresses. Software shall reprogram the address after receiving a SET_ADDRESS descriptor. The USBADRA is used to accelerate the SET_ADDRESS sequence by allowing the DCD to preset the USBADR register before the status phase of the SET_ADDRESS descriptor. This is a read/write register. Writes must be DWORD writes. HW_USBCTRL_DEVICEADDR 0x154 Table 8-43. HW_USBCTRL_DEVICEADDR 3 1 3 0 2 9 2 8 USBADR 2 7 2 6 2 5 2 4 USBADRA 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RSVD 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-33 USB High-Speed Host/Device Controller Table 8-44. HW_USBCTRL_DEVICEADDR Bit Field Descriptions BITS 31:25 USBADR 24 USBADRA LABEL RW RESET RW 0x0 RW 0x0 DEFINITION Device Address. These bits correspond to the USB device address. Device Address Advance. Default=0. When this bit is 0', any writes to USBADR are instantaneous. When this bit is written to a 1 at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: 1. IN is ACKed to endpoint 0. (USBADR is updated from staging register). 2. OUT/SETUP occur to endpoint 0. (USBADR is not updated). 3. Device Reset occurs (USBADR is reset to 0). Note: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD cannot write of the device address within 2ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. Reserved. Must be written as zeros. During runtime, the values of these bits are undefined. 23:0 RSVD RO 0x0 DESCRIPTION: DEVICE-ADDR EXAMPLE: Empty Example. 8.6.23 Next Asynchronous Address Register (Host Controller mode) Description In Host Controller mode, this 32-bit register contains the address of the next asynchronous queue head to be executed by the host. Bits [4:0] of this register cannot be modified by the system software and will always return a 0 when read. HW_USBCTRL_ASYNCLISTADDR 0x158 i.MX23 Applications Processor Reference Manual, Rev. 1 8-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-45. HW_USBCTRL_ASYNCLISTADDR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 ASYBASE 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 RSVD DEFINITION Link Pointer Low (LPL). These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (OH). Only used by the host controller. Reserved. These bits are reserved and their value has no effect on operation. 0 1 0 0 Table 8-46. HW_USBCTRL_ASYNCLISTADDR Bit Field Descriptions BITS LABEL 31:5 ASYBASE RW RESET RW 0x0 4:0 RSVD RO 0x0 DESCRIPTION: ASYNC-LIST-ADDR (host-controller) EXAMPLE: Empty Example. 8.6.24 Endpoint List Address Register (Device Controller mode) Description In Device Controller mode, this register contains the address of the top of the endpoint list in system memory. Bits [10:0] of this register cannot be modified by the system software and will always return a 0 when read. The memory structure referenced by this physical memory pointer is assumed 64-byte. This is a read/write register. Writes must be DWORD writes. HW_USBCTRL_ENDPOINTLISTADDR 0x158 Table 8-47. HW_USBCTRL_ENDPOINTLISTADDR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 EPBASE 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 RSVD 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-35 USB High-Speed Host/Device Controller Table 8-48. HW_USBCTRL_ENDPOINTLISTADDR Bit Field Descriptions BITS 31:11 EPBASE LABEL RW RESET RW 0x0 DEFINITION Endpoint List Pointer (Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Heads (QH). (i.e., one queue head per endpoint and direction.) Reserved. These bits are reserved and their value has no effect on operation. 10:0 RSVD RO 0x0 DESCRIPTION: EndPoint List Address EXAMPLE: Empty Example. 8.6.25 Embedded TT Asynchronous Buffer Status and Control Register (Host Controller mode) Description This register contains parameters needed for internal TT operations. This register is not used in the device controller operation. This is a read/write register. Writes must be DWORD writes. HW_USBCTRL_TTCTRL Table 8-49. HW_USBCTRL_TTCTRL 3 1 RSVD1 3 0 2 9 2 8 2 7 TTHA 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RSVD2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x15c Table 8-50. HW_USBCTRL_TTCTRL Bit Field Descriptions BITS 31 RSVD1 LABEL RW RESET RO 0x0 DEFINITION Reserved. These bits are reserved and their value has no effect on operation. Internal TT Hub Address Representation. Default is 0 (Read/Write). This field is used to match against the Hub Address field in QH and siTD to determine if the packet is routed to the internal TT for directly attached FS/LS devices. If the Hub Address in the QH or siTD does not match this address then the packet will be broadcast on the High Speed ports destined for a downstream High Speed hub with the address in the QH/siTD. Reserved. These bits are reserved and their value has no effect on operation. 30:24 TTHA RW 0x0 23:0 RSVD2 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller DESCRIPTION: TT (internal operation) Control EXAMPLE: Empty Example. 8.6.26 Programmable Burst Size Register Description This register is used to control dynamically change the burst size used during data movement on the initiator (master) interface. This is a read/write register. Writes must be DWORD writes. The default value is 0x00001010. HW_USBCTRL_BURSTSIZE 0x160 Table 8-51. HW_USBCTRL_BURSTSIZE 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RSVD 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 TXPBURST 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 RXPBURST 0 3 0 2 0 1 0 0 Table 8-52. HW_USBCTRL_BURSTSIZE Bit Field Descriptions BITS 31:16 RSVD LABEL RW RESET RO 0x0 DEFINITION Reserved. These bits are reserved and their value has no effect on operation. Programmable TX Burst Length. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus. Programmable RX Burst Length. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory. 15:8 TXPBURST RW 0x10 7:0 RXPBURST RW 0x10 DESCRIPTION: controls (dynamically) burst size for usb->ahb EXAMPLE: Empty Example. 8.6.27 Host Transmit Pre-Buffer Packet Timing Register Description The fields in this register control performance tuning associated with how the host controller posts data to the TX latency FIFO before moving the data onto the USB bus. The specific areas of performance include the how much data to post into the FIFO and an estimate for how long that operation should take in the target system. Definitions: T0 = Standard packet overhead T1 = Time to send data payload Tff = Time to i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-37 USB High-Speed Host/Device Controller fetch packet into TX FIFO up to specified level. Ts = Total Packet Flight Time (send-only) packet Ts = T0 + T1 Tp = Total Packet Time (fetch and send) packet Tp = Tff + T0 + T1 Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure Tp remains before the end of the (micro)frame. If so it proceeds to pre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the (micro)frame is < Ts then the packet attempt ceases and the packet is tried at a later time. Although this is not an error condition and the host controller will eventually recover, a mark will be made the scheduler health counter to note the occurrence of a "back-off" event. When a back-off event is detected, the partial packet fetched may need to be discarded from the latency buffer to make room for periodic traffic that will begin after the next SOF. Too many back-off events can waste bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated). Back-offs can be minimized with use of the TSCHHEALTH (Tff) described below. This is a read/write register. Writes must be DWORD writes. The default value of this register is 0x00000000. HW_USBCTRL_TXFILLTUNING 0x164 Table 8-53. HW_USBCTRL_TXFILLTUNING 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 TXFIFOTHRES 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 TXSCHEALTH 0 9 0 8 0 7 0 6 0 5 0 4 0 3 TXSCHOH 0 2 0 1 0 0 RSVD2 RSVD1 Table 8-54. HW_USBCTRL_TXFILLTUNING Bit Field Descriptions BITS 31:22 RSVD2 LABEL RW RESET RO 0x0 DEFINITION Reserved. These bits are reserved and their value has no effect on operation. FIFO Burst Threshold. This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set. Reserved. These bits are reserved and their value has no effect on operation. 21:16 TXFIFOTHRES RW 0x0 15:13 RSVD1 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSVD0 USB High-Speed Host/Device Controller Table 8-54. HW_USBCTRL_TXFILLTUNING Bit Field Descriptions BITS LABEL 12:8 TXSCHEALTH RW RESET RW 0x0 DEFINITION Scheduler Health Counter. This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. Reserved. This bit is reserved and its value has no effect on operation. Scheduler Overhead. This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode for OTG & SPH. The time unit represented in this register is 6.333us when a device is connected in Full Speed Mode for OTG & SPH. The time unit represented in this register is always 1.267 in the MPH product. 7 RSVD0 RO 0x0 6:0 TXSCHOH RW 0x0 DESCRIPTION: TX Fill Tuning EXAMPLE: Empty Example. 8.6.28 Inter-Chip Control Register Description HW_USBCTRL_IC_USB Table 8-55. HW_USBCTRL_IC_USB 0x16c This register is present but not used in this implementation. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSVD 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 IC_ENABLE 0 2 0 1 IC_VDD 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-39 USB High-Speed Host/Device Controller Table 8-56. HW_USBCTRL_IC_USB Bit Field Descriptions BITS LABEL 31:4 RSVD 3 IC_ENABLE RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Inter-Chip Transceiver Enable. These bits enables the InterChip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to 0b11 in the PORTSCx. Writing a '1' to each bit selects the IC_USB interface for that port. If the Controller is not MultiPort, IC8 to IC2 will be '0' and Read-Only. Inter-Chip Transceiver Voltage. Selects the voltage being supplied to the peripheral through each port (MPH case). VOLTAGE_NONE = 0x0 . VOLTAGE_1_0 = 0x1 . VOLTAGE_1_2 = 0x2 . VOLTAGE_1_5 = 0x3 . VOLTAGE_1_8 = 0x4 . VOLTAGE_3_0 = 0x5 . RESERVED0 = 0x6 . RESERVED1 = 0x7 . 2:0 IC_VDD RW 0x0 DESCRIPTION: This register enables and controls the IC_USB FS/LS transceiver. EXAMPLE: Empty Example. 8.6.29 ULPI Viewport Register Description HW_USBCTRL_ULPI Table 8-57. HW_USBCTRL_ULPI 0x170 This register is present but not used in this implementation. 3 1 ULPIWU 3 0 ULPIRUN 2 9 ULPIRW 2 8 RSVD0 2 7 ULPISS 2 6 2 5 ULPIPORT 2 4 2 3 2 2 2 1 2 0 ULPIADDR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 ULPIDATRD 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ULPIDATWR 0 3 0 2 0 1 0 0 Table 8-58. HW_USBCTRL_ULPI Bit Field Descriptions BITS 31 30 29 28 27 26:24 23:16 LABEL ULPIWU ULPIRUN ULPIRW RSVD0 ULPISS ULPIPORT ULPIADDR RW RW RW RW RO RO RW RW RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 DEFINITION Not used. Read as 0. Not used. Read as 0. Not used. Read as 0. Not used. Read as 0. Not used. Read as 0. Not used. Read as 0. Not used. Read as 0. i.MX23 Applications Processor Reference Manual, Rev. 1 8-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-58. HW_USBCTRL_ULPI Bit Field Descriptions BITS LABEL 15:8 ULPIDATRD 7:0 ULPIDATWR RW RESET RO 0x0 RW 0x0 DEFINITION Not used. Read as 0. Not used. Read as 0. DESCRIPTION: ULPI control EXAMPLE: Empty Example. 8.6.30 Endpoint NAK Register Description HW_USBCTRL_ENDPTNAK 0x178 Table 8-59. HW_USBCTRL_ENDPTNAK 3 1 3 0 2 9 2 8 2 7 2 6 RSVD1 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 EPTN 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 EPRN DEFINITION Reserved. TX Endpoint NAK. Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. EPTN[4] = Endpoint 4 EPTN[3] = Endpoint 3 EPTN[2] = Endpoint 2 EPTN[1] = Endpoint 1 EPTN[0] = Endpoint 0 Reserved. RX Endpoint NAK. Each RX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. EPRN[4] = Endpoint 4 EPRN[3] = Endpoint 3 EPRN[2] = Endpoint 2 EPRN[1] = Endpoint 1 EPRN[0] = Endpoint 0 0 1 0 0 Table 8-60. HW_USBCTRL_ENDPTNAK Bit Field Descriptions BITS 31:21 RSVD1 20:16 EPTN LABEL RW RESET RO 0x0 RW 0x0 15:5 4:0 RSVD0 EPRN RO 0x0 RW 0x0 DESCRIPTION: NAK-sent indicator i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-41 USB High-Speed Host/Device Controller EXAMPLE: Empty Example. 8.6.31 Endpoint NAK Enable Register Description HW_USBCTRL_ENDPTNAKEN 0x17c Table 8-61. HW_USBCTRL_ENDPTNAKEN 3 1 3 0 2 9 2 8 2 7 2 6 RSVD1 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 EPTNE 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 EPRNE Freescale Semiconductor Preliminary--Subject to Change Without Notice 0 1 0 0 Table 8-62. HW_USBCTRL_ENDPTNAKEN Bit Field Descriptions BITS 31:21 RSVD1 20:16 EPTNE LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. TX Endpoint NAK Enable. Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. EPTNE[4] = Endpoint 4 EPTNE[3] = Endpoint 3 EPTNE[2] = Endpoint 2 EPTNE[1] = Endpoint 1 EPTNE[0] = Endpoint 0 Reserved. RX Endpoint NAK Enable. Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. EPRNE[4] = Endpoint 4 EPRNE[3] = Endpoint 3 EPRNE[2] = Endpoint 2 EPRNE[1] = Endpoint 1 EPRNE[0] = Endpoint 0 15:5 4:0 RSVD0 EPRNE RO 0x0 RW 0x0 DESCRIPTION: NAK-sent indicator enable EXAMPLE: Empty Example. 8.6.32 Port Status and Control 1 Register Description Host Controller: A host controller must implement one to eight port registers. The number of port registers implemented by a particular instantiation of a host controller is documented in the HCSPARAMs register and is fixed at 1 in this implementation. Software uses this information as an input parameter to determine i.MX23 Applications Processor Reference Manual, Rev. 1 8-42 USB High-Speed Host/Device Controller how many ports need service. This register is only reset when power is initially applied or in response to a controller reset. The initial conditions of a port are: - No device connected - Port disabled If the port has port power control, this state remains until software applies power to the port by setting port power to 1. Device Controller: A device controller must implement only port register 1 and it does not support power control. Port control in device mode is only used for status port reset, suspend, and current connect status. It is also used to initiate test mode or force signaling and allows software to put the PHY into low power suspend mode and disable the PHY clock. * Default Value: 00010000000000000000XX0000000000b (Host mode) 00010000000000000001XX0000000100b (Device mode) X = Unknown HW_USBCTRL_PORTSC1 Table 8-63. HW_USBCTRL_PORTSC1 3 1 PTS 3 0 2 9 STS 2 8 PTW 2 7 PSPD 2 6 2 5 SRT 2 4 PFSC 2 3 PHCD 2 2 WKOC 2 1 WKDS 2 0 WKCN 1 9 1 8 PTC 1 7 1 6 1 5 PIC 1 4 1 3 PO 1 2 PP 1 1 LS 1 0 0 9 HSP 0 8 PR 0 7 SUSP 0 6 FPR 0 5 OCC 0 4 OCA 0 3 PEC 0 2 PE 0 1 CSC 0 0 CCS 0x184 Table 8-64. HW_USBCTRL_PORTSC1 Bit Field Descriptions BITS 31:30 PTS LABEL RW RESET RW 0x0 DEFINITION Parallel Transceiver Select. For this implementation, always set to 00b for UTMI. UTMI = 0 UTMI/UTMI+. PHIL = 1 Phillips-Classic. ULPI = 2 ULPI. SERIAL = 3 Serial/1.1FS. 29 28 STS PTW RW 0x0 RW 0x1 27:26 PSPD RW 0x0 Serial Transceiver Select. Always 0. Parallel Transceiver Width. This bit is always 0, indicating an 8-bit (60-MHz) UTMI interface. Port Speed. This register field indicates the speed at which the port is operating. For high-speed mode operation in the host controller and high-speed/fullspeed operation in the device controller, the port routing steers data to the protocol engine. This bit is not defined in the EHCI specification. FULL = 0 Full Speed. HIGH = 2 High Speed. 25 24 SRT PFSC RW 0x0 RW 0x0 Reserved. Port Force Full Speed Connect. Default = 0. Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as high-speed. This is useful for testing full-speed configurations with a high-speed host, hub or device. This bit is not defined in the EHCI specification. This bit is for debugging purposes. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-43 USB High-Speed Host/Device Controller Table 8-64. HW_USBCTRL_PORTSC1 Bit Field Descriptions BITS 23 PHCD LABEL RW RESET RW 0x0 DEFINITION PHY Low Power Suspend - Clock Disable (PLPSCD). Default = 0. Writing this bit to a 1 will disable the PHY clock. Writing a 0 enables it. Reading this bit will indicate the status of the PHY clock. In Device Mode: The PHY can be put into Low Power Suspend running (USBCMD Run/Stop=0) or the host has signaled suspend (PORTSC SUSPEND=1). Lowpower suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit. In Host Mode: The PHY can be put into Low Power Suspend device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. This bit is not defined in the EHCI specification. Wake on Over-current Enable (WKOC_E). Default = 0. Writing this bit to a 1 enables the port to be sensitive to over-current conditions as wake-up events. This field is 0 if Port Power (PP) is 0. Wake on Disconnect Enable (WKDSCNNT_E). Default=0. Writing this bit to a 1 enables the port to be sensitive to device disconnects as wake-up events. This field is 0 if Port Power (PP) is 0 or in device mode. Wake on Connect Enable (WKCNNT_E). Default=0. Writing this bit to a 1 enables the port to be sensitive to device connects as wake-up events. This field is 0 if Port Power (PP) is 0 or in device mode. Port Test Control. Default = 0000b. Any other value than 0 indicates that the port is operating in test mode. Refer to Chapter 9 of the USB Specification Revision 2.0 for details on each test mode. The TEST_FORCE_ENABLE_FS and TEST_FORCE_ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the TEST_FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_DISABLE will allow the port state machines to progress normally from that point. Note: Low speed operations are not supported. TEST_DISABLE = 0 Disable. TEST_J_STATE = 1 J-State. TEST_K_STATE = 2 K-State. TEST_J_SE0_NAK = 3 Host:SE0/Dev:NAK. TEST_PACKET = 4 Test-Packet. TEST_FORCE_ENABLE_HS = 5 Force-Enable-HS. TEST_FORCE_ENABLE_FS = 6 Force-Enable-FS. TEST_FORCE_ENABLE_LS = 7 Force-Enable-LS. 22 WKOC RW 0x0 21 WKDS RW 0x0 20 WKCN RW 0x0 19:16 PTC RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-64. HW_USBCTRL_PORTSC1 Bit Field Descriptions BITS 15:14 PIC LABEL RW RESET RW 0x0 DEFINITION Port Indicator Control. Default = 0. Refer to the USB Specification Revision 2.0 for a description on how these bits are to be used. OFF = 0 OFF. AMBER = 1 Amber. GREEN = 2 Green. UNDEF = 3 undefined. 13 PO RW 0x0 12 PP RW 0x0 11:10 LS RW 0x0 Port Owner. Port owner handoff is not implemented in this design, therefore this bit will always read back as 0. The EHCI definition is include here for reference: Default = 0. This bit unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0 to 1 transition. This bit unconditionally goes to 1 whenever the Configured bit is 0. System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). Software writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit means that an internal companion controller owns and controls the port. Port Power (PP). This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e., PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port, the PP bit in each affected port may be transitioned by the host controller driver from a 1 to a 0 (removing power from the port). This feature is implemented in the host/OTG controller (PPC = 1). In a device implementation, port power control is not necessary. Line Status. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. The bit encodings are listed below. In Host Mode: The use of linestate by the host controller driver is not necessary (unlike EHCI), because the port controller state machine and the port routing manage the connection of LS and FS. In Device Mode: The use of linestate by the device controller driver is not necessary. SE0 = 0 SE0. K_STATE = 1 K. J_STATE = 2 J. UNDEF = 3 Undefined. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-45 USB High-Speed Host/Device Controller Table 8-64. HW_USBCTRL_PORTSC1 Bit Field Descriptions BITS 9 HSP LABEL RW RESET RW 0x0 DEFINITION High-Speed Port. Default = 0. When the bit is 1, the host/device connected to the port is in high-speed mode and if set to 0, the host/device connected to the port is not in a high-speed mode. Note: HSP is redundant with PSPD(27:26) but will remain in the design for compatibility. This bit is not defined in the EHCI specification. Port Reset This field is 0 if Port Power (PP) is 0. In Host Mode: (Read/Write). 1 = Port is in Reset. 0 = Port is not in Reset. Default 0. When software writes a 1 to this bit, the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to 0 after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a 0 after the reset duration is timed in the driver. In Device Mode: This bit is a Read-Only status bit. Device reset from the USB bus is also indicated in the USBSTS register. 8 PR RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-46 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-64. HW_USBCTRL_PORTSC1 Bit Field Descriptions BITS 7 SUSP LABEL RW RESET RW 0x0 DEFINITION Suspend In Host Mode: (Read/Write) 0 = Port not in suspend state. 1 = Port in suspend state. Default = 0. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits Port State 0x Disable 10 Enable 11 Suspend When in suspend state, the downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to 0 when software sets the Force Port Resume bit to 0. The host controller ignores a write of 0 to this bit. If host software sets this bit to a 1 when the port is not enabled (i.e., Port enabled bit is a 0) the results are undefined. This field is 0 if Port Power (PP) is 0 in host mode. In Device Mode: (Read-Only) 1 = Port in suspend state. 0 = Port not in suspend state. Default=0. In device mode, this bit is a Read-Only status bit. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-47 USB High-Speed Host/Device Controller Table 8-64. HW_USBCTRL_PORTSC1 Bit Field Descriptions BITS 6 FPR LABEL RW RESET RW 0x0 DEFINITION Force Port Resume. 0 = No resume (K-state) detected/driven on port. 1 = Resume detected/driven on port. Default = 0. In Host Mode: Software sets this bit to 1 to drive resume signaling. The Host Controller sets this bit to 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a 1 because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to 1. This bit will automatically change to 0 after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a 0 after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a 1. This bit will remain a 1 until the port has switched to the high-speed idle. Writing a 0 has no effect because the port controller will time the resume operation and clear the bit when the port control state switches to HS or FS idle. This field is 0 if Port Power (PP) is 0 in host mode. This bit is not-EHCI compatible. In Device Mode: After the device has been in Suspend State for 5 ms or more, software must set this bit to 1 to drive resume signaling before clearing. The Device Controller will set this bit to 1 if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit transitions to a 1 because a J-to-K transition has been detected, the Port Change Detect bit in the USBSTS register is also set to 1. Over-Current Change. 0 = Default. 1 = This bit gets set to 1 when there is a change to Over-Current Active. Software clears this bit by writing a 1 to this bit position. For host/OTG implementations, the user can provide over-current detection to the vbus_pwr_fault input for this condition. For device-only implementations, this bit shall always be 0. 5 OCC RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-48 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-64. HW_USBCTRL_PORTSC1 Bit Field Descriptions BITS 4 OCA LABEL RW RESET RW 0x0 DEFINITION Over-Current Active. 0 = This port does not have an over-current condition. 1 = This port currently has an over-current condition. Default = 0. This bit will automatically transition from 1 to 0 when the over current condition is removed. For host/OTG implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition. For device-only implementations this bit shall always be 0. Port Enable/Disable Change. 0 = No change. 1 = Port enabled/disabled status has changed. Default = 0. In Host Mode: For the root hub, this bit gets set to a 1 only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a 1 to it. This field is 0 if Port Power (PP) is 0. In Device Mode: The device port is always enabled. (This bit will be 0) Port Enabled/Disabled. 0 = Disable. 1 = Enable. Default = 0. In Host Mode: Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a 1 to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled, (0) downstream propagation of data is blocked except for reset. This field is 0 if Port Power (PP) is 0 in host mode. In Device Mode: The device port is always enabled. (This bit will be 1) 3 PEC RW 0x0 2 PE RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-49 USB High-Speed Host/Device Controller Table 8-64. HW_USBCTRL_PORTSC1 Bit Field Descriptions BITS 1 CSC LABEL RW RESET RW 0x0 DEFINITION Connect Status Change. 0 = No change. 1 = Change in Current Connect Status. Default = 0. In Host Mode: Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a 1 to it. This field is 0 if Port Power (PP) is 0 in host mode. In Device Mode: This bit is undefined in device controller mode. Current Connect Status. In Host Mode: 0 = No device is present. 1 = Device is present on port. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is 0 if Port Power (PP) is 0 in host mode. In Device Mode: 0 = Not Attached. 1 = Attached. Default = 0. A 1 indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A 0 indicates that the device did not attach successfully or was forcibly disconnected by the software writing a 0 to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. 0 CCS RW 0x0 DESCRIPTION: port status and control EXAMPLE: Empty Example. 8.6.33 OTG Status and Control Register Description Host Controller: A host controller implements one On-The-Go (OTG) Status and Control register corresponding to Port 0 of the host controller. The OTGSC register has four sections: OTG Interrupt Enables (Read/Write) OTG Interrupt Status (Read/Write to Clear) OTG Status Inputs (Read-Only) OTG Controls (Read/Write) The status inputs are debounced using a 1-ms time constant. Values on the status i.MX23 Applications Processor Reference Manual, Rev. 1 8-50 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller inputs that do not persist for more than 1 ms will not cause an update of the status input register, or cause an OTG interrupt. See also USBMODE register. The default value of this register is 0x00000120. HW_USBCTRL_OTGSC Table 8-65. HW_USBCTRL_OTGSC 3 1 RSVD2 3 0 DPIE 2 9 ONEMSE 2 8 BSEIE 2 7 BSVIE 2 6 ASVIE 2 5 AVVIE 2 4 IDIE 2 3 RSVD1 2 2 DPIS 2 1 ONEMSS 2 0 BSEIS 1 9 BSVIS 1 8 ASVIS 1 7 AVVIS 1 6 IDIS 1 5 RSVD0 1 4 DPS 1 3 ONEMST 1 2 BSE 1 1 BSV 1 0 ASV 0 9 AVV 0 8 0 7 HABA 0 6 HADP 0 5 IDPU 0 4 DP 0 3 OT 0 2 HAAR 0 1 VC 0 0 VD 0x1a4 Table 8-66. HW_USBCTRL_OTGSC Bit Field Descriptions BITS 31 30 29 28 27 26 25 24 23 22 LABEL RSVD2 DPIE ONEMSE BSEIE BSVIE ASVIE AVVIE IDIE RSVD1 DPIS RW RO RW RW RW RESET 0x0 0x0 0x0 0x0 DEFINITION Reserved. Data Pulse Interrupt Enable 1 Millisecond Timer Interrupt Enable B Session End Interrupt Enable. Setting this bit enables the B session end interrupt. B Session Valid Interrupt Enable. Setting this bit enables the B session valid interrupt. A Session Valid Interrupt Enable. Setting this bit enables the A session valid interrupt. A VBus Valid Interrupt Enable. Setting this bit enables the A VBus valid interrupt. USB ID Interrupt Enable. Setting this bit enables the USB ID interrupt. Reserved. Data Pulse Interrupt Status. This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when USBMODE.CM = Host (11) and PORTSC(0).PortPower = Off (0). Software must write a 1 to clear this bit. 1 Millisecond Timer Interrupt Status. This bit is set once every millisecond. Software must write a 1 to clear this bit. B Session End Interrupt Status. This bit is set when VBus has fallen below the B session end threshold. Software must write a 1 to clear this bit. B Session Valid Interrupt Status. This bit is set when VBus has either risen above or fallen below the B session valid threshold (0.8 VDC). Software must write a 1 to clear this bit. A Session Valid Interrupt Status. This bit is set when VBus has either risen above or fallen below the A session valid threshold (0.8 VDC). Software must write a 1 to clear this bit. RW 0x0 RW 0x0 RW 0x0 RW 0x0 RO 0x0 RW 0x0 21 ONEMSS RW 0x0 20 BSEIS RW 0x0 19 BSVIS RW 0x0 18 ASVIS RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-51 ID USB High-Speed Host/Device Controller Table 8-66. HW_USBCTRL_OTGSC Bit Field Descriptions BITS 17 AVVIS LABEL RW RESET RW 0x0 DEFINITION A VBus Valid Interrupt Status. This bit is set when VBus has either risen above or fallen below the VBus valid threshold (4.4 VDC) on an A device. Software must write a 1 to clear this bit. USB ID Interrupt Status. This bit is set when a change on the ID input has been detected. Software must write a 1 to clear this bit. Reserved. Data Bus Pulsing Status. A 1 indicates data bus pulsing is being detected on the port. 1 Millisecond Timer Toggle. This bit toggles once per millisecond. B Session End. Indicates VBus is below the B session end threshold. B Session Valid. Indicates VBus is above the B session valid threshold. A Session Valid. Indicates VBus is above the A session valid threshold. A VBus Valid. Indicates VBus is above the A VBus valid threshold. USB ID. 0 = A device. 1 = B device. Hardware Assist B-Disconnect to A-connect. 0 = Disabled. 1 = Enable automatic B-disconnect to A-connect sequence. Hardware Assist Data-Pulse 1 = Start Data Pulse Sequence. ID Pullup. This bit provide control over the ID pullup resister. 0 = off. 1 = on (default). When this bit is 0, the ID input will not be sampled. Data Pulsing. Setting this bit causes the pullup on DP to be asserted for data pulsing during SRP. OTG Termination. This bit must be set when the OTG device is in device mode, this controls the pulldown on DM. Hardware Assist Auto-Reset. 0 = Disabled. 1 = Enable automatic reset after connect on host port. VBUS Charge. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. VBUS_Discharge. Setting this bit causes VBus to discharge through a resistor. 16 IDIS RW 0x0 15 14 RSVD0 DPS RO 0x0 RW 0x0 13 12 11 10 9 8 ONEMST BSE BSV ASV AVV ID RW 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 7 HABA RW 0x0 6 5 HADP IDPU RW 0x0 RW 0x1 4 DP RW 0x0 3 OT RW 0x0 2 HAAR RW 0x0 1 VC RW 0x0 0 VD RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-52 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller DESCRIPTION: OTG status/control EXAMPLE: Empty Example. 8.6.34 USB Device Mode Register Description HW_USBCTRL_USBMODE Table 8-67. HW_USBCTRL_USBMODE 0x1a8 Default Value:0x00000000 (implementation OTGmode not selected). 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 RSVD 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 VBPS 0 4 SDIS 0 3 SLOM 0 2 ES 0 1 CM 0 0 Table 8-68. HW_USBCTRL_USBMODE Bit Field Descriptions BITS 31:6 RSVD 5 VBPS LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Vbus Power Select 0 = Output is 0. 1 = Output is 1. This bit is connected to the vbus_pwr_select output and can be used for any generic control but is named to be used by logic that selects between an on-chip Vbus power source (charge pump) and an off-chip source in systems when both are available. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-53 USB High-Speed Host/Device Controller Table 8-68. HW_USBCTRL_USBMODE Bit Field Descriptions BITS 4 SDIS LABEL RW RESET RW 0x0 DEFINITION Stream Disable Mode. 0 = Inactive (default). 1 = Active. In Device Mode: Setting to a 1 disables double priming on both RX and TX for low bandwidth systems. This mode, when enabled, ensures that the RX and TX buffers are sufficient to contain an entire packet, so that the usual double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active. In Host Mode: Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significative when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING to characterize the adjustments needed for the scheduler when using this feature. Note: The use of this feature substantially limits of the overall USB performance that can be achieved. Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. 0 = Setup Lockouts On (default). 1 = Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMD). 3 SLOM RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-54 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-68. HW_USBCTRL_USBMODE Bit Field Descriptions BITS 2 ES LABEL RW RESET RW 0x0 DEFINITION Endian Select. This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words. 0 = Little Endian (default): First byte referenced in least significant byte of 32-bit word. 1 = Big Endian: First byte referenced in most significant byte of 32-bit word. Controller Mode. Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host & device capability, the controller will default to an idle state and will need to be initialized to the desired operating mode after reset. For combination host/device controllers, this register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. IDLE = 0x0 IDLE. DEVICE = 0x2 DEVICE. HOST = 0x3 HOST. 1:0 CM RW 0x0 DESCRIPTION: device mode EXAMPLE: Empty Example. 8.6.35 Endpoint Setup Status Register Description HW_USBCTRL_ENDPTSETUPSTAT 0x1ac Table 8-69. HW_USBCTRL_ENDPTSETUPSTAT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 ENDPTSETUPSTAT 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-55 RSVD USB High-Speed Host/Device Controller Table 8-70. HW_USBCTRL_ENDPTSETUPSTAT Bit Field Descriptions BITS LABEL 31:5 RSVD 4:0 ENDPTSETUPSTAT RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. This register is only used in device mode. DESCRIPTION: endpoint setup status EXAMPLE: Empty Example. 8.6.36 Endpoint Prime Register Description HW_USBCTRL_ENDPTPRIME 0x1b0 This register is used in device mode only. Table 8-71. HW_USBCTRL_ENDPTPRIME 3 1 3 0 2 9 2 8 2 7 2 6 RSVD1 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 PETB 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 PERB Freescale Semiconductor Preliminary--Subject to Change Without Notice 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-56 USB High-Speed Host/Device Controller Table 8-72. HW_USBCTRL_ENDPTPRIME Bit Field Descriptions BITS 31:21 RSVD1 20:16 PETB LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Prime Endpoint Transmit Buffer. For each endpoint, a corresponding bit is used to request that a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a 1 to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PETB[4] = Endpoint 4. PETB[3] = Endpoint 3. PETB[2] = Endpoint 2. PETB[1] = Endpoint 1. PETB[0] = Endpoint 0. Reserved. Prime Endpoint Receive Buffer. For each endpoint, a corresponding bit is used to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a 1 to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PERB[4] = Endpoint 4. PERB[3] = Endpoint 3. PERB[2] = Endpoint 2. PERB[1] = Endpoint 1. PERB[0] = Endpoint 0. 15:5 4:0 RSVD0 PERB RO 0x0 RW 0x0 DESCRIPTION: endpoint prime request EXAMPLE: Empty Example. 8.6.37 Endpoint Flush Register Description HW_USBCTRL_ENDPTFLUSH 0x1b4 This register is used in device-mode only. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-57 USB High-Speed Host/Device Controller Table 8-73. HW_USBCTRL_ENDPTFLUSH 3 1 3 0 2 9 2 8 2 7 2 6 RSVD1 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 FETB 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 FERB 0 1 0 0 Table 8-74. HW_USBCTRL_ENDPTFLUSH Bit Field Descriptions BITS 31:21 RSVD1 20:16 FETB LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Flush Endpoint Transmit Buffer. Writing a 1 to a bit(s) in this register will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for 1 of the associated endpoints, then that transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful. FETB[4] = Endpoint 4. FETB[3] = Endpoint 3. FETB[2] = Endpoint 2. FETB[1] = Endpoint 1. FETB[0] = Endpoint 0. Reserved. Flush Endpoint Receive Buffer. Writing a 1 to a bit(s) will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful. FERB[4] = Endpoint 4. FERB[3] = Endpoint 3. FERB[2] = Endpoint 2. FERB[1] = Endpoint 1. FERB[0] = Endpoint 0. 15:5 4:0 RSVD0 FERB RO 0x0 RW 0x0 DESCRIPTION: endpoint flush request EXAMPLE: Empty Example. 8.6.38 Endpoint Status Register Description HW_USBCTRL_ENDPTSTAT 0x1b8 This register is used in device mode only. i.MX23 Applications Processor Reference Manual, Rev. 1 8-58 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-75. HW_USBCTRL_ENDPTSTAT 3 1 3 0 2 9 2 8 2 7 2 6 RSVD1 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 ETBR 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 ERBR 0 1 0 0 Table 8-76. HW_USBCTRL_ENDPTSTAT Bit Field Descriptions BITS 31:21 RSVD1 20:16 ETBR LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved. Endpoint Transmit Buffer Ready. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a 1 by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. Note: These bits will be momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ETBR[4] = Endpoint 4. ETBR[3] = Endpoint 3. ETBR[2] = Endpoint 2. ETBR[1] = Endpoint 1. ETBR[0] = Endpoint 0. Reserved. Endpoint Receive Buffer Ready. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a 1 by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. Note: These bits will be momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ERBR[4] = Endpoint 4. ERBR[3] = Endpoint 3. ERBR[2] = Endpoint 2. ERBR[1] = Endpoint 1. ERBR[0] = Endpoint 0. 15:5 4:0 RSVD0 ERBR RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-59 USB High-Speed Host/Device Controller DESCRIPTION: endpoint ready EXAMPLE: Empty Example. 8.6.39 Endpoint Complete Register Description HW_USBCTRL_ENDPTCOMPLETE 0x1bc This register is used in device-mode only. Table 8-77. HW_USBCTRL_ENDPTCOMPLETE 3 1 3 0 2 9 2 8 2 7 2 6 RSVD1 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 ETCE 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RSVD0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 ERCE Freescale Semiconductor Preliminary--Subject to Change Without Notice 0 1 0 0 Table 8-78. HW_USBCTRL_ENDPTCOMPLETE Bit Field Descriptions BITS 31:21 RSVD1 20:16 ETCE LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Endpoint Transmit Complete Event. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a 1 will clear the corresponding bit in this register. ETCE[4] = Endpoint 4. ETCE[3] = Endpoint 3. ETCE[2] = Endpoint 2. ETCE[1] = Endpoint 1. ETCE[0] = Endpoint 0. Reserved. Endpoint Receive Complete Event. Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a 1 will clear the corresponding bit in this register. ERCE[4] = Endpoint 4. ERCE[3] = Endpoint 3. ERCE[2] = Endpoint 2. ERCE[1] = Endpoint 1. ERCE[0] = Endpoint 0. 15:5 4:0 RSVD0 ERCE RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-60 USB High-Speed Host/Device Controller DESCRIPTION: endpoint complete EXAMPLE: Empty Example. 8.6.40 Endpoint Control 0 Register Description Every Device will implement Endpoint0 as a control endpoint. The default value of this register is 0x00800080. HW_USBCTRL_ENDPTCTRL0 0x1c0 Table 8-79. HW_USBCTRL_ENDPTCTRL0 3 1 3 0 2 9 2 8 RSVD6 2 7 2 6 2 5 2 4 2 3 TXE 2 2 2 1 RSVD5 2 0 1 9 TXT 1 8 1 7 RSVD4 1 6 TXS 1 5 1 4 1 3 1 2 RSVD3 1 1 1 0 0 9 0 8 0 7 RXE 0 6 0 5 RSVD2 0 4 0 3 RXT 0 2 0 1 RSVD1 0 0 RXS Table 8-80. HW_USBCTRL_ENDPTCTRL0 Bit Field Descriptions BITS 31:24 RSVD6 23 TXE LABEL RW RESET RO 0x0 RW 0x1 DEFINITION Reserved. TX Endpoint Enable. 1 = Enabled. Endpoint0 is always enabled. Reserved. Bit reserved and should be read as zeroes. TX Endpoint Transmit Type. Endpoint0 is fixed as a Control endpoint. CONTROL = 0 Control. 22:20 RSVD5 19:18 TXT RO 0x0 RW 0x0 17 16 RSVD4 TXS RO 0x0 RW 0x0 Reserved. Endpoint Stall. 0 = Endpoint OK (default). 1 = Endpoint Stalled. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Note: There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a 1 to it, then follow this procedure: Continually write this stall bit until it is set OR until a new SETUP has been received by checking the associated ENDPTSETUPSTAT bit. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-61 USB High-Speed Host/Device Controller Table 8-80. HW_USBCTRL_ENDPTCTRL0 Bit Field Descriptions BITS 15:8 RSVD3 7 RXE LABEL RW RESET RO 0x0 RW 0x1 DEFINITION Reserved. Bit reserved and should be read as zeroes. RX Endpoint Enable. 1 = Enabled. Endpoint0 is always enabled. Reserved. Bit reserved and should be read as zeroes. RX Endpoint Receive Type. Endpoint0 is fixed as a Control endpoint. CONTROL = 0 Control. 6:4 3:2 RSVD2 RXT RO 0x0 RW 0x0 1 0 RSVD1 RXS RO 0x0 RW 0x0 Reserved. RX Endpoint Stall. 0 = Endpoint OK (default). 1 = Endpoint Stalled. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Note: There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a 1 to it, then follow this procedure: Continually write this stall bit until it is set OR until a new SETUP has been received by checking the associated ENDPTSETUPSTAT bit. DESCRIPTION: endpoint control registers [0-n] EXAMPLE: Empty Example. 8.6.41 Endpoint Control 1 Register Description Register HW_USBCTRL_ENDPTCTRL1 is the control register for endpoint 1 in a device. CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint/direction. HW_USBCTRL_ENDPTCTRL1 0x1c4 i.MX23 Applications Processor Reference Manual, Rev. 1 8-62 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-81. HW_USBCTRL_ENDPTCTRL1 3 1 3 0 2 9 2 8 RSVD6 2 7 2 6 2 5 2 4 2 3 TXE 2 2 TXR 2 1 TXI 2 0 RSVD5 1 9 TXT 1 8 1 7 TXD 1 6 TXS 1 5 1 4 1 3 1 2 RSVD3 1 1 1 0 0 9 0 8 0 7 RXE 0 6 RXR 0 5 RXI 0 4 RSVD2 0 3 RXT 0 2 0 1 RXD 0 0 RXS Table 8-82. HW_USBCTRL_ENDPTCTRL1 Bit Field Descriptions BITS 31:24 RSVD6 23 TXE LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. TX Endpoint Enable. 0 = Disabled (default). 1 = Enabled. An endpoint should be enabled only after it has been configured. TX Data Toggle Reset. Write 1 to reset PID sequence. Whenever a configuration event is received for this endpoint, software must write a 1 to this bit in order to synchronize the data PIDs between the host and device. TX Data Toggle Inhibit. 0 = PID Sequencing Enabled (default). 1 = PID Sequencing Disabled. This bit is only used for test and should always be written as 0. Writing a 1 to this bit will cause this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet. Reserved. TX Endpoint Transmit Type. CONTROL = 0 Control. ISO = 1 Isochronous. BULK = 2 Bulk. INT = 3 Interrupt. 22 TXR RW 0x0 21 TXI RW 0x0 20 RSVD5 19:18 TXT RO 0x0 RW 0x0 17 TXD RW 0x0 TX Endpoint Data Source. 0 = Dual Port Memory Buffer/DMA Engine (default). Should always be written as 0. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-63 USB High-Speed Host/Device Controller Table 8-82. HW_USBCTRL_ENDPTCTRL1 Bit Field Descriptions BITS 16 TXS LABEL RW RESET RW 0x0 DEFINITION Endpoint Stall. 0 = Endpoint OK. 1 = Endpoint Stalled. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. Note (control endpoint types only): There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However, Should the DCD observe that the stall bit is not set after writing a 1 to it, then follow this procedure: Continually write this stall bit until it is set OR until a new SETUP has been received by checking the associated ENDPTSETUPSTAT bit. Reserved. RX Endpoint Enable. 0 = Disabled (default). 1 = Enabled. An Endpoint should be enabled only after it has been configured. Data Toggle Reset. Write 1 to reset PID Sequence. Whenever a configuration event is received for this endpoint, software must write a 1 to this bit in order to synchronize the data PIDs between the host and device. RX Data Toggle Inhibit. 0 = Disabled (default). 1 = Enabled. This bit is only used for test and should always be written as 0. Writing a 1 to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packet regardless of their data PID. Reserved. RX Endpoint Receive Type. CONTROL = 0 Control. ISO = 1 Isochronous. BULK = 2 Bulk. INT = 3 Interrupt. 15:8 7 RSVD3 RXE RO 0x0 RW 0x0 6 RXR RW 0x0 5 RXI RW 0x0 4 3:2 RSVD2 RXT RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 8-64 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-82. HW_USBCTRL_ENDPTCTRL1 Bit Field Descriptions BITS 1 RXD LABEL RW RESET RW 0x0 DEFINITION RX Endpoint Data Sink. 0 = Dual Port Memory Buffer/DMA Engine (default). Should always be written as 0. RX Endpoint Stall. 0 = Endpoint OK (default). 1 = Endpoint Stalled. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. Note (control endpoint types only): There is a slight delay (50 clocks maximum) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a 1 to it, then follow this procedure: Continually write this stall bit until it is set OR until a new SETUP has been received by checking the associated ENDPTSETUPSTAT bit. 0 RXS RW 0x0 DESCRIPTION: endpoint control [0-n] EXAMPLE: Empty Example. 8.6.42 Endpoint Control 2 Register Description Register HW_USBCTRL_ENDPTCTRL2 is the control register for endpoint 2 in a device. See the bit field defintions and descriptions of register HW_USBCTRL_ENDPTCTRL1. CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint/direction. HW_USBCTRL_ENDPTCTRL2 0x1c8 Table 8-83. HW_USBCTRL_ENDPTCTRL2 3 1 3 0 2 9 2 8 RSVD6 2 7 2 6 2 5 2 4 2 3 TXE 2 2 TXR 2 1 TXI 2 0 RSVD5 1 9 TXT 1 8 1 7 TXD 1 6 TXS 1 5 1 4 1 3 1 2 RSVD3 1 1 1 0 0 9 0 8 0 7 RXE 0 6 RXR 0 5 RXI 0 4 RSVD2 0 3 RXT 0 2 0 1 RXD 0 0 RXS i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-65 USB High-Speed Host/Device Controller Table 8-84. HW_USBCTRL_ENDPTCTRL2 Bit Field Descriptions BITS 31:24 23 22 21 20 19:18 LABEL RSVD6 TXE TXR TXI RSVD5 TXT RW RO RW RW RW RO RW RESET 0x0 0x0 0x0 0x0 0x0 0x0 DEFINITION CONTROL = 0 Control ISO = 1 Isochronous BULK = 2 Bulk INT = 3 Int 17 16 15:8 7 6 5 4 3:2 TXD TXS RSVD3 RXE RXR RXI RSVD2 RXT RW RW RO RW RW RW RO RW 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 CONTROL = 0 Control ISO = 1 Isochronous BULK = 2 Bulk INT = 3 Int 1 0 RXD RXS RW 0x0 RW 0x0 EXAMPLE: Empty Example. 8.6.43 Endpoint Control 3 Register Description Register HW_USBCTRL_ENDPTCTRL3 is the control register for endpoint 3 in a device. See the bit field defintions and descriptions of register HW_USBCTRL_ENDPTCTRL1. CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint/direction. HW_USBCTRL_ENDPTCTRL3 0x1cc Table 8-85. HW_USBCTRL_ENDPTCTRL3 3 1 3 0 2 9 2 8 RSVD6 2 7 2 6 2 5 2 4 2 3 TXE 2 2 TXR 2 1 TXI 2 0 RSVD5 1 9 TXT 1 8 1 7 TXD 1 6 TXS 1 5 1 4 1 3 1 2 RSVD3 1 1 1 0 0 9 0 8 0 7 RXE 0 6 RXR 0 5 RXI 0 4 RSVD2 0 3 RXT 0 2 0 1 RXD 0 0 RXS Table 8-86. HW_USBCTRL_ENDPTCTRL3 Bit Field Descriptions BITS 31:24 23 22 21 20 LABEL RSVD6 TXE TXR TXI RSVD5 RW RO RW RW RW RO RESET 0x0 0x0 0x0 0x0 0x0 DEFINITION i.MX23 Applications Processor Reference Manual, Rev. 1 8-66 Preliminary--Subject to Change Without Notice Freescale Semiconductor USB High-Speed Host/Device Controller Table 8-86. HW_USBCTRL_ENDPTCTRL3 Bit Field Descriptions BITS 19:18 TXT LABEL RW RESET RW 0x0 DEFINITION CONTROL = 0 Control ISO = 1 Isochronous BULK = 2 Bulk INT = 3 Int 17 16 15:8 7 6 5 4 3:2 TXD TXS RSVD3 RXE RXR RXI RSVD2 RXT RW RW RO RW RW RW RO RW 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 CONTROL = 0 Control ISO = 1 Isochronous BULK = 2 Bulk INT = 3 Int 1 0 RXD RXS RW 0x0 RW 0x0 EXAMPLE: Empty Example. 8.6.44 Endpoint Control 4 Register Description Register HW_USBCTRL_ENDPTCTRL4 is the control register for endpoint 4 in a device. See the bit field defintions and descriptions of register HW_USBCTRL_ENDPTCTRL1. CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint/direction. HW_USBCTRL_ENDPTCTRL4 0x1d0 Table 8-87. HW_USBCTRL_ENDPTCTRL4 3 1 3 0 2 9 2 8 RSVD6 2 7 2 6 2 5 2 4 2 3 TXE 2 2 TXR 2 1 TXI 2 0 RSVD5 1 9 TXT 1 8 1 7 TXD 1 6 TXS 1 5 1 4 1 3 1 2 RSVD3 1 1 1 0 0 9 0 8 0 7 RXE 0 6 RXR 0 5 RXI 0 4 RSVD2 0 3 RXT 0 2 0 1 RXD 0 0 RXS Table 8-88. HW_USBCTRL_ENDPTCTRL4 Bit Field Descriptions BITS 31:24 23 22 21 20 19:18 LABEL RSVD6 TXE TXR TXI RSVD5 TXT RW RO RW RW RW RO RW RESET 0x0 0x0 0x0 0x0 0x0 0x0 DEFINITION CONTROL = 0 Control ISO = 1 Isochronous BULK = 2 Bulk INT = 3 Int 17 16 TXD TXS RW 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 8-67 USB High-Speed Host/Device Controller Table 8-88. HW_USBCTRL_ENDPTCTRL4 Bit Field Descriptions BITS 15:8 7 6 5 4 3:2 LABEL RSVD3 RXE RXR RXI RSVD2 RXT RW RO RW RW RW RO RW RESET 0x0 0x0 0x0 0x0 0x0 0x0 DEFINITION CONTROL = 0 Control ISO = 1 Isochronous BULK = 2 Bulk INT = 3 Int 1 0 RXD RXS RW 0x0 RW 0x0 EXAMPLE: Empty Example. USBCTRL Block v1.4, Revision 1.11 8.6.45 i.MX23 Applications Processor Reference Manual, Rev. 1 8-68 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 9 Integrated USB 2.0 PHY This chapter describes the integrated USB 2.0 full-speed and high-speed PHY available on the i.MX23. Programmable registers are described in Section 9.4, "Programmable Registers." 9.1 Overview The i.MX23 contains an integrated USB 2.0 PHY macrocell capable of connecting to PC host systems at the USB full-speed (FS) rate of 12 Mbits/s or at the USB 2.0 high-speed (HS) rate of 480 Mbits/s. See Figure 9-1 for a block diagram of the PHY. The integrated PHY provides a standard UTM interface. The USB_DP and USB_DN pins connect directly to a USB device connector. USB 2.0 Controller UTMI Digital USB_DP Analog RX/TX System PLL Digital TX Digital RX On-Chip RAM AHB Slave Bus ARM APBX Bridge DCLK Bus Interface AHB Master Bus USB_DN Crystal Oscillator Integrated USB 2.0 PHY (UTMI Macrocell) Figure 9-1. USB 2.0 PHY Block Diagram The following subsections describe the external interfaces, internal interfaces, major blocks, and programable registers that comprise the integrated USB 2.0 PHY. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9-1 Integrated USB 2.0 PHY 9.2 * * Operation The digital portions of the USBPHY block include the UTMI, digital transmitter, digital receiver, and the programmable registers. The analog transceiver section comprises an analog receiver and an analog transmitter, as shown in Figure 9-2. The UTM provides a 16-bit interface to the USB controller. This interface is clocked at 30 MHz. 9.2.1 UTMI The UTMI block handles the line_state bits, reset buffering, suspend distribution, transceiver speed selection, and transceiver termination selection. The PLL supplies a 120-MHz signal to all of the digital logic. The UTMI block does a final divide-by-four to develop the 30-MHz clock used in the interface. 9.2.2 Digital Transmitter The digital transmitter receives the 16-bit transmit data from the USB controller and handles the tx_valid, tx_validh and tx_ready handshake. In addition, it contains the transmit serializer that converts the 16-bit parallel words at 30 MHz to a single bitstream at 480 Mbit for high-speed or 12 Mbit for full-speed. It does this while implementing the bit-stuffing algorithm and the NRZI encoder that are used to remove the DC component from the serial bitstream. The output of this encoder is sent to the full-speed (FS) or high-speed (HS) drivers in the analog transceiver section's transmitter block. 9.2.3 Digital Receiver The digital receiver receives the raw serial bitstream from the full speed (FS) differential transceiver, and a 9X, 480-MHz sampled data from the high speed (HS) differential transceiver. As the phase of the USB host transmitter shifts relative to the local PLL, the receiver section's HS DLL tracks these changes to give a reliable sample of the incoming 480-Mbit/s bitstream. Since this sample point shifts relative to the PLL phase used by the digital logic, a rate-matching elastic buffer is provided to cross this clock domain boundary. Once the bitstream is in the local clock domain, an NRZI decoder and bit unstuffer restore the original payload data bitstream and pass it to a deserializer and holding register. The receive state machine handles the rx_valid, rx_validh, and handshake with the USB controller. The handshake is not interlocked, in that there is no rx_ready signal coming from the controller. The controller must take each 16-bit value as presented by the PHY. The receive state machine provides an rx_active signal to the controller that indicates when it is inside a valid packet (SYNC detected, etc.). 9.2.4 Analog Receiver The analog receiver comprises five differential receivers, two single-ended receivers, and a 9X, 480-MHz HS data sampling module, as shown in Figure 9-2 and described further in this section. i.MX23 Applications Processor Reference Manual, Rev. 1 9-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Integrated USB 2.0 PHY RPU Enable HS Current Source Enable HS Drive Enable HS Data Drive FS Driver Output Enable FS DataDrive Assert SE0 FS Edge Mode Select Test and discrete power-down controls Sampled Data 9X Oversample Sampled Squelch Transmitter VDDIO (3.3V) 1500 VDDIO (3.3 V) 200 K (2 each) USB_DP Squelch HS Differential RCVR USB_DN USB Cable FS Differential RCVR HS_Disconnect_Detect 15 K 15 K USB_Plugged_In_Detect Single-Ended Detector SE_DP Single-Ended Detector SE_DM Receiver Figure 9-2. USB 2.0 PHY Analog Transceiver Block Diagram 9.2.4.1 HS Differential Receiver The high-speed differential receiver is both a differential analog receiver and threshold comparator. Its output is a one if the differential signal is greater than a 0-V threshold. Its output is 0, otherwise. Its purpose is to discriminate the 400-mV differential voltage resulting from the high-speed drivers current flow into the dual 45 terminations found on each leg of the differential pair. The envelope or squelch detector, described below, ensures that the differential signal has sufficient magnitude to be valid. The HS differential receiver tolerates up to 500 mV of common mode offset. 9.2.4.2 Squelch Detector The squelch detector is a differential analog receiver and threshold comparator. Its output is a 1 if the differential magnitude is less than a nominal 100-mV threshold. Its output is 0, otherwise. Its purpose is to invalidate the HS differential receiver when the incoming signal is simply too low to receive reliably. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9-3 Integrated USB 2.0 PHY 9.2.4.3 FS Differential Receiver The full-speed differential receiver is both a differential analog receiver and threshold comparator. The crossover voltage falls between 1.3 V and 2.0 V. Its output is a 1 when the USB_DP line is above the crossover point and the USB_DN line is below the crossover point. 9.2.4.4 HS Disconnect Detector This host-side function is not used in i.MX23 applications, but is included to make a complete UTMI macrocell. It is a differential analog receiver and threshold comparator. Its output is a 1 if the differential magnitude is greater than a nominal 575-mV threshold. Its output is 0, otherwise. 9.2.4.5 USB Plugged-In Detector The USB plugged-in detector looks for both USB_DP and USB_DN to be high. There is a pair of large on-chip pullup resistors (200K) that hold both USB_DP and USB_DN high when the USB cable is not attached. The USB plugged-in detector signals a 0 in this case. When in device mode, the host/hub interface that is upstream from the i.MX23 contains a 15K pulldown resistor that easily overrides the 200K pullup. When plugged in, at least one signal in the pair will be low, which will force the plugged-in detector's output high. 9.2.4.6 Single-Ended USB_DP Receiver The single-ended USB_DP receiver output is high whenever the USB_DP input is above its nominal 1.8-V threshold. 9.2.4.7 Single-Ended USB_DN Receiver The single-ended USB_DN receiver output is high whenever the USB_DN input is above its nominal 1.8-V threshold. 9.2.4.8 9X Oversample Module The 9X oversample module uses nine identically spaced phases of the 480-MHz clock to sample a high speed bit data. The squelch signal is sampled only 1X. 9.2.5 Analog Transmitter The analog transmitter comprises two differential drivers: one for high-speed signaling and one for full-speed signaling. It also contains the switchable 1.5K pullup resistor. See Figure 9-2. i.MX23 Applications Processor Reference Manual, Rev. 1 9-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Integrated USB 2.0 PHY 9.2.5.1 Switchable High-Speed 45 Termination Resistors High-speed current mode differential signaling requires good 90 differential termination at each end of the USB cable. This results from switching in 45 terminating resistors from each signal line to ground at each end of the cable. Because each signal is parallel terminated with 45 at each end, each driver sees a 22.5 load. This is much too low of a load impedance for full-speed signaling levels--hence the need for switchable high-speed terminating resistors. Switchable trimming resistors are provided to tune the actual termination resistance of each device, as shown in Figure 9-3. The HW_USBPHY_TX_TXCAL45DP bit field, for example, allows one of 16 trimming resistor values to be placed in parallel with the 45 terminator on the USB_DP signal. 9.2.5.2 Full-Speed Differential Driver The full-speed differential drivers are essentially "open drain" low-impedance pulldown devices that are switched in a differential mode for full-speed signaling, i.e., either one or the other device is turned on to signal the "J" state or the "K" state. These drivers are both turned on, simultaneously, for high-speed signaling. This has the effect of switching in both 45 terminating resistors. The tx_fs_hiz signal originates in the digital transmitter section. The hs_term signal that also controls these drivers comes from the UTMI. 9.2.5.3 High-Speed Differential Driver The high-speed differential driver receives a 17.78-mA current from the constant current source and essentially steers it down either the USB_DP signal or the USB_DN signal or alternatively to ground. This current will produce approximately a 400-mV drop across the 22.5 termination seen by the driver when it is steered onto one of the signal lines. The approximately 17.78-mA current source is referenced back to the integrated voltage-band-gap circuit. The Iref, IBias, and V to I circuits are shared with the integrated battery charger. 9.2.5.4 Switchable 1.5K USB_DP Pullup Resistor The i.MX23 contains a switchable 1.5K pullup resistor on the USB_DP signal. This resistor is switched on to tell the host/hub controller that a full-speed-capable device is on the USB cable, powered on, and ready. This resistor is switched off at power-on reset so the host does not recognize a USB device until processor software enables the announcement of a full-speed device. 9.2.5.5 Switchable 15K USB_DP Pulldown Resistor The i.MX23 contains a switchable 15K pulldown resistor on both USB_DP and USB_DN signals. This is used in host mode to tell the device controller that a host is present. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9-5 Integrated USB 2.0 PHY To External Temperature Sensor To Battery Charger Vbg Ibias V to I HW_USBPHY_PWD: TXPWDV2I, TXPWDIBIAS HW_USBPHY_TX: D_CAL Current trim Current Steering current switch 17.78mA data_p,hs_xcvr data_n,hs_xcvr current switch USB_DP USB Cable USB_DN 45 HW_USBPHY_TX_ TXCAL45DP HW_USBPHY_TX_ TXCAL45DN HW_USBPHY_TX: TXENCAL45DP,DN 45 FS DRVR FS DRVR data_p,data_n, fs_hiz, hs_term Figure 9-3. USB 2.0 PHY Transmitter Block Diagram i.MX23 Applications Processor Reference Manual, Rev. 1 9-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Integrated USB 2.0 PHY Table 9-1 summarizes the response of the PHY analog transmitter to various states of UTMI input and key transmit/receive state machine states. Table 9-1. USB PHY Terminator States UTMI OPMODE 00=Normal UTM TERM 0 1 1 1 1 0 0 0 1 1 0 0 1 1 1 1 0 0 0 1 1 0 UTM XCVR 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 0 1 0 0 1 0 1 T/R X T R R T X T R X X X X T R R T X T R X X X Function HS FS FS CHIRP CHIRP DISCONNECT HS HS FS CHIRP DISCONNECT HS FS FS CHIRP CHIRP DISCONNECT HS HS FS CHIRP DISCONNECT 45 HIZ 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1500 HIZ 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 SUSPEND 01=NoDrive POR 10=NoNRZI NoBitStuff 11= Invalid 9.2.6 Recommended Register Configuration for USB Certification The register settings in this section are recommended for passing USB certification. The following settings lower the J/K levels to certifiable limits: HW_USBPHY_TX_TXCAL45DP = 0x0 HW_USBPHY_TX_TXCAL45DN = 0x0 HW_USBPHY_TX_D_CAL = 0x7 The following settings help lower jitter in extreme conditions, for example, during heavy SDRAM usage with worst-case bit patterns: HW_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD = 0x1 HW_CLKCTRL_PLLCTRL0_CP_SEL = 0x2 Note that HW_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD is controlled by the SFTRST and CLKGATE bits in the AUDIOIN block. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9-7 Integrated USB 2.0 PHY 9.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. 9.4 Programmable Registers The USB 2.0 integrated PHY contains the following directly programmable registers. 9.4.1 USB PHY Power-Down Register Description HW_USBPHY_PWD HW_USBPHY_PWD_SET HW_USBPHY_PWD_CLR HW_USBPHY_PWD_TOG Table 9-2. HW_USBPHY_PWD 0x000 0x004 0x008 0x00c The USB PHY Power-Down Register provides overall control of the PHY power state. 3 1 3 0 2 9 2 8 2 7 2 6 RSVD2 2 5 2 4 2 3 2 2 2 1 2 0 RXPWDRX 1 9 RXPWDDIFF 1 8 RXPWD1PT1 1 7 RXPWDENV 1 6 1 5 RSVD1 1 4 1 3 1 2 TXPWDV2I 1 1 TXPWDIBIAS 1 0 TXPWDFS 0 9 0 8 0 7 0 6 0 5 RSVD0 0 4 0 3 0 2 0 1 0 0 Table 9-3. HW_USBPHY_PWD Bit Field Descriptions BITS LABEL 31:21 RSVD2 20 RXPWDRX RW RESET RO 0x0 RW 0x1 DEFINITION Reserved. 0 = Normal operation. 1 = Power-down the entire USB PHY receiver block except for the full-speed differential receiver. 0 = Normal operation. 1 = Power-down the USB high-speed differential receiver. 0 = Normal operation. 1 = Power-down the USB full-speed differential receiver. 0 = Normal operation. 1 = Power-down the USB high-speed receiver envelope detector (squelch signal). Reserved. 19 RXPWDDIFF RW 0x1 18 RXPWD1PT1 RW 0x1 17 RXPWDENV RW 0x1 16:13 RSVD1 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 9-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Integrated USB 2.0 PHY Table 9-3. HW_USBPHY_PWD Bit Field Descriptions BITS LABEL 12 TXPWDV2I RW RESET RW 0x1 DEFINITION 0 = Normal operation. 1 = Power-down the USB PHY transmit V-to-I converter and the current mirror. Note that these circuits are shared with the battery charge circuit. Setting this to 1 does not power-down these circuits, unless the corresponding bit in the battery charger is also set for power-down. 0 = Normal operation. 1 = Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path. Note that these circuits are shared with the battery charge circuit. Setting this bit to 1 does not power-down these circuits, unless the corresponding bit in the battery charger is also set for power-down. 0 = Normal operation. 1 = Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output. Reserved. 11 TXPWDIBIAS RW 0x1 10 TXPWDFS RW 0x1 9:0 RSVD0 RO 0x0 DESCRIPTION: This register is used to control the USB PHY power state. See bits description for details. EXAMPLE: Empty Example. 9.4.2 USB PHY Transmitter Control Register Description HW_USBPHY_TX HW_USBPHY_TX_SET HW_USBPHY_TX_CLR HW_USBPHY_TX_TOG 0x010 0x014 0x018 0x01c The USB PHY Transmitter Control Register handles the transmit controls. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9-9 Integrated USB 2.0 PHY Table 9-4. HW_USBPHY_TX 3 1 3 0 2 9 2 8 2 7 USBPHY_TX_EDGECTRL 2 6 2 5 USBPHY_TX_SYNC_INVERT 2 4 USBPHY_TX_SYNC_MUX 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TXENCAL45DN TXENCAL45DP TXCAL45DN TXCAL45DP Table 9-5. HW_USBPHY_TX Bit Field Descriptions BITS LABEL 31:29 RSVD5 28:26 USBPHY_TX_EDGECTRL RW RESET RO 0x0 RW 0x4 DEFINITION Reserved. Controls the edge-rate of the current sensing transistors used in HS transmit. NOT FOR CUSTOMER USE. NOT FOR CUSTOMER USE. While in testmode enables clock jitter analysis by resyncing data to the USB_DP and USB_DM pins. 0 = no Sync, 1 = Sync. When EMI clock is ungated, the USB data is resynced with EMI clock (for EMI jitter analysis), otherwise the USB clock is used for resync. Enables multiplexer to synchronize data from the USB_DP and USB_DM pins 0 = No sync, 1 = Sync. NOT FOR CUSTOMER USE. Reserved. This bit is not used and must remain cleared. Reserved. Decode to select a 45-Ohm resistance to the USB_DP output pin. Maximum resistance = 0000. Resistance is centered by design at 0110. Reserved. This bit is not used and must remain cleared. Reserved. Decode to select a 45-Ohm resistance to the USB_DN output pin. Maximum resistance = 0000. Resistance is centered by design at 0110. Reserved. Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% 25 USBPHY_TX_SYNC_INVERT RW 0x0 24 USBPHY_TX_SYNC_MUX RW 0x0 23:22 21 20 19:16 RSVD4 TXENCAL45DP RSVD3 TXCAL45DP RO RW RO RW 0x0 0x0 0x0 0x6 15:14 13 12 11:8 RSVD2 TXENCAL45DN RSVD1 TXCAL45DN RO RW RO RW 0x0 0x0 0x0 0x6 7:4 3:0 RSVD0 D_CAL RO 0x0 RW 0x7 DESCRIPTION: This register is used to control several items related USB Phy transmitter. i.MX23 Applications Processor Reference Manual, Rev. 1 9-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor D_CAL RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVD0 Integrated USB 2.0 PHY EXAMPLE: Empty Example. 9.4.3 USB PHY Receiver Control Register Description HW_USBPHY_RX HW_USBPHY_RX_SET HW_USBPHY_RX_CLR HW_USBPHY_RX_TOG Table 9-6. HW_USBPHY_RX 0x020 0x024 0x028 0x02c The USB PHY Receiver Control Register handles receive path controls. 3 1 3 0 2 9 2 8 2 7 RSVD2 2 6 2 5 2 4 2 3 2 2 RXDBYPASS 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 RSVD1 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 DISCONADJ 0 4 0 3 RSVD0 0 2 0 1 ENVADJ 0 0 Table 9-7. HW_USBPHY_RX Bit Field Descriptions BITS LABEL 31:23 RSVD2 22 RXDBYPASS RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. 0 = Normal operation. 1 = Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver. This test mode is intended for lab use only. Reserved. The DISCONADJ field adjusts the trip point for the disconnect detector: 0000 = Trip-Level Voltage is 0.57500 V 0001 = Trip-Level Voltage is 0.56875 V 0010 = Trip-Level Voltage is 0.58125 V 0011 = Trip-Level Voltage is 0.58750 V 01XX = Reserved 1XXX = Reserved Reserved. The ENVADJ field adjusts the trip point for the envelope detector. 0000 = Trip-Level Voltage is 0.12500 V 0001 = Trip-Level Voltage is 0.10000 V 0010 = Trip-Level Voltage is 0.13750 V 0011 = Trip-Level Voltage is 0.15000 V 01XX = Reserved 1XXX = Reserved 21:7 6:4 RSVD1 DISCONADJ RO 0x0 RW 0x0 3 2:0 RSVD0 ENVADJ RO 0x0 RW 0x0 DESCRIPTION: This register is used to control several items related USB Phy receiver i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9-11 Integrated USB 2.0 PHY EXAMPLE: Empty Example. 9.4.4 USB PHY General Control Register Description The USB PHY General Control Register handles Host controls. This register also includes interrupt enables and connectivity detect enables and results. HW_USBPHY_CTRL HW_USBPHY_CTRL_SET HW_USBPHY_CTRL_CLR HW_USBPHY_CTRL_TOG Table 9-8. HW_USBPHY_CTRL 3 1 3 0 2 9 2 8 HOST_FORCE_LS_SE0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 ENIRQRESUMEDETECT 0 8 0 7 0 6 0 5 DEVPLUGIN_POLARITY 0 4 ENDEVPLUGINDETECT 0 3 HOSTDISCONDETECT_IRQ 0 2 ENIRQHOSTDISCON 0 1 ENHOSTDISCONDETECT 0 0 0x030 0x034 0x038 0x03c ENIRQDEVPLUGIN DATA_ON_LRADC UTMI_SUSPENDM ENOTGIDDETECT DEVPLUGIN_IRQ RESUME_IRQ CLKGATE SFTRST RSVD2 RSVD3 RSVD1 Table 9-9. HW_USBPHY_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Writing a 1 to this bit will soft-reset the HW_USBPHY_PWD, HW_USBPHY_TX, HW_USBPHY_RX, and HW_USBPHY_CTRL registers. Gate UTMI Clocks. Clear to 0 to run clocks. Set to 1 to gate clocks. Set this to save power while the USB is not actively being used. Configuration state is kept while the clock is gated. Used by the PHY to indicate a powered-down state. If all the power-down bits in the HW_USBPHY_PWD are enabled, UTMI_SUSPENDM will be 0, otherwise 1. UTMI_SUSPENDM is negative logic, as required by the UTMI specification. Forces the next FS packet that is transmitted to have a EOP with low-speed timing. This bit is used in host mode for the resume sequence. After the packet is transferred, this bit is cleared. The design can use this function to force the LS SE0 or use the HW_USBPHY_CTRL_UTMI_SUSPENDM to trigger this event when leaving suspend. This bit is used in conjunction with HW_USBPHY_DEBUG_HOST_RESUME_DEBUG. Reserved. 30 CLKGATE RW 0x1 29 UTMI_SUSPENDM RO 0x0 28 HOST_FORCE_LS_SE0 RW 0x0 27:14 RSVD3 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 9-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSVD0 Integrated USB 2.0 PHY Table 9-9. HW_USBPHY_CTRL Bit Field Descriptions BITS LABEL 13 DATA_ON_LRADC 12 DEVPLUGIN_IRQ RW RESET RW 0x0 RW 0x0 DEFINITION Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. Indicates that the device is connected. Reset this bit by writing a 1 to the SCT clear address space and not by a general write. Enables interrupt for the detection of connectivity to the USB line. Indicates that the host is sending a wake-up after suspend. This bit is also set on a reset during suspend. Use this bit to wake up from suspend for either the resume or the reset case. Reset this bit by writing a 1 to the SCT clear address space and not by a general write. Enables interrupt for detection of a non-J state on the USB line. This should only be enabled after the device has entered suspend mode. Reserved. Enables circuit to detect resistance of MiniAB ID pin. Reserved. For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in. If set to 1, then it trips the interrupt if the device is unplugged. For device mode, enables 200-KOhm pullups for detecting connectivity to the host. Indicates that the device has disconnected in high-speed mode. Reset this bit by writing a 1 to the SCT clear address space and not by a general write. Enables interrupt for detection of disconnection to Device when in high-speed host mode. This should be enabled after ENDEVPLUGINDETECT is enabled. For host mode, enables high-speed disconnect detector. This signal allows the override of enabling the detection that is normally done in the UTMI controller. The UTMI controller enables this circuit whenever the host sends a start-of-frame packet. Due to a on chip issue (Errata #2791), software must pay attention to when to assert the ENHOSTDISCONDETECT bit in HW_USBPHY_CTRL register: 1. Only set HW_USBPHY_CTRL.ENHOSTDISCONDETECT during high speed host mode. 2. Do not set HW_USBPHY_CTRL.ENHOSTDISCONDETECT during the reset and speed negotiation period. 3. Do not set HW_USBPHY_CTRL.ENHOSTDISCONDETECT during host suspend/resume sequence. Reserved. 11 10 ENIRQDEVPLUGIN RESUME_IRQ RW 0x0 RW 0x0 9 ENIRQRESUMEDETECT RW 0x0 8 7 6 5 RSVD2 ENOTGIDDETECT RSVD1 DEVPLUGIN_POLARITY RO RW RO RW 0x0 0x0 0x0 0x0 4 3 ENDEVPLUGINDETECT HOSTDISCONDETECT_IRQ RW 0x0 RW 0x0 2 ENIRQHOSTDISCON RW 0x0 1 ENHOSTDISCONDETECT RW 0x0 0 RSVD0 RO 0x0 DESCRIPTION: This register is used to control high-level items related USB PHY. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9-13 Integrated USB 2.0 PHY EXAMPLE: Empty Example. 9.4.5 USB PHY Status Register Description HW_USBPHY_STATUS Table 9-10. HW_USBPHY_STATUS 0x040 The USB PHY Status Register holds results of IRQ and other detects. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 HOSTDISCONDETECT_STATUS 0 2 0 1 0 0 DEVPLUGIN_STATUS RESUME_STATUS OTGID_STATUS RSVD4 RSVD3 RSVD2 RSVD1 Table 9-11. HW_USBPHY_STATUS Bit Field Descriptions BITS LABEL 31:11 RSVD4 10 RESUME_STATUS 9 8 RSVD3 OTGID_STATUS RW RESET RO 0x0 RO 0x0 RO 0x0 RW 0x0 DEFINITION Reserved. Indicates that the host is sending a wake-up after suspend and has triggered an interrupt. Reserved. Indicates the results of ID pin on MiniAB plug. False (0) is when ID resistance is less than Ra_Plug_ID, indicating host (A) side. True (1) is when ID resistance is greater than Rb_Plug_ID, indicating device (B) side. Reserved. Indicates that the device has been connected on the USB_DP and USB_DM lines. Reserved. Indicates that the device has disconnected while in high-speed host mode. Reserved. 7 6 5:4 3 2:0 RSVD2 DEVPLUGIN_STATUS RSVD1 HOSTDISCONDETECT_STAT US RSVD0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 DESCRIPTION: This register is a status register and contains IRQ and other status. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 9-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSVD0 Integrated USB 2.0 PHY 9.4.6 USB PHY Debug Register Description HW_USBPHY_DEBUG HW_USBPHY_DEBUG_SET HW_USBPHY_DEBUG_CLR HW_USBPHY_DEBUG_TOG Table 9-12. HW_USBPHY_DEBUG 0x050 0x054 0x058 0x05c This register is used to debug the USB PHY. 3 1 3 0 2 9 HOST_RESUME_DEBUG 2 8 2 7 SQUELCHRESETLENGTH 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 SQUELCHRESETCOUNT 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 DEBUG_INTERFACE_HOLD 0 0 ENSQUELCHRESET ENHSTPULLDOWN ENTX2RXCOUNT HSTPULLDOWN Table 9-13. HW_USBPHY_DEBUG Bit Field Descriptions BITS LABEL 31 RSVD3 30 CLKGATE RW RESET RO 0x0 RW 0x1 DEFINITION Reserved. Gate Test Clocks. Clear to 0 for running clocks. Set to 1 to gate clocks. Set this to save power while the USB is not actively being used. Configuration state is kept while the clock is gated. Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. Duration of RESET in terms of the number of 480-MHz cycles. Set bit to allow squelch to reset high-speed receive. Reserved. Delay in between the detection of squelch to the reset of high-speed RX. Reserved. Set this bit to allow a countdown to transition in between TX and RX. Delay in between the end of transmit to the beginning of receive. This is a Johnson count value and thus will count to 8. Reserved. Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown. Set bit 4 to 1 to override the control of the USB_DM 15-KOhm pulldown. Clear to 0 to disable. 29 HOST_RESUME_DEBUG RW 0x1 RW 0xf RW 0x1 RO 0x0 RW 0x18 RO 0x0 RW 0x0 RW 0x0 28:25 SQUELCHRESETLENGTH 24 ENSQUELCHRESET 23:21 RSVD2 20:16 SQUELCHRESETCOUNT 15:13 RSVD1 12 ENTX2RXCOUNT 11:8 TX2RXCOUNT 7:6 5:4 RSVD0 ENHSTPULLDOWN RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9-15 OTGIDPIOLOCK TX2RXCOUNT CLKGATE RSVD2 RSVD3 RSVD1 RSVD0 Integrated USB 2.0 PHY Table 9-13. HW_USBPHY_DEBUG Bit Field Descriptions BITS LABEL 3:2 HSTPULLDOWN RW RESET RW 0x0 DEFINITION Set bit 3 to 1 to pull down 15-KOhm on USB_DP line. Set bit 2 to 1 to pull down 15-KOhm on USB_DM line. Clear to 0 to disable. Use holding registers to assist in timing for external UTMI interface. Once OTG ID is determined from HW_USBPHY_STATUS_OTGID_STATUS, use this to hold the value. This is to save power for the comparators that are used to determine the ID status. 1 0 DEBUG_INTERFACE_HOLD OTGIDPIOLOCK RW 0x0 RW 0x0 DESCRIPTION: Register not intended for customer use. EXAMPLE: Empty Example. 9.4.7 UTMI Debug Status Register 0 Description The UTMI Debug Status Register 0 holds multiple views for counters and status of state machines. This is used in conjunction with the HW_USBPHY_DEBUG1.DBG_ADDRESS field to choose which function to view. The default is described in the bit fields below and is used to count errors. HW_USBPHY_DEBUG0_STATUS 0x060 Table 9-14. HW_USBPHY_DEBUG0_STATUS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 UTMI_RXERROR_FAIL_COUNT 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 LOOP_BACK_FAIL_COUNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SQUELCH_COUNT Table 9-15. HW_USBPHY_DEBUG0_STATUS Bit Field Descriptions BITS LABEL 31:26 SQUELCH_COUNT RW RESET RO 0x0 DEFINITION Running count of the squelch reset instead of normal end for HS RX. i.MX23 Applications Processor Reference Manual, Rev. 1 9-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Integrated USB 2.0 PHY Table 9-15. HW_USBPHY_DEBUG0_STATUS Bit Field Descriptions BITS LABEL 25:16 UTMI_RXERROR_FAIL_COU NT 15:0 LOOP_BACK_FAIL_COUNT RW RESET RO 0x0 RO 0x0 DEFINITION Running count of the UTMI_RXERROR. Running count of the failed pseudo-random generator loopback. Each time entering testmode, counter goes to "900d" and will count up for every detected packet failure in digital/analog loopback tests. DESCRIPTION: Register not intended for customer use. EXAMPLE: Empty Example. 9.4.8 UTMI Debug Status Register 1 Description HW_USBPHY_DEBUG1 HW_USBPHY_DEBUG1_SET HW_USBPHY_DEBUG1_CLR HW_USBPHY_DEBUG1_TOG Table 9-16. HW_USBPHY_DEBUG1 0x070 0x074 0x078 0x07c Chooses the muxing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 ENTAILADJVD 1 3 1 2 ENTX2TX 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 DBG_ADDRESS 0 1 0 0 RSVD1 Table 9-17. HW_USBPHY_DEBUG1 Bit Field Descriptions BITS LABEL 31:15 RSVD1 14:13 ENTAILADJVD RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% This bit has no function in this system. Reserved. Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS. 12 11:4 3:0 ENTX2TX RSVD0 DBG_ADDRESS RW 0x1 RO 0x0 RW 0x0 DESCRIPTION: Register not intended for customer use. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9-17 RSVD0 Integrated USB 2.0 PHY EXAMPLE: Empty Example. 9.4.9 UTMI RTL Version Description HW_USBPHY_VERSION Table 9-18. HW_USBPHY_VERSION 0x080 Fields for RTL Version. 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 9-19. HW_USBPHY_VERSION Bit Field Descriptions BITS 31:24 MAJOR 23:16 MINOR 15:0 STEP LABEL RW RESET RO 0x4 RO 0x0 RO 0x0 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: Empty Example. 9.4.10 USB PHY IP Block Register Description The USB PHY IP Block Register IS FOR INTERNAL USE ONLY. It provides control of miscellaneous control bits found in other non-USB PIO control blocks that affects USB operations. HW_USBPHY_IP HW_USBPHY_IP_SET HW_USBPHY_IP_CLR HW_USBPHY_IP_TOG 0x090 0x094 0x098 0x09c i.MX23 Applications Processor Reference Manual, Rev. 1 9-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Integrated USB 2.0 PHY Table 9-20. HW_USBPHY_IP 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 ANALOG_TESTMODE 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 EN_USB_CLKS 0 1 0 0 PLL_LOCKED Table 9-21. HW_USBPHY_IP Bit Field Descriptions BITS 31:25 RSVD1 24:23 DIV_SEL LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. TEST MODE FOR INTERNAL USE ONLY. This field is currently NOT supported. These bits came from the clkctrl PIO control block (clkctrl_pllctrl0_div_sel). DEFAULT = 0x0 PLL frequency is 480 MHz LOWER = 0x1 Lower the PLL fequency from 480MHz to 384MHz LOWEST = 0x2 Lower the PLL fequency from 480MHz to 288MHz UNDEFINED = 0x3 Undefined 22:21 LFR_SEL RW 0x0 TEST MODE FOR INTERNAL USE ONLY. Adjusts loop filter resistor. These bits came from the clkctrl PIO control block (clkctrl_pllctrl0_lfr_sel). DEFAULT = 0x0 Default loop filter resistor TIMES_2 = 0x1 Doubles the loop filter resistor TIMES_05 = 0x2 Halves the loop filter resistor UNDEFINED = 0x3 Undefined 20:19 CP_SEL RW 0x0 TEST MODE FOR INTERNAL USE ONLY. Adjusts charge pump current. These bits came from the clkctrl PIO control block (clkctrl_pllctrl0_cp_sel). DEFAULT = 0x0 Default charge pump current TIMES_2 = 0x1 Doubles charge pump current TIMES_05 = 0x2 Halves the charge pump current UNDEFINED = 0x3 Undefined 18 TSTI_TX_DP RW 0x0 17 TSTI_TX_DM RW 0x0 16 ANALOG_TESTMODE RW 0x0 15:3 2 RSVD0 EN_USB_CLKS RO 0x0 RW 0x0 Analog testmode bit. Drives value on the DP pad. Default value is 1'b0. This bit came from the test control module. Analog testmode bit. Drives value on the DM pad. Default value is 1'b0. This bit came from the test control module. Analog testmode bit. Set to 0 for normal operation. Set to 1 for engineering debug of analog PHY block. This bit came from the test control module. Reserved. If set to 0, 9-phase PLL outputs for USB PHY are powered down. If set to 1, 9-phase PLL outputs for USB PHY are powered up. Additionally, the UTMICLK120_GATE and UTMICLK30_GATE must be deasserted in the UTMI phy to enable USB operation. This bit came from the clkctrl PIO control block (clkctrl_pllctrl0_en_usb_clks). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 9-19 PLL_POWER TSTI_TX_DM TSTI_TX_DP LFR_SEL DIV_SEL CP_SEL RSVD1 RSVD0 Integrated USB 2.0 PHY Table 9-21. HW_USBPHY_IP Bit Field Descriptions BITS LABEL 1 PLL_LOCKED RW RESET RW 0x0 DEFINITION Software controlled bit to indicate when the USB PLL has locked. Software needs to wait 10 us after enabling the PLL POWER bit (0) before asserting this bit. If set to 0, tells the UTMI module that the USB PLL has not locked. If set to 1, tells the UTMI module that the USB PLL has locked. Software should clear this bit prior to turning off the USB PLL. This bit came from the clkctrl module. USB PLL Power On (0 = PLL off; 1 = PLL On). Allow 10 us after turning the PLL on before using the PLL as a clock source. This is the time the PLL takes to lock to 480 MHz. This bit came from the clkctrl PIO control block (clkctrl_pllctrl0_power). 0 PLL_POWER RW 0x0 DESCRIPTION: This register contains control bits in other non AUSTIN USB applications. EXAMPLE: Empty Example. USBPHY Block v4.0, Revision 1.52 9.4.11 i.MX23 Applications Processor Reference Manual, Rev. 1 9-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 10 AHB-to-APBH Bridge with DMA This chapter describes the AHB-to-APBH bridge on the i.MX23, along with its central DMA function and implementation examples. Programmable registers are described in Section 10.5, "Programmable Registers." 10.1 Overview The AHB-to-APBH bridge provides the i.MX23 with an inexpensive peripheral attachment bus running on the AHB's HCLK. (The "H" in APBH denotes that the APBH is synchronous to HCLK, as compared to APBX, which runs on the crystal-derived XCLK.) As shown in Figure 10-1, the AHB-to-APBH bridge includes the AHB-to-APB PIO bridge for memory-mapped I/O to the APB devices, as well as a central DMA facility for devices on this bus and a vectored interrupt controller for the ARM926 core. Each one of the APB peripherals, including the vectored interrupt controller, are documented in their own chapters elsewhere in this document. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-1 AHB-to-APBH Bridge with DMA AHB AHB Slave AHB Master AHB-to-APBH DMA APBH Master AHB-to-APBH Bridge Interrupt Collector ATA_NAND0 APBH SSP1 ATA_NAND1 SSP2 ATA_NAND2 ATA_NAND3 Figure 10-1. AHB-to-APBH Bridge DMA Block Diagram The DMA controller uses the APBH bus to transfer read and write data to and from each peripheral. There is no separate DMA bus for these devices. Contention between the DMA's use of the APBH bus and the AHB-to-APB bridge functions' use of the APBH is mediated by internal arbitration logic. For contention between these two units, the DMA is favored and the AHB slave will report "not ready" via its HREADY output until the bridge transfer can complete. The arbiter tracks repeated lockouts and inverts the priority, guaranteeing the CPU every fourth transfer on the APB. 10.2 AHBH DMA The DMA supports eight channels of DMA services, as shown in Table 10-1. The shared DMA resource allows each independent channel to follow a simple chained command list. Command chains are built up using the general structure, as shown in Figure 10-2. i.MX23 Applications Processor Reference Manual, Rev. 1 10-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-1. APBH DMA Channel Assignments aPBH DMA Channel # USAGE 0 1 2 3 4 5 6 7 Reserved SSP1 SSP2 Reserved NAND_DEVICE0 NAND_DEVICE1 NAND_DEVICE2 NAND_DEVICE3 A single command structure or channel command word specifies a number of operations to be performed by the DMA in support of a given device. Thus, the CPU can set up large units of work, chaining together many DMA channel command words, pass them off to the DMA, and have no further concern for the device until the DMA completion interrupt occurs. The goal here, as with the entire design of the i.MX23, is to have enough intelligence in the DMA and the devices to keep the interrupt frequency from any device below 1-kHz (arrival intervals longer than 1 ms). Thus, a single command structure can issue 32-bit PIO write operations to key registers in the associated device using the same APB bus and controls that it uses to write DMA data bytes to the device. For example, this allows a chain of operations to be issued to the ATANAND controller to send NAND command bytes, address bytes, and data transfers where the command and address structure is completely under software control, but the administration of that transfer is handled autonomously by the DMA. Each DMA structure can have from 0 to 15 PIO words appended to it. The #PIOWORDs field, if non-zero, instructs the DMA engine to copy these words to the APB, beginning at PADDR = 0x0000 and incrementing its PADDR for each cycle. The DMA master generates only normal read/write transfers to the APBH. It does not generate SCT set, clear, or toggle transfers. word 0 NEXTCMDADDR CMDPIOWORDS NANDWAIT4READY WAIT4ENDCMD SEMAPHORE NANDLOCK IRQONCMPLT CHAIN word 1 XFER_COUNT word 2 word 3-n BUFFER ADDRESS PIOWORD Figure 10-2. AHB-to-APBH Bridge DMA Channel Command Structure i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice COMMAND 10-3 AHB-to-APBH Bridge with DMA Once any requested PIO words have been transferred to the peripheral, the DMA examines the two-bit command field in the channel command structure. Table 10-2 shows the four commands implemented by the DMA. Table 10-2. APBH DMA Commands DMA COMMAND 00 01 10 USAGE NO_DMA_XFER. Perform any requested PIO word transfers, but terminate the command before any DMA transfer. DMA_WRITE. Perform any requested PIO word transfers, then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ. Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. DMA_SENSE. Perform any requested PIO word transfers, then perform a conditional branch to the next chained device. Follow the NEXTCMD_ADDR pointer if the peripheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. This command becomes a no-operation for any channel other than a GPMI channel. 11 DMA_WRITE operations copy data bytes to system memory (on-chip RAM or SDRAM) from the associated peripheral. Each peripheral has a target PADDR value that it expects to receive DMA bytes. This association is synthesized in the DMA. The DMA_WRITE transfer uses the BUFFER_ADDDRESS word in the command structure to point to the beginning byte to write data from the peripheral. DMA_READ operations copy data bytes to the APB peripheral from system memory. The DMA engine contains a shared byte aligner that aligns bytes from system memory to or from the peripherals. Peripherals always assume little-endian-aligned data arrives or departs on their 32-bit APB. The DMA_READ transfer uses the BUFFER_ADDRESS word in the command structure to point to the DMA data buffer to be read by the DMA_READ command. The NO_DMA_XFER command is used to write PIO words to a device without performing any DMA data byte transfers. This command is useful in such applications as activating the NAND devices CHECKSTATUS operation. The check status command in the NAND peripheral reads a status byte from the NAND device, performs an XOR and MASK against an expected value supplied as part of the PIO transfer. Once the read check completes (see Section 10.3.1, "NAND Read Status Polling Example,"), the NO_DMA_XFER command completes. The result in the peripheral is that its PSENSE line is driven by the results of the comparison. The sense flip-flop is only updated by CHECKSTATUS for the device that is executed. At some future point, the chain contains a DMA command structure with the fourth and final command value, i.e., the DMA_SENSE command. As each DMA command completes, it triggers the DMA to load the next DMA command structure in the chain. The normal flow list of DMA commands is found by following the NEXTCMD_ADDR pointer in the DMA command structure. The DMA_SENSE command uses the DMA buffer pointer word of the command structure in a slightly different way. Namely, it points to an alternate DMA command structure chain or list. The DMA_SENSE command examines the sense line of the associated peripheral. If the i.MX23 Applications Processor Reference Manual, Rev. 1 10-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA sense line is "true," then the DMA follows the standard list found whose next command is found from the pointer in the NEXTCMD_ADDR word of the command structure. If the sense line is "false," then the DMA follows the alternate list whose next command is found from the pointer in the DMA Buffer Pointer word of the DMA_SENSE command structure (see Figure 10-3). The sense command ignores the CHAIN bit, so that both pointers must be valid when the DMA comes to sense command. If the wait-for-end-command bit (WAIT4ENDCMD) is set in a command structure, then the DMA channel waits for the device to signal completion of a command by toggling the ENDCMCD signal before proceeding to load and execute the next command structure. The semaphore is decremented after the end command is seen. A detailed bit-field view of the DMA command structure is shown in Table 10-3, which shows a field that specifies the number of bytes to be transferred by this DMA command. The transfer-count mechanism is duplicated in the associated peripheral, either as an implied or specified count in the peripheral. Table 10-3. DMA Channel Command Word in System Memory 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 111111111 987654321 NEXT_COMMAND_ADDRESS 1 0 0 9 0 8 0 7 0 6 DECREMENT SEMAPHORE 0 5 0 4 0 3 0 2 0 1 0 0 NANDwAIT4READY IRQ_COMPLETE WAIT4ENDCMD NANDLOCK Number DMA Bytes to Transfer Number PIO Words to Write DMA Buffer or Alternate CCW Zero or More PIO Words to Write to the Associated Peripheral Starting at its Base Address on the APBH Bus Figure 10-3 also shows the CHAIN bit in bit 2 of the second word of the command structure. This bit is set to 1 if the NEXT_COMMAND_ADDRESS contains a pointer to another DMA command structure. If a null pointer (0) is loaded into the NEXT_COMMAND_ADDRESS, it will not be detected by the DMA hardware. Only the CHAIN bit indicates whether a valid list exists beyond the current structure. If the IRQ_COMPLETE bit is set in the command structure, then the last act of the DMA before loading the next command is to set the interrupt status bit corresponding to the current channel. The sticky interrupt request bit in the DMA CSR remains set until cleared by software. It can be used to interrupt the CPU. The NAND_LOCK bit is monitored by the DMA channel arbiter. Once a NAND channel ([7:4]) succeeds in the arbiter with its NAND_LOCK bit set, then the arbiter will ignore the other three NAND channels until a command is completed in which the NAND_LOCK is not set. Notice that the semantic here is that the NAND_LOCK state is to limit scheduling of a non-locked DMA. A DMA channel can go i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice COMMAND CHAIN 10-5 AHB-to-APBH Bridge with DMA from unlocked to locked in the arbiter at the beginning of a command when the NAND_LOCK bit is set. When the last DMA command of an atomic sequence is completed, the lock should be removed. To accomplish this, the last command does not have the NAND_LOCK bit. It is still locked in the atomic state within the arbiter when the command starts, so that it is the only NAND command that can be executed. At the end, it drops from the atomic state within the arbiter. The NAND_WAIT4READY bit also has a special use for DMA channels [7:4], i.e., the NAND device channels. The NAND device supplies a sample of the ready line for the NAND device. This ready value is used to hold off of a command with this bit set until the ready line is asserted to 1. Once the arbiter sees a command with a wait-for-ready set, it holds off that channel until ready is asserted. will continue without waiting for the interrupt. Receiving an IRQ for HALTONTERMINATE (HOT) is a new feature in the APBH/X DMA descriptor that allows certain peripheral block (e.g. GPMI, SSP, I2C) to signal to the DMA engine that an error has occurred. In prior chips, if a block stalled due to an error, the only practical way to discover this in s/w was via a timer of some sort, or to poll the block. Now, an HOT signal is sent from the peripheral to the DMA engine and causes an IRQ after terminating the DMA descriptor being executed. Note not all peripheral block support this termination feature. Therefore, it is recommended that software use this signal as follows: * Always set HALTONTERMINATE to 1 in a DMA descriptor. That way, if a peripheral signals HOT, the transfer will end, leaving the peripheral block and the DMA engine synchronized (but at the end of a command). When an IRQ from an APBH/X channel is received, and the IRQ is determined to be due to an error (as opposed to an IRQONCOMPLETE interrupt) the software should: -- Reset the channel. -- Determine the error from error reporting in the peripheral block, then manage the error in the peripheral that is attached to that channel in whatever appropriate way exists for that device (software recovery, device reset, block reset, etc). * Each channel has an eight-bit counting semaphore that controls whether it is in the run or idle state. When the semaphore is non-zero, the channel is ready to run and process commands and DMA transfers. Whenever a command finishes its DMA transfer, it checks the DECREMENT_SEMAPHORE bit. If set, it decrements the counting semaphore. If the semaphore goes to 0 as a result, then the channel enters the IDLE state and remains there until the semaphore is incremented by software. When the semaphore goes to non-zero and the channel is in its IDLE state, then it uses the value in the HW_APBH_CHn_NXTCMDAR (next command address register) to fetch a pointer to the next command to process. NOTE: This is a double indirect case. This method allows software to append to a running command list under the protection of the counting semaphore. To start processing the first time, software creates the command list to be processed. It writes the address of the first command into the HW_APBH_CHn_NXTCMDAR register, and then writes a 1 to the counting semaphore in HW_APBH_CHn_SEMA. The DMA channel loads HW_APBH_CHn_CURCMDAR i.MX23 Applications Processor Reference Manual, Rev. 1 10-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA register and then enters the normal state machine processing for the next command. When software writes a value to the counting semaphore, it is added to the semaphore count by hardware, protecting the case where both hardware and software are trying to change the semaphore on the same clock edge. Software can examine the value of HW_APBH_CHn_CURCMDAR at any time to determine the location of the command structure currently being processed. 10.3 10.3.1 Implementation Examples NAND Read Status Polling Example Figure 10-3 shows a more complicated scenario. This subset of a NAND device workload shows that the first two command structures are used during the data-write phase of an NAND device write operation (CLE and ALE transfers omitted for clarity). * After writing the data, one must wait until the NAND device status register indicates that the write charge has been transferred. This is built into the workload using a check status command in the NAND in a loop created from the next two DMA command structures. The NO_DMA_TRANSFER command is shown here performing the read check, followed by a DMA_SENSE command to branch the DMA command structure list, based on the status of a bit in the external NAND device. * i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-7 AHB-to-APBH Bridge with DMA 1 PIO, chaining, DMA read NEXTCMD_ADDR 512 1 0 0 1 10 BUFFER ADDRESS ATANAND0= read data No PIO, chaining, DMA read NEXTCMD_ADDR 16 0 0 0 1 10 BUFFER ADDRESS 16-Byte Spare Area 1 PIO, chaining, no DMA, Check NAND status & set sense line NEXTCMD_ADDR 0 1 0 0 1 00 BUFFER ADDRESS ATANAND0= check status No PIO, chaining, no DMA, conditional branch based on sense line NEXTCMD_ADDR 0 0 0 0 1 11 BUFFER ADDRESS 512-Byte Data Block 1 PIO, chaining, DMA read NEXTCMD_ADDR 512 1 0 0 1 10 BUFFER ADDRESS ATANAND0= read data No PIO,IRQ, no chaining, DMA read NEXTCMD_ADDR=0 16 0 0 1 0 10 BUFFER ADDRESS 16-Byte Spare Area 512-Byte Data Block Figure 10-3. AHB-to-APBH Bridge DMA NAND Read Status Polling with DMA Sense Command The example in Figure 10-3 shows the workload continuing immediately to the next NAND page transfer. However, one could perform a second sense operation to see if an error occurred after the write. One could then point the sense command alternate branch at a NO_DMA_XFER command with the interrupt bit set. If the CHAIN bit is not set on this failure branch, then the CPU is interrupted immediately, and the channel process is also immediately terminated in the presence of a workload-detected NAND error bit. Note that each word of the three-word DMA command structure corresponds to a PIO register of the DMA that is accessible on the APBH bus. Normally, the DMA copies the next command structure onto these registers for processing at the start of each command by following the value of the pointer previously loaded into the NEXTCMD_ADDR register. i.MX23 Applications Processor Reference Manual, Rev. 1 10-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA To start DMA processing for the first command, initialize the PIO registers of the desired channel, as follows: * First, load the next command address register with a pointer to the first command to be loaded. * Then, write a 1 to the counting semaphore register. This causes the DMA to schedule the targeted channel for DMA command structure load, as if it just finished its previous command. 10.4 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. 10.5 Programmable Registers This section describes the programmable registers of the AHB-to-APBH bridge block. 10.5.1 AHB to APBH Bridge Control and Status Register 0 Description HW_APBH_CTRL0 HW_APBH_CTRL0_SET HW_APBH_CTRL0_CLR HW_APBH_CTRL0_TOG Table 10-4. HW_APBH_CTRL0 0x000 0x004 0x008 0x00C The APBH CTRL 0 provides overall control of the AHB to APBH bridge and DMA. 3 1 3 0 2 9 AHB_BURST8_EN 2 8 APB_BURST4_EN 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 RESET_CHANNEL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 CLKGATE_CHANNEL 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 FREEZE_CHANNEL 0 3 0 2 0 1 0 0 CLKGATE SFTRST RSVD0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-9 AHB-to-APBH Bridge with DMA Table 10-5. HW_APBH_CTRL0 Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Set this bit to zero to enable normal APBH DMA operation. Set this bit to one (default) to disable clocking with the APBH DMA and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the APBH DMA block to its default state. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. Set this bit to one (default) to enable AHB 8-beat burst. Set to zero to disable 8-beat burst on AHB interface. Set this bit to one (default) to enable apb master do a 4 continous writes when a device request a burst dma. Set to zero will treat a burst dma request as 4 individual request. Reserved, always set to zero. Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state. The bit is reset after the channel resources are cleared. SSP1 = 0x02 SSP2 = 0x04 ATA = 0x10 NAND0 = 0x10 NAND1 = 0x20 NAND2 = 0x40 NAND3 = 0x80 30 29 28 CLKGATE AHB_BURST8_EN APB_BURST4_EN RW 0x1 RW 0x1 RW 0x0 27:24 RSVD0 23:16 RESET_CHANNEL RO 0x000000 RW 0x0 15:8 CLKGATE_CHANNEL RW 0x00 These bit must be set to zero for normal operation of each channel. When set to one they gate off the individual clocks to the channels. SSP1 = 0x02 SSP2 = 0x04 ATA = 0x10 NAND0 = 0x10 NAND1 = 0x20 NAND2 = 0x40 NAND3 = 0x80 7:0 FREEZE_CHANNEL RW 0x0 Setting a bit in this field will freeze the DMA channel associated with it. This field is a direct input to the DMA channel arbiter. When frozen, the channel is denied access to the central DMA resources. SSP1 = 0x02 SSP2 = 0x04 ATA = 0x10 NAND0 = 0x10 NAND1 = 0x20 NAND2 = 0x40 NAND3 = 0x80 DESCRIPTION: This register contains module softreset, clock gating, channel clock gating/freeze bits. EXAMPLE: Empty Example. 10.5.2 AHB to APBH Bridge Control and Status Register 1 Description The APBH CTRL one provides overall control of the interrupts generated by the AHB to APBH DMA. i.MX23 Applications Processor Reference Manual, Rev. 1 10-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA HW_APBH_CTRL1 HW_APBH_CTRL1_SET HW_APBH_CTRL1_CLR HW_APBH_CTRL1_TOG Table 10-6. HW_APBH_CTRL1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 CH7_CMDCMPLT_IRQ_EN 2 2 CH6_CMDCMPLT_IRQ_EN 2 1 CH5_CMDCMPLT_IRQ_EN 2 0 CH4_CMDCMPLT_IRQ_EN 1 9 CH3_CMDCMPLT_IRQ_EN 1 8 CH2_CMDCMPLT_IRQ_EN 1 7 CH1_CMDCMPLT_IRQ_EN 1 6 CH0_CMDCMPLT_IRQ_EN 1 5 1 4 1 3 1 2 1 1 1 0 0x010 0x014 0x018 0x01C 0 9 0 8 0 7 CH7_CMDCMPLT_IRQ 0 6 CH6_CMDCMPLT_IRQ 0 5 CH5_CMDCMPLT_IRQ 0 4 CH4_CMDCMPLT_IRQ 0 3 CH3_CMDCMPLT_IRQ 0 2 CH2_CMDCMPLT_IRQ 0 1 CH1_CMDCMPLT_IRQ 0 0 CH0_CMDCMPLT_IRQ RSVD1 Table 10-7. HW_APBH_CTRL1 Bit Field Descriptions BITS LABEL 31:24 RSVD1 CH7_CMDCMPLT_IRQ_EN 23 RW RESET RO 0x00000000 RW 0x0 DEFINITION Reserved, always set to zero. Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. Reserved, always set to zero. Interrupt request status bit for APBH DMA channel 7. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBH DMA channel 6. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBH DMA channel 5. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 22 21 20 19 18 17 16 15:8 7 CH6_CMDCMPLT_IRQ_EN CH5_CMDCMPLT_IRQ_EN CH4_CMDCMPLT_IRQ_EN CH3_CMDCMPLT_IRQ_EN CH2_CMDCMPLT_IRQ_EN CH1_CMDCMPLT_IRQ_EN CH0_CMDCMPLT_IRQ_EN RSVD0 CH7_CMDCMPLT_IRQ RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RO 0x00000000 RW 0x0 6 CH6_CMDCMPLT_IRQ RW 0x0 5 CH5_CMDCMPLT_IRQ RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD0 10-11 AHB-to-APBH Bridge with DMA Table 10-7. HW_APBH_CTRL1 Bit Field Descriptions BITS LABEL 4 CH4_CMDCMPLT_IRQ RW RESET RW 0x0 DEFINITION Interrupt request status bit for APBH DMA channel 4. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBH DMA channel 3. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBH DMA channel 2. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBH DMA channel 1. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBH DMA channel 0. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 3 CH3_CMDCMPLT_IRQ RW 0x0 2 CH2_CMDCMPLT_IRQ RW 0x0 1 CH1_CMDCMPLT_IRQ RW 0x0 0 CH0_CMDCMPLT_IRQ RW 0x0 DESCRIPTION: This register contains the per channel interrupt status bits and the per channel interrupt enable bits. Each channel has a dedicated interrupt vector in the vectored interrupt controller. EXAMPLE: BF_WR(APBH_CTRL1, CH5_CMDCMPLT_IRQ, 0); // use bitfield write macro BF_APBH_CTRL1.CH5_CMDCMPLT_IRQ = 0; // or, assign to register struct's bitfield 10.5.3 AHB to APBH Bridge Control and Status Register 2 Description HW_APBH_CTRL2 HW_APBH_CTRL2_SET HW_APBH_CTRL2_CLR HW_APBH_CTRL2_TOG Table 10-8. HW_APBH_CTRL2 0x020 0x024 0x028 0x02C The APBH CTRL 2 provides channel error interrupts generated by the AHB to APBH DMA. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 CH7_ERROR_STATUS 2 2 CH6_ERROR_STATUS 2 1 CH5_ERROR_STATUS 2 0 CH4_ERROR_STATUS 1 9 CH3_ERROR_STATUS 1 8 CH2_ERROR_STATUS 1 7 CH1_ERROR_STATUS 1 6 CH0_ERROR_STATUS 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 CH7_ERROR_IRQ 0 6 CH6_ERROR_IRQ 0 5 CH5_ERROR_IRQ 0 4 CH4_ERROR_IRQ 0 3 CH3_ERROR_IRQ 0 2 CH2_ERROR_IRQ 0 1 CH1_ERROR_IRQ 0 0 CH0_ERROR_IRQ RSVD1 i.MX23 Applications Processor Reference Manual, Rev. 1 10-12 Preliminary--Subject to Change Without Notice RSVD0 Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-9. HW_APBH_CTRL2 Bit Field Descriptions BITS LABEL 31:24 RSVD1 CH7_ERROR_STATUS 23 RW RESET RO 0x00000000 RO 0x0 DEFINITION Reserved, always set to zero. Error status bit for APBX DMA Channel 7. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 22 CH6_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 6. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 21 CH5_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 5. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 20 CH4_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 4. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 19 CH3_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 3. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 18 CH2_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 2. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 17 CH1_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 1. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 16 CH0_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 0. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 15:8 RSVD0 RO 0x00000000 Reserved, always set to zero. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-13 AHB-to-APBH Bridge with DMA Table 10-9. HW_APBH_CTRL2 Bit Field Descriptions BITS LABEL 7 CH7_ERROR_IRQ RW RESET RW 0x0 DEFINITION Error interrupt status bit for APBX DMA Channel 7. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 6. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 5. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 4. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 3. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 2. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 1. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 0. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 6 CH6_ERROR_IRQ RW 0x0 5 CH5_ERROR_IRQ RW 0x0 4 CH4_ERROR_IRQ RW 0x0 3 CH3_ERROR_IRQ RW 0x0 2 CH2_ERROR_IRQ RW 0x0 1 CH1_ERROR_IRQ RW 0x0 0 CH0_ERROR_IRQ RW 0x0 DESCRIPTION: This register contains the per channel interrupt status bits and the per channel interrupt enable bits. Each channel has a dedicated interrupt vector in the vectored interrupt controller. EXAMPLE: BF_WR(APBH_CTRL1, CH5_CMDCMPLT_IRQ, 0); // use bitfield write macro BF_APBH_CTRL1.CH5_CMDCMPLT_IRQ = 0; // or, assign to register struct's bitfield 10.5.4 AHB to APBH DMA Device Assignment Register Description HW_APBH_DEVSEL 0x030 This register allows reassignment of the APBH device connected to the DMA Channels. i.MX23 Applications Processor Reference Manual, Rev. 1 10-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-10. HW_APBH_DEVSEL 3 1 3 0 CH7 2 9 2 8 2 7 2 6 CH6 2 5 2 4 2 3 2 2 CH5 2 1 2 0 1 9 1 8 CH4 1 7 1 6 1 5 1 4 CH3 1 3 1 2 1 1 1 0 CH2 0 9 0 8 0 7 0 6 CH1 0 5 0 4 0 3 0 2 CH0 0 5 0 4 0 3 0 2 0 1 0 0 0 1 0 0 Table 10-11. HW_APBH_DEVSEL Bit Field Descriptions BITS 31:28 27:24 23:20 19:16 15:12 11:8 7:4 3:0 LABEL CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 RW RO RO RO RO RO RO RO RO RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 DEFINITION Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. DESCRIPTION: This register contains channel mux sel bits. N/A for apbh bridge dma. EXAMPLE: Empty Example. 10.5.5 APBH DMA Channel 0 Current Command Address Register Description The APBH DMA channel 0 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBH_CH0_CURCMDAR 0x040 Table 10-12. HW_APBH_CH0_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 CMD_ADDR Table 10-13. HW_APBH_CH0_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 0. DESCRIPTION: APBH DMA Channel 0 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-15 AHB-to-APBH Bridge with DMA EXAMPLE: Empty Example. 10.5.6 APBH DMA Channel 0 Next Command Address Register Description The APBH DMA Channel 0 Next Command Address register contains the address of the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to 1 in the DMA command word to process command lists. HW_APBH_CH0_NXTCMDAR 0x050 Table 10-14. HW_APBH_CH0_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-15. HW_APBH_CH0_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 0. DESCRIPTION: APBH DMA Channel 0 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 0 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty Example. 10.5.7 APBH DMA Channel 0 Command Register Description The APBH DMA Channel 0 command register specifies the DMA transaction to perform for the current command chain item. HW_APBH_CH0_CMD Table 10-16. HW_APBH_CH0_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 NANDWAIT4READY 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 0x060 SEMAPHORE CMDWORDS NANDLOCK i.MX23 Applications Processor Reference Manual, Rev. 1 10-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor COMMAND RSVD1 CHAIN AHB-to-APBH Bridge with DMA Table 10-17. HW_APBH_CH0_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the DMA device, starting with the base PIO address of the DMA device register and incrementing from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. A value of one indicates that the ATA/NAND DMA channel will will wait until the ATA/NAND device reports 'ready' before executing the command. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the ATA/NAND DMA channel will remain "locked" in the arbiter at the expense of other ATA/NAND DMA channels. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5 NANDWAIT4READY RO 0x0 4 NANDLOCK RO 0x0 3 IRQONCMPLT RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-17 AHB-to-APBH Bridge with DMA Table 10-17. HW_APBH_CH0_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH0_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers 10- Read transfer 11- SENSE NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. DMA_SENSE = 0x3 Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty Example. 10.5.8 APBH DMA Channel 0 Buffer Address Register Description The APBH DMA Channel 0 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBH_CH0_BAR Table 10-18. HW_APBH_CH0_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x070 ADDRESS Table 10-19. HW_APBH_CH0_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 10-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty Example. 10.5.9 APBH DMA Channel 0 Semaphore Register Description The APBH DMA Channel 0 semaphore register is used to synchronize the CPU instruction stream and the DMA chain processing state. HW_APBH_CH0_SEMA Table 10-20. HW_APBH_CH0_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x080 PHORE RSVD2 Table 10-21. HW_APBH_CH0_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 10-19 AHB-to-APBH Bridge with DMA EXAMPLE: Empty Example. 10.5.10 AHB to APBH DMA Channel 0 Debug Information Description This register gives debug visibility into the APBH DMA Channel 0 state machine and controls. HW_APBH_CH0_DEBUG1 Table 10-22. HW_APBH_CH0_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 0x090 RD_FIFO_FULL READY BURST SENSE Table 10-23. HW_APBH_CH0_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device This bit is reserved for this DMA Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device This bit is reserved for this DMA Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device This bit is reserved for this Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the DMA Channel Lock for a GPMI Channel. This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. 30 29 28 27 BURST KICK END SENSE RO 0x0 RO 0x0 RO 0x0 RO 0x0 26 READY RO 0x0 25 LOCK RO 0x0 24 23 22 21 NEXTCMDADDRVALID RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY RO 0x0 RO 0x1 RO 0x0 RO 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 10-20 Preliminary--Subject to Change Without Notice RSVD1 LOCK KICK REQ END Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-23. HW_APBH_CH0_DEBUG1 Bit Field Descriptions BITS LABEL 20 WR_FIFO_FULL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 0 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 19:5 4:0 RSVD1 STATEMACHINE RO 0x0 RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 0. EXAMPLE: Empty example. 10.5.11 AHB to APBH DMA Channel 0 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 0. HW_APBH_CH0_DEBUG2 0x0A0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-21 AHB-to-APBH Bridge with DMA Table 10-24. HW_APBH_CH0_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 10-25. HW_APBH_CH0_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 0. EXAMPLE: Empty example. 10.5.12 APBH DMA Channel 1 Current Command Address Register Description The APBH DMA Channel 1 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBH_CH1_CURCMDAR 0x0B0 Table 10-26. HW_APBH_CH1_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-27. HW_APBH_CH1_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 1. DESCRIPTION: APBH DMA Channel 1 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 10-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA EXAMPLE: pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR_RD(1); // read the whole register, since there is only one field pCurCmd = (hw_apbh_chn_cmd_t *) BF_RDn(APBH_CHn_CURCMDAR, 1, CMD_ADDR); // or, use multi-register bitfield read macro pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR(1).CMD_ADDR; // or, assign from bitfield of indexed register's struct 10.5.13 APBH DMA Channel 1 Next Command Address Register Description The APBH DMA Channel 1 Next Command Address register contains the address of the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to 1 in the DMA command word to process command lists. HW_APBH_CH1_NXTCMDAR 0x0C0 Table 10-28. HW_APBH_CH1_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-29. HW_APBH_CH1_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 1. DESCRIPTION: APBH DMA Channel 1 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 1 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: HW_APBH_CHn_NXTCMDAR_WR(1, (reg32_t) pCommandTwoStructure); // write the entire register, since there is only one field BF_WRn(APBH_CHn_NXTCMDAR, 1, (reg32_t) pCommandTwoStructure); // or, use multi-register bitfield write macro HW_APBH_CHn_NXTCMDAR(1).CMD_ADDR = (reg32_t) pCommandTwoStructure; // or, assign to bitfield of indexed register's struct 10.5.14 APBH DMA Channel 1 Command Register Description The APBH DMA Channel 1 command register specifies the cycle to perform for the current command chain item. HW_APBH_CH1_CMD 0x0D0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-23 AHB-to-APBH Bridge with DMA Table 10-30. HW_APBH_CH1_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 NANDWAIT4READY 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 SEMAPHORE CMDWORDS NANDLOCK Table 10-31. HW_APBH_CH1_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SSP1 device. A value of 0 indicates a 64 KBytes trasnfer size. This field indicates the number of command words to send to the SSP1, starting with the base PIO address of the SSP1 control register and incrementing from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. A value of one indicates that the ATA/NAND DMA channel will will wait until the ATA/NAND device reports 'ready' before execute the command. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the ATA/NAND DMA channel will remain "locked" in the arbiter at the expense of other ATA/NAND DMA channels. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5 NANDWAIT4READY RO 0x0 4 NANDLOCK RO 0x0 3 IRQONCMPLT RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 10-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor COMMAND RSVD1 CHAIN AHB-to-APBH Bridge with DMA Table 10-31. HW_APBH_CH1_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH1_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, i.e. data sent from the SSP1 (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. DMA_SENSE = 0x3 Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty Example. 10.5.15 APBH DMA Channel 1 Buffer Address Register Description The APBH DMA Channel 1 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBH_CH1_BAR Table 10-32. HW_APBH_CH1_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0E0 ADDRESS Table 10-33. HW_APBH_CH1_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-25 AHB-to-APBH Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: hw_apbh_chn_bar_t dma_data; dma_data.ADDRESS = (reg32_t) pDataBuffer; 10.5.16 APBH DMA Channel 1 Semaphore Register Description The APBH DMA Channel 1 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBH_CH1_SEMA Table 10-34. HW_APBH_CH1_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x0F0 PHORE RSVD2 Table 10-35. HW_APBH_CH1_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 10-26 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBH Bridge with DMA EXAMPLE: BF_WR(APBH_CHn_SEMA, 1, INCREMENT_SEMA, 2); // increment semaphore by two current_sema = BF_RD(APBH_CHn_SEMA, 1, PHORE); // get instantaneous value 10.5.17 AHB to APBH DMA Channel 1 Debug Information Description This register gives debug visibility into the APBH DMA Channel 1 state machine and controls. HW_APBH_CH1_DEBUG1 Table 10-36. HW_APBH_CH1_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 0x100 RD_FIFO_FULL READY BURST SENSE Table 10-37. HW_APBH_CH1_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device This bit is reserved for this DMA Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device This bit is reserved for this DMA Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device This bit is reserved for this Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the DMA Channel Lock for a GPMI Channel. This bit reflect the internal bit which indicates whether the channel's next command address is valid. This bit reflect the current state of the DMA Channel's Read FIFO Empty signal. This bit reflect the current state of the DMA Channel's Read FIFO Full signal. This bit reflect the current state of the DMA Channel's Write FIFO Empty signal. 30 29 28 27 BURST KICK END SENSE RO 0x0 RO 0x0 RO 0x0 RO 0x0 26 READY RO 0x0 25 LOCK RO 0x0 24 23 22 21 NEXTCMDADDRVALID RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY RO 0x0 RO 0x1 RO 0x0 RO 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 LOCK KICK REQ END 10-27 AHB-to-APBH Bridge with DMA Table 10-37. HW_APBH_CH1_DEBUG1 Bit Field Descriptions BITS LABEL 20 WR_FIFO_FULL RW RESET RO 0x0 DEFINITION This bit reflect the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 1 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 19:5 4:0 RSVD1 STATEMACHINE RO 0x0 RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 1. EXAMPLE: Empty example. 10.5.18 AHB to APBH DMA Channel 1 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 1. HW_APBH_CH1_DEBUG2 0x110 i.MX23 Applications Processor Reference Manual, Rev. 1 10-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-38. HW_APBH_CH1_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 10-39. HW_APBH_CH1_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 1. EXAMPLE: Empty example. 10.5.19 APBH DMA Channel 2 Current Command Address Register Description The APBH DMA Channel 2 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBH_CH2_CURCMDAR 0x120 Table 10-40. HW_APBH_CH2_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-41. HW_APBH_CH2_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 2. DESCRIPTION: APBH DMA Channel 2 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-29 AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.20 APBH DMA Channel 2 Next Command Address Register Description The APBH DMA Channel 2 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBH_CH2_NXTCMDAR 0x130 Table 10-42. HW_APBH_CH2_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-43. HW_APBH_CH2_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 2. DESCRIPTION: APBH DMA Channel 2 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 0 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty Example. 10.5.21 APBH DMA Channel 2 Command Register Description The APBH DMA Channel 2 command register specifies the cycle to perform for the current command chain item. HW_APBH_CH2_CMD Table 10-44. HW_APBH_CH2_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 NANDWAIT4READY 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 0x140 SEMAPHORE CMDWORDS NANDLOCK i.MX23 Applications Processor Reference Manual, Rev. 1 10-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor COMMAND RSVD1 CHAIN AHB-to-APBH Bridge with DMA Table 10-45. HW_APBH_CH2_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SSP2 device. A value of 0 indicates a 64 KBytes transfer size. This field contains the number of command words to send to the SSP2, starting with the base PIO address of the SSP2 control register and incrementing from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. A value of one indicates that the ATA/NAND DMA channel will will wait until the ATA/NAND device reports 'ready' before execute the command. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the ATA/NAND DMA channel will remain "locked" in the arbiter at the expense of other ATA/NAND DMA channels. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5 NANDWAIT4READY RO 0x0 4 NANDLOCK RO 0x0 3 IRQONCMPLT RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-31 AHB-to-APBH Bridge with DMA Table 10-45. HW_APBH_CH2_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH2_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, i.e. data sent from the APBH Device (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. DMA_SENSE = 0x3 Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 10.5.22 APBH DMA Channel 2 Buffer Address Register Description The APBH DMA Channel 2 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBH_CH2_BAR Table 10-46. HW_APBH_CH2_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x150 ADDRESS Table 10-47. HW_APBH_CH2_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 10-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 10.5.23 APBH DMA Channel 2 Semaphore Register Description The APBH DMA Channel 2 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBH_CH2_SEMA Table 10-48. HW_APBH_CH2_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x160 PHORE RSVD2 Table 10-49. HW_APBH_CH2_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 10-33 AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.24 AHB to APBH DMA Channel 2 Debug Information Description This register gives debug visibility into the APBH DMA Channel 2 state machine and controls. HW_APBH_CH2_DEBUG1 Table 10-50. HW_APBH_CH2_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 0x170 RD_FIFO_FULL READY BURST SENSE Table 10-51. HW_APBH_CH2_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device This bit is reserved for this DMA Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device This bit is reserved for this DMA Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device This bit is reserved for this Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the DMA Channel Lock for a GPMI Channel. This bit reflect the internal bit which indicates whether the channel's next command address is valid. This bit reflect the current state of the DMA Channel's Read FIFO Empty signal. This bit reflect the current state of the DMA Channel's Read FIFO Full signal. This bit reflect the current state of the DMA Channel's Write FIFO Empty signal. 30 29 28 27 BURST KICK END SENSE RO 0x0 RO 0x0 RO 0x0 RO 0x0 26 READY RO 0x0 25 LOCK RO 0x0 24 23 22 21 NEXTCMDADDRVALID RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY RO 0x0 RO 0x1 RO 0x0 RO 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 10-34 Preliminary--Subject to Change Without Notice RSVD1 LOCK KICK REQ END Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-51. HW_APBH_CH2_DEBUG1 Bit Field Descriptions BITS LABEL 20 WR_FIFO_FULL RW RESET RO 0x0 DEFINITION This bit reflect the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 2 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 19:5 4:0 RSVD1 STATEMACHINE RO 0x0 RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 2. EXAMPLE: Empty example. 10.5.25 AHB to APBH DMA Channel 2 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 2. HW_APBH_CH2_DEBUG2 0x180 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-35 AHB-to-APBH Bridge with DMA Table 10-52. HW_APBH_CH2_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 10-53. HW_APBH_CH2_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 2. EXAMPLE: Empty example. 10.5.26 APBH DMA Channel 3 Current Command Address Register Description The APBH DMA Channel 3 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBH_CH3_CURCMDAR 0x190 Table 10-54. HW_APBH_CH3_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-55. HW_APBH_CH3_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 3. DESCRIPTION: APBH DMA Channel 3 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 10-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.27 APBH DMA Channel 3 Next Command Address Register Description The APBH DMA Channel 3 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBH_CH3_NXTCMDAR 0x1A0 Table 10-56. HW_APBH_CH3_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-57. HW_APBH_CH3_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 3. DESCRIPTION: APBH DMA Channel 3 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 3 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 10.5.28 APBH DMA Channel 3 Command Register Description The APBH DMA Channel 3 command register specifies the cycle to perform for the current command chain item. HW_APBH_CH3_CMD Table 10-58. HW_APBH_CH3_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 NANDWAIT4READY 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 0x1B0 SEMAPHORE CMDWORDS NANDLOCK i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice COMMAND RSVD1 CHAIN 10-37 AHB-to-APBH Bridge with DMA Table 10-59. HW_APBH_CH3_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device egister. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the DMA device, starting with the base PIO address of the DMA device and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. A value of one indicates that the ATA/NAND DMA channel will will wait until the ATA/NAND device reports 'ready' before execute the command. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the ATA/NAND DMA channel will remain "locked" in the arbiter at the expense of other ATA/NAND DMA channels. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5 NANDWAIT4READY RO 0x0 4 NANDLOCK RO 0x0 3 IRQONCMPLT RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 10-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-59. HW_APBH_CH3_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH3_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, i.e. data sent from the APBH device (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. DMA_SENSE = 0x3 Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 10.5.29 APBH DMA Channel 3 Buffer Address Register Description The APBH DMA Channel 3 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBH_CH3_BAR Table 10-60. HW_APBH_CH3_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x1C0 ADDRESS Table 10-61. HW_APBH_CH3_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-39 AHB-to-APBH Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 10.5.30 APBH DMA Channel 3 Semaphore Register Description The APBH DMA Channel 3 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBH_CH3_SEMA Table 10-62. HW_APBH_CH3_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x1D0 PHORE RSVD2 Table 10-63. HW_APBH_CH3_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 10-40 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.31 AHB to APBH DMA Channel 3 Debug Information Description This register gives debug visibility into the APBH DMA Channel 3 state machine and controls. HW_APBH_CH3_DEBUG1 Table 10-64. HW_APBH_CH3_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 0x1E0 RD_FIFO_FULL READY BURST SENSE Table 10-65. HW_APBH_CH3_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device This bit is reserved for this DMA Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device This bit is reserved for this DMA Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device This bit is reserved for this Channel and always reads 0. For Channels 4-7, this bit reflects the current state of the DMA Channel Lock for a GPMI Channel. This bit reflect the internal bit which indicates whether the channel's next command address is valid. This bit reflect the current state of the DMA Channel's Read FIFO Empty signal. This bit reflect the current state of the DMA Channel's Read FIFO Full signal. This bit reflect the current state of the DMA Channel's Write FIFO Empty signal. 30 29 28 27 BURST KICK END SENSE RO 0x0 RO 0x0 RO 0x0 RO 0x0 26 READY RO 0x0 25 LOCK RO 0x0 24 23 22 21 NEXTCMDADDRVALID RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY RO 0x0 RO 0x0 RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 LOCK KICK REQ END 10-41 AHB-to-APBH Bridge with DMA Table 10-65. HW_APBH_CH3_DEBUG1 Bit Field Descriptions BITS LABEL 20 WR_FIFO_FULL RW RESET RO 0x0 DEFINITION This bit reflect the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 3 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 19:5 4:0 RSVD1 STATEMACHINE RO 0x0 RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 3. EXAMPLE: Empty example. 10.5.32 AHB to APBH DMA Channel 3 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 3. HW_APBH_CH3_DEBUG2 0x1F0 i.MX23 Applications Processor Reference Manual, Rev. 1 10-42 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-66. HW_APBH_CH3_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 10-67. HW_APBH_CH3_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 3. EXAMPLE: Empty example. 10.5.33 APBH DMA Channel 4 Current Command Address Register Description The APBH DMA Channel 4 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBH_CH4_CURCMDAR 0x200 Table 10-68. HW_APBH_CH4_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-69. HW_APBH_CH4_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 4. DESCRIPTION: APBH DMA Channel 4 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-43 AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.34 APBH DMA Channel 4 Next Command Address Register Description The APBH DMA Channel 4 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBH_CH4_NXTCMDAR 0x210 Table 10-70. HW_APBH_CH4_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-71. HW_APBH_CH4_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 4. DESCRIPTION: APBH DMA Channel 4 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 4 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 10.5.35 APBH DMA Channel 4 Command Register Description The APBH DMA Channel 4 command register specifies the cycle to perform for the current command chain item. HW_APBH_CH4_CMD Table 10-72. HW_APBH_CH4_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 NANDWAIT4READY 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 0x220 SEMAPHORE CMDWORDS NANDLOCK i.MX23 Applications Processor Reference Manual, Rev. 1 10-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor COMMAND RSVD1 CHAIN AHB-to-APBH Bridge with DMA Table 10-73. HW_APBH_CH4_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI ATANAND_0 device HW_GPMI_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the GPMI, starting with the base PIO address of the GPMI (HW_GPMI_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. A value of one indicates that the ATA/NAND DMA channel will will wait until the ATA/NAND device reports 'ready' before execute the command. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the ATA/NAND DMA channel will remain "locked" in the arbiter at the expense of other ATA/NAND DMA channels. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5 NANDWAIT4READY RO 0x0 4 NANDLOCK RO 0x0 3 IRQONCMPLT RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-45 AHB-to-APBH Bridge with DMA Table 10-73. HW_APBH_CH4_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH4_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, i.e. data sent from the GPMI (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. DMA_SENSE = 0x3 Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 10.5.36 APBH DMA Channel 4 Buffer Address Register Description The APBH DMA Channel 1 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBH_CH4_BAR Table 10-74. HW_APBH_CH4_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x230 ADDRESS Table 10-75. HW_APBH_CH4_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 10-46 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 10.5.37 APBH DMA Channel 4 Semaphore Register Description The APBH DMA Channel 4 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBH_CH4_SEMA Table 10-76. HW_APBH_CH4_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x240 PHORE RSVD2 Table 10-77. HW_APBH_CH4_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 10-47 AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.38 AHB to APBH DMA Channel 4 Debug Information Description This register gives debug visibility into the APBH DMA Channel 4 state machine and controls. HW_APBH_CH4_DEBUG1 Table 10-78. HW_APBH_CH4_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 0x250 RD_FIFO_FULL READY BURST SENSE Table 10-79. HW_APBH_CH4_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 27 26 25 24 23 22 21 20 BURST KICK END SENSE READY LOCK NEXTCMDADDRVALID RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 10-48 Preliminary--Subject to Change Without Notice RSVD1 LOCK KICK REQ END Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-79. HW_APBH_CH4_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 4 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. WAIT_READY = 0x1F When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 4. EXAMPLE: Empty example. 10.5.39 AHB to APBH DMA Channel 4 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 4. HW_APBH_CH4_DEBUG2 0x260 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-49 AHB-to-APBH Bridge with DMA Table 10-80. HW_APBH_CH4_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 10-81. HW_APBH_CH4_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 4. EXAMPLE: Empty example. 10.5.40 APBH DMA Channel 5 Current Command Address Register Description The APBH DMA Channel 5 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBH_CH5_CURCMDAR 0x270 Table 10-82. HW_APBH_CH5_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-83. HW_APBH_CH5_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 5. DESCRIPTION: APBH DMA Channel 5 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 10-50 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.41 APBH DMA Channel 5 Next Command Address Register Description The APBH DMA Channel 5 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBH_CH5_NXTCMDAR 0x280 Table 10-84. HW_APBH_CH5_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-85. HW_APBH_CH5_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 5. DESCRIPTION: APBH DMA Channel 5 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 5 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 10.5.42 APBH DMA Channel 5 Command Register Description The APBH DMA Channel 5 command register specifies the cycle to perform for the current command chain item. HW_APBH_CH5_CMD Table 10-86. HW_APBH_CH5_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 NANDWAIT4READY 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 0x290 SEMAPHORE CMDWORDS NANDLOCK i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice COMMAND RSVD1 CHAIN 10-51 AHB-to-APBH Bridge with DMA Table 10-87. HW_APBH_CH5_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI ATANAND_1 device HW_GPMI_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the GPMI, starting with the base PIO address of the GPMI (HW_GPMI_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. A value of one indicates that the ATA/NAND DMA channel will will wait until the ATA/NAND device reports 'ready' before execute the command. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the ATA/NAND DMA channel will remain "locked" in the arbiter at the expense of other ATA/NAND DMA channels. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5 NANDWAIT4READY RO 0x0 4 NANDLOCK RO 0x0 3 IRQONCMPLT RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 10-52 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-87. HW_APBH_CH5_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH5_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, i.e. data sent from the GPMI (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. DMA_SENSE = 0x3 Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 10.5.43 APBH DMA Channel 5 Buffer Address Register Description The APBH DMA Channel 5 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBH_CH5_BAR Table 10-88. HW_APBH_CH5_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x2A0 ADDRESS Table 10-89. HW_APBH_CH5_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-53 AHB-to-APBH Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 10.5.44 APBH DMA Channel 5 Semaphore Register Description The APBH DMA Channel 5 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBH_CH5_SEMA Table 10-90. HW_APBH_CH5_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x2B0 PHORE RSVD2 Table 10-91. HW_APBH_CH5_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 10-54 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.45 AHB to APBH DMA Channel 5 Debug Information Description This register gives debug visibility into the APBH DMA Channel 5 state machine and controls. HW_APBH_CH5_DEBUG1 Table 10-92. HW_APBH_CH5_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 0x2C0 RD_FIFO_FULL READY BURST SENSE Table 10-93. HW_APBH_CH5_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 27 26 25 24 23 22 21 20 BURST KICK END SENSE READY LOCK NEXTCMDADDRVALID RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 LOCK KICK REQ END 10-55 AHB-to-APBH Bridge with DMA Table 10-93. HW_APBH_CH5_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 5 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. WAIT_READY = 0x1F When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 5. EXAMPLE: Empty example. 10.5.46 AHB to APBH DMA Channel 5 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 5. HW_APBH_CH5_DEBUG2 0x2D0 i.MX23 Applications Processor Reference Manual, Rev. 1 10-56 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-94. HW_APBH_CH5_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 10-95. HW_APBH_CH5_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 5. EXAMPLE: Empty example. 10.5.47 APBH DMA Channel 6 Current Command Address Register Description The APBH DMA Channel 6 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBH_CH6_CURCMDAR 0x2E0 Table 10-96. HW_APBH_CH6_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-97. HW_APBH_CH6_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 6. DESCRIPTION: APBH DMA Channel 6 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-57 AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.48 APBH DMA Channel 6 Next Command Address Register Description The APBH DMA Channel 6 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBH_CH6_NXTCMDAR 0x2F0 Table 10-98. HW_APBH_CH6_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-99. HW_APBH_CH6_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 6. DESCRIPTION: APBH DMA Channel 6 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 6 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 10.5.49 APBH DMA Channel 6 Command Register Description The APBH DMA Channel 6 command register specifies the cycle to perform for the current command chain item. HW_APBH_CH6_CMD Table 10-100. HW_APBH_CH6_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 NANDWAIT4READY 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 0x300 SEMAPHORE CMDWORDS NANDLOCK i.MX23 Applications Processor Reference Manual, Rev. 1 10-58 Preliminary--Subject to Change Without Notice Freescale Semiconductor COMMAND RSVD1 CHAIN AHB-to-APBH Bridge with DMA Table 10-101. HW_APBH_CH6_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI ATANAND_2 device HW_GPMI_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the GPMI, starting with the base PIO address of the GPMI (HW_GPMI_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. A value of one indicates that the ATA/NAND DMA channel will will wait until the ATA/NAND device reports 'ready' before execute the command. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the ATA/NAND DMA channel will remain "locked" in the arbiter at the expense of other ATA/NAND DMA channels. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5 NANDWAIT4READY RO 0x0 4 NANDLOCK RO 0x0 3 IRQONCMPLT RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-59 AHB-to-APBH Bridge with DMA Table 10-101. HW_APBH_CH6_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH6_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, i.e. data sent from the GPMI (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. DMA_SENSE = 0x3 Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 10.5.50 APBH DMA Channel 6 Buffer Address Register Description The APBH DMA Channel 6 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBH_CH6_BAR Table 10-102. HW_APBH_CH6_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x310 ADDRESS Table 10-103. HW_APBH_CH6_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 10-60 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 10.5.51 APBH DMA Channel 6 Semaphore Register Description The APBH DMA Channel 6 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBH_CH6_SEMA Table 10-104. HW_APBH_CH6_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x320 PHORE RSVD2 Table 10-105. HW_APBH_CH6_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 10-61 AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.52 AHB to APBH DMA Channel 6 Debug Information Description This register gives debug visibility into the APBH DMA Channel 6 state machine and controls. HW_APBH_CH6_DEBUG1 0x330 Table 10-106. HW_APBH_CH6_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL READY BURST SENSE Table 10-107. HW_APBH_CH6_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 27 26 25 24 23 22 21 20 BURST KICK END SENSE READY LOCK NEXTCMDADDRVALID RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 10-62 Preliminary--Subject to Change Without Notice RSVD1 LOCK KICK REQ END Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-107. HW_APBH_CH6_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 6 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. WAIT_READY = 0x1F When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 6. EXAMPLE: Empty example. 10.5.53 AHB to APBH DMA Channel 6 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 6. HW_APBH_CH6_DEBUG2 0x340 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-63 AHB-to-APBH Bridge with DMA Table 10-108. HW_APBH_CH6_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 10-109. HW_APBH_CH6_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 6. EXAMPLE: Empty example. 10.5.54 APBH DMA Channel 7 Current Command Address Register Description The APBH DMA Channel 7 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBH_CH7_CURCMDAR 0x350 Table 10-110. HW_APBH_CH7_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-111. HW_APBH_CH7_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 7. DESCRIPTION: APBH DMA Channel 7 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 10-64 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.55 APBH DMA Channel 7 Next Command Address Register Description The APBH DMA Channel 7 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBH_CH7_NXTCMDAR 0x360 Table 10-112. HW_APBH_CH7_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 10-113. HW_APBH_CH7_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 7. DESCRIPTION: APBH DMA Channel 7 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 7 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 10.5.56 APBH DMA Channel 7 Command Register Description The APBH DMA Channel 7 command register specifies the cycle to perform for the current command chain item. HW_APBH_CH7_CMD Table 10-114. HW_APBH_CH7_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 NANDWAIT4READY 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 0x370 SEMAPHORE CMDWORDS NANDLOCK i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice COMMAND RSVD1 CHAIN 10-65 AHB-to-APBH Bridge with DMA Table 10-115. HW_APBH_CH7_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI ATANAND_3 device HW_GPMI_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the GPMI, starting with the base PIO address of the GPMI (HW_GPMI_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. A value of one indicates that the ATA/NAND DMA channel will will wait until the ATA/NAND device reports 'ready' before execute the command. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the ATA/NAND DMA channel will remain "locked" in the arbiter at the expense of other ATA/NAND DMA channels. It is ignored for non-ATA/NAND DMA channels. A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5 NANDWAIT4READY RO 0x0 4 NANDLOCK RO 0x0 3 IRQONCMPLT RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 10-66 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-115. HW_APBH_CH7_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH7_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, i.e. data sent from the GPMI (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. DMA_SENSE = 0x3 Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 10.5.57 APBH DMA Channel 7 Buffer Address Register Description The APBH DMA Channel 7 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBH_CH7_BAR Table 10-116. HW_APBH_CH7_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x380 ADDRESS Table 10-117. HW_APBH_CH7_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-67 AHB-to-APBH Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 10.5.58 APBH DMA Channel 7 Semaphore Register Description The APBH DMA Channel 7 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBH_CH7_SEMA Table 10-118. HW_APBH_CH7_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x390 PHORE RSVD2 Table 10-119. HW_APBH_CH7_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 10-68 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBH Bridge with DMA EXAMPLE: Empty example. 10.5.59 AHB to APBH DMA Channel 7 Debug Information Description This register gives debug visibility into the APBH DMA Channel 7 state machine and controls. HW_APBH_CH7_DEBUG1 0x3A0 Table 10-120. HW_APBH_CH7_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL READY BURST SENSE Table 10-121. HW_APBH_CH7_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 27 26 25 24 23 22 21 20 BURST KICK END SENSE READY LOCK NEXTCMDADDRVALID RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 LOCK KICK REQ END 10-69 AHB-to-APBH Bridge with DMA Table 10-121. HW_APBH_CH7_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 7 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. WAIT_READY = 0x1F When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 7. EXAMPLE: Empty example. 10.5.60 AHB to APBH DMA Channel 7 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 7. HW_APBH_CH7_DEBUG2 0x3B0 i.MX23 Applications Processor Reference Manual, Rev. 1 10-70 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBH Bridge with DMA Table 10-122. HW_APBH_CH7_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 10-123. HW_APBH_CH7_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBH DMA Channel 7. EXAMPLE: Empty example. 10.5.61 APBH Bridge Version Register Description This register always returns a known read value for debug purposes it indicates the version of the block. HW_APBH_VERSION Table 10-124. HW_APBH_VERSION 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x3F0 Table 10-125. HW_APBH_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x02 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x00 RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 10-71 AHB-to-APBH Bridge with DMA EXAMPLE: if (HW_APBH_VERSION.B.MAJOR != 1) Error(); APBH Block v2.0, Revision 1.57 i.MX23 Applications Processor Reference Manual, Rev. 1 10-72 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 11 AHB-to-APBX Bridge with DMA This chapter describes the AHB-to-APBX bridge on the i.MX23, along with its central DMA function and implementation examples. Programmable registers are described in Section 11.5, "Programmable Registers." 11.1 Overview The AHB-to-APBX bridge provides the i.MX23 with an inexpensive peripheral attachment bus running on the AHB's XCLK. (The "X" in APBX denotes that the APBX runs on a crystal-derived clock, as compared to APBH, which is synchronous to HCLK.) As shown in Figure 12-1, the AHB-to-APBX bridge includes the AHB-to-APB PIO bridge for memory-mapped I/O to the APB devices, as well a central DMA facility for devices on this bus and a vectored interrupt controller for the ARM926 core. Each one of the APB peripherals are documented in their own chapters elsewhere in this document. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-1 AHB-to-APBX Bridge with DMA AH B AHB Sla ve AH B M aste r AHB -to-A PB X DM A AP BX M AS TER A H B-to-AP BX B ridge A UDIO IN A UDIO O U T Serial Audio Interface 1 (SAIF1) SP DIF Transm it I2C SA IF2 APBX UA RT1 RX UA RT1 TX UA RT2 RX UA RT 2 TX Figure 11-1. AHB-to-APBX Bridge DMA Block Diagram The DMA controller uses the APBX bus to transfer read and write data to and from each peripheral. There is no separate DMA bus for these devices. Contention between the DMA's use of the APBX bus and AHB-to-APB bridge functions' use of the APBX is mediated by internal arbitration logic. For contention between these two units, the DMA is favored and the AHB slave will report not ready via its HREADY output until the bridge transfer completes. The arbiter tracks repeated lockouts and inverts the priority, so that the CPU is guaranteed every fourth transfer on the APB. 11.2 APBX DMA The DMA supports sixteen channels of DMA services, as shown in Table 11-1. The shared DMA resource allows each independent channel to follow a simple chained command list. Command chains are built up using the DMA command structure, as shown in Figure 11-2. i.MX23 Applications Processor Reference Manual, Rev. 1 11-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-1. APBX DMA Channel Assignments APBX DMA Channel # USAGE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Audio ADCs Audio DACs SPDIF TX I2C SAIF1 Reserved UART1 RX, IrDA RX UART1 TX, IrDA TX UART2 RX UART2 TX SAIF2 Reserved Reserved Reserved Reserved Reserved A single command structure or channel command word specifies a number of operations to be performed by the DMA in support of a given device. Thus, the CPU can set up large units of work, chaining together many DMA channel command words, pass them off to the DMA and have no further concern for the device until the DMA completion interrupt occurs. The i.MX23 is designed to have enough intelligence in the DMA and the devices to keep the interrupt frequency from any device below 1 kHz (arrival intervals longer than 1 ms). Thus, a single command structure can issue 32-bit PIO write operations to key registers in the associated device using the same APB bus and controls it uses to write DMA data bytes to the device. For example, this allows a chain of operations to be issued to the serial audio interface to send command bytes, address bytes, and data transfers, where the command and address structure is completely under software control, but the administration of that transfer is handled autonomously by the DMA. Each DMA structure can have from 0 to 15 PIO words appended to it. The #PIOWORDs field, if non-zero, instructs the DMA engine to copy these words to the APB beginning at PADDR = 0x0000 and incrementing its PADDR for each cycle. (Note that for APBX DMA Channel 6, which is the UART/IrDA RX channel, the first PIO word in the DMA command is CTRL0. However, for APBX DMA Channel 7, which is the UART/IrDA TX, the first PIO word in a DMA command is CTRL1.) The HW_APBX_DEVSEL_CHx bit fields allow reassignment of the APBX device connected to DMA channels 2, 6, and 7. The DMA channel can be programmed to enable an alternate channel owner--for example, SAIF2 instead of SPDIF for Channel 2. Note that the CHx bit fields can be set only once after the chip is reset. To have the DMA channel provide DMA for another device, the chip must be reset and the HW_APBX_DEVSEL register must be reprogrammed. Whichever device is selected for the DMA i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-3 AHB-to-APBX Bridge with DMA channel remains the selected device until the chip is reset and the DMA channel selected for another device. The DMA master generates only normal read/write transfers to the APBX. It does not generate set, clear, or toggle SCT transfers. word 0 NEXTCMDADDR WAIT4ENDCMD SEMAPHORE IRQONCMPLT CHAIN CMDWORDS word 1 XFER_COUNT word 2 word 3-n BUFFER ADDRESS PIOWORD Value Figure 11-2. AHB-to-APBX Bridge DMA Channel Command Structure Once any requested PIO words have been transferred to the peripheral, the DMA examines the two-bit command field in the channel command structure. Table 11-2 shows the four commands implemented by the DMA. Table 11-2. APBX DMA Commands DMA COMMAND 00 01 10 11 Usage NO_DMA_XFER. Perform any requested PIO word transfers, but terminate the command before any DMA transfer. DMA_WRITE. Perform any requested PIO word transfers, and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ. Perform any requested PIO word transfers, and then perform a DMA transfer to the peripheral for the specified number of bytes. Reserved DMA_WRITE operations copy data bytes to system memory (on-chip RAM or SDRAM) from the associated peripheral. Each peripheral has a target PADDR value that it expects to receive DMA bytes. This association is synthesized in the DMA. The DMA_WRITE transfer uses the BUFFER_ADDDRESS word in the command structure to point to the beginning byte to write data from the peripheral. DMA_READ operations copy data bytes to the APB peripheral from system memory. The DMA engine contains a shared byte aligner that aligns bytes from system memory to or from the peripherals. Peripherals always assume little-endian-aligned data arrives or departs on their 32-bit APB. The DMA_READ transfer uses the BUFFER_ADDRESS word in the command structure to point to the DMA data buffer to be read by the DMA_READ command. i.MX23 Applications Processor Reference Manual, Rev. 1 11-4 Preliminary--Subject to Change Without Notice COMMAND Freescale Semiconductor AHB-to-APBX Bridge with DMA The NO_DMA_XFER command is used to write PIO words to a device without performing any DMA data byte transfers. As each DMA command completes, it triggers the DMA to load the next DMA command structure in the chain. The normal flow list of DMA commands is found by following the NEXTCMD_ADDR pointer in the DMA command structure. If the wait-for-end-command bit (WAIT4ENDCMD) is set in a command structure, then the DMA channel will wait for the device to signal completion of a command by toggling the apx_endcmcd signal before proceeding to load and execute the next command structure. The semaphore is decremented after the end command is seen. A detailed bit-field view of the DMA command structure is shown in Table 11-3, which shows a field that specifies the number of bytes to be transferred by this DMA command. The transfer count mechanism is duplicated in the associated peripheral, either as an implied or specified count in the peripheral. Table 11-3. DMA Channel Command Word in System Memory 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 111111111 987654321 NEXT_COMMAND_ADDRESS 1 0 0 9 0 8 0 7 0 6 DECREMENT SEMAPHORE 0 5 0 4 0 3 0 2 0 1 0 0 IRQ_COMPLETE WAIT4ENDCMD Number DMA Bytes to Transfer Number PIO Words to Write Reserved DMA Buffer or Alternate CCW Zero or More PIO Words to Write to the Associated Peripheral Starting at its Base Address on the APBX Bus Figure 11-3 shows the CHAIN bit in bit 2 of the second word of the command structure. This bit is set to 1 if the NEXT_COMMAND_ADDRESS contains a pointer to another DMA command structure. If a null pointer (0) is loaded into the NEXT_COMMAND_ADDRESS, it will not be detected by the DMA hardware. Only the CHAIN bit indicates whether a valid list exists beyond the current structure. If the IRQ_COMPLETE bit is set in the command structure, then the last act of the DMA before loading the next command is to set the interrupt status bit corresponding to the current channel. The sticky interrupt request bit in the DMA CSR remains set until cleared by software. It can be used to interrupt the CPU. Each channel has an eight-bit counting semaphore that controls whether it is in the run or idle state. When the semaphore is non-zero, the channel is ready to run and process commands and DMA transfers. Whenever a command finishes its DMA transfer, it checks the DECREMENT_SEMAPHORE bit. If set, it decrements the counting semaphore. If the semaphore goes to 0 as a result, then the channel enters the IDLE state and remains there until the semaphore is incremented by software. When the semaphore goes to i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice COMMAND Reserved CHAIN 11-5 AHB-to-APBX Bridge with DMA non-zero and the channel is in its IDLE state, then it uses the value in the HW_APBX_CHn_NXTCMDAR (next command address register) to fetch a pointer to the next command to process. NOTE: this is a double indirect case. This method allows software to append to a running command list under the protection of the counting semaphore. Receiving an IRQ for HALTONTERMINATE (HOT) is a new feature in the APBH/X DMA descriptor that allows certain peripheral block (e.g. GPMI, SSP, I2C) to signal to the DMA engine that an error has occurred. In prior chips, if a block stalled due to an error, the only practical way to discover this in s/w was via a timer of some sort, or to poll the block. Now, an HOT signal is sent from the peripheral to the DMA engine and causes an IRQ after terminating the DMA descriptor being executed. Note not all peripheral block support this termination feature. Therefore, it is recommended that s/w use this signal as follows: Always set HALTONTERMINATE to 1 in a DMA descriptor. That way, if a peripheral signals HOT, the transfer will end, leaving the peripheral block and the DMA engine synchronized (but at the end of a command). * When an IRQ from an APBH/X channel is received, and the IRQ is determined to be due to an error (as opposed to an IRQONCOMPLETE interrupt) the software should: 1. reset the channel, and 2. determine the error from error reporting in the peripheral block, then manage the error in the peripheral that is attached to that channel in whatever appropriate way exists for that device (software recovery, device reset, block reset, etc). To start processing the first time, software creates the command list to be processed. It writes the address of the first command into the HW_APBX_CHn_NXTCMDAR register, and then writes a 1 to the counting semaphore in HW_APBX_CHn_SEMA. The DMA channel loads HW_APBX_CHn_CURCMDAR register and then enters the normal state machine processing for the next command. When software writes a value to the counting semaphore, it is added to the semaphore count by hardware, protecting the case where both hardware and software are trying to change the semaphore on the same clock edge. Software can examine the value of HW_APBX_CHn_CURCMDAR at any time to determine the location of the command structure that is currently being processed. * 11.3 DMA Chain Example The example in Figure 11-3 shows how to bring the basic items together to make a simple DMA chain to read PCM samples and send them out the Audio Output (DAC) using one DMA channel. This example shows three command structures linked together using their normal command list pointers. The first command writes a single PIO word to the HW_AUDIOOUT_CTRL0 register with a new word count for the DAC. This first command also performs a 512 byte DMA_READ operation to read the data block bytes into the DAC. A second and a third DMA command structure also performs a DMA_READ operation to handle circular buffer style outputs. The completion of each command structure generates an interrupt request. In addition, each command structure decrements the semaphore. If the decompression software i.MX23 Applications Processor Reference Manual, Rev. 1 11-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA has not provided a buffer in a timely fashion, then the DMA will stall. Without the decrement semaphore interlocking, then the DMA will continue to output a stream of samples. In this mode, it is up to software to use the interrupts to synchronize outputs so that underruns do not occur. 1 PIO, IRQ, DecSema chaining, DMA read NEXTCMD_ADDR 512=0x200 0x104E BUFFER ADDRESS HW_AUDIOOUT_CTRL0 1 PIO, IRQ, DecSema, chaining, DMA read NEXTCMD_ADDR 512=0x200 512-Byte Data Block (64 PCM stereo samples) (1.33 ms @ 48 kHz) 0x104E BUFFER ADDRESS HW_AUDIOOUT_CTRL0 512-Byte Data Block (64 PCM stereo samples) (1.33 ms @ 48 kHz) 512-Byte Data Block (64 PCM stereo samples) (1.33 ms @ 48 kHz) 1 PIO,IRQ, DecSema, chaining, DMA read NEXTCMD_ADDR 512=0x200 0x104E BUFFER ADDRESS HW_AUDIOOUT_CTRL0 Pointer to next ccw Pointer to DMA buffer Figure 11-3. AHB-to-APBX Bridge DMA AUDIOOUT (DAC) Example Command Chain Note that each word of the three-word DMA Command structure corresponds to a PIO register of the DMA that is accessible on the APBX bus. Normally, the DMA copies the next command structure onto these registers for processing at the start of each command by following the value of the pointer previously loaded into the NEXTCMD_ADDR register. In order to start DMA processing, for the first command, one must initialize the PIO registers of the desired channel. FIrst load the next command address register with a pointer to the first command to be loaded. Then write a 1 to the counting semaphore register. This causes the DMA to schedule the targeted channel for DMA command structure load, as if it just finished its previous command. 11.4 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-7 AHB-to-APBX Bridge with DMA 11.5 Programmable Registers This section describes the programmable registers of the AHB-to-APBX bridge block. 11.5.1 AHB to APBX Bridge Control Register 0 Description HW_APBX_CTRL0 HW_APBX_CTRL0_SET HW_APBX_CTRL0_CLR HW_APBX_CTRL0_TOG Table 11-4. HW_APBX_CTRL0 0x000 0x004 0x008 0x00C The APBX CTRL 0 provides overall control and IRQ status of the AHB to APBX bridge and DMA. 3 1 SFTRST 3 0 CLKGATE 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSVD0 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-5. HW_APBX_CTRL0 Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Set this bit to zero to enable normal APBX DMA operation. Set this bit to one (default) to disable clocking with the APBX DMA and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the APBX DMA block to its default state. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. Reserved, always set to zero. 30 29:0 CLKGATE RSVD0 RW 0x1 RO 0x000000 DESCRIPTION: This register contains softreset, clock gating bits. EXAMPLE: No Example. 11.5.2 AHB to APBX Bridge Control Register 1 Description HW_APBX_CTRL1 HW_APBX_CTRL1_SET HW_APBX_CTRL1_CLR HW_APBX_CTRL1_TOG 0x010 0x014 0x018 0x01C The APBX CTRL 1 provides channel complete IRQ status of the AHB to APBX bridge and DMA. i.MX23 Applications Processor Reference Manual, Rev. 1 11-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-6. HW_APBX_CTRL1 3 1 CH15_CMDCMPLT_IRQ_EN 3 0 CH14_CMDCMPLT_IRQ_EN 2 9 CH13_CMDCMPLT_IRQ_EN 2 8 CH12_CMDCMPLT_IRQ_EN 2 7 CH11_CMDCMPLT_IRQ_EN 2 6 CH10_CMDCMPLT_IRQ_EN 2 5 CH9_CMDCMPLT_IRQ_EN 2 4 CH8_CMDCMPLT_IRQ_EN 2 3 CH7_CMDCMPLT_IRQ_EN 2 2 CH6_CMDCMPLT_IRQ_EN 2 1 CH5_CMDCMPLT_IRQ_EN 2 0 CH4_CMDCMPLT_IRQ_EN 1 9 CH3_CMDCMPLT_IRQ_EN 1 8 CH2_CMDCMPLT_IRQ_EN 1 7 CH1_CMDCMPLT_IRQ_EN 1 6 CH0_CMDCMPLT_IRQ_EN 1 5 CH15_CMDCMPLT_IRQ 1 4 CH14_CMDCMPLT_IRQ 1 3 CH13_CMDCMPLT_IRQ 1 2 CH12_CMDCMPLT_IRQ 1 1 CH11_CMDCMPLT_IRQ 1 0 CH10_CMDCMPLT_IRQ 0 9 CH9_CMDCMPLT_IRQ 0 8 CH8_CMDCMPLT_IRQ 0 7 CH7_CMDCMPLT_IRQ 0 6 CH6_CMDCMPLT_IRQ 0 5 CH5_CMDCMPLT_IRQ 0 4 CH4_CMDCMPLT_IRQ 0 3 CH3_CMDCMPLT_IRQ 0 2 CH2_CMDCMPLT_IRQ 0 1 CH1_CMDCMPLT_IRQ 0 0 CH0_CMDCMPLT_IRQ Table 11-7. HW_APBX_CTRL1 Bit Field Descriptions BITS LABEL 31 CH15_CMDCMPLT_IRQ_EN RW RESET RW 0x0 DEFINITION Setting this bit enables the generation of an interrupt request for APBX DMA Channel 15. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 14. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 13. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 12. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 11. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 10. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 9. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 8. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 7. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 6. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 5. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 4. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 3. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 2. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1. Setting this bit enables the generation of an interrupt request for APBX DMA Channel 0. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CH14_CMDCMPLT_IRQ_EN CH13_CMDCMPLT_IRQ_EN CH12_CMDCMPLT_IRQ_EN CH11_CMDCMPLT_IRQ_EN CH10_CMDCMPLT_IRQ_EN CH9_CMDCMPLT_IRQ_EN CH8_CMDCMPLT_IRQ_EN CH7_CMDCMPLT_IRQ_EN CH6_CMDCMPLT_IRQ_EN CH5_CMDCMPLT_IRQ_EN CH4_CMDCMPLT_IRQ_EN CH3_CMDCMPLT_IRQ_EN CH2_CMDCMPLT_IRQ_EN CH1_CMDCMPLT_IRQ_EN CH0_CMDCMPLT_IRQ_EN RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-9 AHB-to-APBX Bridge with DMA Table 11-7. HW_APBX_CTRL1 Bit Field Descriptions BITS LABEL 15 CH15_CMDCMPLT_IRQ RW RESET RW 0x0 DEFINITION Interrupt request status bit for APBX DMA Channel 15. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 14. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 13. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 12. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 11. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 10. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 9. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 8. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 7. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 6. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 5. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 4. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 3. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 14 CH14_CMDCMPLT_IRQ RW 0x0 13 CH13_CMDCMPLT_IRQ RW 0x0 12 CH12_CMDCMPLT_IRQ RW 0x0 11 CH11_CMDCMPLT_IRQ RW 0x0 10 CH10_CMDCMPLT_IRQ RW 0x0 9 CH9_CMDCMPLT_IRQ RW 0x0 8 CH8_CMDCMPLT_IRQ RW 0x0 7 CH7_CMDCMPLT_IRQ RW 0x0 6 CH6_CMDCMPLT_IRQ RW 0x0 5 CH5_CMDCMPLT_IRQ RW 0x0 4 CH4_CMDCMPLT_IRQ RW 0x0 3 CH3_CMDCMPLT_IRQ RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-7. HW_APBX_CTRL1 Bit Field Descriptions BITS LABEL 2 CH2_CMDCMPLT_IRQ RW RESET RW 0x0 DEFINITION Interrupt request status bit for APBX DMA Channel 2. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 1. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Interrupt request status bit for APBX DMA Channel 0. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 1 CH1_CMDCMPLT_IRQ RW 0x0 0 CH0_CMDCMPLT_IRQ RW 0x0 DESCRIPTION: This register contains the per channel interrupt status bits. Each channel has a dedicated interrupt vector in the vectored interrupt controller. EXAMPLE: BF_WR(APBX_CTRL1, CH5_CMDCMPLT_IRQ, 0); // use bitfield write macro BF_APBX_CTRL1.CH5_CMDCMPLT_IRQ = 0; // or, assign to register struct's bitfield 11.5.3 AHB to APBX Bridge Control and Status Register 2 Description HW_APBX_CTRL2 HW_APBX_CTRL2_SET HW_APBX_CTRL2_CLR HW_APBX_CTRL2_TOG Table 11-8. HW_APBX_CTRL2 0x020 0x024 0x028 0x02C The APBX CTRL 2 provides channel error interrupts generated by the AHB to APBX DMA. 3 1 CH15_ERROR_STATUS 3 0 CH14_ERROR_STATUS 2 9 CH13_ERROR_STATUS 2 8 CH12_ERROR_STATUS 2 7 CH11_ERROR_STATUS 2 6 CH10_ERROR_STATUS 2 5 CH9_ERROR_STATUS 2 4 CH8_ERROR_STATUS 2 3 CH7_ERROR_STATUS 2 2 CH6_ERROR_STATUS 2 1 CH5_ERROR_STATUS 2 0 CH4_ERROR_STATUS 1 9 CH3_ERROR_STATUS 1 8 CH2_ERROR_STATUS 1 7 CH1_ERROR_STATUS 1 6 CH0_ERROR_STATUS 1 5 CH15_ERROR_IRQ 1 4 CH14_ERROR_IRQ 1 3 CH13_ERROR_IRQ 1 2 CH12_ERROR_IRQ 1 1 CH11_ERROR_IRQ 1 0 CH10_ERROR_IRQ 0 9 CH9_ERROR_IRQ 0 8 CH8_ERROR_IRQ 0 7 CH7_ERROR_IRQ 0 6 CH6_ERROR_IRQ 0 5 CH5_ERROR_IRQ 0 4 CH4_ERROR_IRQ 0 3 CH3_ERROR_IRQ 0 2 CH2_ERROR_IRQ 0 1 CH1_ERROR_IRQ 0 0 CH0_ERROR_IRQ i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-11 AHB-to-APBX Bridge with DMA Table 11-9. HW_APBX_CTRL2 Bit Field Descriptions BITS LABEL 31 CH15_ERROR_STATUS RW RESET RO 0x0 DEFINITION Error status bit for APBX DMA Channel 15. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 30 CH14_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 14. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 29 CH13_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 13. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 28 CH12_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 12. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 27 CH11_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 11. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 26 CH10_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 10. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 25 CH9_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 9. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 24 CH8_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 8. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. i.MX23 Applications Processor Reference Manual, Rev. 1 11-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-9. HW_APBX_CTRL2 Bit Field Descriptions BITS LABEL 23 CH7_ERROR_STATUS RW RESET RO 0x0 DEFINITION Error status bit for APBX DMA Channel 7. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 22 CH6_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 6. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 21 CH5_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 5. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 20 CH4_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 4. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 19 CH3_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 3. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 18 CH2_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 2. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 17 CH1_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 1. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 16 CH0_ERROR_STATUS RO 0x0 Error status bit for APBX DMA Channel 0. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. TERMINATION = 0x0 An early termination from the device causes error IRQ. BUS_ERROR = 0x1 An AHB bus error causes error IRQ. 15 CH15_ERROR_IRQ RW 0x0 Error interrupt status bit for APBX DMA Channel 15. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-13 AHB-to-APBX Bridge with DMA Table 11-9. HW_APBX_CTRL2 Bit Field Descriptions BITS LABEL 14 CH14_ERROR_IRQ RW RESET RW 0x0 DEFINITION Error interrupt status bit for APBX DMA Channel 14. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 13. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 12. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 11. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 10. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 9. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 8. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 7. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 6. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 5. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 4. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 3. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 2. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 13 CH13_ERROR_IRQ RW 0x0 12 CH12_ERROR_IRQ RW 0x0 11 CH11_ERROR_IRQ RW 0x0 10 CH10_ERROR_IRQ RW 0x0 9 CH9_ERROR_IRQ RW 0x0 8 CH8_ERROR_IRQ RW 0x0 7 CH7_ERROR_IRQ RW 0x0 6 CH6_ERROR_IRQ RW 0x0 5 CH5_ERROR_IRQ RW 0x0 4 CH4_ERROR_IRQ RW 0x0 3 CH3_ERROR_IRQ RW 0x0 2 CH2_ERROR_IRQ RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-9. HW_APBX_CTRL2 Bit Field Descriptions BITS LABEL 1 CH1_ERROR_IRQ RW RESET RW 0x0 DEFINITION Error interrupt status bit for APBX DMA Channel 1. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Error interrupt status bit for APBX DMA Channel 0. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 0 CH0_ERROR_IRQ RW 0x0 DESCRIPTION: This register contains the per channel bus error interrupt status bits and the per channel completion interrupt enable bits. Each channel has a dedicated interrupt vector in the vectored interrupt controller. EXAMPLE: Exmpty Example 11.5.4 AHB to APBX Bridge Channel Register Description HW_APBX_CHANNEL_CTRL HW_APBX_CHANNEL_CTRL_SET HW_APBX_CHANNEL_CTRL_CLR HW_APBX_CHANNEL_CTRL_TOG 0x030 0x034 0x038 0x03C The APBX CHANNEL CTRL provides reset/freeze control of each DMA channel. Table 11-10. HW_APBX_CHANNEL_CTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RESET_CHANNEL 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 FREEZE_CHANNEL 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-15 AHB-to-APBX Bridge with DMA Table 11-11. HW_APBX_CHANNEL_CTRL Bit Field Descriptions BITS LABEL 31:16 RESET_CHANNEL RW RESET RW 0x0 DEFINITION Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state. The bit is reset after the channel resources are cleared. AUDIOIN = 0x0001 AUDIOOUT = 0x0002 SPDIF_TX = 0x0004 I2C = 0x0008 SAIF1 = 0x0010 UART0_RX = 0x0040 UART0_TX = 0x0080 UART1_RX = 0x0100 UART1_TX = 0x0200 SAIF2 = 0x0400 15:0 FREEZE_CHANNEL RW 0x0 Setting a bit in this field will freeze the DMA channel associated with it. This field is a direct input to the DMA channel arbiter. When frozen, the channel is deined access to the central DMA resources. AUDIOIN = 0x0001 AUDIOOUT = 0x0002 SPDIF_TX = 0x0004 I2C = 0x0008 SAIF1 = 0x0010 UART0_RX = 0x0040 UART0_TX = 0x0080 UART1_RX = 0x0100 UART1_TX = 0x0200 SAIF2 = 0x0400 DESCRIPTION: This register contains individual channel reset/freeze bits. EXAMPLE: Empty Example. 11.5.5 AHB to APBX DMA Device Assignment Register Description HW_APBX_DEVSEL Table 11-12. HW_APBX_DEVSEL 0x040 This register allows reassignment of the APBX device connected to the DMA Channels. 3 1 CH15 3 0 2 9 CH14 2 8 2 7 CH13 2 6 2 5 CH12 2 4 2 3 CH11 2 2 2 1 CH10 2 0 1 9 CH9 1 8 1 7 CH8 1 6 1 5 CH7 1 4 1 3 CH6 1 2 1 1 CH5 1 0 0 9 CH4 0 8 0 7 CH3 0 6 0 5 CH2 0 4 0 3 CH1 0 2 0 1 CH0 0 0 Table 11-13. HW_APBX_DEVSEL Bit Field Descriptions BITS 31:30 29:28 27:26 25:24 23:22 LABEL CH15 CH14 CH13 CH12 CH11 RW RO RO RO RO RO RESET 0x0 0x0 0x0 0x0 0x0 DEFINITION Reserved. Reserved. Reserved. Reserved. Reserved. i.MX23 Applications Processor Reference Manual, Rev. 1 11-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-13. HW_APBX_DEVSEL Bit Field Descriptions BITS 21:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 LABEL CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 RW RO RO RO RW RW RO RO RO RO RO RO RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 DEFINITION Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. DESCRIPTION: This register provides a mechanism for assigning the device which is attached to DMA channels 6 and 7. EXAMPLE: Empty Example. 11.5.6 APBX DMA Channel 0 Current Command Address Register Description The APBX DMA Channel 0 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH0_CURCMDAR 0x100 Table 11-14. HW_APBX_CH0_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-15. HW_APBX_CH0_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 0. DESCRIPTION: APBX DMA Channel 0 is controlled by a variable sized command structure. This register points to the command structure currently being executed. EXAMPLE: pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBX_CHn_CURCMDAR_RD(0); // read the whole register, since there is only one field pCurCmd = (hw_apbh_chn_cmd_t *) BF_RDn(APBX_CHn_CURCMDAR, 0, CMD_ADDR); // or, use multi-register bitfield read macro pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBX_CHn_CURCMDAR(0).CMD_ADDR; // or, assign from bitfield of indexed register's struct i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-17 AHB-to-APBX Bridge with DMA 11.5.7 APBX DMA Channel 0 Next Command Address Register Description The APBX DMA Channel 0 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH0_NXTCMDAR 0x110 Table 11-16. HW_APBX_CH0_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-17. HW_APBX_CH0_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 0. DESCRIPTION: APBX DMA Channel 0 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 0 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: HW_APBX_CHn_NXTCMDAR_WR(0, (reg32_t) pCommandTwoStructure); // write the entire register, since there is only one field BF_WRn(APBX_CHn_NXTCMDAR, 0, (reg32_t) pCommandTwoStructure); // or, use multi-register bitfield write macro HW_APBX_CHn_NXTCMDAR(0).CMD_ADDR = (reg32_t) pCommandTwoStructure; // or, assign to bitfield of indexed register's struct 11.5.8 APBX DMA Channel 0 Command Register Description The APBX DMA Channel 0 command register specifies the DMA transaction to perform for the current command chain item. HW_APBX_CH0_CMD Table 11-18. HW_APBX_CH0_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 CMDWORDS 1 3 1 2 1 1 1 0 0 9 0 8 0 7 WAIT4ENDCMD 0 6 SEMAPHORE 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 COMMAND 0 0 0x120 RSVD1 RSVD0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor CHAIN AHB-to-APBX Bridge with DMA Table 11-19. HW_APBX_CH0_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the ADC device HW_AUDIOIN_DATA. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the ADC, starting with the base PIO address of the ADC (HW_AUDIOIN_CTRL) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will wait for the end of command signal to be sent from the ABPX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH0_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 15:12 CMDWORDS RO 0x00 11:8 7 RSVD1 WAIT4ENDCMD RO 0x0 RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 2 CHAIN RO 0x0 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: hw_apbh_chn_cmd_t dma_cmd; dma_cmd.XFER_COUNT = 512; // transfer 512 bytes i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-19 AHB-to-APBX Bridge with DMA dma_cmd.COMMAND = BV_APBX_CHn_CMD_COMMAND__DMA_WRITE; // transfer to system memory from peripheral device dma_cmd.CHAIN = 1; // chain an additional command structure on to the list dma_cmd.IRQONCMPLT = 1; // generate an interrupt on completion of this command structure 11.5.9 APBX DMA Channel 0 Buffer Address Register Description The APBX DMA Channel 0 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH0_BAR Table 11-20. HW_APBX_CH0_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x130 ADDRESS Table 11-21. HW_APBX_CH0_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: hw_apbh_chn_bar_t dma_data; dma_data.ADDRESS = (reg32_t) pDataBuffer; 11.5.10 APBX DMA Channel 0 Semaphore Register Description The APBX DMA Channel 0 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH0_SEMA Table 11-22. HW_APBX_CH0_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x140 PHORE RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 11-20 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-23. HW_APBX_CH0_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE: BF_WR(APBX_CHn_SEMA, 0, INCREMENT_SEMA, 2); // increment semaphore by two current_sema = BF_RD(APBX_CHn_SEMA, 0, PHORE); // get instantaneous value 11.5.11 AHB to APBX DMA Channel 0 Debug Information Description This register gives debug visibility into the APBX DMA Channel 0 state machine and controls. HW_APBX_CH0_DEBUG1 Table 11-24. HW_APBX_CH0_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 0x150 RD_FIFO_FULL BURST RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END 11-21 AHB-to-APBX Bridge with DMA Table 11-25. HW_APBX_CH0_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 0 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 30 29 28 BURST KICK END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 RO 0x0 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 19:5 4:0 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RSVD1 STATEMACHINE i.MX23 Applications Processor Reference Manual, Rev. 1 11-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 0. EXAMPLE: Empty example. 11.5.12 AHB to APBX DMA Channel 0 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 0. HW_APBX_CH0_DEBUG2 Table 11-26. HW_APBX_CH0_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x160 Table 11-27. HW_APBX_CH0_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 0. EXAMPLE: Empty example. 11.5.13 APBX DMA Channel 1 Current Command Address Register Description The APBX DMA Channel 1 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH1_CURCMDAR 0x170 Table 11-28. HW_APBX_CH1_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-23 AHB-to-APBX Bridge with DMA Table 11-29. HW_APBX_CH1_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 1. DESCRIPTION: APBX DMA Channel 1 is controlled by a variable sized command structure. This register points to the command structure currently being executed. EXAMPLE: pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBX_CHn_CURCMDAR_RD(1); // read the whole register, since there is only one field pCurCmd = (hw_apbh_chn_cmd_t *) BF_RDn(APBX_CHn_CURCMDAR, 1, CMD_ADDR); // or, use multi-register bitfield read macro pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBX_CHn_CURCMDAR(1).CMD_ADDR; // or, assign from bitfield of indexed register's struct 11.5.14 APBX DMA Channel 1 Next Command Address Register Description The APBX DMA Channel 1 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH1_NXTCMDAR 0x180 Table 11-30. HW_APBX_CH1_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-31. HW_APBX_CH1_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 1. DESCRIPTION: APBX DMA Channel 1 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 1 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: HW_APBX_CHn_NXTCMDAR_WR(1, (reg32_t) pCommandTwoStructure); // write the entire register, since there is only one field BF_WRn(APBX_CHn_NXTCMDAR, 1, (reg32_t) pCommandTwoStructure); // or, use multi-register bitfield write macro HW_APBX_CHn_NXTCMDAR(1).CMD_ADDR = (reg32_t) pCommandTwoStructure; // or, assign to bitfield of indexed register's struct i.MX23 Applications Processor Reference Manual, Rev. 1 11-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA 11.5.15 APBX DMA Channel 1 Command Register Description The APBX DMA Channel 1 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH1_CMD Table 11-32. HW_APBX_CH1_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 CMDWORDS 1 3 1 2 1 1 1 0 0 9 0 8 0 7 WAIT4ENDCMD 0 6 SEMAPHORE 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 COMMAND 0 0 0x190 RSVD1 RSVD0 Table 11-33. HW_APBX_CH1_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DAC device HW_AUDIOOUT_DATA. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the DAC, starting with the base PIO address of the DAC (HW_AUDIOOUT_CTRL) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:8 7 RSVD1 WAIT4ENDCMD RO 0x0 RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice CHAIN 11-25 AHB-to-APBX Bridge with DMA Table 11-33. HW_APBX_CH1_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH1_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty Example. 11.5.16 APBX DMA Channel 1 Buffer Address Register Description The APBX DMA Channel 1 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH1_BAR Table 11-34. HW_APBX_CH1_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x1A0 ADDRESS Table 11-35. HW_APBX_CH1_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 11-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: hw_apbh_chn_bar_t dma_data; dma_data.ADDRESS = (reg32_t) pDataBuffer; 11.5.17 APBX DMA Channel 1 Semaphore Register Description The APBX DMA Channel 1 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH1_SEMA Table 11-36. HW_APBX_CH1_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x1B0 PHORE RSVD2 Table 11-37. HW_APBX_CH1_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 11-27 AHB-to-APBX Bridge with DMA EXAMPLE: BF_WR(APBX_CHn_SEMA, 1, INCREMENT_SEMA, 2); // increment semaphore by two current_sema = BF_RD(APBX_CHn_SEMA, 1, PHORE); // get instantaneous value 11.5.18 AHB to APBX DMA Channel 1 Debug Information Description This register gives debug visibility into the APBX DMA Channel 1 state machine and controls. HW_APBX_CH1_DEBUG1 Table 11-38. HW_APBX_CH1_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 0x1C0 RD_FIFO_FULL BURST RSVD2 Table 11-39. HW_APBX_CH1_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 BURST KICK END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL i.MX23 Applications Processor Reference Manual, Rev. 1 11-28 Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-39. HW_APBX_CH1_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 1 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 1. EXAMPLE: Empty example. 11.5.19 AHB to APBX DMA Channel 1 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 1. HW_APBX_CH1_DEBUG2 0x1D0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-29 AHB-to-APBX Bridge with DMA Table 11-40. HW_APBX_CH1_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-41. HW_APBX_CH1_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 1. EXAMPLE: Empty example. 11.5.20 APBX DMA Channel 2 Current Command Address Register Description The APBX DMA Channel 2 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH2_CURCMDAR 0x1E0 Table 11-42. HW_APBX_CH2_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-43. HW_APBX_CH2_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 2. DESCRIPTION: APBX DMA Channel 2 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 11-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.21 APBX DMA Channel 2 Next Command Address Register Description The APBX DMA Channel 2 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH2_NXTCMDAR 0x1F0 Table 11-44. HW_APBX_CH2_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-45. HW_APBX_CH2_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 2. DESCRIPTION: APBX DMA Channel 2 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 0 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty Example. 11.5.22 APBX DMA Channel 2 Command Register Description The APBX DMA Channel 2 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH2_CMD Table 11-46. HW_APBX_CH2_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 CMDWORDS 1 3 1 2 1 1 1 0 0 9 0 8 0 7 WAIT4ENDCMD 0 6 SEMAPHORE 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 COMMAND 0 0 0x200 RSVD1 RSVD0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice CHAIN 11-31 AHB-to-APBX Bridge with DMA Table 11-47. HW_APBX_CH2_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SPDIF or SAIF1 device. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the SPDIF, starting with the base PIO address of the SPDIF or SAIF1 and incrementing from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH2_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 15:12 CMDWORDS RO 0x00 11:8 7 RSVD1 WAIT4ENDCMD RO 0x0 RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 2 CHAIN RO 0x0 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 11-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA 11.5.23 APBX DMA Channel 2 Buffer Address Register Description The APBX DMA Channel 2 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH2_BAR Table 11-48. HW_APBX_CH2_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x210 ADDRESS Table 11-49. HW_APBX_CH2_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.24 APBX DMA Channel 2 Semaphore Register Description The APBX DMA Channel 2 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH2_SEMA Table 11-50. HW_APBX_CH2_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x220 PHORE RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 11-33 AHB-to-APBX Bridge with DMA Table 11-51. HW_APBX_CH2_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE: Empty example. 11.5.25 AHB to APBX DMA Channel 2 Debug Information Description This register gives debug visibility into the APBX DMA Channel 2 state machine and controls. HW_APBX_CH2_DEBUG1 Table 11-52. HW_APBX_CH2_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 0x230 RD_FIFO_FULL BURST RSVD2 Table 11-53. HW_APBX_CH2_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device 30 BURST RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-34 Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-53. HW_APBX_CH2_DEBUG1 Bit Field Descriptions BITS 29 KICK LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 2 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 28 END RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 RO 0x0 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 19:5 4:0 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RSVD1 STATEMACHINE DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 2. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-35 AHB-to-APBX Bridge with DMA 11.5.26 AHB to APBX DMA Channel 2 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 2. HW_APBX_CH2_DEBUG2 Table 11-54. HW_APBX_CH2_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x240 Table 11-55. HW_APBX_CH2_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 2. EXAMPLE: Empty example. 11.5.27 APBX DMA Channel 3 Current Command Address Register Description The APBX DMA Channel 3 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH3_CURCMDAR 0x250 Table 11-56. HW_APBX_CH3_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-57. HW_APBX_CH3_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 3. i.MX23 Applications Processor Reference Manual, Rev. 1 11-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA DESCRIPTION: APBX DMA Channel 3 is controlled by a variable sized command structure. This register points to the command structure currently being executed. EXAMPLE: Empty example. 11.5.28 APBX DMA Channel 3 Next Command Address Register Description The APBX DMA Channel 3 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH3_NXTCMDAR 0x260 Table 11-58. HW_APBX_CH3_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-59. HW_APBX_CH3_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 3. DESCRIPTION: APBX DMA Channel 3 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 3 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.29 APBX DMA Channel 3 Command Register Description The APBX DMA Channel 3 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH3_CMD 0x270 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-37 AHB-to-APBX Bridge with DMA Table 11-60. HW_APBX_CH3_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 SEMAPHORE CMDWORDS Table 11-61. HW_APBX_CH3_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the I2C device HW_I2C_DATA. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the I2C, starting with the base PIO address of the I2C (HW_I2C_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor COMMAND RSVD1 RSVD0 CHAIN AHB-to-APBX Bridge with DMA Table 11-61. HW_APBX_CH3_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH3_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 11.5.30 APBX DMA Channel 3 Buffer Address Register Description The APBX DMA Channel 3 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH3_BAR Table 11-62. HW_APBX_CH3_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x280 ADDRESS Table 11-63. HW_APBX_CH3_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-39 AHB-to-APBX Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.31 APBX DMA Channel 3 Semaphore Register Description The APBX DMA Channel 3 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH3_SEMA Table 11-64. HW_APBX_CH3_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x290 PHORE RSVD2 Table 11-65. HW_APBX_CH3_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 11-40 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.32 AHB to APBX DMA Channel 3 Debug Information Description This register gives debug visibility into the APBX DMA Channel 3 state machine and controls. HW_APBX_CH3_DEBUG1 Table 11-66. HW_APBX_CH3_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 0x2A0 RD_FIFO_FULL BURST RSVD2 Table 11-67. HW_APBX_CH3_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 BURST KICK END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END 11-41 AHB-to-APBX Bridge with DMA Table 11-67. HW_APBX_CH3_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 3 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 3. EXAMPLE: Empty example. 11.5.33 AHB to APBX DMA Channel 3 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 3. HW_APBX_CH3_DEBUG2 0x2B0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-42 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-68. HW_APBX_CH3_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-69. HW_APBX_CH3_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 3. EXAMPLE: Empty example. 11.5.34 APBX DMA Channel 4 Current Command Address Register Description The APBX DMA Channel 4 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH4_CURCMDAR 0x2C0 Table 11-70. HW_APBX_CH4_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-71. HW_APBX_CH4_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 4. DESCRIPTION: APBX DMA Channel 4 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-43 AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.35 APBX DMA Channel 4 Next Command Address Register Description The APBX DMA Channel 4 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH4_NXTCMDAR 0x2D0 Table 11-72. HW_APBX_CH4_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-73. HW_APBX_CH4_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 4. DESCRIPTION: APBX DMA Channel 4 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 4 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.36 APBX DMA Channel 4 Command Register Description The APBX DMA Channel 4 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH4_CMD Table 11-74. HW_APBX_CH4_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 CMDWORDS 1 3 1 2 1 1 1 0 0 9 0 8 0 7 WAIT4ENDCMD 0 6 SEMAPHORE 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 COMMAND 0 0 0x2E0 RSVD1 RSVD0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor CHAIN AHB-to-APBX Bridge with DMA Table 11-75. HW_APBX_CH4_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the SAIF1 device. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the SAIF1. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH4_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 15:12 CMDWORDS RO 0x00 11:8 7 RSVD1 WAIT4ENDCMD RO 0x0 RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 2 CHAIN RO 0x0 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-45 AHB-to-APBX Bridge with DMA 11.5.37 APBX DMA Channel 4 Buffer Address Register Description The APBX DMA Channel 4 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH4_BAR Table 11-76. HW_APBX_CH4_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x2F0 ADDRESS Table 11-77. HW_APBX_CH4_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device associate with this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.38 APBX DMA Channel 4 Semaphore Register Description The APBX DMA Channel 4 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH4_SEMA Table 11-78. HW_APBX_CH4_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x300 PHORE RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 11-46 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-79. HW_APBX_CH4_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE: Empty example. 11.5.39 AHB to APBX DMA Channel 4 Debug Information Description This register gives debug visibility into the APBX DMA Channel 4 state machine and controls. HW_APBX_CH4_DEBUG1 Table 11-80. HW_APBX_CH4_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 0x310 RD_FIFO_FULL BURST RSVD2 Table 11-81. HW_APBX_CH4_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device 30 BURST RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END 11-47 AHB-to-APBX Bridge with DMA Table 11-81. HW_APBX_CH4_DEBUG1 Bit Field Descriptions BITS 29 KICK LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 4 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 28 END RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 RO 0x0 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 19:5 4:0 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RSVD1 STATEMACHINE DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 4. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 11-48 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA 11.5.40 AHB to APBX DMA Channel 4 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 4. HW_APBX_CH4_DEBUG2 Table 11-82. HW_APBX_CH4_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x320 Table 11-83. HW_APBX_CH4_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 4. EXAMPLE: Empty example. 11.5.41 APBX DMA Channel 5 Current Command Address Register Description The APBX DMA Channel 5 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH5_CURCMDAR 0x330 Table 11-84. HW_APBX_CH5_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-85. HW_APBX_CH5_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 5. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-49 AHB-to-APBX Bridge with DMA DESCRIPTION: APBX DMA Channel 5 is controlled by a variable sized command structure. This register points to the command structure currently being executed. EXAMPLE: Empty example. 11.5.42 APBX DMA Channel 5 Next Command Address Register Description The APBX DMA Channel 5 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH5_NXTCMDAR 0x340 Table 11-86. HW_APBX_CH5_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-87. HW_APBX_CH5_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 5. DESCRIPTION: APBX DMA Channel 5 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 5 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.43 APBX DMA Channel 5 Command Register Description The APBX DMA Channel 5 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH5_CMD 0x350 i.MX23 Applications Processor Reference Manual, Rev. 1 11-50 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-88. HW_APBX_CH5_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 CMDWORDS 1 3 1 2 1 1 1 0 0 9 0 8 0 7 WAIT4ENDCMD 0 6 SEMAPHORE 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 COMMAND 0 0 RSVD1 RSVD0 Table 11-89. HW_APBX_CH5_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DRI device HW_DRI_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the DRI, starting with the base PIO address of the DRI (HW_DRI_CTRL) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH5_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 15:12 CMDWORDS RO 0x00 11:8 7 RSVD1 WAIT4ENDCMD RO 0x0 RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 2 CHAIN RO 0x0 1:0 COMMAND RO 0x00 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice CHAIN 11-51 AHB-to-APBX Bridge with DMA DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 11.5.44 APBX DMA Channel 5 Buffer Address Register Description The APBX DMA Channel 5 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH5_BAR Table 11-90. HW_APBX_CH5_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x360 ADDRESS Table 11-91. HW_APBX_CH5_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.45 APBX DMA Channel 5 Semaphore Register Description The APBX DMA Channel 5 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH5_SEMA 0x370 i.MX23 Applications Processor Reference Manual, Rev. 1 11-52 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-92. HW_APBX_CH5_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 PHORE RSVD2 Table 11-93. HW_APBX_CH5_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE: Empty example. 11.5.46 AHB to APBX DMA Channel 5 Debug Information Description This register gives debug visibility into the APBX DMA Channel 5 state machine and controls. HW_APBX_CH5_DEBUG1 0x380 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 11-53 AHB-to-APBX Bridge with DMA Table 11-94. HW_APBX_CH5_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL BURST RSVD2 Table 11-95. HW_APBX_CH5_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 BURST KICK END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL i.MX23 Applications Processor Reference Manual, Rev. 1 11-54 Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-95. HW_APBX_CH5_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 5 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 5. EXAMPLE: Empty example. 11.5.47 AHB to APBX DMA Channel 5 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 5. HW_APBX_CH5_DEBUG2 0x390 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-55 AHB-to-APBX Bridge with DMA Table 11-96. HW_APBX_CH5_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-97. HW_APBX_CH5_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 5. EXAMPLE: Empty example. 11.5.48 APBX DMA Channel 6 Current Command Address Register Description The APBX DMA Channel 6 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH6_CURCMDAR 0x3A0 Table 11-98. HW_APBX_CH6_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-99. HW_APBX_CH6_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 6. DESCRIPTION: APBX DMA Channel 6 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 11-56 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.49 APBX DMA Channel 6 Next Command Address Register Description The APBX DMA Channel 6 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH6_NXTCMDAR 0x3B0 Table 11-100. HW_APBX_CH6_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-101. HW_APBX_CH6_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 6. DESCRIPTION: APBX DMA Channel 6 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 6 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.50 APBX DMA Channel 6 Command Register Description The APBX DMA Channel 6 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH6_CMD Table 11-102. HW_APBX_CH6_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 CMDWORDS 1 3 1 2 1 1 1 0 0 9 0 8 0 7 WAIT4ENDCMD 0 6 SEMAPHORE 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 COMMAND 0 0 0x3C0 RSVD1 RSVD0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice CHAIN 11-57 AHB-to-APBX Bridge with DMA Table 11-103. HW_APBX_CH6_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART, starting with the base PIO address of the UART (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH6_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 15:12 CMDWORDS RO 0x00 11:8 7 RSVD1 WAIT4ENDCMD RO 0x0 RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 2 CHAIN RO 0x0 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 11-58 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA 11.5.51 APBX DMA Channel 6 Buffer Address Register Description The APBX DMA Channel 6 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH6_BAR Table 11-104. HW_APBX_CH6_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x3D0 ADDRESS Table 11-105. HW_APBX_CH6_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.52 APBX DMA Channel 6 Semaphore Register Description The APBX DMA Channel 6 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH6_SEMA Table 11-106. HW_APBX_CH6_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x3E0 PHORE RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 11-59 AHB-to-APBX Bridge with DMA Table 11-107. HW_APBX_CH6_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE: Empty example. 11.5.53 AHB to APBX DMA Channel 6 Debug Information Description This register gives debug visibility into the APBX DMA Channel 6 state machine and controls. HW_APBX_CH6_DEBUG1 0x3F0 Table 11-108. HW_APBX_CH6_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL BURST RSVD2 Table 11-109. HW_APBX_CH6_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device 30 BURST RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-60 Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-109. HW_APBX_CH6_DEBUG1 Bit Field Descriptions BITS 29 KICK LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 6 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 28 END RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 RO 0x0 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 19:5 4:0 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RSVD1 STATEMACHINE DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 6. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-61 AHB-to-APBX Bridge with DMA 11.5.54 AHB to APBX DMA Channel 6 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 6. HW_APBX_CH6_DEBUG2 0x400 Table 11-110. HW_APBX_CH6_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-111. HW_APBX_CH6_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 6. EXAMPLE: Empty example. 11.5.55 APBX DMA Channel 7 Current Command Address Register Description The APBX DMA Channel 7 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH7_CURCMDAR 0x410 Table 11-112. HW_APBX_CH7_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-113. HW_APBX_CH7_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for channel 7. i.MX23 Applications Processor Reference Manual, Rev. 1 11-62 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA DESCRIPTION: APBX DMA Channel 7 is controlled by a variable sized command structure. This register points to the command structure currently being executed. EXAMPLE: Empty example. 11.5.56 APBX DMA Channel 7 Next Command Address Register Description The APBX DMA Channel 7 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH7_NXTCMDAR 0x420 Table 11-114. HW_APBX_CH7_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-115. HW_APBX_CH7_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for channel 7. DESCRIPTION: APBX DMA Channel 7 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 7 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.57 APBX DMA Channel 7 Command Register Description The APBX DMA Channel 7 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH7_CMD 0x430 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-63 AHB-to-APBX Bridge with DMA Table 11-116. HW_APBX_CH7_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 SEMAPHORE CMDWORDS Table 11-117. HW_APBX_CH7_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART, starting with the base PIO address of the UART (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-64 Preliminary--Subject to Change Without Notice Freescale Semiconductor COMMAND RSVD1 RSVD0 CHAIN AHB-to-APBX Bridge with DMA Table 11-117. HW_APBX_CH7_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH7_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 11.5.58 APBX DMA Channel 7 Buffer Address Register Description The APBX DMA Channel 7 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH7_BAR Table 11-118. HW_APBX_CH7_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x440 ADDRESS Table 11-119. HW_APBX_CH7_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-65 AHB-to-APBX Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.59 APBX DMA Channel 7 Semaphore Register Description The APBX DMA Channel 7 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH7_SEMA Table 11-120. HW_APBX_CH7_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x450 PHORE RSVD2 Table 11-121. HW_APBX_CH7_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 11-66 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.60 AHB to APBX DMA Channel 7 Debug Information Description This register gives debug visibility into the APBX DMA Channel 7 state machine and controls. HW_APBX_CH7_DEBUG1 0x460 Table 11-122. HW_APBX_CH7_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL BURST RSVD2 Table 11-123. HW_APBX_CH7_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 BURST KICK END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END 11-67 AHB-to-APBX Bridge with DMA Table 11-123. HW_APBX_CH7_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 7 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 7. EXAMPLE: Empty example. 11.5.61 AHB to APBX DMA Channel 7 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 7. HW_APBX_CH7_DEBUG2 0x470 i.MX23 Applications Processor Reference Manual, Rev. 1 11-68 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-124. HW_APBX_CH7_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-125. HW_APBX_CH7_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 7. EXAMPLE: Empty example. 11.5.62 APBX DMA Channel 8 Current Command Address Register Description The APBX DMA Channel 8 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH8_CURCMDAR 0x480 Table 11-126. HW_APBX_CH8_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-127. HW_APBX_CH8_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for Channel 8. DESCRIPTION: APBX DMA Channel 8 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-69 AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.63 APBX DMA Channel 8 Next Command Address Register Description The APBX DMA Channel 8 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH8_NXTCMDAR 0x490 Table 11-128. HW_APBX_CH8_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-129. HW_APBX_CH8_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for Channel 8. DESCRIPTION: APBX DMA Channel 8 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 8 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.64 APBX DMA Channel 8 Command Register Description The APBX DMA Channel 8 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH8_CMD Table 11-130. HW_APBX_CH8_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 0x4A0 SEMAPHORE CMDWORDS i.MX23 Applications Processor Reference Manual, Rev. 1 11-70 Preliminary--Subject to Change Without Notice Freescale Semiconductor COMMAND RSVD1 RSVD0 CHAIN AHB-to-APBX Bridge with DMA Table 11-131. HW_APBX_CH8_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART, starting with the base PIO address of the UART (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH8_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 2 CHAIN RO 0x0 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-71 AHB-to-APBX Bridge with DMA with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 11.5.65 APBX DMA Channel 8 Buffer Address Register Description The APBX DMA Channel 8 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH8_BAR Table 11-132. HW_APBX_CH8_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x4B0 ADDRESS Table 11-133. HW_APBX_CH8_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.66 APBX DMA Channel 8 Semaphore Register Description The APBX DMA Channel 8 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH8_SEMA 0x4C0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-72 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-134. HW_APBX_CH8_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 PHORE RSVD2 Table 11-135. HW_APBX_CH8_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE: Empty example. 11.5.67 AHB to APBX DMA Channel 8 Debug Information Description This register gives debug visibility into the APBX DMA Channel 8 state machine and controls. HW_APBX_CH8_DEBUG1 0x4D0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 11-73 AHB-to-APBX Bridge with DMA Table 11-136. HW_APBX_CH8_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL BURST RSVD2 Table 11-137. HW_APBX_CH8_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 BURST KICK END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL i.MX23 Applications Processor Reference Manual, Rev. 1 11-74 Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-137. HW_APBX_CH8_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 8 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 8. EXAMPLE: Empty example. 11.5.68 AHB to APBX DMA Channel 8 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 8. HW_APBX_CH8_DEBUG2 0x4E0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-75 AHB-to-APBX Bridge with DMA Table 11-138. HW_APBX_CH8_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-139. HW_APBX_CH8_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 8. EXAMPLE: Empty example. 11.5.69 APBX DMA Channel 9 Current Command Address Register Description The APBX DMA Channel 9 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH9_CURCMDAR 0x4F0 Table 11-140. HW_APBX_CH9_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-141. HW_APBX_CH9_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for Channel 9. DESCRIPTION: APBX DMA Channel 9 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 11-76 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.70 APBX DMA Channel 9 Next Command Address Register Description The APBX DMA Channel 9 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH9_NXTCMDAR 0x500 Table 11-142. HW_APBX_CH9_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-143. HW_APBX_CH9_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for Channel 9. DESCRIPTION: APBX DMA Channel 9 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 9 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.71 APBX DMA Channel 9 Command Register Description The APBX DMA Channel 9 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH9_CMD Table 11-144. HW_APBX_CH9_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 CMDWORDS 1 3 1 2 1 1 1 0 0 9 0 8 0 7 WAIT4ENDCMD 0 6 SEMAPHORE 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 COMMAND 0 0 0x510 RSVD1 RSVD0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice CHAIN 11-77 AHB-to-APBX Bridge with DMA Table 11-145. HW_APBX_CH9_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART, starting with the base PIO address of the UART (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH9_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 15:12 CMDWORDS RO 0x00 11:8 7 RSVD1 WAIT4ENDCMD RO 0x0 RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 2 CHAIN RO 0x0 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 11-78 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA 11.5.72 APBX DMA Channel 9 Buffer Address Register Description The APBX DMA Channel 9 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH9_BAR Table 11-146. HW_APBX_CH9_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x520 ADDRESS Table 11-147. HW_APBX_CH9_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.73 APBX DMA Channel 9 Semaphore Register Description The APBX DMA Channel 9 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH9_SEMA Table 11-148. HW_APBX_CH9_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x530 PHORE RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 11-79 AHB-to-APBX Bridge with DMA Table 11-149. HW_APBX_CH9_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE: Empty example. 11.5.74 AHB to APBX DMA Channel 9 Debug Information Description This register gives debug visibility into the APBX DMA Channel 9 state machine and controls. HW_APBX_CH9_DEBUG1 0x540 Table 11-150. HW_APBX_CH9_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL BURST RSVD2 Table 11-151. HW_APBX_CH9_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device 30 BURST RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-80 Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-151. HW_APBX_CH9_DEBUG1 Bit Field Descriptions BITS 29 KICK LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 9 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 28 END RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 RO 0x0 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 19:5 4:0 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RSVD1 STATEMACHINE DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 9. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-81 AHB-to-APBX Bridge with DMA 11.5.75 AHB to APBX DMA Channel 9 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 9. HW_APBX_CH9_DEBUG2 0x550 Table 11-152. HW_APBX_CH9_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-153. HW_APBX_CH9_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 9. EXAMPLE: Empty example. 11.5.76 APBX DMA Channel 10 Current Command Address Register Description The APBX DMA Channel 10 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH10_CURCMDAR 0x560 Table 11-154. HW_APBX_CH10_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-155. HW_APBX_CH10_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for Channel 10. i.MX23 Applications Processor Reference Manual, Rev. 1 11-82 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA DESCRIPTION: APBX DMA Channel 10 is controlled by a variable sized command structure. This register points to the command structure currently being executed. EXAMPLE: Empty example. 11.5.77 APBX DMA Channel 10 Next Command Address Register Description The APBX DMA Channel 10 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH10_NXTCMDAR 0x570 Table 11-156. HW_APBX_CH10_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-157. HW_APBX_CH10_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for Channel 10. DESCRIPTION: APBX DMA Channel 10 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 10 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.78 APBX DMA Channel 10 Command Register Description The APBX DMA Channel 10 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH10_CMD 0x580 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-83 AHB-to-APBX Bridge with DMA Table 11-158. HW_APBX_CH10_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 SEMAPHORE CMDWORDS Table 11-159. HW_APBX_CH10_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART, starting with the base PIO address of the UART (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-84 Preliminary--Subject to Change Without Notice Freescale Semiconductor COMMAND RSVD1 RSVD0 CHAIN AHB-to-APBX Bridge with DMA Table 11-159. HW_APBX_CH10_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH10_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 11.5.79 APBX DMA Channel 10 Buffer Address Register Description The APBX DMA Channel 10 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH10_BAR Table 11-160. HW_APBX_CH10_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x590 ADDRESS Table 11-161. HW_APBX_CH10_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-85 AHB-to-APBX Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.80 APBX DMA Channel 10 Semaphore Register Description The APBX DMA Channel 10 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH10_SEMA Table 11-162. HW_APBX_CH10_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x5A0 PHORE RSVD2 Table 11-163. HW_APBX_CH10_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 11-86 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.81 AHB to APBX DMA Channel 10 Debug Information Description This register gives debug visibility into the APBX DMA Channel 10 state machine and controls. HW_APBX_CH10_DEBUG1 0x5B0 Table 11-164. HW_APBX_CH10_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL BURST RSVD2 Table 11-165. HW_APBX_CH10_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 BURST KICK END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x1 RO 0x0 RO 0x1 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END 11-87 AHB-to-APBX Bridge with DMA Table 11-165. HW_APBX_CH10_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 10 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 10. EXAMPLE: Empty example. 11.5.82 AHB to APBX DMA Channel 10 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 10. HW_APBX_CH10_DEBUG2 0x5C0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-88 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-166. HW_APBX_CH10_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-167. HW_APBX_CH10_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 10. EXAMPLE: Empty example. 11.5.83 APBX DMA Channel 11 Current Command Address Register Description The APBX DMA Channel 11 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH11_CURCMDAR 0x5D0 Table 11-168. HW_APBX_CH11_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-169. HW_APBX_CH11_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for Channel 11. DESCRIPTION: APBX DMA Channel 11 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-89 AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.84 APBX DMA Channel 11 Next Command Address Register Description The APBX DMA Channel 11 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH11_NXTCMDAR 0x5E0 Table 11-170. HW_APBX_CH11_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-171. HW_APBX_CH11_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for Channel 11. DESCRIPTION: APBX DMA Channel 11 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 11 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.85 APBX DMA Channel 11 Command Register Description The APBX DMA Channel 11 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH11_CMD Table 11-172. HW_APBX_CH11_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 CMDWORDS 1 3 1 2 1 1 1 0 0 9 0 8 0 7 WAIT4ENDCMD 0 6 SEMAPHORE 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 COMMAND 0 0 0x5F0 RSVD1 RSVD0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-90 Preliminary--Subject to Change Without Notice Freescale Semiconductor CHAIN AHB-to-APBX Bridge with DMA Table 11-173. HW_APBX_CH11_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART, starting with the base PIO address of the UART (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH11_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 15:12 CMDWORDS RO 0x00 11:8 7 RSVD1 WAIT4ENDCMD RO 0x0 RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 2 CHAIN RO 0x0 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-91 AHB-to-APBX Bridge with DMA 11.5.86 APBX DMA Channel 11 Buffer Address Register Description The APBX DMA Channel 11 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH11_BAR Table 11-174. HW_APBX_CH11_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x600 ADDRESS Table 11-175. HW_APBX_CH11_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.87 APBX DMA Channel 11 Semaphore Register Description The APBX DMA Channel 11 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH11_SEMA Table 11-176. HW_APBX_CH11_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x610 PHORE RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 11-92 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-177. HW_APBX_CH11_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE: Empty example. 11.5.88 AHB to APBX DMA Channel 11 Debug Information Description This register gives debug visibility into the APBX DMA Channel 11 state machine and controls. HW_APBX_CH11_DEBUG1 0x620 Table 11-178. HW_APBX_CH11_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL BURST RSVD2 Table 11-179. HW_APBX_CH11_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device 30 BURST RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END 11-93 AHB-to-APBX Bridge with DMA Table 11-179. HW_APBX_CH11_DEBUG1 Bit Field Descriptions BITS 29 KICK LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 11 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 28 END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 19:5 4:0 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RSVD1 STATEMACHINE DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 11. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 11-94 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA 11.5.89 AHB to APBX DMA Channel 11 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 11. HW_APBX_CH11_DEBUG2 0x630 Table 11-180. HW_APBX_CH11_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-181. HW_APBX_CH11_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 11. EXAMPLE: Empty example. 11.5.90 APBX DMA Channel 12 Current Command Address Register Description The APBX DMA Channel 12 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH12_CURCMDAR 0x640 Table 11-182. HW_APBX_CH12_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-183. HW_APBX_CH12_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for Channel 12. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-95 AHB-to-APBX Bridge with DMA DESCRIPTION: APBX DMA Channel 12 is controlled by a variable sized command structure. This register points to the command structure currently being executed. EXAMPLE: Empty example. 11.5.91 APBX DMA Channel 12 Next Command Address Register Description The APBX DMA Channel 12 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH12_NXTCMDAR 0x650 Table 11-184. HW_APBX_CH12_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-185. HW_APBX_CH12_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for Channel 12. DESCRIPTION: APBX DMA Channel 12 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 12 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.92 APBX DMA Channel 12 Command Register Description The APBX DMA Channel 12 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH12_CMD 0x660 i.MX23 Applications Processor Reference Manual, Rev. 1 11-96 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-186. HW_APBX_CH12_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 SEMAPHORE CMDWORDS Table 11-187. HW_APBX_CH12_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART, starting with the base PIO address of the UART (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice COMMAND RSVD1 RSVD0 CHAIN 11-97 AHB-to-APBX Bridge with DMA Table 11-187. HW_APBX_CH12_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH12_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 11.5.93 APBX DMA Channel 12 Buffer Address Register Description The APBX DMA Channel 12 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH12_BAR Table 11-188. HW_APBX_CH12_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x670 ADDRESS Table 11-189. HW_APBX_CH12_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 11-98 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.94 APBX DMA Channel 12 Semaphore Register Description The APBX DMA Channel 12 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH12_SEMA Table 11-190. HW_APBX_CH12_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x680 PHORE RSVD2 Table 11-191. HW_APBX_CH12_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 11-99 AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.95 AHB to APBX DMA Channel 12 Debug Information Description This register gives debug visibility into the APBX DMA Channel 12 state machine and controls. HW_APBX_CH12_DEBUG1 0x690 Table 11-192. HW_APBX_CH12_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL BURST RSVD2 Table 11-193. HW_APBX_CH12_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 BURST KICK END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL i.MX23 Applications Processor Reference Manual, Rev. 1 11-100 Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-193. HW_APBX_CH12_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 12 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 12. EXAMPLE: Empty example. 11.5.96 AHB to APBX DMA Channel 12 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 12. HW_APBX_CH12_DEBUG2 0x6A0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-101 AHB-to-APBX Bridge with DMA Table 11-194. HW_APBX_CH12_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-195. HW_APBX_CH12_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 12. EXAMPLE: Empty example. 11.5.97 APBX DMA Channel 13 Current Command Address Register Description The APBX DMA Channel 13 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH13_CURCMDAR 0x6B0 Table 11-196. HW_APBX_CH13_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-197. HW_APBX_CH13_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for Channel 13. DESCRIPTION: APBX DMA Channel 13 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 11-102 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.98 APBX DMA Channel 13 Next Command Address Register Description The APBX DMA Channel 13 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH13_NXTCMDAR 0x6C0 Table 11-198. HW_APBX_CH13_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-199. HW_APBX_CH13_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for Channel 13. DESCRIPTION: APBX DMA Channel 13 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 13 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.99 APBX DMA Channel 13 Command Register Description The APBX DMA Channel 13 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH13_CMD Table 11-200. HW_APBX_CH13_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 CMDWORDS 1 3 1 2 1 1 1 0 0 9 0 8 0 7 WAIT4ENDCMD 0 6 SEMAPHORE 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 COMMAND 0 0 0x6D0 RSVD1 RSVD0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice CHAIN 11-103 AHB-to-APBX Bridge with DMA Table 11-201. HW_APBX_CH13_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART, starting with the base PIO address of the UART (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH13_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 15:12 CMDWORDS RO 0x00 11:8 7 RSVD1 WAIT4ENDCMD RO 0x0 RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 2 CHAIN RO 0x0 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 11-104 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA 11.5.100 APBX DMA Channel 13 Buffer Address Register Description The APBX DMA Channel 13 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH13_BAR Table 11-202. HW_APBX_CH13_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x6E0 ADDRESS Table 11-203. HW_APBX_CH13_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.101 APBX DMA Channel 13 Semaphore Register Description The APBX DMA Channel 13 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH13_SEMA Table 11-204. HW_APBX_CH13_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x6F0 PHORE RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 11-105 AHB-to-APBX Bridge with DMA Table 11-205. HW_APBX_CH13_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE: Empty example. 11.5.102 AHB to APBX DMA Channel 13 Debug Information Description This register gives debug visibility into the APBX DMA Channel 13 state machine and controls. HW_APBX_CH13_DEBUG1 0x700 Table 11-206. HW_APBX_CH13_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL BURST RSVD2 Table 11-207. HW_APBX_CH13_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device 30 BURST RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-106 Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-207. HW_APBX_CH13_DEBUG1 Bit Field Descriptions BITS 29 KICK LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 13 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 28 END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 19:5 4:0 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RSVD1 STATEMACHINE DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 13. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-107 AHB-to-APBX Bridge with DMA 11.5.103 AHB to APBX DMA Channel 13 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 13. HW_APBX_CH13_DEBUG2 0x710 Table 11-208. HW_APBX_CH13_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-209. HW_APBX_CH13_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 13. EXAMPLE: Empty example. 11.5.104 APBX DMA Channel 14 Current Command Address Register Description The APBX DMA Channel 14 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH14_CURCMDAR 0x720 Table 11-210. HW_APBX_CH14_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-211. HW_APBX_CH14_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for Channel 14. i.MX23 Applications Processor Reference Manual, Rev. 1 11-108 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA DESCRIPTION: APBX DMA Channel 14 is controlled by a variable sized command structure. This register points to the command structure currently being executed. EXAMPLE: Empty example. 11.5.105 APBX DMA Channel 14 Next Command Address Register Description The APBX DMA Channel 14 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH14_NXTCMDAR 0x730 Table 11-212. HW_APBX_CH14_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-213. HW_APBX_CH14_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for Channel 14. DESCRIPTION: APBX DMA Channel 14 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 14 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.106 APBX DMA Channel 14 Command Register Description The APBX DMA Channel 14 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH14_CMD 0x740 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-109 AHB-to-APBX Bridge with DMA Table 11-214. HW_APBX_CH14_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HALTONTERMINATE 0 7 WAIT4ENDCMD 0 6 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 0 0 SEMAPHORE CMDWORDS Table 11-215. HW_APBX_CH14_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART, starting with the base PIO address of the UART (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. 15:12 CMDWORDS RO 0x00 11:9 8 RSVD1 HALTONTERMINATE RO 0x0 RO 0x0 7 WAIT4ENDCMD RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-110 Preliminary--Subject to Change Without Notice Freescale Semiconductor COMMAND RSVD1 RSVD0 CHAIN AHB-to-APBX Bridge with DMA Table 11-215. HW_APBX_CH14_CMD Bit Field Descriptions BITS 2 CHAIN LABEL RW RESET RO 0x0 DEFINITION A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH14_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. 11.5.107 APBX DMA Channel 14 Buffer Address Register Description The APBX DMA Channel 14 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH14_BAR Table 11-216. HW_APBX_CH14_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x750 ADDRESS Table 11-217. HW_APBX_CH14_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-111 AHB-to-APBX Bridge with DMA DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.108 APBX DMA Channel 14 Semaphore Register Description The APBX DMA Channel 14 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH14_SEMA Table 11-218. HW_APBX_CH14_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x760 PHORE RSVD2 Table 11-219. HW_APBX_CH14_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 11-112 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.109 AHB to APBX DMA Channel 14 Debug Information Description This register gives debug visibility into the APBX DMA Channel 14 state machine and controls. HW_APBX_CH14_DEBUG1 0x770 Table 11-220. HW_APBX_CH14_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL BURST RSVD2 Table 11-221. HW_APBX_CH14_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. 30 29 28 BURST KICK END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END 11-113 AHB-to-APBX Bridge with DMA Table 11-221. HW_APBX_CH14_DEBUG1 Bit Field Descriptions BITS LABEL 19:5 RSVD1 STATEMACHINE 4:0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved PIO Display of the DMA Channel 14 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE = 0x14 When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM = 0x1D If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 14. EXAMPLE: Empty example. 11.5.110 AHB to APBX DMA Channel 14 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 14. HW_APBX_CH14_DEBUG2 0x780 i.MX23 Applications Processor Reference Manual, Rev. 1 11-114 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-222. HW_APBX_CH14_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-223. HW_APBX_CH14_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 14. EXAMPLE: Empty example. 11.5.111 APBX DMA Channel 15 Current Command Address Register Description The APBX DMA Channel 15 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. HW_APBX_CH15_CURCMDAR 0x790 Table 11-224. HW_APBX_CH15_CURCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-225. HW_APBX_CH15_CURCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RO 0x00000000 DEFINITION Pointer to command structure currently being processed for Channel 15. DESCRIPTION: APBX DMA Channel 15 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-115 AHB-to-APBX Bridge with DMA EXAMPLE: Empty example. 11.5.112 APBX DMA Channel 15 Next Command Address Register Description The APBX DMA Channel 15 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. HW_APBX_CH15_NXTCMDAR 0x7A0 Table 11-226. HW_APBX_CH15_NXTCMDAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CMD_ADDR Table 11-227. HW_APBX_CH15_NXTCMDAR Bit Field Descriptions BITS LABEL 31:0 CMD_ADDR RW RESET RW 0x00000000 DEFINITION Pointer to next command structure for Channel 15. DESCRIPTION: APBX DMA Channel 15 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 15 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE: Empty example. 11.5.113 APBX DMA Channel 15 Command Register Description The APBX DMA Channel 15 command register specifies the cycle to perform for the current command chain item. HW_APBX_CH15_CMD Table 11-228. HW_APBX_CH15_CMD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 XFER_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 CMDWORDS 1 3 1 2 1 1 1 0 0 9 0 8 0 7 WAIT4ENDCMD 0 6 SEMAPHORE 0 5 0 4 0 3 IRQONCMPLT 0 2 0 1 COMMAND 0 0 0x7B0 RSVD1 RSVD0 i.MX23 Applications Processor Reference Manual, Rev. 1 11-116 Preliminary--Subject to Change Without Notice Freescale Semiconductor CHAIN AHB-to-APBX Bridge with DMA Table 11-229. HW_APBX_CH15_CMD Bit Field Descriptions BITS LABEL 31:16 XFER_COUNT RW RESET RO 0x0 DEFINITION This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART, starting with the base PIO address of the UART (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH15_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER = 0x0 Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE = 0x1 Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ = 0x2 Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 15:12 CMDWORDS RO 0x00 11:8 7 RSVD1 WAIT4ENDCMD RO 0x0 RO 0x0 6 SEMAPHORE RO 0x0 5:4 3 RSVD0 IRQONCMPLT RO 0x0 RO 0x0 2 CHAIN RO 0x0 1:0 COMMAND RO 0x00 DESCRIPTION: The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-117 AHB-to-APBX Bridge with DMA 11.5.114 APBX DMA Channel 15 Buffer Address Register Description The APBX DMA Channel 15 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. HW_APBX_CH15_BAR Table 11-230. HW_APBX_CH15_BAR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x7C0 ADDRESS Table 11-231. HW_APBX_CH15_BAR Bit Field Descriptions BITS LABEL 31:0 ADDRESS RW RESET RO 0x00000000 DEFINITION Address of system memory buffer to be read or written over the AHB bus. DESCRIPTION: This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE: Empty example. 11.5.115 APBX DMA Channel 15 Semaphore Register Description The APBX DMA Channel 15 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. HW_APBX_CH15_SEMA Table 11-232. HW_APBX_CH15_SEMA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT_SEMA 0 3 0 2 0 1 0 0 0x7D0 PHORE RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 11-118 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor AHB-to-APBX Bridge with DMA Table 11-233. HW_APBX_CH15_SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 PHORE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 15:8 7:0 RSVD1 INCREMENT_SEMA RO 0x0 RW 0x00 DESCRIPTION: Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE: Empty example. 11.5.116 AHB to APBX DMA Channel 15 Debug Information Description This register gives debug visibility into the APBX DMA Channel 15 state machine and controls. HW_APBX_CH15_DEBUG1 0x7E0 Table 11-234. HW_APBX_CH15_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 NEXTCMDADDRVALID 2 3 RD_FIFO_EMPTY 2 2 2 1 WR_FIFO_EMPTY 2 0 WR_FIFO_FULL 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 STATEMACHINE 0 1 0 0 RD_FIFO_FULL BURST RSVD2 Table 11-235. HW_APBX_CH15_DEBUG1 Bit Field Descriptions BITS 31 REQ LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Request Signal from the APB device This bit reflects the current state of the DMA Burst Signal from the APB device 30 BURST RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 KICK REQ END 11-119 AHB-to-APBX Bridge with DMA Table 11-235. HW_APBX_CH15_DEBUG1 Bit Field Descriptions BITS 29 KICK LABEL RW RESET RO 0x0 DEFINITION This bit reflects the current state of the DMA Kick Signal sent to the APB Device This bit reflects the current state of the DMA End Command Signal sent from the APB Device Reserved This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 15 state machine state. IDLE = 0x00 This is the idle state of the DMA state machine. REQ_CMD1 = 0x01 State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 = 0x02 State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 = 0x03 State in which the DMA is waiting to receive the second word of a command. XFER_DECODE = 0x04 The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT = 0x05 The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 = 0x06 State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ = 0x07 This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH = 0x08 During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT = 0x09 When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE = 0x0C During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ = 0x0D During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN = 0x0E Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE = 0x0F The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT = 0x1C During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. CHECK_WAIT = 0x1E If the Chain bit is a 0, the state machine enters this state and effectively halts. 28 END RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 27:25 RSVD2 NEXTCMDADDRVALID 24 23 22 21 20 19:5 4:0 RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL RSVD1 STATEMACHINE DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 15. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 11-120 Preliminary--Subject to Change Without Notice Freescale Semiconductor AHB-to-APBX Bridge with DMA 11.5.117 AHB to APBX DMA Channel 15 Debug Information Description This register gives debug visibility for the APB and AHB byte counts for DMA Channel 15. HW_APBX_CH15_DEBUG2 0x7F0 Table 11-236. HW_APBX_CH15_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_BYTES 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB_BYTES 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 11-237. HW_APBX_CH15_DEBUG2 Bit Field Descriptions BITS LABEL 31:16 APB_BYTES RW RESET RO 0x0 DEFINITION This value reflects the current number of APB bytes remaining to be transfered in the current transfer. This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 15:0 AHB_BYTES RO 0x0 DESCRIPTION: This register allows debug visibility of the APBX DMA Channel 15. EXAMPLE: Empty example. 11.5.118 APBX Bridge Version Register Description This register always returns a known read value for debug purposes it indicates the version of the block. HW_APBX_VERSION Table 11-238. HW_APBX_VERSION 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x800 Table 11-239. HW_APBX_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x02 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11-121 AHB-to-APBX Bridge with DMA Table 11-239. HW_APBX_VERSION Bit Field Descriptions BITS 23:16 MINOR LABEL RW RESET RO 0x01 DEFINITION Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 15:0 STEP RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_APBX_VERSION.B.MAJOR != 1) Error(); APBX Block v2.1, Revision 1.30 11.5.119 i.MX23 Applications Processor Reference Manual, Rev. 1 11-122 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 12 External Memory Interface (EMI) This chapter describes the external memory interface (EMI) on the i.MX23. It describes the DRAM controller and EMI power management. Programmable registers for both the DRAM controller are described in Section 12.5, "Programmable Registers." 12.1 Overview The i.MX23 supports off-chip DRAM storage via the EMI controller, which is connected to the four internal AHB/AXI busses. The EMI supports multiple external memory types, including: * * 1.8-V Mobile DDR Standard 2.5V DDR1 The DRAM controller supports up to two external chip-select signals for the i.MX23 platform. Programmable registers within the DRAM controller allow great flexibility for device timings, low-power operation, and performance tuning. Note the differences between the two package options: * * The 128-pin LQFP has 1 chip enable. Maximum DRAM supported is 64MB. The 169-pin BGA has 2 chip enables. Maximum DRAM supported is 128MB. The EMI uses two primary clocks: the AHB bus HCLK and the DRAM source clock EMI_CLK. The maximum specified frequencies for these two clocks can be found in Chapter 2, "Characteristics and Specifications. The memory controller operates at frequencies that are asynchronous to the rest of the i.MX23. The EMI consists of two major components: * * DRAM controller Delay compensation circuitry (DCC) i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-1 External Memory Interface (EMI) A block diagram of the external memory controller is shown in Figure 12-1. A R M C o re D M I M A X I0 AH B1 AH B2 AH B3 HC LK S S S S D R A M P o rts DRAM PIO Registers APBH EMI PIO Registers DRAM C o n t r o l le r AHB2 D RAM Phy In t e r fa c e EM I 0 1 2 3 DRAM Figure 12-1. External Memory Interface (EMI) Top-Level Block Diagram 12.1.1 AHB Address Ranges The EMI supports a 512-Mbyte DRAM address space at address 0x40000000. The 512-Mbyte DRAM address space is broken down within the DRAM controller as shown in Figure 12-2. Unused Bank[1:0] CS[1:0] Row[#row-1:0] Column[#col-1:0] Byte[0] Figure 12-2. DRAM Controller AHB Address Breakdown Note: This DRAM memory range is not available if the DRAM memory controller is not initialized. A memory access to this range without initializing the DRAM memory controller will result in a system bus hang or a bus error, depending on the state of the TRAP_INIT and TRAP_SR bits in the HW_EMI_CTRL register. The DRAM controller has programmability to support variously sized DRAM devices. Thus, the number of rows and columns are programmable. In addition, the number of external devices that are in use is programmable, as well. With this organization, the DRAM chips form one large contiguous address space: dram_memory_available = 2 * 2#col * 2#row * (# dram_devices) * (# banks_per_device) For example, with 10 column bits, 12 row bits, 1 external device and 4 banks per device, the total memory space available would be 32 Mbytes, as follows: 2 * 210 * 212 * 1 * 4 = 33,554,432 bytes i.MX23 Applications Processor Reference Manual, Rev. 1 12-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) 12.2 DRAM Controller The DRAM controller handles all of the accesses to the off-chip DRAM devices, including refresh cycles, entry into and exit from low-power modes, and data transfers. This controller supports the following devices: * * 1.8-V mobile DDR 2.5-V DDR1 The EMI also supports the connection of simple or multiple external devices with the matrix shown in Table 2-11. See Section 12.6, "EMI Memory Parameters and Register Settings," for configuration examples for DDR and mDDR devices. The architecture of the DRAM controller is shown in Figure 12-3. 12.2.1 Delay Compensation Circuit (DCC) The delay compensation circuit (DCC) controls the source-synchronous write and read clocks for data transfer to and from DRAM devices. It is responsible for synchronizing the inbound DRAM data using the DRAM clock (in bypass mode) or the DQS signals. This is done by implementing a series of buffers to delay the clock or DQS signals and then picking the correct tap from the buffer chain to use to sample the data. DRAM Controller AXI Layer 0 AHB Layer 1 AHB Layer 2 AHB Layer 3 Slave Port Interface and Arbitration DRAM State Machines (DDR) Delay Compensation Circuit EMI Pins AHB Layer 2 AHB Slave Port (Control Registers) Figure 12-3. DRAM Controller Architecture 12.2.2 Address Mapping The memory controller automatically maps user addresses to the DRAM memory in a contiguous block. Addressing starts at system address 0x40000000 and extends up to a maximum system address of 0x5FFFFFFF. This allows for a maximum of 512 Mbytes of DRAM storage. This mapping is accomplished by setting certain bit fields in the internal DRAM controller registers. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-3 External Memory Interface (EMI) 12.2.2.1 * * * * * DDR Address Mapping Options The address structure of DDR devices consists of these fields: Datapath Column Row Chip Select Bank The DRAM controller extracts these fields from the lower 30 bits of the system address. The exact bit positions for each field are defined in the programmable registers of the controller. The order of extraction, however, is always fixed as: Bank-Chip Select-Row-Column-Datapath The maximum widths of each of these fields are fixed at: * * * * * Bank = 2 bits Chip Select = 2 bits Row = 13 bits Column = 12 bits Datapath = 1 bit The actual width of the column and row fields are programmable using the device address width bit fields (ADDR_PINS and COLUMN_SIZE) in the memory controller. These maximum values, when combined, define the maximum 512-Mbyte addressable DRAM memory space. Figure 12-4 shows the positioning of the fields within the system address: Note that practically, the maximum addressable external memory is limited to 128MB for the 169BGA and 64MB for the 128QFP packages. This is because most larger DRAMs require 14 row bits and the EMI controller supports a maximum of 13 row bits. 29 Bank 28 27 Chip Select 26 25 Row 13 12 Column 1 0 Datapath Figure 12-4. Memory Controller Memory Map: Maximum The ADDR_PINS and COLUMN_SIZE bit fields can each range from their maximum values down to a minimum value defined only by the size of the attached device. This allows the memory controller to function with a wide variety of memory device sizes. The settings for the ADDR_PINS and COLUMN_SIZE bit fields control how the address map is used to decode the user address to the DRAM chip selects and row and column addresses. It is assumed that the values in these bit fields never exceed the maximum values of 13 rows and 12 columns. Using the example shown in Figure 12-4, if the memory i.MX23 Applications Processor Reference Manual, Rev. 1 12-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) controller is wired to devices with 10 row pins and 11 column bits, the maximum accessible memory space would be reduced. The accessible memory space for this configuration is 64 Mbytes. The address map for this configuration is shown in Figure 12-5. Note that address bits 26-29 are not used. These bits are ignored when generating the address to the DRAM devices. 29 Don't Care 26 25 Bank 24 23 Chip Select 22 21 Row 12 11 Column 1 0 Datapath Figure 12-5. Example Memory Map: 10 Row Bits, 11 Column Bits Note: The Chip Select, Row, Bank, and Column fields are used to address an entire 16-bit memory word. For example, for a read starting at byte address 0x1, the Datapath bit would be a 1 in order to address this byte directly. Reads and writes are 16-bit memory word-aligned if the Datapath bit is 0. 12.2.2.2 Memory Controller Address Control The available number of accessible memory rows and columns is determined by comparing the maximum values configured with the values programmed into the HW_DRAM_CTL10_ADDR_PINS and HW_DRAM_CTL11_COLUMN_SIZE bit fields. Note that the ADDR_PINS and COLUMN_SIZE bit fields are represented as differences between the maximum configured value and the actual number of pins connected. The number of connected chip selects and their connection orientation is based on the programming in the HW_DRAM_CTL14_CS_MAP bit field. Because the internal DRAM controller supports up to 4 memory chips, this field is structured to support either one, two, or four memory chips. However, because only 2 memory chip selects are pinned out on the 169BGA package and only 1 memory chip select is pinned out on the 128QFP package, not all CS_MAP configurations can be used. Below are examples of valid system configurations for the CS_MAP bit field: * * * CS_MAP = b0001: One memory device is connected to EMI_CE0n (configuration supported in 128LQFP and 169BGA). CS_MAP = b0010: One memory device is connected to EMI_CE1n (configuration supported in 169BGA only). CS_MAP = b0011: Two memory devices are connected - one to EMI_CE0n and one to EMI_CE1n. (configuration supported in 169BGA only). 12.2.2.3 Out-of-Range Address Checking The memory controller is equipped with an out-of-range address checking feature that compares all incoming addresses against the addressable physical memory space. If a transaction is addressed to an out-of-range memory location, then bit 0 of the INT_STATUS bit field is set to 1 to alert the user of this i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-5 External Memory Interface (EMI) condition. The memory controller records the address, source ID, length and type of transaction that caused the out-of-range interrupt in the following bit fields: HW_DRAM_CTL35_OUT_OF_RANGE_ADDR HW_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID HW_DRAM_CTL21_OUT_OF_RANGE_LENGTH HW_DRAM_CTL09_OUT_OF_RANGE_TYPE Reading the out-of-range bit fields initiates the memory controller to empty these bit fields and allow them to store out-of-range access information for future errors. The interrupt should be acknowledged by setting bit 0 of the HW_DRAM_CTL16_INT_ACK bit field to 1, which will in turn cause bit 0 of the HW_DRAM_CTL18_INT_STATUS bit field to be cleared to 0. If a second out-of-range access occurs before the first out-of-range interrupt is acknowledged, then bit 1 of the INT_STATUS bit field is set to 1 to indicate that multiple out-of-range accesses have occurred. If the out-of-range bit fields have been read when the second out-of-range error occurs, then the details for this transaction are stored in the out-of-range bit fields. If they have not been read, then the details of the second error are lost. Even though the address has been identified as erroneous, the memory controller will still process the read or write transaction. A read transaction will return random data which the user must receive to avoid stalling the memory controller. A write transaction will write the associated data to an unknown location in the memory array, potentially over-writing other stored data. The command cannot be aborted once accepted into the memory controller. Note that there is no mechanism to indicate an IRQ to the ARM core when this condition occurs. These registers are provided for debugging convenience and can be used with the AHB arbiter debug trap function. To capture an out-of-range error, set an address range with the HW_DIGCTL_DEBUG_TRAP_ADDR_LOW/HIGH registers and enable the trap using HW_DIGCTL_CTRL_TRAP_ENABLE. 12.2.3 Read Data Capture The read data capture logic is responsible for capturing the DQ outputs from the DRAM devices and passing the data back to the EMI clock domain. The DQS strobes used to capture data are delayed to ensure that the rising and falling edges of the strobes are in the middle of the valid window of data. DDR (dual data rate) devices send a data strobe (DQS) signal coincident with the read data so that the read data can be reliably captured by the memory controller. The edges of this strobe are aligned with the data output by the DRAM devices. The board traces for the data and the associated data strobe signals should be routed with the same length allowing the rising and falling edges of the data strobe to arrive at the SOC pads. i.MX23 Applications Processor Reference Manual, Rev. 1 12-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) A delayed version of the data strobe signal must be used to capture the data. The delay added to the data strobe signals should be such that the margin to capture the read data is maximized. Because the frequency of the data strobe signal is matched to the system clock, the delay is a relative number based on the period of the system clock. In the example shown in Figure 12-6, the delay is set to approximately 25% of the system clock. The delay compensation circuit keeps this relative delay constant so that the read data from the DRAM devices can be reliably captured. CLK Data Strobe Data Capture Data Strobe DQS Delay Figure 12-6. DQS Read Timing 12.2.3.1 DQS Gating Control For the read path, the flight paths must be taken into consideration. There is a certain time lag from when the clock is sent from the memory controller to when the data and DQS signals are received at the memory controller from the memory. Since the DQS from the memory will be sent coincident with the data, and the data must be captured reliably, the DQS signal must be delayed so that it is centered in the data valid window (nominally approximately 1/4 cycle). The DQS bus is a bidirectional bus that is driven by the memory controller on writes and the memory on reads. When neither device is driving the bus, DQS will remain in a high-impedance state. However, DQS is only relevant to the memory controller during reads in order to capture valid data. For this reason, the DQS signal from memory must be gated so that it is ignored at all other times. Gating of the DQS signal is shown in Figure 12-7. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-7 External Memory Interface (EMI) Write Command DQS Read Command... Gate Gated DQS Figure 12-7. DQS Gating The timing of when to start gating the DQS depends on the design itself, the flight time of the clock to memory, and the flight time of the data/DQS to the memory controller, as follows: * * * If the round trip time is between 1/2 cycle and 11/2 cycles, program the caslat_lin parameter equal to the caslat parameter. If the round trip time is less than 1/2 cycle, program the caslat_lin parameter one value less (which translates to 1/2 cycle) than the caslat parameter to open the gate 1/2 cycle sooner. If the round trip time is longer than 11/2 cycles, program the caslat_lin parameter one value more (which translates to 1/2 cycle) than the caslat parameter to open the gate 1/2 cycle later. In addition, the caslat_lin_gate parameter controls the opening of the gating signal. Nominally, caslat_lin_gate should have the same value as the caslat_lin parameter. However, to accommodate the skew of the memory devices, it may be necessary to open the gate a 1/2-cycle sooner or later. Adjusting the value of caslat_lin_gate modifies the gate opening by this factor. There is a requirement that the DQS signals must be known and low when the memory controller is not driving. Because of the large variance in access times for the mobile devices, the gate for the DQS received by the memory controller must be active for longer than the period of time that the memory drives the DQS. Maintaining the DQS bus low when neither the memory controller nor the memory is driving ensures a clean DQS received by the memory controller. 12.2.3.2 mDDR Read Data Timing Registers When using an mDDR external DRAM device, control of the read data timing is provided through multiple registers, as shown in Figure 12-8. First, the HW_DRAM_CTL04_DLL_BYPASS_MODE selects whether the DCC DLL circuitry is enabled or bypassed. Programming a 1 into this register disables the DLL auto-sync functionality and instead uses a fixed delay-chain select point programmed into the HW_DRAM_CTL19_DLL_DQS_DELAY_BYPASS1 and 0 bit fields. Programming a 0 into the DLL_BYPASS_MODE field enables the DLL auto-sync mode, utilizing the HW_DRAM_CTL18_DLL_DQS_DELAY_BYPASS1 and 0 values to define the percentage of the clock period of delay to add to the DQS inputs before being used as data capture controls. The BYPASS_MODE or control bit is set based on the desired EMI_CLK frequency. At frequencies above 80 MHz, the BYPASS_MODE should be disabled, allowing the DLL to auto-sync. Frequencies below this point show enable the BYPASS_MODE. i.MX23 Applications Processor Reference Manual, Rev. 1 12-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) 12.2.4 Write Data Timing DDR DRAM devices require that the DQS data strobe arrive at the DRAM devices within a certain window around the clock. Figure 12-8 describes this relationship. The value for tdqss is specified in fractions of a clock cycle. Most DRAM devices specify this value between 0.25 and 0.2 of a clock cycle. This translates to a valid window of between 0.4 and 0.5 of a clock cycle. CLK Write Ideal Data (DQ) Ideal Data Strobe (DQS) tdqss DQS Arrival Window Figure 12-8. DRAM DQS Arrival Time Requirements The data transfer timing from the memory controller to the DRAM for writes is similar to the read transfer from the DRAM devices to the memory controller. However, there are two differences: * * The DRAM devices expect the data strobe signal to be shifted by the memory controller to allow the DRAM the maximum margin for capturing the data with the data strobe signal. The first rising edge of the data strobe signal sent from the memory controller must occur near the rising edge of the clock at the DRAM. This is called the arrival window. DRAM devices typically specify this window as 0.8clk to 1.2clk. Refer to Figure 12-9 for details. The DCC maintains two delay lines for sending write data and the write data strobe. The first delay line delays the main clock such that the write data strobe transition is as near to the clock edge at the DRAM as possible under typical operating conditions. The second delay line adjusts the clock that is used to output the write data. This clock should be adjusted to maximize the setup and hold requirements around the write strobe. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-9 External Memory Interface (EMI) CLK DQ At Controller DQS DQ Arrival window At DRAM DQS Flight DQS Write Time Delay Figure 12-9. DQS Write Timing Achieving the coincident data strobe signal arrival at a certain point in a clock cycle at the DRAM is a function of the generation of the data strobe signal and the physical delays in transmitting this signal from one point to another. Figure 12-10 illustrates this path in the memory controller. The write data sent along with the data strobe must be aligned such that the strobe rises and falls within the valid region of the data with maximum setup and hold characteristics. This translates into the write data being clocked 1/4 cycle before the rising edge of the data strobe. This relationship is illustrated in Figure 12-10. DQS CLK_WR Write Data 1/4 Cycle (ideal) Figure 12-10. Write Data and DQS Relationship The write data itself originates from a register within the core of the memory controller clocked by the EMI clock. Both the clk_wr and clk_dqs_out signals from the core clock are controlled by the programmable bit fields HW_DRAM_CTL20_WR_DQS_SHIFT and HW_DRAM_CTL19_DQS_OUT_SHIFT, i.MX23 Applications Processor Reference Manual, Rev. 1 12-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) as shown in Figure 12-11. These bit fields allow these two clocks to be delayed a fixed percentage of the core clock, as illustrated by the example in Figure 12-12. I/O PAD WRITE_DATA_OUT OEN DQ to DRAM PROGRAMMABLE DELAY EMI_CLK HW_DRAM_CTL20_WR_DQS_SHIFT PROGRAMMABLE DELAY I/O PAD EMI_CLK OEN HW_DRAM_CTL19_DQS_OUT_SHIFT DQS to DRAM Figure 12-11. Write Data with Programmable Delays DDR Clock DQS Signal at Input of I/O Cell Typical 0.58 clk DQS Signal at DRAM 0.42 clk Figure 12-12. WR_DQS_SHIFT Delay Setting Example 12.2.5 DRAM Clock Programmable Delay The i.MX23 DRAM controller uses an architecture where the address and control signals are launched from the negative edge of the internal EMI clock. The data, DQS, and DM signals are launched from the rising edge of that same clock. At certain higher clock frequencies, this architecture may cause issues with the timing of the signals at the DRAM device relative to the clock itself because the i.MX23 has less flight delay for the clock signals than the address and command signals. To compensate for this situation, a programmable delay chain is available to delay the output clock to the DRAM device. The delay chain is illustrated in Figure 12-13. This chain consists of 32 delay taps. The delay is voltage-dependent. No other output signals are affected. The control for this delay is located in the DIGCTL register space in HW_DIGCTL_EMICLK_DELAY_NUM_TAPS. By default, this delay value is 0. In practice, this is not i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-11 External Memory Interface (EMI) expected to be used, but it is available as a precaution against high board loads where the address and command signals may not have enough setup time relative to the DRAM clock at the device(s). PROGRAMMABLE DELAY I/O PAD EMI_CLK OEN HW_DIGCTL_EMICLK_DELAY_NUM_TAPS CLK to DRAM Figure 12-13. DRAM Clock Programmable Delay 12.2.6 Low-Power Operation In many applications, it is desirable to minimize the power consumption of the memory controller and the memory devices. The memory controller provides various user-configurable low-power options to address power savings. In addition, a partial-array self-refresh option is included for mobile memory devices. 12.2.6.1 Low-Power Modes There are five low-power modes available in the memory controller. The low-power modes are listed from least to most power saving. Note: It is not possible to exit one low-power mode and enter another low-power mode simultaneously. The user should plan for a minimum delay between exit and entry between the two low-power modes of 15 cycles in which the memory controller must remain stable. * Mode 1: Memory Power-Down--The memory controller sets the memory devices into power-down, which reduces the overall power consumption of the system, but has the least effect of all the low-power modes. In this mode, the memory controller and memory clocks are fully operational, but the CKE input bit to the memory devices is deasserted. The memory controller continues to monitor memory refresh needs and automatically brings the memory out of power-down to perform these refreshes. When a refresh is required, the CKE input bit to the memory devices is re-enabled. This action brings the memory devices out of power-down. Once the refresh has been completed, the memory devices are returned to power-down by deasserting the CKE input bit. Mode 2: Memory Power-Down with Memory Clock Gating--The memory controller sets the memory devices into power-down and gates off the clock to the memory devices. Refreshes are handled as in the Memory Power-Down mode (Mode 1), with the exception that gating on the memory clock is removed before asserting the CKE pin. After the refresh has been completed, the memory devices are returned to power-down with the clock gated. Before the memory devices are removed from power-down, the clock is gated on again. Although this mode is supported in both mobile and non-mobile memory devices, clock gating while in power-down is only allowed for mobile memory devices. Therefore, the memory controller will only attempt to gate the clock if it is configured for mobile device operation. For non-mobile memory devices in this low-power * i.MX23 Applications Processor Reference Manual, Rev. 1 12-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) * * * mode, the memory controller operates identically to the Memory Power-Down mode without the clock gating (Mode 1). Mode 3: Memory Self-Refresh--The memory controller sets the memory devices into self-refresh. In this mode, the memory controller and memory clocks are fully operational and the CKE input bit to the memory devices is deasserted. Since the memory automatically refreshes its contents, the memory controller does not need to send explicit refreshes to the memory. Mode 4: Memory Self-Refresh with Memory Clock Gating--The memory controller sets the memory devices into self-refresh and gates off the clock to the memory devices. Before the memory devices are removed from self-refresh, the clock is gated on again. Mode 5: Memory Self-Refresh with Memory and Controller Clock Gating--This is the deepest low-power mode of the memory controller. The memory controller sets the memory devices into self-refresh and gates off the clock to the memory devices. In addition, the clock to the memory controller and the programming bit fields are gated off, except to a small portion of the DLL, which must remain active to maintain the lock. Before the memory devices are removed from self-refresh, the memory controller and memory clocks are gated on. 12.2.6.2 * Low-Power Mode Control The memory controller may enter and exit the various low-power modes in the following ways: Automatic Entry--When the memory controller is idle, four timing counters begin counting the cycles of inactivity. If any of the counters expires, the memory controller enters the low-power mode associated with that counter. Manual Entry--The user may initiate any low-power mode by setting the bit of the LOWPOWER_CONTROL bit field associated with the desired mode. The memory controller enters the selected low-power mode when it is has completed its current burst. Hardware Entry--If the memory pins are being shared between the memory controller and an external source, a handshaking interface is used to control bus activity. The Memory Self-Refresh mode (Mode 3) of the memory controller is used to facilitate the pin sharing. * * Automatic and manual entry methods are both controlled by two bit fields: LOWPOWER_CONTROL and LOWPOWER_AUTO_ENABLE located in HW_DRAM_CTL16. The LOWPOWER_CONTROL bit field contains individual enable/disable bits for each low-power mode, and the LOWPOWER_AUTO_ENABLE bit field controls whether each mode is entered automatically or manually. 12.2.6.3 * * * * * Automatic Entry Automatic entry occurs if all of the following conditions are true: The hardware entry interface is not active or transitioning. The mode is programmed for automatic entry by setting the relevant bit in the LOWPOWER_AUTO_ENABLE bit field to 1. The particular mode is enabled in the LOWPOWER_CONTROL bit field. The memory controller is idle. The counter associated with this mode expires. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-13 External Memory Interface (EMI) There are four counters in all to cover the five low-power modes. There are separate counters for each of the three memory self-refresh low-power modes (Modes 3, 4 and 5). Memory Power-Down mode (Mode 1) and Memory Power-Down with Memory Clock Gating mode (Mode 2) share the same counter. The counters determine the number of idle cycles before entry into the associated low-power mode. All of these counters are re-initialized each time there is a new read or write transaction entering or executing in the memory controller. This ensures that the memory controller does not enter any of the low-power modes when active. All five low-power modes can be entered through automatic entry and are exited automatically when any of the following conditions occur: * * * A new read or write transaction appears at the memory controller interface. The memory controller must refresh the memory when in either of the power-down modes (Modes 1 or 2). After completing the memory refresh, the memory controller re-enters power-down. The counter for a deeper low-power mode expires. The memory controller must exit the current low-power mode in order to enter the deeper low-power mode. A minimum of 15 cycles occur between exit from one low-power mode before entering into the next low-power mode, even if the counters expire within 15 cycles of each other. Note that the memory controller does not enter a less deep low-power mode, regardless of which counters expire. 12.2.6.4 * * * Manual "On-Demand" Entry Manual entry occurs if all of the following conditions are true: The hardware entry interface is not active or transitioning. The mode is programmed for manual entry by clearing the relevant bit in the LOWPOWER_AUTO_ENABLE bit field to 0. The particular mode is set to 1 in the LOWPOWER_CONTROL bit field. For manual entry, the LOWPOWER_CONTROL bit field triggers entry into the low-power modes. The memory controller does not need to be idle when a low-power mode bit is enabled. When a particular mode that is programmed for manual entry is enabled, the memory controller completes the current memory burst access, and then, regardless of the activity inside the memory controller or at the memory interface, it enters the selected low-power mode. If new transactions enter the memory controller while it is in one of the low-power modes, they accumulate inside the memory controller's command queue until the queue is full. Exit from a manually-entered low-power mode is also manual. Clearing the LOWPOWER_CONTROL bit field bits to 0 disables the low-power mode of the memory controller, and command processing resumes. In the deepest low-power mode (Mode 5), the clock to the programming registers module is gated off. However, manual low-power mode exit requires the user to clear the LOWPOWER_CONTROL bit field to 0, which is not possible when the clock is off. As a result, the user should not manually activate the deepest low-power mode. If Memory Self-Refresh with Memory and Controller Clock Gating mode (Mode 5) is entered manually, the device cannot be brought out of low-power mode again! i.MX23 Applications Processor Reference Manual, Rev. 1 12-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) If a different LOWPOWER_CONTROL bit is set to 1 while in one of the low-power modes, or on clearing of the original bit to 0, the memory controller exits the current low-power mode. There will be at least a 15 cycle delay before the memory controller is fully operational or enters the new low-power mode. NOTE: There is a deadlock possibility that exists when using the manual low-power mode entry. If a read cycle from the ARM core occurs to the DRAM when a manual low-power mode is active, the ARM cycle does not complete. There is no other device within the SOC that can deactivate the low-power mode. Thus, the system will be deadlocked. The same can occur with multiple write cycles that will fill the two-command deep write buffer of the memory controller. 12.2.6.5 Register Programming The low-power modes of the memory controller are controlled through the LOWPOWER_CONTROL and LOWPOWER_AUTO_ENABLE bit fields in HW_DRAM_CTL16. These five-bit bit fields each contain one bit for controlling each low-power mode. The LOWPOWER_CONTROL bit field enables the associated low-power mode, and the LOWPOWER_AUTO_ENABLE bit field sets the entry method into that mode as manual or automatic. Table 12-1 shows the relationship between the five bits of the lowpower_control and lowpower_auto_enable bit fields and the various low-power modes. Table 12-1. Low-Power Mode Bit Fields Low-Power Mode Enable Entry Memory Power-Down (Mode 1) Memory Power-Down with Memory Clock Gating (Mode 2) Memory Self-Refresh (Mode 3) Memory Self-Refresh with Memory Clock Gating (Mode 4) Memory Self-Refresh with Memory and Controller Clock Gating (Mode 5) LOWPOWER_CONTROL [4] =1 LOWPOWER_AUTO_ENABLE [4] * 0 = Manual * 1 = Automatic LOWPOWER_AUTO_ENABLE [3] * 0 = Manual * 1 = Automatic LOWPOWER_AUTO_ENABLE [2] * 0 = Manual * 1 = Automatic LOWPOWER_AUTO_ENABLE [1] * 0 = Manual * 1 = Automatic LOWPOWER_AUTO_ENABLE [0] * 0 = Manual * 1 = Automatic LOWPOWER_CONTROL [3] =1 LOWPOWER_CONTROL [2] =1 LOWPOWER_CONTROL [1] =1 LOWPOWER_CONTROL [0] =1 When a LOWPOWER_CONTROL bit field bit is set to 1 by the user, the memory controller checks the LOWPOWER_AUTO_ENABLE bit field. * If the associated bit in the LOWPOWER_AUTO_ENABLE bit field is set to 1, then the memory controller watches the associated counter for expiration, and then enters that low-power mode.Table 12-2 shows the correlation between the low-power modes and the counters that control each mode's automatic entry. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-15 External Memory Interface (EMI) * If the associated bit in the LOWPOWER_AUTO_ENABLE bit field is cleared to 0, then the memory controller completes its current memory burst access and then enters the specified low-power mode. Table 12-2. Low-Power Mode Counters Low-Power Mode Counter Memory Power-Down (Mode 1) Memory Power-Down with Memory Clock Gating (Mode 2) Memory Self-Refresh (Mode 3) Memory Self-Refresh with Memory Clock Gating (Mode 4) Memory Self-Refresh with Memory and Controller Clock Gating (Mode 5) HW_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT HW_DRAM_CTL30_ LOWPOWER_POWER_DOWN_CNT HW_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT HW_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT HW_DRAM_CTL29_LOWPOWER_INTERNAL_CNT Note that the values in the LOWPOWER_AUTO_ENABLE bit field are only relevant when the associated LOWPOWER_CONTROL bit is set to 1. Multiple bits of the LOWPOWER_CONTROL and LOWPOWER_AUTO_ENABLE bit fields can be set to 1 at the same time. When this happens, the memory controller always enters the deepest low-power mode of all the modes that are enabled. If the memory controller is already in one low-power mode when a deeper low-power mode is requested automatically or manually, it must first exit the current low-power mode, and then enter the deeper low-power mode. A minimum 15-cycle delay occurs before the second entry. The timing for automatic entry into any of the low-power modes is based on the number of idle cycles that have elapsed in the memory controller. There are four counters related to the five low-power modes to determine when any particular low-power mode will be entered if the automatic entry option is chosen. The counters are also shown in Table 12-2. Since the two power-down modes share one counter, if the user wishes to enter Memory Power-Down mode (Mode 1) automatically, then the Memory Power-Down with Memory Clock Gating mode (Mode 2) must not be enabled. 12.2.6.6 Refresh Masking Regular refresh commands are issued at the same intervals while the memory controller is operating normally, is idle, or is in any of the low-power modes. However, for memory arrays with multiple chip selects, the memory controller supports the ability to mask refreshes while in any of the low-power modes. By clearing bits of the HW_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE bit field to 0, auto-refreshes will be masked for the associated chip selects. It is the user's responsibility to ensure that refreshes are not constantly masked, and that each chip select is refreshed periodically. i.MX23 Applications Processor Reference Manual, Rev. 1 12-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) 12.2.6.7 Mobile DDR Devices When using a mobile device, the HW_DRAM_CTL05_EN_LOWPOWER_MODE bit field must be set to 1. This enables the memory controller to use the initialization sequence and EMRS addressing appropriate to mobile devices. When the EN_LOWPOWER_MODE bit field is cleared to 0, a standard DDRSDRAM device may be used. 12.2.6.8 Partial Array Self-Refresh For mobile devices, the memory controller is capable of supporting refreshes to subsections of the memory array. To facilitate this capability, separate bit fields are provided to supply the EMRS data for each chip select. These are EMRS_DATA_x bit fields, where X represents the chip select. Having separate control bit fields for the EMRS data allows the individual chips to set their own masked refresh. The WRITE_MODEREG bit field controls the writing of this EMRS data into the registers. When WRITE_MODEREG is set to 1 initially, the EMRS register of chip select 0 will be written. Each subsequent setting of the WRITE_MODEREG bit field to 1 writes the EMRS register of the next chip select (1, 2, then 3). Note that the memory controller does not check if operations attempt to access addresses outside of the refresh ranges set by the EMRS registers. Any accesses to these addresses may result in corrupt or lost data. 12.2.7 EMI Clock Frequency Change Requirements Running the EMI block at different operational frequencies involves changing the DRAM controller timing registers and the EMI clock control registers (Chapter 4, "Clock Generation and Control," for the EMI clock control registers). To change the EMI frequency safely without losing current memory state, the following steps are required: 1. Call code in non-cached, non-buffered OCRAM or ROM (code cannot be executing out of DRAM). 2. Software saves interrupt enable state and disables interrupts. 3. Software flushes instruction and data caches. 4. Software puts DRAM controller in self-refresh mode. 5. Software writes new DRAM controller timing register values (this step is optional, perform if necessary). 6. Software writes new clock frequency. 7. Software polls for EMI clock stability. 8. Software takes DRAM controller out of self-refresh mode. 9. Software restores saved interrupt enable state. 10. Return. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-17 External Memory Interface (EMI) 12.3 Power Management The EMI has multiple levels of power management. Architectural power management is controlled by bits in the programmable registers. The DRAM controller also has automatic engagement of various power-saving modes that are documented in Section 12.2.6, "Low-Power Operation." The highest level of power-savings in the DRAM controller is achieved by enabling the EMI Clock Gate in the EMI Control register. When enabled, access to all PIO registers except the control register's Soft Reset and Clock Gate bits is disabled, and the DRAM controller is completely shut down. The next step in power savings is the individual DRAM clock gate, which controls the state machines and associated logic. These are also available in the EMI Control Register. Note: The DRAM control registers have a low-power setting, Level 5, that turns off the DRAM clock inside the controller. It is recommended that Level 5 of the DRAM low-power modes not be used. Instead, use Level 4, which will put the DRAM chip into a self-refresh mode and disable the external clock and CKE. Then, use the EMI Control Register clock gate for the entire EMI or the DRAM-only gate. The DRAM controller interface, however, has multiple levels of low-power options available. They are, in increasing order of power savings: 1. Memory Power-Down--Controller and EMI_CLK are active, but EMI_CKE is pulled low to the memory devices. 2. Memory Power-Down with Memory Clock Gating--The controller clock remains active, but the EMI_CLK is gated off, and EMI_CKE is pulled low. 3. Memory Self-Refresh--The controller puts the memory devices into self-refresh mode. The controller clock and EMI_CLK remain active, but EMI_CKE is pulled low. 4. Memory Self-Refresh with Memory Clock Gating--The controller puts the memory devices into self-refresh mode. The controller clock remains active, but the EMI_CLK is gated off, and EMI_CKE is pulled low. 5. Memory Self-Refresh with Controller and Memory Clock Gating--The controller puts the memory devices into self-refresh mode. Then, the controller and EMI_CLK are gated off. The only clock that remains active is the clock to the DLL, which must remain active to maintain DLL lock. The DRAM controller can be programmed to enter these modes automatically, or they can be entered manually via control register accesses. It is expected that Freescale software will set up the DRAM controller to automatically enter modes 1 and 2, but that modes 3-4 would be entered manually after specific requests from the software. Avoid using Level 5. 12.4 AXI/AHB Port Arbitration The EMI port arbiter supports three operational arbitration modes. The arbiter is provided with PIO control fields, including a two bit HW_EMI_CTRL_ARB_MODE field, which selects one of the three modes. The three arbitration modes are described below. i.MX23 Applications Processor Reference Manual, Rev. 1 12-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) 12.4.1 Legacy Timestamp Mode When commands are logged into one of the four command queue channels, they are issued a 6-bit sequential count or timestamp. The commands in these four independent channels are then granted access to the downstream controller placement queue in strict timestamp order. The grant decision is simple and is purely combinational in design. Waiting commands can be granted every cycle provided that the placement queue isn't full. 12.4.2 Timestamp/write-priority Hybrid Mode This new arbitration mode consists of cycling through 2 different priority modes: the legacy timestamp mode (described above) and a new write priority mode. The arbiter first grants a requesting channel based on the timestamp scheme and then goes into the write priority mode. There it loops though all the high priority write channels (3 of the channels can be programmed as high priority write: AXI0, AHB2 and AHB3) a programmed number of iterations granting pending write operations only. It then goes back to timestamp priority mode to grant the operation with the next oldest timestamp. The cycle thus continues alternating between the timestamp and write priority modes. It is important to remember that in the write-priority mode one iteration means to loop through all high priority ports once granting ports with pending commands. And the order in which we consider (or scan through) each port is fixed. The hardware loops through the ports 2, 3 and 0 granting pending commands, in that order. This constitutes one iteration. And this is done repeatedly for the number of iterations programmed. The ordering was set by considering the importance, or priority, of writes of the various masters attached to these busses and therefore is chip specific. The arbiter receives three 1-bit high priority write masks (HW_EMI_CTRL_HIGH_PRIORITY_WRITE) which select the ports to be given high priority write status. It is also be provided with a 3-bit HP write loop count (HW_EMI_CTRL_PRIORITY_WRITE_ITER), which indicates the maximum number of iterations through the write loop. The write loop will exit when there are no more high priority writes available or when the loop counter reaches the maximum loop count value. The high priority write loop could be skipped if no HP writes are pending. The maximum loop count allowed is 5. These two parameters are PIO programmable. In practice, software would likely set the ARM data port to have high priority write status and the maximum loop counter would likely be programmed to a value of at least two. This would give highly preferential treatment to ARM data writes and ensure that they get additional commands into the memory controller's placement queue ahead of all other commands. By looping on the writes, we also enable the memory controller to get a stream of write operations that should improve efficiency. Since the arbiter moves back into the timestamp loop periodically, low-priority ports should still have reasonable access to the placement queue. If problems with starvation occur, the maximum loop counter should be programmed to a lower value. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-19 External Memory Interface (EMI) 12.4.3 Port Priority Mode This mode requires the user to program the ports to have a highest to lowest priority. When multiple ports have commands pending, the port with the highest priority will always be granted without regard to timestamp. This mode does not address the problem of possible port starvation. This mode doesn't inherently guarantee that a read cannot get out of order with a previously issued address-paired write and return stale data. The two previously defined modes guarantee this. However, based on the typical use case, this scenario should only occur on certain port pairs. So if care is taken when programming the port priorities this mode will avoid such errors in this typical case. This mode is very simple, efficient and fully programmable. For this mode it is recommended that the default value be used for the HW_EMI_CTRL_PORT_PRIORITY_ORDER field. 12.5 Programmable Registers This section describes the programmable registers of the external memory interface (EMI). 12.5.1 EMI Control Register Description HW_EMI_CTRL HW_EMI_CTRL_SET HW_EMI_CTRL_CLR HW_EMI_CTRL_TOG Table 12-3. HW_EMI_CTRL 0x000 0x004 0x008 0x00C EMI Interface Control Register. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 DLL_SHIFT_RESET 2 4 2 3 2 2 2 1 2 0 1 9 1 8 PORT_PRIORITY_ORDER 1 7 1 6 1 5 1 4 1 3 PRIORITY_WRITE_ITER 1 2 1 1 1 0 0 9 HIGH_PRIORITY_WRITE 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 MEM_WIDTH RESET_OUT DLL_RESET ARB_MODE AXI_DEPTH TRAP_INIT TRAP_SR SFTRST RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 i.MX23 Applications Processor Reference Manual, Rev. 1 12-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSVD0 External Memory Interface (EMI) Table 12-4. HW_EMI_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Reset EMI register block. 0 = EMI controller is not reset. 1 = EMI controller is reset. Note: This soft reset only affects the EMI registers . There is also a soft-reset for the DRAM controller in the DRAM registers. Reserved When set, causes an AHB ERROR response on any access to the DRAM memory space if the DRAM controller is in Self-Refresh mode. When set, causes an AHB ERROR response on any access to the DRAM memory space if the DRAM controller has not been initialized (specifically when START is not set). Specifies the number of commands allowed in the AXI port queue. ONE = 0x0 Allow only one command. TWO = 0x1 Allow two commands. THREE = 0x2 Allow three commands. FOUR = 0x3 Allow four commands. 30 29 RSVD6 TRAP_SR RO 0x0 RW 0x0 28 TRAP_INIT RW 0x1 27:26 AXI_DEPTH RW 0x3 25 24 DLL_SHIFT_RESET DLL_RESET RW 0x0 RW 0x0 RW 0x0 23:22 ARB_MODE When set, forces the DRAM controller DLL startpoint shift logic into a reset state. When set, forces the DRAM controller into a reset state. This field sets the arbitration mode for the DRAM port controller. The supported arbitration schemes are: simple timestamp priority method; enhanced high-priority write and timestamp hibrid method; and port priority method. The programming options are: TIMESTAMP = 0x0 Timestamp Priority (37xx arbitration) WRITE_HYBRID = 0x1 Write Priority Hybrid PORT_PRIORITY = 0x2 Fixed Port Priority 21 RSVD5 20:16 PORT_PRIORITY_ORDER RO 0x0 RW 0x8 Reserved This field specifies the priority order 1-4 (1= highest priority) of the 4 arbitrated ports. The field values define the following order (highest to lowest): (NOTE: Values 0x18-0x1F select PORT1230.) PORT0123 = 0x00 Priority Order: AXI0, AHB1, AHB2, AHB3 PORT0312 = 0x01 Priority Order: AXI0, AHB3, AHB1, AHB2 PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1 PORT0321 = 0x03 Priority Order: AXI0, AHB3, AHB2, AHB1 PORT0213 = 0x04 Priority Order: AXI0, AHB2, AHB1, AHB3 PORT0132 = 0x05 Priority Order: AXI0, AHB1, AHB3, AHB2 PORT1023 = 0x06 Priority Order: AHB1, AXI0, AHB2, AHB3 PORT1302 = 0x07 Priority Order: AHB1, AHB3, AXI0, AHB2 PORT1230 = 0x08 Priority Order: AHB1, AHB2, AHB3, AXI0 PORT1320 = 0x09 Priority Order: AHB1, AHB3, AHB2, AXI0 PORT1203 = 0x0A Priority Order: AHB1, AHB2, AXI0, AHB3 PORT1032 = 0x0B Priority Order: AHB1, AXI0, AHB3, AHB2 PORT2013 = 0x0C Priority Order: AHB2, AXI0, AHB1, AHB3 PORT2301 = 0x0D Priority Order: AHB2, AHB3, AXI0, AHB1 PORT2130 = 0x0E Priority Order: AHB2, AHB1, AHB3, AXI0 PORT2310 = 0x0F Priority Order: AHB2, AHB3, AHB1, AXI0 PORT2103 = 0x10 Priority Order: AHB2, AHB1, AXI0, AHB3 PORT2031 = 0x11 Priority Order: AHB2, AXI0, AHB3, AHB1 PORT3012 = 0x12 Priority Order: AHB3, AXI0, AHB1, AHB2 PORT3201 = 0x13 Priority Order: AHB3, AHB2, AXI0, AHB1 PORT3120 = 0x14 Priority Order: AHB3, AHB1, AHB2, AXI0 PORT3210 = 0x15 Priority Order: AHB3, AHB2, AHB1, AXI0 PORT3102 = 0x16 Priority Order: AHB3, AHB1, AXI0, AHB2 PORT3021 = 0x17 Priority Order: AHB3, AXI0, AHB2, AHB1 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-21 External Memory Interface (EMI) Table 12-4. HW_EMI_CTRL Bit Field Descriptions BITS LABEL 15 RSVD4 14:12 PRIORITY_WRITE_ITER RW RESET RO 0x0 RW 0x4 DEFINITION 11 10:8 RSVD3 HIGH_PRIORITY_WRITE RO 0x0 RW 0x0 7 6 5 4 3:0 RSVD2 MEM_WIDTH RSVD1 RESET_OUT RSVD0 RO 0x0 RW 0x1 RO 0x0 RW 0x0 RO 0x0 Reserved When the hybrid port arbitration scheme is enabled, this field specifies how many times to iterate through the high-priority write phase. This field's range is 1-5 iterations. NOTE: The number of iterations is this field value plus 1. Reserved Specifies which AHB ports to the EMI have high write priority when the enhanced memory arbitration scheme is enabled. When set bits 12-14 specify high priority for AHB0, AHB2 and AHB3 respectively. The ports are defined as follows: AXI0 = DCP/BCH/PXP port, AHB2 = ARM Data, AHB3 = USB/DMA/ECC8. Reserved 0 = 8-bit memory. 1 = 16-bit memory. Reserved 0 = Reset output is low. 1 = Reset output is high. Reserved DESCRIPTION: The EMI Control register is used to control several high-level items related to the EMI controller. This register should be used in conjunction with the DRAM register bits. EXAMPLE: Empty Example. 12.5.2 EMI Version Register Description HW_EMI_VERSION Table 12-5. HW_EMI_VERSION 0x0F0 This register always returns a known read value for debug purposes. It indicates the version of the block. 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 12-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) Table 12-6. HW_EMI_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x02 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x01 RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: Empty Example. EMI Block v2.1, Revision 1 12.5.3 DRAM Control Register 00 Description HW_DRAM_CTL00 Table 12-7. HW_DRAM_CTL00 0x000 DRAM control register. See bit fields for detailed descriptions. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 AHB0_W_PRIORITY 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 AHB0_R_PRIORITY 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB0_FIFO_TYPE_REG 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 12-8. HW_DRAM_CTL00 Bit Field Descriptions BITS LABEL 31:25 RSVD4 AHB0_W_PRIORITY 24 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Priority of write commands from port 0. Sets the priority of write commands from AHB port 0 relative to the other AHB Ports. A value of 0 is the highest priority. Reserved. Priority of read commands from port 0. Sets the priority of read commands from AHB port 0 relative to the other AHB Ports. A value of 0 is the highest priority. 23:17 RSVD3 AHB0_R_PRIORITY 16 RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice ADDR_CMP_EN RSVD4 RSVD3 RSVD2 RSVD1 12-23 External Memory Interface (EMI) Table 12-8. HW_DRAM_CTL00 Bit Field Descriptions BITS LABEL 15:9 RSVD2 AHB0_FIFO_TYPE_REG 8 RW RESET RO 0x0 RW 0x0 DEFINITION 7:1 0 RSVD1 ADDR_CMP_EN RO 0x0 RW 0x0 Reserved. Clock domain relativity between port 0 and memory controller core. Sets the relativity of the clock domains between AHB port 0 and the memory controller core clock. 0 = Asynchronous 1 = Synchronous Reserved. Enable address collision detection for command queue placement logic. Enables address collision/data coherency detection as a condition when using the placement logic to fill the command queue. 0 = Disabled 1 = Enabled DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.4 DRAM Control Register 01 Description HW_DRAM_CTL01 Table 12-9. HW_DRAM_CTL01 0x004 DRAM control register. See bit fields for detailed descriptions. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 AHB2_FIFO_TYPE_REG 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 AHB1_W_PRIORITY 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB1_R_PRIORITY 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 AHB1_FIFO_TYPE_REG RSVD4 RSVD3 RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 12-24 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor External Memory Interface (EMI) Table 12-10. HW_DRAM_CTL01 Bit Field Descriptions BITS LABEL 31:25 RSVD4 AHB2_FIFO_TYPE_REG 24 RW RESET RO 0x0 RW 0x0 DEFINITION 23:17 RSVD3 AHB1_W_PRIORITY 16 RO 0x0 RW 0x0 15:9 8 RSVD2 AHB1_R_PRIORITY RO 0x0 RW 0x0 7:1 0 RSVD1 AHB1_FIFO_TYPE_REG RO 0x0 RW 0x0 Reserved. Clock domain relativity between port 2 and memory controller core. Sets the relativity of the clock domains between AHB port 2 and the memory controller core clock. 0 = Asynchronous 1 = Synchronous Reserved. Priority of write commands from port 1. Sets the priority of write commands from AHB port 1 relative to the other AHB Ports. A value of 0 is the highest priority. Reserved. Priority of read commands from port 1. Sets the priority of read commands from AHB port 1 relative to the other AHB Ports. A value of 0 is the highest priority. Reserved. Clock domain relativity between port 1 and memory controller core. Sets the relativity of the clock domains between AHB port 1 and the memory controller core clock. 0 = Asynchronous 1 = Synchronous DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.5 DRAM Control Register 02 Description HW_DRAM_CTL02 Table 12-11. HW_DRAM_CTL02 0x008 DRAM control register. See bit fields for detailed descriptions. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 AHB3_R_PRIORITY 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 AHB3_FIFO_TYPE_REG 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 AHB2_W_PRIORITY 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 AHB2_R_PRIORITY RSVD4 RSVD3 RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 12-25 External Memory Interface (EMI) Table 12-12. HW_DRAM_CTL02 Bit Field Descriptions BITS LABEL 31:25 RSVD4 AHB3_R_PRIORITY 24 RW RESET RO 0x0 RW 0x0 DEFINITION 23:17 RSVD3 AHB3_FIFO_TYPE_REG 16 RO 0x0 RW 0x0 15:9 8 RSVD2 AHB2_W_PRIORITY RO 0x0 RW 0x0 7:1 0 RSVD1 AHB2_R_PRIORITY RO 0x0 RW 0x0 Reserved. Priority of read commands from port 3. Sets the priority of read commands from AHB port 3 relative to the other AHB Ports. A value of 0 is the highest priority. Reserved. Clock domain relativity between port 3 and memory controller core. Sets the relativity of the clock domains between AHB port 3 and the memory controller core clock. 0 = Asynchronous 1 = Synchronous Reserved. Priority of write commands from port 2. Sets the priority of write commands from AHB port 2 relative to the other AHB Ports. A value of 0 is the highest priority. Reserved. Priority of read commands from port 2. Sets the priority of read commands from AHB port 2 relative to the other AHB Ports. A value of 0 is the highest priority. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.6 DRAM Control Register 03 Description HW_DRAM_CTL03 Table 12-13. HW_DRAM_CTL03 0x00C DRAM control register. See bit fields for detailed descriptions. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 AUTO_REFRESH_MODE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 AHB3_W_PRIORITY AREFRESH RSVD4 RSVD3 RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 12-26 Preliminary--Subject to Change Without Notice RSVD1 AP Freescale Semiconductor External Memory Interface (EMI) Table 12-14. HW_DRAM_CTL03 Bit Field Descriptions BITS LABEL 31:25 RSVD4 AUTO_REFRESH_MODE 24 RW RESET RO 0x0 RW 0x0 DEFINITION 23:17 RSVD3 AREFRESH 16 RO 0x0 W 0x0 O 15:9 8 RSVD2 AP RO 0x0 RW 0x0 7:1 0 RSVD1 AHB3_W_PRIORITY RO 0x0 RW 0x0 Reserved. Controls whether auto-refresh will be at next burst or next command boundary. Sets the mode for when the automatic refresh will occur. If auto_refresh_mode is set and a refresh is required to memory, the memory controller will delay this refresh until the end of the current transaction (if the transaction is fully contained inside a single page), or until the current transaction hits the end of the current page. 0 = Issue refresh on the next DRAM burst boundary, even if the current command is not complete. 1 = Issue refresh on the next command boundary. Reserved. Initiate auto-refresh when specified by AUTO_REFRESH_MODE. Initiates an automatic refresh to the DRAM devices based on the setting of the AUTO_REFRESH_MODE bit field. If there are any open banks when this bit field is set, the memory controller will automatically close these banks before issuing the auto-refresh command. This bit field will always read back 0. 0 = No action 1 = Issue refresh to the DRAM devices Reserved. Enable auto pre-charge mode of controller. Enables auto pre-charge mode for DRAM devices. NOTE: This bit field may not be modified after the START bit field has been asserted. 0 = Auto pre-charge mode disabled. Memory banks will stay open until another request requires this bank, the maximum open time (tras_max) has elapsed, or a refresh command closes all the banks. 1 = Auto pre-charge mode enabled. All read and write transactions must be terminated by an auto pre-charge command. If a transaction consists of multiple read or write bursts, only the last command is issued with an auto pre-charge. Reserved. Priority of write commands from port 3. Sets the priority of write commands from AHB port 3 relative to the other AHB Ports. A value of 0 is the highest priority. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-27 External Memory Interface (EMI) 12.5.7 DRAM Control Register 04 Description HW_DRAM_CTL04 Table 12-15. HW_DRAM_CTL04 0x010 DRAM control register. See bit fields for detailed descriptions. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 DLL_BYPASS_MODE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 DLLLOCKREG 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 CONCURRENTAP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BANK_SPLIT_EN RSVD4 RSVD3 RSVD2 Table 12-16. HW_DRAM_CTL04 Bit Field Descriptions BITS LABEL 31:25 RSVD4 DLL_BYPASS_MODE 24 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Enable the DLL bypass feature of the controller. Defines the behavior of the DLL bypass logic and establishes which set of delay parameters will be used. 0 = The values programmed in the DLL_DQS_DELAY_X, DQS_OUT_SHIFT, and WR_DQS_SHIFT are used. These parameters add fractional increments of the clock to the specified lines. 1 = The values programmed into the DLL_DQS_DELAY_BYPASS_X, DQS_OUT_SHIFT_BYPASS, and WR_DQS_SHIFT_BYPASS are used. These parameters specify the actual number of delay elements added to each of the lines. If the total delay time programmed into the delay parameters exceeds the number of delay elements in the delay chain, then the delay will be set to the maximum number of delay elements in the delay chain. 0 = Normal operational atuo-sync mode. 1 = Bypass the auto-sync DLL master delay line. Reserved. Status of DLL lock coming out of master delay. DLL lock/unlock. Reserved. Allow controller to issue commands to other banks while a bank is in auto pre-charge. Enables concurrent auto pre-charge. Some DRAM devices do not allow one bank to be auto pre-charged while another bank is reading or writing. The JEDEC standard allows concurrent auto pre-charge. Set this parameter for the DRAM device being used. 0 = Concurrent auto pre-charge disabled. 1 = Concurrent auto pre-charge enabled. 23:17 RSVD3 DLLLOCKREG 16 15:9 8 RSVD2 CONCURRENTAP RO 0x0 RO 0x0 RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 12-28 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor External Memory Interface (EMI) Table 12-16. HW_DRAM_CTL04 Bit Field Descriptions BITS LABEL 7:1 RSVD1 BANK_SPLIT_EN 0 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Enable bank splitting for command queue placement logic. Enables bank splitting as a condition when using the placement logic to fill the command queue. 0 = Disabled 1 = Enabled DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.8 DRAM Control Register 05 Description HW_DRAM_CTL05 Table 12-17. HW_DRAM_CTL05 0x014 DRAM control register. See bit fields for detailed descriptions. 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 EN_LOWPOWER_MODE INTRPTAPBURST INTRPTREADA FAST_WRITE RSVD4 RSVD3 RSVD2 Table 12-18. HW_DRAM_CTL05 Bit Field Descriptions BITS LABEL 31:25 RSVD4 INTRPTREADA 24 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Allow the controller to interrupt a combined read with auto pre-charge command with another read command. Enables interrupting of a combined read with auto pre-charge command with another read command to the same bank before the first read command is completed. 0 = Disable interrupting the combined read with auto pre-charge command with another read command to the same bank. 1 = Enable interrupting the combined read with auto pre-charge command with another read command to the same bank. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 12-29 External Memory Interface (EMI) Table 12-18. HW_DRAM_CTL05 Bit Field Descriptions BITS LABEL 23:17 RSVD3 INTRPTAPBURST 16 RW RESET RO 0x0 RW 0x0 DEFINITION 15:9 8 RSVD2 FAST_WRITE RO 0x0 RW 0x0 7:1 0 RSVD1 EN_LOWPOWER_MODE RO 0x0 RW 0x0 Reserved. Allow the controller to interrupt an auto pre-charge command with another command. Enables interrupting an auto pre-charge command with another command for a different bank. If enabled, the current operation will be interrupted. However, the bank will be pre-charged as if the current operation were allowed to continue. 0 = Disable interrupting an auto pre-charge operation on a different bank. 1 = Enable interrupting an auto pre-charge operation on a different bank. Reserved. Sets when write commands are issued to DRAM devices. Controls when the write commands are issued to the DRAM devices. 0 = The memory controller will issue a write command to the DRAM devices when it has received enough data for one DRAM burst. In this mode, write data can be sent in any cycle relative to the write command. This mode also allows for multi-word write command data to arrive in non-sequential cycles. 1 = The memory controller will issue a write command to the DRAM devices after the first word of the write data is received by the memory controller. The first word can be sent at any time relative to the write command. In this mode, multi-word write command data must be available to the memory controller in sequential cycles. Reserved. Enable low-power mode in controller. Enables the low-power mode of the memory controller. 0 = Disabled 1 = Enabled DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.9 DRAM Control Register 06 Description HW_DRAM_CTL06 0x018 DRAM control register. See bit fields for detailed descriptions. i.MX23 Applications Processor Reference Manual, Rev. 1 12-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) Table 12-19. HW_DRAM_CTL06 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 POWER_DOWN 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 PLACEMENT_EN 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 NO_CMD_INIT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 INTRPTWRITEA RSVD4 RSVD3 RSVD2 Table 12-20. HW_DRAM_CTL06 Bit Field Descriptions BITS LABEL 31:25 RSVD4 POWER_DOWN 24 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Disable clock enable and set DRAMs in power-down state. When this bit field is written with a 1, the memory controller will complete processing of the current burst for the current transaction (if any), issue a pre-charge all command and then disable the clock enable signal to the DRAM devices. Any subsequent commands in the command queue will be suspended until this bit field is written with a 0. 0 = Enable full power state. 1 = Disable the clock enable and power down the memory controller. Reserved. Enable placement logic for command queue. Enables using the placement logic to fill the command queue. 0 = Placement logic is disabled. The command queue is a straight FIFO. 1 = Placement logic is enabled. The command queue will be filled according to the placement logic factors. Reserved. Disable DRAM commands until TDLL has expired during initialization. Disables DRAM commands until DLL initialization is complete and tdll has expired. 0 = Issue only REF and PRE commands during DLL initialization of the DRAM devices. 1 = Do not issue any type of command during DLL initialization of the DRAM devices. Reserved. Allow the controller to interrupt a combined write with auto pre-charge command with another write command. Enables interrupting of a combined write with auto pre-charge command with another read or write command to the same bank before the first write command is completed. 0 = Disable interrupting a combined write with auto pre-charge command with another read or write command to the same bank. 1 = Enable interrupting a combined write with auto pre-charge command with another read or write command to the same bank. 23:17 RSVD3 PLACEMENT_EN 16 RO 0x0 RW 0x0 15:9 8 RSVD2 NO_CMD_INIT RO 0x0 RW 0x0 7:1 0 RSVD1 INTRPTWRITEA RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 12-31 External Memory Interface (EMI) DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.10 DRAM Control Register 07 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL07 Table 12-21. HW_DRAM_CTL07 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RW_SAME_EN 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 REG_DIMM_ENABLE 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x01C RD2RD_TURN Table 12-22. HW_DRAM_CTL07 Bit Field Descriptions BITS LABEL 31:25 RSVD4 RW_SAME_EN 24 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Enable read/write grouping for command queue placement logic. Enables read/write grouping as a condition when using the placement logic to fill the command queue. 0 = Disabled 1 = Enabled Reserved. Enable registered DIMM operation of the controller. Enables registered DIMM operations to control the address and command pipeline of the memory controller. 0 = Normal operation 1 = Enable registered DIMM operation Reserved. 23:17 RSVD3 REG_DIMM_ENABLE 16 RO 0x0 RW 0x0 15:9 RSVD2 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 12-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor PRIORITY_EN RSVD4 RSVD3 RSVD2 RSVD1 External Memory Interface (EMI) Table 12-22. HW_DRAM_CTL07 Bit Field Descriptions BITS LABEL 8 RD2RD_TURN RW RESET RW 0x0 DEFINITION Enable insertion of addition turn around clock for back to back reads to different css. Adds an additional clock between back-to-back read operations. The extra clock is required for mobile DDR devices where tac_max > (period/2 + tac_min). Without this additional clock, the first read may drive DQS out at tac_max and the second read may drive DQS out at tac_min, resulting in a contention on the DQS line. 0 = Disabled 1 = Enabled Reserved. Enable priority for command queue placement logic. Enables priority as a condition when using the placement logic to fill the command queue. 0 = Disabled 1 = Enabled 7:1 0 RSVD1 PRIORITY_EN RO 0x0 RW 0x0 DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.11 DRAM Control Register 08 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL08 Table 12-23. HW_DRAM_CTL08 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 TRAS_LOCKOUT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 SREFRESH 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SDR_MODE 0x020 RSVD4 RSVD3 RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 START 12-33 External Memory Interface (EMI) Table 12-24. HW_DRAM_CTL08 Bit Field Descriptions BITS LABEL 31:25 RSVD4 TRAS_LOCKOUT 24 RW RESET RO 0x0 RW 0x0 DEFINITION 23:17 RSVD3 START 16 RO 0x0 RW 0x0 15:9 8 RSVD2 SREFRESH RO 0x0 RW 0x0 7:1 0 RSVD1 SDR_MODE RO 0x0 RW 0x0 Reserved. Allow the controller to execute auto pre-charge commands before TRAS_MIN expires. Defines the tRAS lockout setting for the DRAM device. tRAS lockout allows the memory controller to execute auto pre-charge commands before the TRAS_MIN parameter has expired. 0 = tRAS lockout not supported by memory device. 1 = tRAS lockout supported by memory device. Reserved. Initiate command processing in the controller. With this bit field cleared to 0, the memory controller will not issue any commands to the DRAM devices or respond to any signal activity except for reading and writing bit fields. Once this bit field is set to 1, the memory controller will respond to inputs from the ASIC. When set, the memory controller begins its initialization routine. When the interrupt bit in the INT_STATUS bit field associated with completed initialization is set, the user may begin to submit transactions. 0 = Controller is not in active mode. 1 = Initiate active mode for the memory controller. Reserved. Place DRAMs in self-refresh mode. When this bit field is written with a 1, the DRAM device(s) will be placed in self-refresh mode. For this, the current burst for the current transaction (if any) will complete, all banks will be closed, the self-refresh command will be issued to the DRAM, and the clock enable signal will be de-asserted. The system will remain in self-refresh mode until this bit field is written with a 0. The DRAM devices will return to normal operating mode after the self-refresh exit time (txsr) of the device and any DLL initialization time for the DRAM is reached. The memory controller will resume processing of the commands from the interruption point. This bit field will be updated with an assertion of the srefresh_enter pin, regardless of the behavior on the register interface. To disable self-refresh again after a srefresh_enter pin assertion, the user will need to clear the bit field to 0. 0 = Disable self-refresh mode. 1 = Initiate self-refresh of the DRAM devices. Reserved. Select SDR or DDR mode of the controller. Selects between SDR (single data rate) and DDR (dual data rate) modes. 0 = DDR mode 1 = SDR mode DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions i.MX23 Applications Processor Reference Manual, Rev. 1 12-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) EXAMPLE: Empty Example. 12.5.12 DRAM Control Register 09 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL09 Table 12-25. HW_DRAM_CTL09 3 1 3 0 2 9 2 8 2 7 2 6 2 5 OUT_OF_RANGE_TYPE 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 OUT_OF_RANGE_SOURCE_ID 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x024 WRITE_MODEREG Table 12-26. HW_DRAM_CTL09 Bit Field Descriptions BITS LABEL 31:26 RSVD4 25:24 OUT_OF_RANGE_TYPE RW RESET RO 0x0 RO 0x0 DEFINITION Reserved. Type of command that caused an Out-of-Range interrupt. Holds the type of command that caused an out-of-range interrupt request to the memory devices. Reserved. Source ID of command that caused an Out-of-Range interrupt. Holds the Source ID of the command that caused an out-of-range interrupt request to the memory devices. Reserved. Write EMRS data to the DRAMs. Supplies the EMRS data for each chip select to allow individual chips to set masked refreshing. When this bit field is written with a 1, the mode bit field(s) [EMRS register] within the DRAM devices will be written. Each subsequent write_modereg setting will write the EMRS register of the next chip select. This bit field will always read back as 0. The mode registers are automatically written at initialization of the memory controller. There is no need to initiate a mode register write after setting the START bit field in the memory controller unless some value in these registers needs to be changed after initialization. Note: This bit field may not be changed when the memory is in power-down mode (when the CKE input is de-asserted). 23:18 RSVD3 RO 0x0 17:16 OUT_OF_RANGE_SOURCE_I RO 0x0 D 15:9 8 RSVD2 WRITE_MODEREG RO 0x0 W 0x0 O i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice WRITEINTERP RSVD4 RSVD3 RSVD2 RSVD1 12-35 External Memory Interface (EMI) Table 12-26. HW_DRAM_CTL09 Bit Field Descriptions BITS LABEL 7:1 RSVD1 WRITEINTERP 0 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Allow controller to interrupt a write bursts to the DRAMs with a read command. Defines whether the memory controller can interrupt a write burst with a read command. Some memory devices do not allow this functionality. 0 = The device does not support read commands interrupting write commands. 1 = The device does support read commands interrupting write commands. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.13 DRAM Control Register 10 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL10 Table 12-27. HW_DRAM_CTL10 3 1 3 0 2 9 2 8 2 7 2 6 2 5 AGE_COUNT 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 ADDR_PINS 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 TEMRS 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 Q_FULLNESS 0 0 0x028 RSVD4 RSVD3 RSVD2 Table 12-28. HW_DRAM_CTL10 Bit Field Descriptions BITS LABEL 31:27 RSVD4 26:24 AGE_COUNT RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Initial value of master aging-rate counter for command aging. Holds the initial value of the master aging-rate counter. When using the placement logic to fill the command queue, the command aging counters will be decremented one each time the master aging-rate counter counts down age_count cycles. Reserved. 23:19 RSVD3 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 12-36 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor External Memory Interface (EMI) Table 12-28. HW_DRAM_CTL10 Bit Field Descriptions BITS LABEL 18:16 ADDR_PINS RW RESET RW 0x0 DEFINITION Difference between number of address pins available and number being used. Defines the difference between the maximum number of address pins configured (13) and the actual number of pins being used. The user address is automatically shifted so that the user address space is mapped contiguously into the memory map based on the value of this bit field. Reserved. DRAM TEMRS parameter in cycles. Defines the DRAM extended mode parameter set time, in cycles. Reserved. Quantity that determines command queue full. Defines quantity of data that will be considered full for the command queue. 15:10 RSVD2 TEMRS 9:8 7:2 1:0 RSVD1 Q_FULLNESS RO 0x0 RW 0x0 RO 0x0 RW 0x0 DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.14 DRAM Control Register 11 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL11 Table 12-29. HW_DRAM_CTL11 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 COMMAND_AGE_COUNT 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x02C COLUMN_SIZE MAX_CS_REG Table 12-30. HW_DRAM_CTL11 Bit Field Descriptions BITS LABEL 31:27 RSVD4 26:24 MAX_CS_REG RW RESET RO 0x0 RO 0x4 DEFINITION Reserved. Maximum number of chip selects available. Defines the maximum number of chip selects for the memory controller as the log2 of the number of chip selects. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice CASLAT RSVD4 RSVD3 RSVD2 RSVD1 12-37 External Memory Interface (EMI) Table 12-30. HW_DRAM_CTL11 Bit Field Descriptions BITS LABEL 23:19 RSVD3 18:16 COMMAND_AGE_COUNT RW RESET RO 0x0 RW 0x0 DEFINITION 15:11 RSVD2 10:8 COLUMN_SIZE RO 0x0 RW 0x0 7:3 2:0 RSVD1 CASLAT RO 0x0 RW 0x0 Reserved. Initial value of individual command aging counters for command aging. Holds the initial value of the command aging counters associated with each command in the command queue. When using the placement logic to fill the command queue, the command aging counters decrement one each time the master aging-rate counter counts down age_count cycles. Reserved. Difference between number of column pins available and number being used. Shows the difference between the maximum column width available (12) and the actual number of column pins being used. The user address is automatically shifted so that the user address space is mapped contiguously into the memory map based on the value of this bit field. Reserved. Encoded CAS latency sent to DRAMs during initialization. Sets the CAS (Column Address Strobe) latency encoding that the memory uses. The binary value programmed into this bit field is dependent on the memory device, since the same caslat value may have different meanings to different memories. This will be programmed into the DRAM devices at initialization. The CAS encoding will be specified in the DRAM spec sheet, and should correspond to the CASLAT_LIN bit field. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.15 DRAM Control Register 12 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL12 Table 12-31. HW_DRAM_CTL12 3 1 3 0 2 9 RSVD3 2 8 2 7 2 6 2 5 TWR_INT 2 4 2 3 2 2 2 1 RSVD2 2 0 1 9 1 8 1 7 TRRD 1 6 1 5 1 4 1 3 1 2 OBSOLETE 1 1 1 0 0 9 0 8 0 7 0 6 0 5 RSVD1 0 4 0 3 0 2 0 1 TCKE 0 0 0x030 i.MX23 Applications Processor Reference Manual, Rev. 1 12-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) Table 12-32. HW_DRAM_CTL12 Bit Field Descriptions BITS LABEL 31:27 RSVD3 26:24 TWR_INT RW RESET RO 0x0 RW 0x0 DEFINITION 23:19 RSVD2 18:16 TRRD 15:8 7:3 2:0 OBSOLETE RSVD1 TCKE RO 0x0 RW 0x0 RO 0x0 RO 0x0 RW 0x0 Reserved. DRAM TWR parameter in cycles. Defines the DRAM write recovery time, in cycles. Reserved. DRAM TRRD parameter in cycles. Defines the DRAM activate to activate delay for different banks, in cycles. Reserved. Reserved. Minimum CKE pulse width. Defines the minimum CKE pulse width, in cycles. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.16 DRAM Control Register 13 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL13 Table 12-33. HW_DRAM_CTL13 3 1 3 0 2 9 2 8 2 7 2 6 CASLAT_LIN_GATE 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 CASLAT_LIN 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x034 APREBIT RSVD4 RSVD3 RSVD2 RSVD1 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice TWTR 12-39 External Memory Interface (EMI) Table 12-34. HW_DRAM_CTL13 Bit Field Descriptions BITS LABEL 31:28 RSVD4 27:24 CASLAT_LIN_GATE RW RESET RO 0x0 RW 0x0 DEFINITION 23:20 RSVD3 19:16 CASLAT_LIN RO 0x0 RW 0x0 15:12 RSVD2 11:8 APREBIT RO 0x0 RW 0x0 7:3 2:0 RSVD1 TWTR RO 0x0 RW 0x0 Reserved. Adjusts data capture gate open by half cycles. Adjusts the data capture gate open time by 1/2 cycle increments. This bit field is programmed differently than CASLAT_LIN when there are fixed offsets in the flight path between the memories and the memory controller for clock gating. When CASLAT_LIN_GATE is a larger value than CASLAT_LIN, the data capture window will become shorter. A CASLAT_LIN_GATE value smaller than CASLAT_LIN may have no effect on the data capture window, depending on the fixed offsets in the ASIC and the board. 0000 - 0010 = Reserved 0011 = 1.5 cycles 0100 = 2 cycles 0101 = 2.5 cycles 0110 = 3 cycles 0111 = 3.5 cycles 1000 = 4 cycles 1001 = Reserved 1010 = 5 cycles All other settings are Reserved Reserved. Sets latency from read command send to data receive from/to controller. Sets the CAS latency linear value in 1/2 cycle increments. This sets an internal adjustment for the delay from when the read command is sent from the memory controller to when data will be received back. The window of time in which the data is captured is a fixed length. The CASLAT_LIN bit field adjusts the start of this data capture window. Note: Not all linear values will be supported for the memory devices being used. Refer to the specification for the memory devices being used. 0000 - 0010 = Reserved 0011 = 1.5 cycles 0100 = 2 cycles 0101 = 2.5 cycles 0110 = 3 cycles 0111 = 3.5 cycles 1000 = 4 cycles 1001 = Reserved 1010 = 5 cycles All other settings are reserved Reserved. Location of the auto pre-charge bit in the DRAM address. Defines the location of the auto pre-charge bit in the DRAM address in decimal encoding. Reserved. DRAM TWTR parameter in cycles. Sets the number of cycles needed to switch from a write to a read operation, as dictated by the DDR SDRAM specification. i.MX23 Applications Processor Reference Manual, Rev. 1 12-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.17 DRAM Control Register 14 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL14 Table 12-35. HW_DRAM_CTL14 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 LOWPOWER_REFRESH_ENABLE 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x038 MAX_COL_REG INITAREF Table 12-36. HW_DRAM_CTL14 Bit Field Descriptions BITS LABEL 31:28 RSVD4 27:24 MAX_COL_REG RW RESET RO 0x0 RO 0xd DEFINITION Reserved. Maximum width of column address in DRAMs. Defines the maximum width of column address in the DRAM devices. This value can be used to set the COLUMN_SIZE bit field. column_size = max_col_reg - 23:20 RSVD3 19:16 LOWPOWER_REFRESH_EN ABLE RO 0x0 RW 0x0 15:12 RSVD2 11:8 INITAREF RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice CS_MAP RSVD4 RSVD3 RSVD2 RSVD1 12-41 External Memory Interface (EMI) Table 12-36. HW_DRAM_CTL14 Bit Field Descriptions BITS 7:4 RSVD1 CS_MAP 3:0 LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Sets the mask that determines which chip select pins are active. The user address chip select field will be mapped into the active chip selects indicated by this bit field in ascending order from lowest to highest. This allows the memory controller to map the entire contiguous user address into any group of chip selects. Bit 0 of this bit field corresponds to chip select [0]. Note that the number of chip selects, the number of bits set to 1 in this bit field, must be a power of 2 (2 raised to power of 0, 2 raised to power of 1, 2 raised to power of 2, etc.). NOTE: On the 169-pin BGA package, bits [3:2] of CS_MAP should always be 0. On the 128-pin LQFP, bits [3:1] of CS_MAP should always be 0. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.18 DRAM Control Register 15 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL15 Table 12-37. HW_DRAM_CTL15 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 PORT_BUSY 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 MAX_ROW_REG 0 1 0 0 0x03C RSVD4 RSVD3 RSVD2 Table 12-38. HW_DRAM_CTL15 Bit Field Descriptions BITS 31:28 RSVD4 27:24 TRP LABEL RW RESET RO 0x0 RW 0x0 DEFINITION 23:20 RSVD3 RO 0x0 Reserved. DRAM TRP parameter in cycles. Defines the DRAM pre-charge command time, in cycles. Reserved. i.MX23 Applications Processor Reference Manual, Rev. 1 12-42 Preliminary--Subject to Change Without Notice RSVD1 TDAL TRP Freescale Semiconductor External Memory Interface (EMI) Table 12-38. HW_DRAM_CTL15 Bit Field Descriptions BITS 19:16 TDAL LABEL RW RESET RW 0x0 DEFINITION DRAM TDAL parameter in cycles. Defines the auto pre-charge write recovery time when auto pre-charge is enabled (ap is set), in cycles. This is defined internally as tRP (pre-charge time) + auto pre-charge write recovery time. Note that not all memories use this parameter. If tDAL is defined in the memory specification, then program this bit field to the specified value. If the memory does not specify a tDAL time, then program this bit field to tWR + tRP. DO NOT program this bit field with a value of 0x0 or the memory controller will not function properly when auto pre-charge is enabled. Reserved. Per-port indicator that the controller is processing a command. Indicates that a port is actively processing a command. Each bit controls the corresponding port. 0 = Port is not busy. 1 = Port is busy. Reserved. Maximum width of memory address bus. Defines the maximum width of the memory address bus (number of row bits) for the memory controller. This value can be used to set the ADDR_PINS bit field. ADDR_PINS = MAX_ROW_REG - 15:12 RSVD2 11:8 PORT_BUSY RO 0x0 RO 0x0 7:4 3:0 RSVD1 MAX_ROW_REG RO 0x0 RO 0xd DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.19 DRAM Control Register 16 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL16 0x040 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-43 External Memory Interface (EMI) Table 12-39. HW_DRAM_CTL16 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 LOWPOWER_CONTROL 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 LOWPOWER_AUTO_ENABLE 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 12-40. HW_DRAM_CTL16 Bit Field Descriptions BITS 31:29 RSVD4 28:24 TMRD LABEL RW RESET RO 0x0 RW 0x00 DEFINITION Reserved. DRAM TMRD parameter in cycles. Defines the DRAM mode register set command time, in cycles. Reserved. Controls entry into the low-power modes. Enables the individual low-power modes of the device. Bit 0 = Controls memory self-refresh with memory and controller clock gating mode (Mode 5). Reserved and should always be written to a 0. Gate the clock via the CLKCTRL clock-gate for the EMI instead. Bit 1 = Controls memory self-refresh with memory clock gating mode (Mode 4). Bit 2 = Controls memory self-refresh mode (Mode 3). Bit 3 = Controls memory power-down with memory clock gating mode (Mode 2). Bit 4 = Controls memory power-down mode (Mode 1). For all bits: 0 = Disabled. 1 = Enabled. Reserved. 23:21 RSVD3 20:16 LOWPOWER_CONTROL RO 0x0 RW 0x00 15:13 RSVD2 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 12-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor INT_ACK RSVD4 RSVD3 RSVD2 RSVD1 TMRD External Memory Interface (EMI) Table 12-40. HW_DRAM_CTL16 Bit Field Descriptions BITS LABEL 12:8 LOWPOWER_AUTO_ENABL E RW RESET RW 0x00 DEFINITION Enables automatic entry into the low-power mode on idle. Enables automatic entry into the low-power modes of the memory controller. Bit 0 = Controls memory self-refresh with memory and controller clock gating mode (Mode 5). Reserved and should always be written to a 0. Gate the clock via the CLKCTRL clock-gate for the EMI instead. Bit 1 = Controls memory self-refresh with memory clock gating mode (Mode 4). Reserved and should always be written to a 0. Bit 2 = Controls memory self-refresh mode (Mode 3). Reserved and should always be written to a 0. Bit 3 = Controls memory power-down with memory clock gating mode (Mode 2). Bit 4 = Controls memory power-down mode (Mode 1). For all bits: 0 = Automatic entry into this mode is disabled. The user may enter this mode manually by setting the associated lowpower_control bit. 1 = Automatic entry into this mode is enabled. The mode will be entered automatically when the proper counters expire, and only if the associated lowpower_control bit is set. Reserved. Clear mask of the INT_STATUS bit field. Controls the clearing of the INT_STATUS bit field. If any of the INT_ACK bits are set to a 1 the corresponding bit in the INT_STATUS bit field will be cleared to 0. Any INT_ACK bits written with a 0 will not alter the corresponding bit in the INT_STATUS bit field. This bit field will always read back as 0. 7:4 3:0 RSVD1 INT_ACK RO 0x0 W 0x0 O DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.20 DRAM Control Register 17 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL17 0x044 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-45 External Memory Interface (EMI) Table 12-41. HW_DRAM_CTL17 3 1 3 0 2 9 2 8 DLL_START_POINT 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 DLL_INCREMENT 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DLL_LOCK RSVD1 Table 12-42. HW_DRAM_CTL17 Bit Field Descriptions BITS LABEL 31:24 DLL_START_POINT RW RESET RW 0x00 DEFINITION Initial delay count when searching for lock in master DLL. Sets the number of delay elements to place in the master delay line to start searching for lock in master DLL. Number of delay elements in master DLL lock. Defines the actual number of delay elements used to capture one full clock cycle. This bit field is automatically updated every time a refresh operation is performed. Number of elements to add to DLL_START_POINT when searching for lock. Defines the number of delay elements to recursively increment the DLL_START_POINT bit field with when searching for lock. Reserved. DRAM TRC parameter in cycles. Defines the DRAM period between active commands for the same bank, in cycles. 23:16 DLL_LOCK RO 0x00 15:8 DLL_INCREMENT RW 0x00 7:5 4:0 RSVD1 TRC RO 0x0 RW 0x00 DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.21 DRAM Control Register 18 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL18 0x048 i.MX23 Applications Processor Reference Manual, Rev. 1 12-46 Preliminary--Subject to Change Without Notice Freescale Semiconductor TRC External Memory Interface (EMI) Table 12-43. HW_DRAM_CTL18 3 1 3 0 2 9 2 8 2 7 DLL_DQS_DELAY_1 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 DLL_DQS_DELAY_0 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 INT_STATUS Table 12-44. HW_DRAM_CTL18 Bit Field Descriptions BITS LABEL 31 RSVD4 30:24 DLL_DQS_DELAY_1 RW RESET RO 0x0 RW 0x00 DEFINITION Reserved. Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 1 during reads. Sets the delay for the read_dqs signal from the DDR SDRAM devices for dll_rd_dqs_slice 1. This delay is used center the edges of the read_dqs signal so that the read data will be captured in the middle of the valid window in the I/O logic.Each increment of this bit field adds a delay of 1/128 of the system clock. Reserved. Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 0 during reads. Sets the delay for the read_dqs signal from the DDR SDRAM devices for dll_rd_dqs_slice 0. This delay is used center the edges of the read_dqs signal so that the read data will be captured in the middle of the valid window in the I/O logic.Each increment of this bit field adds a delay of 1/128 of the system clock. Reserved. Status of interrupt features in the controller. Shows the status of all possible interrupts generated by the memory controller. The MSB is the result of a logical OR of all the lower bits. The INT_STATUS bits correspond to these interrupts: Bit 0 = A single access outside the defined PHYSICAL memory space detected. Bit 1 = Multiple accesses outside the defined PHYSICAL memory space detected. Bit 2 = DRAM initialization complete. Bit 3 = DLL unlock condition detected. Bit 4 = Logical OR of all lower bits. Reserved. Mask for controller_int signals from the INT_STATUS bit field. Active-high mask bits that control the value of the memory controller_int signal on the ASIC interface. This mask is inverted and then logically AND'ed with the outputs of the INT_STATUS bit field. 23 RSVD3 22:16 DLL_DQS_DELAY_0 RO 0x0 RW 0x00 15:13 RSVD2 12:8 INT_STATUS RO 0x0 RO 0x00 7:5 4:0 RSVD1 INT_MASK RO 0x0 RW 0x00 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice INT_MASK RSVD4 RSVD3 RSVD2 RSVD1 12-47 External Memory Interface (EMI) DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.22 DRAM Control Register 19 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL19 Table 12-45. HW_DRAM_CTL19 3 1 3 0 2 9 2 8 DQS_OUT_SHIFT_BYPASS 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 DLL_DQS_DELAY_BYPASS_1 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 DLL_DQS_DELAY_BYPASS_0 0 3 0 2 0 1 0 0 0x04C Table 12-46. HW_DRAM_CTL19 Bit Field Descriptions BITS LABEL 31:24 DQS_OUT_SHIFT_BYPASS RW RESET RW 0x00 DEFINITION Sets the delay for the clk_dqs_out signal of the dll_wr_dqs_slice when the DLL is being bypassed. This is used to ensure correct data capture in the I/O logic. The value programmed into this bit field sets the actual number of delay elements in the clk_dqs_out line. If the total delay time programmed exceeds the number of delay elements in the delay chain, then the delay will be set internally to the maximum number of delay elements available. Reserved. Sets the delay for the clk_dqs_out signal of the dll_wr_dqs_slice to ensure correct data capture in the I/O logic. Each increment of this bit field adds a delay of 1/128 of the system clock. 23 RSVD1 22:16 DQS_OUT_SHIFT RO 0x0 RW 0x00 i.MX23 Applications Processor Reference Manual, Rev. 1 12-48 Preliminary--Subject to Change Without Notice DQS_OUT_SHIFT RSVD1 Freescale Semiconductor External Memory Interface (EMI) Table 12-46. HW_DRAM_CTL19 Bit Field Descriptions BITS LABEL 15:8 DLL_DQS_DELAY_BYPASS_ 1 RW RESET RW 0x00 DEFINITION Sets the delay for the read_dqs signal from the DDR SDRAM devices for dll_rd_dqs_slice 1 for reads when the DLL is being bypassed. This delay is used center the edges of the read_dqs signal so that the read data will be captured in the middle of the valid window in the I/O logic. The value programmed into this bit field sets the actual number of delay elements in the read_dqs line. If the total delay time programmed exceeds the number of delay elements in the delay chain, then the delay will be set internally to the maximum number of delay elements available. Sets the delay for the read_dqs signal from the DDR SDRAM devices for dll_rd_dqs_slice 0 for reads when the DLL is being bypassed. This delay is used center the edges of the read_dqs signal so that the read data will be captured in the middle of the valid window in the I/O logic. The value programmed into this bit field sets the actual number of delay elements in the read_dqs line. If the total delay time programmed exceeds the number of delay elements in the delay chain, then the delay will be set internally to the maximum number of delay elements available. 7:0 DLL_DQS_DELAY_BYPASS_ 0 RW 0x00 DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.23 DRAM Control Register 20 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL20 Table 12-47. HW_DRAM_CTL20 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 WR_DQS_SHIFT_BYPASS 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x050 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice WR_DQS_SHIFT TRAS_MIN TRCD_INT RSVD1 12-49 External Memory Interface (EMI) Table 12-48. HW_DRAM_CTL20 Bit Field Descriptions BITS LABEL 31:24 TRCD_INT RW RESET RW 0x00 DEFINITION DRAM TRCD parameter in cycles. Defines the DRAM RAS to CAS delay, in cycles DRAM TRAS_MIN parameter in cycles. Defines the DRAM minimum row activate time, in cycles. Sets the delay for the clk_wr signal when the DLL is being bypassed. This is used to ensure correct data capture in the I/O logic. The value programmed into this bit field sets the actual number of delay elements in the clk_wr line. If the total delay time programmed exceeds the number of delay elements in the delay chain, then the delay will be set internally to the maximum number of delay elements available. Reserved. Sets the delay for the clk_wr signal to ensure correct data capture in the I/O logic. Each increment of this bit field adds a delay of 1/128 of the system clock. The same delay will be added to the clk_dqs_out signal for each slice. 23:16 TRAS_MIN 15:8 WR_DQS_SHIFT_BYPASS RW 0x00 RW 0x00 7 6:0 RSVD1 WR_DQS_SHIFT RO 0x0 RW 0x00 DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.24 DRAM Control Register 21 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL21 Table 12-49. HW_DRAM_CTL21 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 OUT_OF_RANGE_LENGTH 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x054 OBSOLETE RSVD1 i.MX23 Applications Processor Reference Manual, Rev. 1 12-50 Preliminary--Subject to Change Without Notice Freescale Semiconductor TRFC External Memory Interface (EMI) Table 12-50. HW_DRAM_CTL21 Bit Field Descriptions BITS LABEL 31:24 OBSOLETE 23:18 RSVD1 17:8 OUT_OF_RANGE_LENGTH RW RESET RO 0x0 RO 0x0 RO 0x000 DEFINITION 7:0 TRFC RW 0x00 Reserved. Reserved. Length of command that caused an Out-of-Range interrupt. Holds the length of the command that caused an out-of-range interrupt request to the memory devices. DRAM TRFC parameter in cycles. Defines the DRAM refresh command time, in cycles. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.25 DRAM Control Register 22 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL22 Table 12-51. HW_DRAM_CTL22 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 AHB0_WRCNT 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 AHB0_RDCNT 0 4 0 3 0 2 0 1 0 0 0x058 RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 12-51 External Memory Interface (EMI) Table 12-52. HW_DRAM_CTL22 Bit Field Descriptions BITS LABEL 31:27 RSVD2 26:16 AHB0_WRCNT RW RESET RO 0x0 RW 0x000 DEFINITION 15:11 RSVD1 10:0 AHB0_RDCNT RO 0x0 RW 0x000 Reserved. Number of bytes for an INCR WRITE command on port 0. Holds the number of bytes to send to the memory controller core from AHB port 0 for an INCR WRITE AHB command. The AHB logic will subdivide an INCR request into memory controller core commands of the size of this bit field. The logic will continue sending bursts of this size as the previous request has been transmitted by the AHB port. If the INCR command is terminated on an unnatural boundary, the logic will discard the unnecessary words. The value defined in this bit field should be a multiple of the number of bytes in the AHB port width. Clearing this bit field will cause the port to issue commands of 0 length to the controller core, which the core interprets as the pre-configured value of 1024 bytes. Reserved. Number of bytes for an INCR READ command on port 0. Holds the number of bytes to return to AHB port 0 for an INCR READ AHB command. The AHB logic will subdivide an INCR request into memory controller core commands of the size of this bit field. The logic will continue requesting bursts of this size as soon as the previous request has been received by the AHB port. If the INCR command is terminated on an unnatural boundary, the logic will discard the unnecessary words. The value defined in this bit field should be a multiple of the number of bytes in the AHB port width. Clearing this bit field will cause the port to issue commands of 0 length to the controller core, which the core interprets as the pre-configured value of 1024 bytes. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.26 DRAM Control Register 23 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL23 0x05C i.MX23 Applications Processor Reference Manual, Rev. 1 12-52 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) Table 12-53. HW_DRAM_CTL23 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 AHB1_WRCNT 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 AHB1_RDCNT 0 4 0 3 0 2 0 1 0 0 RSVD2 Table 12-54. HW_DRAM_CTL23 Bit Field Descriptions BITS LABEL 31:27 RSVD2 26:16 AHB1_WRCNT RW RESET RO 0x0 RW 0x000 DEFINITION Reserved. Number of bytes for an INCR WRITE command on port 1. Holds the number of bytes to send to the memory controller core from AHB port 0 for an INCR WRITE AHB command. The AHB logic will subdivide an INCR request into memory controller core commands of the size of this bit field. The logic will continue sending bursts of this size as the previous request has been transmitted by the AHB port. If the INCR command is terminated on an unnatural boundary, the logic will discard the unnecessary words. The value defined in this bit field should be a multiple of the number of bytes in the AHB port width. Clearing this bit field will cause the port to issue commands of 0 length to the controller core, which the core interprets as the pre-configured value of 1024 bytes. Reserved. Number of bytes for an INCR READ command on port 1. Holds the number of bytes to return to AHB port 0 for an INCR READ AHB command. The AHB logic will subdivide an INCR request into memory controller core commands of the size of this bit field. The logic will continue requesting bursts of this size as soon as the previous request has been received by the AHB port. If the INCR command is terminated on an unnatural boundary, the logic will discard the unnecessary words. The value defined in this bit field should be a multiple of the number of bytes in the AHB port width. Clearing this bit field will cause the port to issue commands of 0 length to the controller core, which the core interprets as the pre-configured value of 1024 bytes. 15:11 RSVD1 10:0 AHB1_RDCNT RO 0x0 RW 0x000 DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 12-53 External Memory Interface (EMI) 12.5.27 DRAM Control Register 24 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL24 Table 12-55. HW_DRAM_CTL24 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 AHB2_WRCNT 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 AHB2_RDCNT 0 4 0 3 0 2 0 1 0 0 0x060 RSVD2 Table 12-56. HW_DRAM_CTL24 Bit Field Descriptions BITS LABEL 31:27 RSVD2 26:16 AHB2_WRCNT RW RESET RO 0x0 RW 0x000 DEFINITION Reserved. Number of bytes for an INCR WRITE command on port 2. Holds the number of bytes to send to the memory controller core from AHB port 2 for an INCR WRITE AHB command. The AHB logic will subdivide an INCR request into memory controller core commands of the size of this bit field. The logic will continue sending bursts of this size as the previous request has been transmitted by the AHB port. If the INCR command is terminated on an unnatural boundary, the logic will discard the unnecessary words. The value defined in this bit field should be a multiple of the number of bytes in the AHB port width. Clearing this bit field will cause the port to issue commands of 0 length to the controller core, which the core interprets as the pre-configured value of 1024 bytes. Reserved. Number of bytes for an INCR READ command on port 2. Holds the number of bytes to return to AHB port 2 for an INCR READ AHB command. The AHB logic will subdivide an INCR request into memory controller core commands of the size of this bit field. The logic will continue requesting bursts of this size as soon as the previous request has been received by the AHB port. If the INCR command is terminated on an unnatural boundary, the logic will discard the unnecessary words. The value defined in this bit field should be a multiple of the number of bytes in the AHB port width. Clearing this bit field will cause the port to issue commands of 0 length to the controller core, which the core interprets as the pre-configured value of 1024 bytes. 15:11 RSVD1 10:0 AHB2_RDCNT RO 0x0 RW 0x000 DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions i.MX23 Applications Processor Reference Manual, Rev. 1 12-54 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor External Memory Interface (EMI) EXAMPLE: Empty Example. 12.5.28 DRAM Control Register 25 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL25 Table 12-57. HW_DRAM_CTL25 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 AHB3_WRCNT 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 AHB3_RDCNT 0 4 0 3 0 2 0 1 0 0 0x064 RSVD2 Table 12-58. HW_DRAM_CTL25 Bit Field Descriptions BITS LABEL 31:27 RSVD2 26:16 AHB3_WRCNT RW RESET RO 0x0 RW 0x000 DEFINITION Reserved. Number of bytes for an INCR WRITE command on port 3. Holds the number of bytes to send to the memory controller core from AHB port 3 for an INCR WRITE AHB command. The AHB logic will subdivide an INCR request into memory controller core commands of the size of this bit field. The logic will continue sending bursts of this size as the previous request has been transmitted by the AHB port. If the INCR command is terminated on an unnatural boundary, the logic will discard the unnecessary words. The value defined in this bit field should be a multiple of the number of bytes in the AHB port width. Clearing this bit field will cause the port to issue commands of 0 length to the controller core, which the core interprets as the pre-configured value of 1024 bytes. Reserved. Number of bytes for an INCR READ command on port 3. Holds the number of bytes to return to AHB port 3 for an INCR READ AHB command. The AHB logic will subdivide an INCR request into memory controller core commands of the size of this bit field. The logic will continue requesting bursts of this size as soon as the previous request has been received by the AHB port. If the INCR command is terminated on an unnatural boundary, the logic will discard the unnecessary words. The value defined in this bit field should be a multiple of the number of bytes in the AHB port width. Clearing this bit field will cause the port to issue commands of 0 length to the controller core, which the core interprets as the pre-configured value of 1024 bytes. 15:11 RSVD1 10:0 AHB3_RDCNT RO 0x0 RW 0x000 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 12-55 External Memory Interface (EMI) DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.29 DRAM Control Register 26 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL26 Table 12-59. HW_DRAM_CTL26 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 OBSOLETE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 RSVD1 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 TREF 0 5 0 4 0 3 0 2 0 1 0 0 0x068 Table 12-60. HW_DRAM_CTL26 Bit Field Descriptions BITS LABEL 31:16 OBSOLETE 15:12 RSVD1 11:0 TREF RW RESET RO 0x0 RO 0x0 RW 0x000 DEFINITION Reserved. Reserved. DRAM TREF parameter in cycles. Defines the DRAM cycles between refresh commands. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.30 DRAM Control Register 27 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL27 Table 12-61. HW_DRAM_CTL27 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x06C OBSOLETE i.MX23 Applications Processor Reference Manual, Rev. 1 12-56 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) Table 12-62. HW_DRAM_CTL27 Bit Field Descriptions BITS LABEL 31:0 OBSOLETE RW RESET RO 0x0 DEFINITION Reserved. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.31 DRAM Control Register 28 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL28 Table 12-63. HW_DRAM_CTL28 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x070 OBSOLETE Table 12-64. HW_DRAM_CTL28 Bit Field Descriptions BITS LABEL 31:0 OBSOLETE RW RESET RO 0x0 DEFINITION Reserved. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.32 DRAM Control Register 29 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL29 0x074 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-57 External Memory Interface (EMI) Table 12-65. HW_DRAM_CTL29 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 LOWPOWER_INTERNAL_CNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 LOWPOWER_EXTERNAL_CNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 12-66. HW_DRAM_CTL29 Bit Field Descriptions BITS LABEL 31:16 LOWPOWER_INTERNAL_CN T RW RESET RW 0x0000 DEFINITION Counts idle cycles to self-refresh with memory and controller clk gating. Counts the number of idle cycles before memory self-refresh with memory and controller clock gating low-power mode 5. Counts idle cycles to self-refresh with memory clock gating. Counts the number of idle cycles before memory self-refresh with memory clock gating low-power mode 4. 15:0 LOWPOWER_EXTERNAL_CN RW 0x0000 T DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.33 DRAM Control Register 30 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL30 0x078 i.MX23 Applications Processor Reference Manual, Rev. 1 12-58 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) Table 12-67. HW_DRAM_CTL30 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 LOWPOWER_REFRESH_HOLD 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 LOWPOWER_POWER_DOWN_CNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 12-68. HW_DRAM_CTL30 Bit Field Descriptions BITS LABEL 31:16 LOWPOWER_REFRESH_HO LD RW RESET RW 0x0000 DEFINITION Re-Sync counter for DLL in Clock Gate Mode. Counts the re-synchronization cycles for the DLL in Clock Gate Mode. Counts idle cycles to memory power-down. Counts the number of idle cycles before memory power-down or power-down with memory clock gating low-power mode 1 or 2. 15:0 LOWPOWER_POWER_DOW N_CNT RW 0x0000 DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.34 DRAM Control Register 31 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL31 0x07C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-59 External Memory Interface (EMI) Table 12-69. HW_DRAM_CTL31 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 LOWPOWER_SELF_REFRESH_CNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 12-70. HW_DRAM_CTL31 Bit Field Descriptions BITS 31:16 TDLL LABEL RW RESET RW 0x0000 DEFINITION DRAM TDLL parameter in cycles. Defines the DRAM DLL lock time, in cycles. Counts idle cycles to memory self-refresh. Counts the number of cycles to the next memory self-refresh low-power mode 3. 15:0 LOWPOWER_SELF_REFRES RW 0x0000 H_CNT DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.35 DRAM Control Register 32 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL32 Table 12-71. HW_DRAM_CTL32 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 TXSNR 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 TRAS_MAX 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TDLL 0x080 i.MX23 Applications Processor Reference Manual, Rev. 1 12-60 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) Table 12-72. HW_DRAM_CTL32 Bit Field Descriptions BITS 31:16 TXSNR LABEL RW RESET RW 0x0000 DEFINITION DRAM TXSNR parameter in cycles. Defines the DRAM tXSNR parameter, in cycles. DRAM TRAS_MAX parameter in cycles. Defines the DRAM maximum row active time, in cycles. 15:0 TRAS_MAX RW 0x0000 DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.36 DRAM Control Register 33 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL33 Table 12-73. HW_DRAM_CTL33 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 VERSION 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 TXSR 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x084 Table 12-74. HW_DRAM_CTL33 Bit Field Descriptions BITS LABEL 31:16 VERSION RW RESET RO 0x2041 DEFINITION Controller version number. Holds the version number for this controller. DRAM TXSR parameter in cycles. Defines the DRAM self-refresh exit time, in cycles. 15:0 TXSR RW 0x0000 DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.37 DRAM Control Register 34 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL34 0x088 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-61 External Memory Interface (EMI) Table 12-75. HW_DRAM_CTL34 3 1 3 0 2 9 2 8 RSVD1 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 TINIT 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 12-76. HW_DRAM_CTL34 Bit Field Descriptions BITS 31:24 RSVD1 23:0 TINIT LABEL RW RESET RO 0x0 RW 0x000000 DEFINITION Reserved. DRAM TINIT parameter in cycles. Defines the DRAM initialization time, in cycles. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.38 DRAM Control Register 35 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL35 Table 12-77. HW_DRAM_CTL35 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 OUT_OF_RANGE_ADDR 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x08C RSVD1 Table 12-78. HW_DRAM_CTL35 Bit Field Descriptions BITS LABEL 31 RSVD1 30:0 OUT_OF_RANGE_ADDR RW RESET RO 0x0 RO 0x00000000 DEFINITION Reserved. Address of command that caused an Out-of-Range interrupt. Holds the address of the command that caused an out-of-range interrupt request to the memory devices. i.MX23 Applications Processor Reference Manual, Rev. 1 12-62 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.39 DRAM Control Register 36 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL36 Table 12-79. HW_DRAM_CTL36 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 PWRUP_SREFRESH_EXIT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 ENABLE_QUICK_SREFRESH 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x090 Table 12-80. HW_DRAM_CTL36 Bit Field Descriptions BITS LABEL 31:25 RSVD5 PWRUP_SREFRESH_EXIT 24 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Powerup via self-refresh instead of full memory initialization. Allows controller to exit power-down mode by executing a self-refresh instead of the full memory initialization. 0 = Disabled 1 = Enabled Reserved. Interrupts memory initialization to enter self-refresh mode. When this bit is set, the memory initialization sequence will be interrupted and self-refresh mode will be entered. 0 = Continue memory initialization. 1 = Interrupt memory initialization and enter self-refresh mode. Reserved. Program this field to 0x0. 23:17 RSVD4 RO 0x0 ENABLE_QUICK_SREFRESH RW 0x0 16 15:9 8 RSVD3 RSVD2 RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice ACTIVE_AGING RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 12-63 External Memory Interface (EMI) Table 12-80. HW_DRAM_CTL36 Bit Field Descriptions BITS LABEL 7:1 RSVD1 ACTIVE_AGING 0 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Enable aging of the active command. Enables aging of the active command as a condition when using the placement logic to fill the command queue. 0 = Disabled 1 = Enabled DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.40 DRAM Control Register 37 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL37 Table 12-81. HW_DRAM_CTL37 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 BUS_SHARE_TIMEOUT 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x094 Table 12-82. HW_DRAM_CTL37 Bit Field Descriptions BITS LABEL 31:24 OBSOLETE 23:18 RSVD2 17:8 BUS_SHARE_TIMEOUT RW RESET RO 0x0 RO 0x0 RW 0x000 DEFINITION Reserved. Reserved. Wait time from when the memory controller needs the bus to asserting bus_timeout signal. Sets the wait time for the memory controller when the bus is being shared. This value is loaded into the bus share counter when a command is ready to communicate with the memory devices. When the counter expires, the bus_timeout signal will be asserted indicating to the external source that the memory controller is requesting the shared pins. i.MX23 Applications Processor Reference Manual, Rev. 1 12-64 Preliminary--Subject to Change Without Notice Freescale Semiconductor TREF_ENABLE OBSOLETE RSVD2 RSVD1 External Memory Interface (EMI) Table 12-82. HW_DRAM_CTL37 Bit Field Descriptions BITS LABEL 7:1 RSVD1 TREF_ENABLE 0 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Issue self-refresh commands to the DRAMs every TREF cycles. Enables internal refresh commands. If command refresh mode is configured, then refresh commands will be issued based on the internal tref counter and any refresh commands sent through the command interface. 0 = Internal refresh commands disabled. 1 = Internal refresh commands enabled. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.41 DRAM Control Register 38 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL38 Table 12-83. HW_DRAM_CTL38 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 EMRS2_DATA_0 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 EMRS1_DATA 0 5 0 4 0 3 0 2 0 1 0 0 0x098 RSVD2 Table 12-84. HW_DRAM_CTL38 Bit Field Descriptions BITS LABEL 31:29 RSVD2 28:16 EMRS2_DATA_0 RW RESET RO 0x0 RW 0x0000 DEFINITION Reserved. EMRS2 data for chip select 0. Holds the EMRS2 data written during DDRII initialization for chip select 0. The contents of this bit field will be programmed into the DRAM at initialization or when the write_modereg bit field is written with a 1. Consult the DRAM specification for the correct settings for this bit field. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 12-65 External Memory Interface (EMI) Table 12-84. HW_DRAM_CTL38 Bit Field Descriptions BITS LABEL 15:13 RSVD1 12:0 EMRS1_DATA RW RESET RO 0x0 RW 0x0000 DEFINITION Reserved. EMRS1 data. Holds the EMRS1 data written during DDRII initialization. The contents of this bit field will be programmed into the DRAM at initialization or when the WRITE_MODEREG bit field is written with a 1. Consult the DRAM specification for the correct settings for this bit field. DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.42 DRAM Control Register 39 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL39 Table 12-85. HW_DRAM_CTL39 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 EMRS2_DATA_2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 EMRS2_DATA_1 0 5 0 4 0 3 0 2 0 1 0 0 0x09C RSVD2 Table 12-86. HW_DRAM_CTL39 Bit Field Descriptions BITS LABEL 31:29 RSVD2 28:16 EMRS2_DATA_2 RW RESET RO 0x0 RW 0x0000 DEFINITION Reserved. EMRS2 data for chip select 2. Holds the EMRS2 data written during DDRII initialization for chip select 2. The contents of this bit field will be programmed into the DRAM at initialization or when the WRITE_MODEREG bit field is written with a 1. Consult the DRAM specification for the correct settings for this bit field. Reserved. EMRS2 data for chip select 1. Holds the EMRS2 data written during DDRII initialization for chip select 1. The contents of this bit field will be programmed into the DRAM at initialization or when the WRITE_MODEREG bit field is written with a 1. Consult the DRAM specification for the correct settings for this bit field. 15:13 RSVD1 12:0 EMRS2_DATA_1 RO 0x0 RW 0x0000 i.MX23 Applications Processor Reference Manual, Rev. 1 12-66 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor External Memory Interface (EMI) DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. 12.5.43 DRAM Control Register 40 Description DRAM control register. See bit fields for detailed descriptions. HW_DRAM_CTL40 Table 12-87. HW_DRAM_CTL40 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 EMRS2_DATA_3 0 5 0 4 0 3 0 2 0 1 0 0 0x0A0 TPDEX Table 12-88. HW_DRAM_CTL40 Bit Field Descriptions BITS 31:16 TPDEX LABEL RW RESET RW 0x0000 DEFINITION DRAM TPDEX parameter in cycles. Defines the DRAM power-down exit command period, in cycles. Reserved. EMRS2 data for chip select 3. Holds the EMRS2 data written during DDRII initialization for chip select 3. The contents of this bit field will be programmed into the DRAM at initialization or when the WRITE_MODEREG bit field is written with a 1. Consult the DRAM specification for the correct settings for this bit field. 15:13 RSVD1 12:0 EMRS2_DATA_3 RO 0x0 RW 0x0000 DESCRIPTION: DRAM Control registers. Individual fields control various aspects of the DRAM interface. See bit fields for descriptions EXAMPLE: Empty Example. DRAM Block v2.1, Revision 1.50 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 12-67 External Memory Interface (EMI) 12.6 12.6.1 EMI Memory Parameters and Register Settings Mobile DDR (5 nsec) Parameters Table 12-89. Frequency Dependent Parameters Parameter TCKE TDAL TDLL TEMRS TINIT TMRD TPDEX TRAS_MAX TRAS_MIN TRC TRCD_INT TREF TRFC TRP TRRD TWR_INT TWTR TXSNR TXSR 24 MHz 48 MHz 60 MHz 96 MHz 120 MHz 133 MHz 160 MHz 0x0001 0x03 0x0000 0x02 0x000012C1 0x02 0x0002 0x0687 0x01 0x02 0x01 0x000000B3 0x0003 0x01 0x01 0x02 0x03 0x0003 0x0004 0x0001 0x03 0x0000 0x02 0x00002582 0x02 0x0002 0x0D17 0x01 0x03 0x01 0x0000016F 0x0005 0x01 0x01 0x02 0x03 0x0006 0x0007 0x0001 0x03 0x0000 0x02 0x00002EE5 0x02 0x0002 0x1060 0x03 0x04 0x01 0x000001CC 0x0006 0x01 0x01 0x02 0x03 0x0008 0x0009 0x0001 0x04 0x0000 0x02 0x00004B0D 0x02 0x0002 0x1A3B 0x04 0x06 0x02 0x000002E6 0x000A 0x02 0x01 0x02 0x03 0x000C 0x000D 0x0001 0x04 0x0000 0x02 0x00005DCA 0x02 0x0002 0x20CA 0x05 0x07 0x02 0x000003A1 0x000C 0x02 0x02 0x02 0x03 0x000F 0x0011 0x0001 0x04 0x0000 0x02 0x00006665 0x02 0x0002 0x23CD 0x06 0x08 0x02 0x000003F7 0x000D 0x02 0x02 0x02 0x03 0x0010 0x0012 0x0001 0x05 0x0000 0x02 0x00007D00 0x02 0x0002 0x2BB6 0x07 0x09 0x03 0x000004DA 0x0010 0x03 0x02 0x02 0x03 0x0014 0x0016 12.6.1.1 Bypass Cutoff Suggested bypass cutoff frequency is 60 MHz. 12.6.1.2 Bypass Mode Enabled Table 12-90. Delays Parameter 24 MHz 48 MHz 60 MHz DLL_DQS_DELAY_BYPASS_0 DLL_DQS_DELAY_BYPASS_1 DQS_OUT_SHIFT_BYPASS WR_DQS_SHIFT_BYPASS 0x24 0x24 0x01 0x23 0x13 0x13 0x01 0x12 0x0E 0x0E 0x01 0x0D i.MX23 Applications Processor Reference Manual, Rev. 1 12-68 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) 12.6.1.3 Bypass Mode Disabled Table 12-91. DLL Parameter 60 MHz 96 MHz 120 MHz 133 MHz DLL_INCREMENT DLL_START_POINT TBD TBD TBD TBD TBD TBD TBD TBD Table 12-92. Delays Parameter Value DLL_DQS_DELAY_1 DLL_DQS_DELAY_0 DQS_OUT_SHIFT WR_DQS_SHIFT 0x20 0x20 0x7F 0x1C 12.6.1.4 Example Register Settings //////////////////////////////////////////////////////////////////////////////// // // Filename: mobile_ddr_mt46h32m16lf_5_regs_3_160MHz.h // // Description: Initialization register values for EMI DRAM controller // //////////////////////////////////////////////////////////////////////////////// // // WARNING! THIS FILE IS AUTOMATICALLY GENERATED. // DO NOT MODIFY THIS FILE DIRECTLY. // // SETTINGS USED TO GENERATE THIS FILE: // // Burst: 4 // CAS: 3 // Freq: 160 MHz // Auto-Precharge: 0 // DLL_Bypass: 0 // //////////////////////////////////////////////////////////////////////////////// { 0x01010001, 0x00010100, 0x01000101, 0x00000001, 0x00000101, 0x00000001, 0x00010000, 0x01000101, 0x01000000, 0x00000001, /* 0x01 ahb0_w_priority 0x01 ahb0_r_priority 0x00 ahb0_fifo_type_reg 0x01 addr_cmp_en */ /* 0x00 ahb2_fifo_type_reg 0x01 ahb1_w_priority 0x01 ahb1_r_priority 0x00 ahb1_fifo_type_reg */ /* 0x01 ahb3_r_priority 0x00 ahb3_fifo_type_reg 0x01 ahb2_w_priority 0x01 ahb2_r_priority */ /* 0x00 auto_refresh_mode 0x00 arefresh 0x00 ap 0x01 ahb3_w_priority */ /* 0x00 dll_bypass_mode 0x00 dlllockreg 0x01 concurrentap 0x01 bank_split_en */ /* 0x00 intrptreada 0x00 intrptapburst 0x00 fast_write 0x01 en_lowpower_mode */ /* 0x00 power_down 0x01 placement_en 0x00 no_cmd_init 0x00 intrptwritea */ /* 0x01 rw_same_en 0x00 reg_dimm_enable 0x01 rd2rd_turn 0x01 priority_en */ /* 0x01 tras_lockout 0x00 start 0x00 srefresh 0x00 sdr_mode */ /* 0x00 out_of_range_type 0x00 out_of_range_source_id 0x00 write_modereg 0x01 writeinterp */ i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-69 External Memory Interface (EMI) 0x07000200, 0x00070203, 0x02020001, 0x06060a03, 0x00000201, 0x03050000, 0x02000000, 0x2d000d09, 0x20200000, 0x02020f0f, 0x0307121c, 0x00000010, 0x00080008, 0x00200020, 0x00200020, 0x00200020, 0x000004da, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00142bb6, 0x00000016, 0x00007d00, 0x00000000, 0x00000101, 0x00040001, 0x00400000, 0x00400040, 0x00020040, }, /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* 0x07 age_count 0x00 addr_pins 000000_10 temrs 0x00 q_fullness */ 0x00 max_cs_reg 0x07 command_age_count 0x02 column_size 0x03 caslat */ 0x02 twr_int 0x02 trrd 0x0001 tcke */ 0x06 caslat_lin_gate 0x06 caslat_lin 0x0a aprebit 0x03 twtr */ 0x00 max_col_reg 0x00 lowpower_refresh_enable 0x02 initaref 0x01 cs_map */ 0x03 trp 0x05 tdal 0x00 port_busy 0x00 max_row_reg */ 0x02 tmrd 0x00 lowpower_control 0x00 lowpower_auto_enable 0x00 int_ack */ 0x2d dll_start_point 0x00 dll_lock 0x0d dll_increment 0x09 trc */ 0x20 dll_dqs_delay_1 0x20 dll_dqs_delay_0 0x00 int_status 0x00 int_mask */ 0x02 dqs_out_shift_bypass 0x02 dqs_out_shift 0x0f dll_dqs_delay_bypass_1 0x0f dll_dqs_delay_bypass_0 */ 0x03 trcd_int 0x07 tras_min 0x12 wr_dqs_shift_bypass 0x1c wr_dqs_shift */ 0x000000 out_of_range_length 0x10 trfc */ 0x0008 ahb0_wrcnt 0x0008 ahb0_rdcnt */ 0x0020 ahb1_wrcnt 0x0020 ahb1_rdcnt */ 0x0020 ahb2_wrcnt 0x0020 ahb2_rdcnt */ 0x0020 ahb3_wrcnt 0x0020 ahb3_rdcnt */ 0x000004da tref */ 0x00000000 */ 0x00000000 */ 0x0000 lowpower_internal_cnt 0x0000 lowpower_external_cnt */ 0x0000 lowpower_refresh_hold 0x0000 lowpower_power_down_cnt */ 0x0000 tdll 0x0000 lowpower_self_refresh_cnt */ 0x0014 txsnr 0x2bb6 tras_max */ 0x0000 version 0x0016 txsr */ 0x00007d00 tinit */ 0x00000000 out_of_range_addr */ 0x00 pwrup_srefresh_exit 0x00 enable_quick_srefresh 0x01 bus_share_enable 0x01 active_aging */ 0x000400 bus_share_timeout 0x01 tref_enable */ 0x0040 emrs2_data_0 0x0000 emrs1_data */ 0x0040 emrs2_data_2 0x0040 emrs2_data_1 */ 0x0002 tpdex 0x0040 emrs2_data_3 */ 12.6.2 Mobile DDR (6 nsec) Table 12-93. Frequency Dependent Parameters Parameter TCKE TDAL TDLL TEMRS TINIT TMRD TPDEX TRAS_MAX TRAS_MIN TRC 24 MHz 48 MHz 60 MHz 96 MHz 120 MHz 133 MHz 167 MHz 0x0002 0x03 0x0000 0x02 0x000012C1 0x02 0x0001 0x0687 0x02 0x02 0x0002 0x03 0x0000 0x02 0x00002582 0x02 0x0002 0x0D17 0x03 0x03 0x0002 0x04 0x0000 0x02 0x00002EE5 0x02 0x0002 0x1060 0x03 0x04 0x0002 0x04 0x0000 0x02 0x00004B0D 0x02 0x0003 0x1A3B 0x05 0x06 0x0002 0x05 0x0000 0x02 0x00005DCA 0x02 0x0004 0x20CA 0x06 0x08 0x0002 0x05 0x0000 0x02 0x00006665 0x02 0x0004 0x23CD 0x06 0x08 0x0002 0x05 0x0000 0x02 0x000081C7 0x02 0x0005 0x2D62 0x07 0x0A i.MX23 Applications Processor Reference Manual, Rev. 1 12-70 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) Table 12-93. Frequency Dependent Parameters (continued) Parameter TRCD_INT TREF TRFC TRP TRRD TWR_INT TWTR TXSNR TXSR 24 MHz 48 MHz 60 MHz 96 MHz 120 MHz 133 MHz 167 MHz 0x01 0x000000B3 0x02 0x01 0x01 0x02 0x02 0x0003 0x0003 0x01 0x0000016F 0x04 0x01 0x01 0x02 0x02 0x0006 0x0006 0x02 0x000001CC 0x05 0x02 0x01 0x02 0x02 0x0008 0x0008 0x02 0x000002E6 0x07 0x02 0x02 0x02 0x02 0x000C 0x000C 0x03 0x000003A1 0x09 0x03 0x02 0x02 0x02 0x000F 0x000F 0x03 0x000003F7 0x0A 0x03 0x02 0x02 0x02 0x0010 0x0010 0x03 0x00000509 0x0C 0x03 0x02 0x02 0x02 0x0014 0x0014 12.6.2.1 Bypass Cutoff Suggested bypass cutoff frequency is 60 MHz. 12.6.2.2 Bypass Mode Enabled Table 12-94. Delays Parameter 24 MHz 48 MHz 60 MHz DLL_DQS_DELAY_BYPASS_0 DLL_DQS_DELAY_BYPASS_1 DQS_OUT_SHIFT_BYPASS WR_DQS_SHIFT_BYPASS 0x1A 0x1A 0x01 0x12 0x0D 0x0D 0x01 0x12 0x0C 0x0C 0x01 0x12 12.6.2.3 Bypass Mode Disabled Table 12-95. DLL Parameter 60 MHz 96 MHz 120 MHz 133 MHz 167 MHz DLL_INCREMENT DLL_START_POINT 0x06 0x28 0x05 0x18 0x05 0x14 0x05 0x14 0x05 0x14 Table 12-96. Delays PARAMETER VALUE DLL_DQS_DELAY_1 DLL_DQS_DELAY_0 DQS_OUT_SHIFT WR_DQS_SHIFT 0x20 0x20 0x7F 0x20 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-71 External Memory Interface (EMI) 12.6.2.4 Example Register Settings //////////////////////////////////////////////////////////////////////////////// // // Filename: mobile_ddr_mt46h16m16lf_6_regs_3_96MHz.h // // Description: Initialization register values for EMI DRAM controller // //////////////////////////////////////////////////////////////////////////////// // // WARNING! THIS FILE IS AUTOMATICALLY GENERATED. // DO NOT MODIFY THIS FILE DIRECTLY. // // SETTINGS USED TO GENERATE THIS FILE: // // Burst: 4 // CAS: 3 // Freq: 96 MHz // Auto-Precharge: 0 // DLL_Bypass: 0 // //////////////////////////////////////////////////////////////////////////////// { 0x01010001, 0x00010100, 0x01000101, 0x00000001, 0x00000101, 0x00000001, 0x00010000, 0x01000001, 0x01000000, 0x00000001, 0x07000200, 0x00070303, 0x02020002, 0x06060a02, 0x00000201, 0x02040000, 0x02000000, 0x18000606, 0x15150000, 0x027f1a1a, 0x02051c12, 0x00000007, 0x00080008, 0x00200020, 0x00200020, 0x00200020, 0x000002e6, 0x00000000, 0x00000000, /* 0x01 ahb0_w_priority 0x01 ahb0_r_priority 0x00 ahb0_fifo_type_reg 0x01 addr_cmp_en */ /* 0x00 ahb2_fifo_type_reg 0x01 ahb1_w_priority 0x01 ahb1_r_priority 0x00 ahb1_fifo_type_reg */ /* 0x01 ahb3_r_priority 0x00 ahb3_fifo_type_reg 0x01 ahb2_w_priority 0x01 ahb2_r_priority */ /* 0x00 auto_refresh_mode 0x00 arefresh 0x00 ap 0x01 ahb3_w_priority */ /* 0x00 dll_bypass_mode 0x00 dlllockreg 0x01 concurrentap 0x01 bank_split_en */ /* 0x00 intrptreada 0x00 intrptapburst 0x00 fast_write 0x01 en_lowpower_mode */ /* 0x00 power_down 0x01 placement_en 0x00 no_cmd_init 0x00 intrptwritea */ /* 0x01 rw_same_en 0x00 reg_dimm_enable 0x00 rd2rd_turn 0x01 priority_en */ /* 0x01 tras_lockout 0x00 start 0x00 srefresh 0x00 sdr_mode */ /* 0x00 out_of_range_type 0x00 out_of_range_source_id 0x00 write_modereg 0x01 writeinterp */ /* 0x07 age_count 0x00 addr_pins 000000_10 temrs 0x00 q_fullness */ /* 0x00 max_cs_reg 0x07 command_age_count 0x03 column_size 0x03 caslat */ /* 0x02 twr_int 0x02 trrd 0x0002 tcke */ /* 0x06 caslat_lin_gate 0x06 caslat_lin 0x0a aprebit 0x02 twtr */ /* 0x00 max_col_reg 0x00 lowpower_refresh_enable 0x02 initaref 0x01 cs_map */ /* 0x02 trp 0x04 tdal 0x00 port_busy 0x00 max_row_reg */ /* 0x02 tmrd 0x00 lowpower_control 0x00 lowpower_auto_enable 0x00 int_ack */ /* 01001110 dll_start_point 0x00 dll_lock 0x06 dll_increment 0x06 trc */ /* 0x15 dll_dqs_delay_1 0x15 dll_dqs_delay_0 0x00 int_status 0x00 int_mask */ /* 0x02 dqs_out_shift_bypass 0x7f dqs_out_shift 0x1a dll_dqs_delay_bypass_1 0x1a dll_dqs_delay_bypass_0 */ /* 0x02 trcd_int 0x05 tras_min 0x1c wr_dqs_shift_bypass 0x12 wr_dqs_shift */ /* 0x000000 out_of_range_length 0x07 trfc */ /* 0x0008 ahb0_wrcnt 0x0008 ahb0_rdcnt */ /* 0x0020 ahb1_wrcnt 0x0020 ahb1_rdcnt */ /* 0x0020 ahb2_wrcnt 0x0020 ahb2_rdcnt */ /* 0x0020 ahb3_wrcnt 0x0020 ahb3_rdcnt */ /* 0x000002e6 tref */ /* 0x00000000 */ /* 0x00000000 */ i.MX23 Applications Processor Reference Manual, Rev. 1 12-72 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) 0x00000000, 0x00000000, 0x00000000, 0x000c1a3b, 0x0000000c, 0x00004b0d, 0x00000000, 0x00000101, 0x00040001, 0x00400000, 0x00400040, 0x00030040, }, /* /* /* /* /* /* /* /* /* /* /* /* 0x0000 lowpower_internal_cnt 0x0000 lowpower_external_cnt */ 0x0000 lowpower_refresh_hold 0x0000 lowpower_power_down_cnt */ 0x0000 tdll 0x0000 lowpower_self_refresh_cnt */ 0x000c txsnr 0x1a3b tras_max */ 0x0000 version 0x000c txsr */ 0x00004b0d tinit */ 0x00000000 out_of_range_addr */ 0x00 pwrup_srefresh_exit 0x00 enable_quick_srefresh 0x01 bus_share_enable 0x01 active_aging */ 0x000400 bus_share_timeout 0x01 tref_enable */ 0x0040 emrs2_data_0 0x0000 emrs1_data */ 0x0040 emrs2_data_2 0x0040 emrs2_data_1 */ 0x0003 tpdex 0x0040 emrs2_data_3 */ 12.6.3 Mobile DDR (7.5 nsec) Table 12-97. Frequency Dependent Parameters Parameter TCKE TDAL TDLL TEMRS TINIT TMRD TPDEX TRAS_MAX TRAS_MIN TRC TRCD_INT TREF TRFC TRP TRRD TWR_INT TWTR TXSNR TXSR 24 MHz 48 MHz 60 MHz 96 MHz 120 MHz 133 MHz 0x0002 0x03 0x0000 0x02 0x000012C1 0x02 0x0001 0x0687 0x02 0x02 0x01 0x00B3 0x02 0x01 0x01 0x02 0x02 0x0003 0x0003 0x0002 0x04 0x0000 0x02 0x00002582 0x02 0x0002 0x0D17 0x03 0x04 0x02 0x016F 0x04 0x02 0x01 0x02 0x02 0x0006 0x0006 0x0002 0x04 0x0000 0x02 0x00002EE5 0x02 0x0002 0x1060 0x03 0x05 0x02 0x01CC 0x05 0x02 0x01 0x02 0x02 0x0008 0x0008 0x0002 0x05 0x0000 0x02 0x00004B0D 0x02 0x0003 0x1A3B 0x05 0x08 0x03 0x02E6 0x07 0x03 0x02 0x02 0x02 0x000C 0x000C 0x0002 0x05 0x0000 0x02 0x00005DCA 0x02 0x0004 0x20CA 0x06 0x0A 0x03 0x03A1 0x09 0x03 0x02 0x02 0x02 0x000F 0x000F 0x0002 0x05 0x0000 0x02 0x00006665 0x02 0x0004 0x23CD 0x06 0x0A 0x03 0x03F7 0x0A 0x03 0x02 0x02 0x02 0x0010 0x0010 12.6.3.1 Bypass Cutoff Suggested bypass cutoff frequency is 72 MHz. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-73 External Memory Interface (EMI) 12.6.3.2 Bypass Mode Enabled Table 12-98. Delays Parameter 24 MHz 48 MHz 60 MHz 72 MHz DLL_DQS_DELAY_BYPASS_0 DLL_DQS_DELAY_BYPASS_1 DQS_OUT_SHIFT_BYPASS WR_DQS_SHIFT_BYPASS 0x19 0x19 0x01 0x18 0x0D 0x0D 0x01 0x0D 0x0B 0x0B 0x01 0x0A 0x0C 0x0C 0x01 0x0C 12.6.3.3 Bypass Mode Disabled Table 12-99. DLL Parameter 60 MHz 96 MHz 120 MHz 133 MHz DLL_INCREMENT DLL_START_POINT 0x22 0x7E 0x15 0x25 0x11 0x19 0x0F 0x19 Table 12-100. Delays Parameter Value DLL_DQS_DELAY_1 DLL_DQS_DELAY_0 DQS_OUT_SHIFT WR_DQS_SHIFT 0x0D 0x0D 0x7F 0x20 12.6.3.4 Example Register Settings //////////////////////////////////////////////////////////////////////////////// // // Filename: mobile_ddr_mt46h16m16lf_7.5_regs_3_120MHz.h // // Description: Initialization register values for EMI DRAM controller // //////////////////////////////////////////////////////////////////////////////// // // WARNING! THIS FILE IS AUTOMATICALLY GENERATED. // DO NOT MODIFY THIS FILE DIRECTLY. // // SETTINGS USED TO GENERATE THIS FILE: // // Burst: 4 // CAS: 3 // Freq: 120 MHz // Auto-Precharge: 0 // DLL_Bypass: 0 // //////////////////////////////////////////////////////////////////////////////// { 0x01010001, /* 0x01 ahb0_w_priority 0x01 ahb0_r_priority 0x00 ahb0_fifo_type_reg 0x01 addr_cmp_en */ i.MX23 Applications Processor Reference Manual, Rev. 1 12-74 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) 0x00010100, 0x01000101, 0x00000001, 0x00000101, 0x00000001, 0x00010000, 0x01000001, 0x01000000, 0x00000001, 0x07000200, 0x00070303, 0x02020002, 0x06060a02, 0x00000201, 0x03050000, 0x02000000, 0x1900110a, 0x1e1e0000, 0x01011919, 0x03061820, 0x00000009, 0x00080008, 0x00200020, 0x00200020, 0x00200020, 0x000003a1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000f20ca, 0x0000000f, 0x00005dca, 0x00000000, 0x00000101, 0x00040001, 0x00400000, 0x00400040, 0x00040040, }, /* 0x00 ahb2_fifo_type_reg 0x01 ahb1_w_priority 0x01 ahb1_r_priority 0x00 ahb1_fifo_type_reg */ /* 0x01 ahb3_r_priority 0x00 ahb3_fifo_type_reg 0x01 ahb2_w_priority 0x01 ahb2_r_priority */ /* 0x00 auto_refresh_mode 0x00 arefresh 0x00 ap 0x01 ahb3_w_priority */ /* 0x00 dll_bypass_mode 0x00 dlllockreg 0x01 concurrentap 0x01 bank_split_en */ /* 0x00 intrptreada 0x00 intrptapburst 0x00 fast_write 0x01 en_lowpower_mode */ /* 0x00 power_down 0x01 placement_en 0x00 no_cmd_init 0x00 intrptwritea */ /* 0x01 rw_same_en 0x00 reg_dimm_enable 0x00 rd2rd_turn 0x01 priority_en */ /* 0x01 tras_lockout 0x00 start 0x00 srefresh 0x00 sdr_mode */ /* 0x00 out_of_range_type 0x00 out_of_range_source_id 0x00 write_modereg 0x01 writeinterp */ /* 0x07 age_count 0x00 addr_pins 0x02 temrs 0x00 q_fullness */ /* 0x00 max_cs_reg 0x07 command_age_count 0x03 column_size 0x03 caslat */ /* 0x02 twr_int 0x02 trrd 0x0002 tcke */ /* 0x06 caslat_lin_gate 0x06 caslat_lin 0x0a aprebit 0x02 twtr */ /* 0x00 max_col_reg 0x00 lowpower_refresh_enable 0x02 initaref 0x01 cs_map */ /* 0x03 trp 0x05 tdal 0x00 port_busy 0x00 max_row_reg */ /* 0x02 tmrd 0x00 lowpower_control 0x00 lowpower_auto_enable 0x00 int_ack */ /* 0x19 dll_start_point 0x00 dll_lock 0x11 dll_increment 0x0a trc */ /* 0x1e dll_dqs_delay_1 0x1e dll_dqs_delay_0 0x00 int_status 0x00 int_mask */ /* 0x01 dqs_out_shift_bypass 0x01 dqs_out_shift 0x19 dll_dqs_delay_bypass_1 0x19 dll_dqs_delay_bypass_0 */ /* 0x03 trcd_int 0x06 tras_min 0x18 wr_dqs_shift_bypass 0x20 wr_dqs_shift */ /* 0x000000 out_of_range_length 0x09 trfc */ /* 0x0008 ahb0_wrcnt 0x0008 ahb0_rdcnt */ /* 0x0020 ahb1_wrcnt 0x0020 ahb1_rdcnt */ /* 0x0020 ahb2_wrcnt 0x0020 ahb2_rdcnt */ /* 0x0020 ahb3_wrcnt 0x0020 ahb3_rdcnt */ /* 0x000003a1 tref */ /* 0x00000000 */ /* 0x00000000 */ /* 0x0000 lowpower_internal_cnt 0x0000 lowpower_external_cnt */ /* 0x0000 lowpower_refresh_hold 0x0000 lowpower_power_down_cnt */ /* 0x0000 tdll 0x0000 lowpower_self_refresh_cnt */ /* 0x000f txsnr 0x20ca tras_max */ /* 0x0000 version 0x000f txsr */ /* 0x00005dca tinit */ /* 0x00000000 out_of_range_addr */ /* 0x00 pwrup_srefresh_exit 0x00 enable_quick_srefresh 0x01 bus_share_enable 0x01 active_aging */ /* 0x000400 bus_share_timeout 0x01 tref_enable */ /* 0x0040 emrs2_data_0 0x0000 emrs1_data */ /* 0x0040 emrs2_data_2 0x0040 emrs2_data_1 */ /* 0x0004 tpdex 0x0000 emrs2_data_3 */ i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-75 External Memory Interface (EMI) 12.6.4 DDR Table 12-101. Frequency Dependent Parameters Parameter TCKE TDAL TDLL TEMRS TINIT TMRD TPDEX TRAS_MAX TRAS_MIN TRC TRCD_INT TREF TRFC TRP TRRD TWR_INT TWTR TXSNR TXSR 80 MHz 96 MHz 120 MHz 133 MHz 167 MHz 0x0000 0x04 0x00C8 0x00 0x00003E80 0x01 0x0001 0x15D6 0x04 0x05 0x02 0x00000269 0x0006 0x02 0x01 0x02 0x01 0x0006 0x00C8 0x0000 0x04 0x00C8 0x00 0x00004B0D 0x02 0x0001 0x1A3B 0x05 0x06 0x02 0x000002E6 0x0007 0x02 0x02 0x02 0x01 0x0008 0x00C8 0x0000 0x04 0x00C8 0x00 0x00005DCA 0x02 0x0001 0x20CA 0x06 0x08 0x02 0x000003A1 0x0009 0x02 0x02 0x02 0x01 0x000A 0x00C8 0x0000 0x04 0x00C8 0x00 0x00006665 0x02 0x0001 0x23CD 0x06 0x08 0x02 0x000003F7 0x000A 0x02 0x02 0x02 0x01 0x000A 0x00C8 0x0000 0x05 0x00C8 0x00 0x000081C7 0x02 0x0001 0x2D62 0x07 0x0A 0x03 0x00000509 0x000C 0x03 0x02 0x02 0x01 0x000D 0x00C8 12.6.4.1 Bypass Mode Disabled Table 12-102. DLL Parameter 80 MHz 96 MHz 120 MHz 133 MHz 167 MHz NOTE: DDR should always be run with bypass disabled. DLL_INCREMENT DLL_START_POINT 0x1C 0x20 0x17 0x2F 0x13 0x26 0x11 0x22 0x0D 0x18 Table 12-103. Delays Parameter 80 MHz 96 MHz 120 MHz 133 MHz 160 MHz DLL_DQS_DELAY_1 DLL_DQS_DELAY_0 DQS_OUT_SHIFT WR_DQS_SHIFT 0x1F 0x1F 0x7F 0x22 0x1F 0x1F 0x7F 0x22 0x1F 0x1F 0x7F 0x23 0x1F 0x1F 0x7F 0x23 0x1F 0x1F 0x7F 0x24 i.MX23 Applications Processor Reference Manual, Rev. 1 12-76 Preliminary--Subject to Change Without Notice Freescale Semiconductor External Memory Interface (EMI) 12.6.4.2 Example Register Settings //////////////////////////////////////////////////////////////////////////////// // // Filename: ddr_mt46v32m16_6t_regs_2.5_167MHz.h // // Description: Initialization register values for EMI DRAM controller // //////////////////////////////////////////////////////////////////////////////// // // WARNING! THIS FILE IS AUTOMATICALLY GENERATED. // DO NOT MODIFY THIS FILE DIRECTLY. // // SETTINGS USED TO GENERATE THIS FILE: // // Burst: 4 // CAS: 2.5 // Freq: 167MHz // Auto-Precharge: 0 // DLL_Bypass: 0 // //////////////////////////////////////////////////////////////////////////////// { 0x01010001, 0x00010100, 0x01000101, 0x00000001, 0x00000101, 0x00000000, 0x00010000, 0x01000001, 0x01000000, 0x00000001, 0x07000200, 0x00070206, 0x02020000, 0x05050a01, 0x0000020f, 0x03050000, 0x02000000, 0x18000d0a, 0x1f1f0000, 0x027f0f0f, 0x03071124, 0x0000000c, 0x00080008, 0x00200020, 0x00200020, 0x00200020, 0x00000509, 0x00000000, 0x00000000, /* 0x01 ahb0_w_priority 0x01 ahb0_r_priority 0x00 ahb0_fifo_type_reg 0x01 addr_cmp_en */ /* 0x00 ahb2_fifo_type_reg 0x01 ahb1_w_priority 0x01 ahb1_r_priority 0x00 ahb1_fifo_type_reg */ /* 0x01 ahb3_r_priority 0x00 ahb3_fifo_type_reg 0x01 ahb2_w_priority 0x01 ahb2_r_priority */ /* 0x00 auto_refresh_mode 0x00 arefresh 0x00 ap 0x01 ahb3_w_priority */ /* 0x00 dll_bypass_mode 0x00 dlllockreg 0x01 concurrentap 0x01 bank_split_en */ /* 0x00 intrptreada 0x00 intrptapburst 0x00 fast_write 0x00 en_lowpower_mode */ /* 0x00 power_down 0x01 placement_en 0x00 no_cmd_init 0x00 intrptwritea */ /* 0x01 rw_same_en 0x00 reg_dimm_enable 0x00 rd2rd_turn 0x01 priority_en */ /* 0x01 tras_lockout 0x00 start 0x00 srefresh 0x00 sdr_mode */ /* 0x00 out_of_range_type 0x00 out_of_range_source_id 0x00 write_modereg 0x01 writeinterp */ /* 0x07 age_count 0x00 addr_pins 0x02 temrs 0x00 q_fullness */ /* 0x00 max_cs_reg 0x07 command_age_count 0x02 column_size 0x06 caslat */ /* 0x02 twr_int 0x02 trrd 0x0000 tcke */ /* 0x05 caslat_lin_gate 0x05 caslat_lin 0x0a aprebit 0x01 twtr */ /* 0x00 max_col_reg 0x00 lowpower_refresh_enable 0x02 initaref 0x01 cs_map */ /* 0x03 trp 0x05 tdal 0x00 port_busy 0x00 max_row_reg */ /* 0x02 tmrd 0x00 lowpower_control 0x00 lowpower_auto_enable 0x00 int_ack */ /* 0x18 dll_start_point 0x00 dll_lock 0x0d dll_increment 0x0a trc */ /* 0x1f dll_dqs_delay_1 0x1f dll_dqs_delay_0 0x00 int_status 0x00 int_mask */ /* 0x02 dqs_out_shift_bypass 0x7f dqs_out_shift 0x0f dll_dqs_delay_bypass_1 0x0f dll_dqs_delay_bypass_0 */ /* 0x03 trcd_int 0x07 tras_min 0x11 wr_dqs_shift_bypass 0x24 wr_dqs_shift */ /* 0x000000 out_of_range_length 00001100 trfc */ /* 0x0008 ahb0_wrcnt 0x0008 ahb0_rdcnt */ /* 0x0020 ahb1_wrcnt 0x0020 ahb1_rdcnt */ /* 0x0020 ahb2_wrcnt 0x0020 ahb2_rdcnt */ /* 0x0020 ahb3_wrcnt 0x0020 ahb3_rdcnt */ /* 0x00000509 tref */ /* 0x00000000 */ /* 0x00000000 */ i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 12-77 External Memory Interface (EMI) 0x00000000, 0x00000000, 0x00c80000, 0x000d2d62, 0x000000c8, 0x000081c7, 0x00000000, 0x00000101, 0x00040001, 0x00000000, 0x00000000, 0x00010000, }, /* /* /* /* /* /* /* /* /* /* /* /* 0x0000 lowpower_internal_cnt 0x0000 lowpower_external_cnt */ 0x0000 lowpower_refresh_hold 0x0000 lowpower_power_down_cnt */ 0x00c8 tdll 0x0000 lowpower_self_refresh_cnt */ 0x000d txsnr 0x2d62 tras_max */ 0x0000 version 0x00c8 txsr */ 0x000081c7 tinit */ 0x00000000 out_of_range_addr */ 0x00 pwrup_srefresh_exit 0x00 enable_quick_srefresh 0x01 bus_share_enable 0x01 active_aging */ 0x000400 bus_share_timeout 0x01 tref_enable */ 0x0000 emrs2_data_0 0x0000 emrs1_data */ 0x0000 emrs2_data_2 0x0000 emrs2_data_1 */ 0x0001 tpdex 0x0000 emrs2_data_3 */ i.MX23 Applications Processor Reference Manual, Rev. 1 12-78 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 13 General-Purpose Media Interface (GPMI) This chapter describes the general-purpose media interface (GPMI) on the i.MX23. Programmable registers are described in Section 13.4, "Programmable Registers." 13.1 Overview The general-purpose media interface (GPMI) controller is a flexible interface to up to four NAND Flash. The NAND Flash mode has configurable address and command behavior, providing support for future devices not yet specified. The GPMI resides on the APBH. The GPMI also provides an interface to the ECC8 and BCH modules to allow direct parity processing. Registers are clocked on the HCLK (CLK_H) domain. The I/O and pin timing are clocked on a dedicated GPMICLK domain. GPMICLK can be set to maximize I/O performance. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13-1 General-Purpose Media Interface (GPMI) Figure 13-1 shows a block diagram of the GPMI controller. A RM Core SRAM System Clock G enerator AHB AHB-to-APBH Bridge AHB SLAVE AHB M ASTER DMA Request 0 DMA Request 1 DMA Request 2 APBH M ASTER APBH GPM I State Machine 0 GPMI State M achine 1 GPMI State M achine 2 DMA Request 3 GPMI State Machine 3 ECC8 and BCH G PM I Pin Arbitration HCLK GPM I GPM I Pin State M achine M emory Controller GPIO G PMICLK GPMI / Memory / GPIO Pin Mux Pins Figure 13-1. General-Purpose Media Interface Controller Block Diagram 13.2 * * * GPMI NAND Flash Mode Individual chip select and ready/busy pins for four NAND Flash. Individual state machine and DMA channel for each chip select. Special command modes work with DMA controller to perform all normal NAND Flash functions without CPU intervention. i.MX23 Applications Processor Reference Manual, Rev. 1 The general-purpose media interface has several features to efficiently support NAND Flash: 13-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor HCLK SHARED DMA General-Purpose Media Interface (GPMI) * Configurable timing based on a dedicated clock allows optimal balance of high NAND Flash performance and low system power. Since current NAND Flash does not support multiple page read/write commands, the GPMI and DMA have been designed to handle complex multi-page operations without CPU intervention. The DMA uses a linked descriptor function with branching capability to automatically handle all of the operations needed to read/write multiple pages: * * Data/Register Read/Write--The GPMI can be programmed to read or write multiple cycles to the NAND Flash address, command or data registers. Wait for NAND Flash Ready--The GPMI's Wait-for-Ready mode can monitor the ready/busy signal of a single NAND Flash and signal the DMA when the device has become ready. It also has a time-out counter and can indicate to the DMA that a time-out error has occurred. The DMAs can conditionally branch to a different descriptor in the case of an error. Check Status--The Read-and-Compare mode allows the GPMI to check NAND Flash status against a reference. If an error is found, the GPMI can instruct the DMA to branch to an alternate descriptor, which attempts to fix the problem or asserts a CPU IRQ. * 13.2.1 Multiple NAND Flash Support The GPMI supports up to four NAND Flash chip selects, each with independent ready/busy signals. Since they share a data bus and control lines, the GPMI can only actively communicate with a single NAND Flash at a time. However, all NAND Flashes can concurrently perform internal read, write, or erase operations. With fast NAND Flash and software support for concurrent NAND Flash operations, this architecture allows the total throughput to approach the data bus speed, which can be as high as 80 MB/s (16-bit bus running at 40 MHz). 13.2.2 GPMI NAND Flash Timing and Clocking The dedicated clock, GPMICLK, is used as a timing reference for NAND Flash I/O. Since various NAND Flashes have different timing requirements, GPMICLK may need to be adjusted for each application. While the actual pin timings are limited by the NAND Flash chips used, the GPMI can support data bus speeds of up to 33 MHz x 16 bits. The actual read/write strobe timing parameters are adjusted as indicated in the register descriptions in Section 13.4, "Programmable Registers." Refer to Chapter 4, "Clock Generation and Control," for more information about setting GPMICLK. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13-3 General-Purpose Media Interface (GPMI) 13.2.3 Basic NAND Flash Timing Figure 13-2 illustrates the operation of the timing parameters in NAND Flash mode. GPMI_CE[3:0] / ALE / CLE GPMI_OEn/ GPMI_WRn TDS TDH TDS Data1 TAS TDH GPMI_DATA Data0 Figure 13-2. BASIC NAND Flash Timing 13.2.4 High-Speed NAND Flash Timing In high-speed NAND Flashes, the read data may not be valid until after the read strobe (RDN) deasserts. This is the case when the minimum tDS is programmed to achieve higher bandwidth. The GPMI implements a feedback read strobe to sample the read data. The feedback read strobe can be delayed to support fast NAND Flash EDO (Extended Data Out) timing where the read strobe may deassert before the read data is valid, and read data is valid for some time after read strobe. NAND Flash EDO timings is applied typically for read cycle frequency above 33MHz. See Figure 13-3. The GPMI provides control over the amount of delay applied to the feedback read strobe. This delay depends on the maximum read access time (tREA) of the NAND Flash and the read pulse width (tRP) used to access the NAND Flash. tRP is specified by HW_GPMI_TIMING0_DATA_SETUP register. When (tREA + 4ns) is less than tRP, no delay is required to sample to NAND Flash read data. (The 4ns provides adequate data setup time for the GPMI.) In this case set HW_GPMI_CTRL1_HALF_PERIOD=0; HW_GPMI_CTRL1_RDN_DELAY=0; HW_GPMI_CTRL1_DLL_ENABLE=0. When (tREA + 4ns) is greater than or equal to tRP, a delay of the feedback read strobe is required to sample to NAND Flash read data. This delay is equal to the difference between these two timings: DELAY= tREA+4ns - tRP. Since the GPMI delay chain is limited to 16ns maximum, if DELAY > 16ns then increase tRP by increasing the value of HW_GPMI_TIMING0_DATA_SETUP until DELAY is less than or equal to 16ns. The GPMI programming for this DELAY depends on the GPMICLK period. The GPMI DLL will not function properly if the GPMICLK period is greater than 32ns: disable the DLL if this is the case. If the GPMICLK period is greater than 16ns (and not greater than 32ns), set the HW_GPMI_CTRL1_HALF_PERIOD=1; This will cause the DLL reference period (RP) to be one-half of the GPMICLK period. If the GPMICLK period is 16ns or less then set the i.MX23 Applications Processor Reference Manual, Rev. 1 13-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor General-Purpose Media Interface (GPMI) HW_GPMI_CTRL1_HALF_PERIOD=0; This will cause the DLL reference period (RP) to be equal to the GPMICLK period. DELAY is a multiple (0 to 1.875) of RP. The HW_GPMI_CTRL1_RDN_DELAY is encoded as a 1-bit integer and 3-bit fraction delay factor. See table below. DELAY is a multiple of the delay factor and the reference period: Table 13-1. HW_GPMI_CTRL1_RDN_DELAY Delay Factor HW_GPMI_CTRL1_RDN_DELAY Delay Factor 0 1 2 3 4 5 6 7 0.000 8 0.125 9 0.250 10 0.375 11 0.500 12 0.625 13 0.750 14 0.875 15 1.000 1.125 1.250 1.375 1.500 1.625 1.750 1.875 -- DELAY = DelayFactor x RP or -- DELAY = HW_GPMI_CTRL1_RDN_DELAY x 0.125 x RP. Use this equation to calculate the value for HW_GPMI_CTRL1_RDN_DELAY. Then set HW_GPMI_CTRL1_DLL_ENABLE=1. GPMI NAND Read Path Timing Diagram (Non-EDO) tRP tREA RDN Read Data A B C FeedbackRDN (tREA + 4ns) is less than tRP, no delay is required on rising edge of FeedbackRDN to sample Read Data GPMI NAND Read Path Timing Diagram (EDO mode) tREA tRP RDN Read Data A B Delay C FeedbackRDN When (tREA + 4ns) is greater than or equal to tRP, a delay of the FeedbackRDN is required to sample to nand read data Figure 13-3. NAND Flash Read Path Timing i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13-5 General-Purpose Media Interface (GPMI) For example, a NAND Flash with tREAmax=20ns, tRPmin=12ns, and tRCmin=25ns (read cycle time) may be programmed as follows: * GPMICLK clock frequency: Consider 480/6=80MHz which is 12.5ns clock period. This is too close to the minimum NAND Flash spec if we program the data setup and hold to 1 GPMICLK cycle. Consider 480/7=68.57MHz which is 14.58ns clock period. With data setup and hold set to 1, we have a tRP of 14.58ns and a tRC of 29.16ns (good margins). Since (tREA +4ns) is greater than tRP, required DELAY = tREA+4ns - tRP = 20 + 4 - 14.58ns = 9.42ns. HALF_PERIOD =0, since GPMICLK period is less than 16ns. So RP=GPMICLK period = 14.58ns. DELAY = HW_GPMI_CTRL1_RDN_DELAY x 0.125 x RP. 9.42ns = HW_GPMI_CTRL1_RDN_DELAY x 0.125 x 14.58ns. HW_GPMI_CTRL1_RDN_DELAY = 5 (round off 5.169) * * * Note: It is recommended that the drive strength of GPMI_RDn and GPMI_WRn output pins be set to 8 mA. This will reduce the transition time under heavy loads. Low transition times will be important when NAND Flash interface read and write cycle times are below 30 ns. The other GPMI pins may remain at 4 mA, since their frequency is only up to half that of GPMI_RDn and GPMI_WRn. 13.2.5 NAND Flash Command and Address Timing Example Figure 13-4 illustrates a command and address being sent to a NAND Flash. Run=1 Run=0 Run=1 Run=0 GPMI_CEn TAS GPMI_ALE TAS GPMI_CLE TDH TDH GPMI_WEn TDS TDS TDH read cmd GPMI_DATA $00 AL[7:0] AL[15:8] Figure 13-4. NAND Flash Command and Address Timing Example 13.2.6 Hardware BCH/ECC (ECC8) Interface The GPMI provides an interface to the ECC8 module. This same interface is used by the BCH module when in BCH mode. This reduces the SoC bus traffic and the software involvement. When in BCH or i.MX23 Applications Processor Reference Manual, Rev. 1 13-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor General-Purpose Media Interface (GPMI) ECC8 mode, parity information is inserted on-the-fly during writes to 8-bit NAND Flash devices. (Note that ECC8 mode is not avaiable with 16-bit devices.) During NAND Flash reads, parity is checked and ECC processing is performed after each read block. In ECC8 mode, during NAND Flash writes, each 512-byte block of payload data is sent to the ECC8 module at the same time it is sent to the NAND Flash. The ECC8 module returns the parity information, which is then appended to the block of data written to the NAND Flash. This is repeated for each block of data written to the NAND Flash. During NAND Flash reads, each block of payload data and parity is redirected to the ECC8 module for ECC processing and memory write, instead of DMA to memory. This works the same way for BCH mode. To program the ECC8 for NAND Flash writes, remove the soft reset and clock gates from HW_ECC8_CTRL_SFTRST and HW_ECC8_CTRL_CLKGATE. The bulk ECC8 programming is actually applied to the GPMI via PIO operations embedded in its DMA command structures. This has a subtle implication when writing to the GPMI ECC8 registers: access to the these registers must be written in progressive register order. Thus, to write to the HW_GPMI_ECCCOUNT register, write first (in order) to registers HW_GPMI_CTRL0, HW_GPMI_COMPARE, and HW_GPMI_ECCCTRL before writing to HW_GPMI_ECCCOUNT. These additional register writes need to be accounted for in the CMDWORDS field of the respective DMA channel command register. See the descriptive text, flowcharts, and code examples in Section 14.2.1, "Reed-Solomon ECC Accelerator," Section 14.2.2, "Reed-Solomon ECC Encoding for NAND Writes," and Section 14.2.3, "Reed-Solomon ECC Decoding for NAND Reads" for more information about using GPMI registers to program the ECC8 function. Note that the HW_GPMI_PAYLOAD and HW_GPMI_AUXILIARY pointers need to be word-aligned for proper ECC8 operation. If those pointers are non-word-aligned, then the ECC8 engine will not operate properly and could possibly corrupt system memory in the adjoining memory regions. Note that when using DMA to read from the NAND, there are two possible interrupts: * * GPMI DMA completion interrupt ECC engine completion interrupt (only used when the data is read using ECC in the DMA descriptor) When the NAND is read using ECC (as configured in the DMA descriptor for that read), the CPU must wait for both interrupts, and the interrupts may occur in either order. That is, the GPMI interrupt may happen before the ECC interrupt, or vice-versa. Software needs to wait until both interrupts have occurred to know that the data has been delivered by the DMA. When the NAND is read without using ECC (as configured in the DMA descriptor for that read), the CPU only needs to wait for the GPMI interrupt. (Indeed, there will be no ECC interrupt, because the ECC engine is not in use.). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13-7 General-Purpose Media Interface (GPMI) 13.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block" for additional information on using the SFTRST and CLKGATE bit fields. i.MX23 Applications Processor Reference Manual, Rev. 1 13-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor General-Purpose Media Interface (GPMI) 13.4 Programmable Registers The following registers provide control for programmable elements of the GPMI module. 13.4.1 GPMI Control Register 0 Description The GPMI control register 0 specifies the GPMI transaction to perform for the current command chain item. HW_GPMI_CTRL0 HW_GPMI_CTRL0_SET HW_GPMI_CTRL0_CLR HW_GPMI_CTRL0_TOG Table 13-2. HW_GPMI_CTRL0 3 1 3 0 2 9 2 8 2 7 TIMEOUT_IRQ_EN 2 6 2 5 COMMAND_MODE 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 ADDRESS_INCREMENT 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x000 0x004 0x008 0x00C WORD_LENGTH Table 13-3. HW_GPMI_CTRL0 Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Set to zero for normal operation. When this bit is set to one (default), then the entire block is held in its reset state. This will not work if the CLKGATE bit is already set to '1'. CLKGATE must be cleared to '0' before issuing a soft reset. Also the GPMICLK must be running for this to work properly. RUN = 0x0 Allow GPMI to operate normally. RESET = 0x1 Hold GPMI in reset. 30 CLKGATE RW 0x1 Set this bit zero for normal operation. Setting this bit to one (default), gates all of the block level clocks off for miniminizing AC energy consumption. RUN = 0x0 Allow GPMI to operate normally. NO_CLKS = 0x1 Do not clock GPMI gates in order to minimize power consumption. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice XFER_COUNT LOCK_CS CLKGATE SFTRST RSVD3 RSVD2 RSVD1 RUN CS 13-9 General-Purpose Media Interface (GPMI) Table 13-3. HW_GPMI_CTRL0 Bit Field Descriptions BITS RUN 29 LABEL RW RESET RW 0x0 DEFINITION The GPMI is busy running a command whenever this bit is set to '1'. The GPMI is idle whenever this bit set to zero. This can be set to one by a CPU write. In addition, the DMA sets this bit each time a DMA command has finished its PIO transfer phase. IDLE = 0x0 The GPMI is idle. BUSY = 0x1 The GPMI is busy running a command. 28 27 RSVD3 TIMEOUT_IRQ_EN RW 0x0 RW 0x0 26 RSVD2 RW 0x0 RW 0x0 Program this field to 0x0. Setting this bit to '1' will enable timeout IRQ for WAIT_FOR_READY commands. The Device_Busy_Timeout value is used for this timeout. Program this field to 0x0. DISABLED = 0x0 Use ATA-PIO mode on the external bus. ENABLED = 0x1 Use ATA-Ultra DMA mode on the external bus. 25:24 COMMAND_MODE 00= Write mode. 01= Read Mode. 10= Read and Compare Mode (setting sense flop). 11= Wait for Ready. WRITE = 0x0 Write mode. READ = 0x1 Read mode. READ_AND_COMPARE = 0x2 Read and Compare mode (setting sense flop). WAIT_FOR_READY = 0x3 Wait for Ready mode. 23 WORD_LENGTH RW 0x0 0= 16-bit Data Bus Mode. 1= 8-bit Data Bus mode. This bit should only be changed when RUN==0. 16_BIT = 0x0 16-bit Data Bus Mode. 8_BIT = 0x1 8-bit Data Bus mode. 22 LOCK_CS RW 0x0 For NAND mode: 0= Deassert chip select (CS) after RUN is complete. 1= Continue to assert chip select (CS) after RUN is complete. For Camera Mode: 0= Dont wait for VSYNC rising edge before capturing data. 1= Wait for VSYNC rising edge before capturing data (Camera mode only). DISABLED = 0x0 Deassert chip select (CS) after RUN is complete. ENABLED = 0x1 Continue to assert chip select (CS) after RUN is complete. 21:20 CS RW 0x0 19:17 RSVD1 RW 0x0 Selects which chip select is active for this command. For WAIT_FOR_READY command, this must be set to b01. Program this field to 0x0. NAND_DATA = 0x0 In NAND mode, this address is used to read and write data bytes. NAND_CLE = 0x1 In NAND mode, this address is used to write command bytes. NAND_ALE = 0x2 In NAND mode, this address is used to write address bytes. 16 ADDRESS_INCREMENT RW 0x0 0= Address does not increment. 1= Increment address. In ATA mode, the address will increment with each cycle. In NAND mode, the address will increment once, after the first cycle (going from CLE to ALE). DISABLED = 0x0 Address does not increment. ENABLED = 0x1 Increment address. 15:0 XFER_COUNT RW 0x0 Number of words (8 or 16 bit wide) to transfer for this command. A value of zero will transfer 64K words. i.MX23 Applications Processor Reference Manual, Rev. 1 13-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor General-Purpose Media Interface (GPMI) DESCRIPTION: The GPMI control register 0 specifies the GPMI transaction to perform for the current command chain item. EXAMPLE: No Example. 13.4.2 GPMI Compare Register Description The GPMI compare register specifies the expect data and the xor mask for comparing to the status values read from the device. This register is used by the Read and Compare command. HW_GPMI_COMPARE Table 13-4. HW_GPMI_COMPARE 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 MASK 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 REFERENCE 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x010 Table 13-5. HW_GPMI_COMPARE Bit Field Descriptions BITS 31:16 MASK LABEL RW RESET RW 0x0000 DEFINITION 16-bit mask which is applied after the read data is XORed with the REFERENCE bit field. 16-bit value which is XORed with data read from the NAND device. 15:0 REFERENCE RW 0x0000 DESCRIPTION: The GPMI compare register specifies the expect data and the xor mask for comparing to the status values read from the device. This register is used by the Read and Compare command. EXAMPLE: No Example. 13.4.3 GPMI Integrated ECC Control Register Description HW_GPMI_ECCCTRL HW_GPMI_ECCCTRL_SET HW_GPMI_ECCCTRL_CLR HW_GPMI_ECCCTRL_TOG 0x020 0x024 0x028 0x02C The GPMI ECC control register handles configuration of the integrated ECC accelerator. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13-11 General-Purpose Media Interface (GPMI) Table 13-6. HW_GPMI_ECCCTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 ECC_CMD 1 3 1 2 ENABLE_ECC 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 BUFFER_MASK 0 3 0 2 0 1 0 0 HANDLE RSVD2 Table 13-7. HW_GPMI_ECCCTRL Bit Field Descriptions BITS 31:16 HANDLE LABEL RW RESET RW 0x0 DEFINITION This is a register available to software to attach an identifier to a transaction in progress. This handle will be available from the ECC register space when the completion interrupt occurs. Always write zeroes to this bit field. ECC Command information. For Reed-Solomon ECC, this value only controls payload correction, the auxiliary area is always covered by 4-bit mode. Note that when using BCH ECC, bit 1 has no effect, and bit 0 determines Encode (0x1) and Decode (0x0). DECODE_4_BIT = 0x0 Reed-Solomon Decode in 4-bit Mode, BCH Decode ENCODE_4_BIT = 0x1 Reed-Solomon Encode in 4-bit Mode, BCH Encode DECODE_8_BIT = 0x2 Reed-Solomon Decode in 8-bit Mode, BCH Decode ENCODE_8_BIT = 0x3 Reed-Solomon Encode in 8-bit Mode, BCH Encode RSVD2 15 14:13 ECC_CMD RO 0x0 RW 0x0 12 ENABLE_ECC RW 0x0 Enable ECC processing of GPMI transfers. ENABLE = 0x1 Use integrated ECC for read and write transfers. DISABLE = 0x0 Integrated ECC remains in idle. i.MX23 Applications Processor Reference Manual, Rev. 1 13-12 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor General-Purpose Media Interface (GPMI) Table 13-7. HW_GPMI_ECCCTRL Bit Field Descriptions BITS LABEL 11:9 RSVD1 BUFFER_MASK 8:0 RW RESET RO 0x00 RW 0x000 DEFINITION Always write zeroes to this bit field. ECC Command information. Single or multiple buffers may be accessed per command. When multiple buffers are accessed, each buffer to be accessed must be adjacent to the next buffer being accessed. When ECC_CMD indicates 8-bit mode, this means that the BUFFER_MASK bits must not contain any zeros between ones. For example, 0b111100000 is valid (4 contiguous buffers), but 0b100110011 is invalid (because buffers 2, 3, 6, and 7 are skipped over). When ECC_CMD indicates 4-bit mode, bits 4 to 7 are not used and must be set to 0x0 so that Buffer 3 will be adjacent to the Auxiliary buffer. For example, 0b100001110 is valid (4 contiguous buffers), but 0b100000111 is invalid (because Buffer 3 is skipped over). Invalid buffer mask values will cause improper and undefined system behavior. The BCH error correction only allows two configurations of the buffer mask - software may either read just the first block on the flash page or the entire flash page. Write operations must be for the entire flash page. BCH_AUXONLY = 0x100 Set to request transfer from only the auxiliary buffer (block 0 on flash). BCH_PAGE = 0x1FF Set to request transfer to/from the entire page. AUXILIARY = 0x100 Set to request transfer to/from the auxiliary buffer. BUFFER7 = 0x080 Set to request transfer to/from data buffer 7. BUFFER6 = 0x040 Set to request transfer to/from data buffer 6. BUFFER5 = 0x020 Set to request transfer to/from data buffer 5. BUFFER4 = 0x010 Set to request transfer to/from data buffer 4. BUFFER3 = 0x008 Set to request transfer to/from data buffer 3. BUFFER2 = 0x004 Set to request transfer to/from data buffer 2. BUFFER1 = 0x002 Set to request transfer to/from data buffer 1. BUFFER0 = 0x001 Set to request transfer to/from data buffer 0. DESCRIPTION: The GPMI ECC control register handles configuration of the integrated ECC accelerator. EXAMPLE: No Example. 13.4.4 GPMI Integrated ECC Transfer Count Register Description HW_GPMI_ECCCOUNT 0x030 The GPMI ECC Transfer Count Register contains the count of bytes that flow through the ECC subsystem. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13-13 General-Purpose Media Interface (GPMI) Table 13-8. HW_GPMI_ECCCOUNT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RSVD2 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 COUNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 13-9. HW_GPMI_ECCCOUNT Bit Field Descriptions BITS 31:16 RSVD2 15:0 COUNT LABEL RW RESET RO 0x0000 RW 0x0000 DEFINITION Always write zeroes to this bit field. Number of bytes to pass through ECC. This is the GPMI transfer count plus the syndrome count that will be inserted into the stream by the ECC. In DMA2ECC_MODE this count must match the HW_GPMI_CTRL0_XFER_COUNT. A value of zero will transfer 64K words. DESCRIPTION: The GPMI ECC Transfer Count Register contains the count of bytes that flow through the ECC subsystem. EXAMPLE: No Example. 13.4.5 GPMI Payload Address Register Description The GPMI payload address register specifies the location of the data buffers in system memory. This value must be word aligned. HW_GPMI_PAYLOAD Table 13-10. HW_GPMI_PAYLOAD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 ADDRESS 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 RSVD0 DEFINITION Pointer to an array of one or more 512 byte payload buffers. Always write zeroes to this bit field. 0 0 0x040 Table 13-11. HW_GPMI_PAYLOAD Bit Field Descriptions BITS LABEL 31:2 ADDRESS RW RESET RW 0x00000000 1:0 RSVD0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 13-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor General-Purpose Media Interface (GPMI) DESCRIPTION: The GPMI payload address register specifies the location of the data buffers in system memory. This value must be word aligned. EXAMPLE: No Example. 13.4.6 GPMI Auxiliary Address Register Description The GPMI auxiliary address register specifies the location of the auxiliary buffers in system memory. This value must be word aligned. HW_GPMI_AUXILIARY Table 13-12. HW_GPMI_AUXILIARY 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 ADDRESS 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 RSVD0 DEFINITION Pointer to ECC control structure and meta-data storage. Always write zeroes to this bit field. 0 0 0x050 Table 13-13. HW_GPMI_AUXILIARY Bit Field Descriptions BITS LABEL 31:2 ADDRESS RW RESET RW 0x00000000 1:0 RSVD0 RO 0x0 DESCRIPTION: The GPMI auxiliary address register specifies the location of the auxiliary buffers in system memory. This value must be word aligned. EXAMPLE: No Example. 13.4.7 GPMI Control Register 1 Description HW_GPMI_CTRL1 HW_GPMI_CTRL1_SET HW_GPMI_CTRL1_CLR HW_GPMI_CTRL1_TOG 0x060 0x064 0x068 0x06C The GPMI control register 1 specifies additional control fields that are not used on a per-transaction basis. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13-15 General-Purpose Media Interface (GPMI) Table 13-14. HW_GPMI_CTRL1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 ABORT_WAIT_FOR_READY3 0 6 ABORT_WAIT_FOR_READY2 0 5 ABORT_WAIT_FOR_READY1 0 4 ABORT_WAIT_FOR_READY0 0 3 0 2 ATA_IRQRDY_POLARITY 0 1 0 0 GANGED_RDYBUSY DMA2ECC_MODE HALF_PERIOD TIMEOUT_IRQ DLL_ENABLE Table 13-15. HW_GPMI_CTRL1 Bit Field Descriptions BITS LABEL 31:24 RSVD3 CE3_SEL 23 RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bit field. This field is NOT implemented. Set this bit to 1 to use the alternate Chip Enable for GPMI_CE3n, and deasert GPMI_CE3n. When set to 0, the alternate Chip Enable (GPMI_CE7n) is deasserted and GPMI_CE3n is active during transfers. This field is NOT implemented. Set this bit to 1 to use the alternate Chip Enable for GPMI_CE2n, and deasert GPMI_CE2n. When set to 0, the alternate Chip Enable (GPMI_CE6n) is deasserted and GPMI_CE2n is active during transfers. This field is NOT implemented. Set this bit to 1 to use the alternate Chip Enable for GPMI_CE1n, and deasert GPMI_CE1n. When set to 0, the alternate Chip Enable (GPMI_CE5n) is deasserted and GPMI_CE1n is active during transfers. This field is NOT implemented. Set this bit to 1 to use the alternate Chip Enable for GPMI_CE0n, and deasert GPMI_CE0n. When set to 0, the alternate Chip Enable (GPMI_CE4n) is deasserted and GPMI_CE0n is active during transfers. Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0. This will free up all, except one, RDY_BUSY input pins. This bit selects which error correction unit will access GPMI. 1 = BCH, 0 = ECC8. Set this bit to 1 to enable the GPMI DLL. This is required for fast NAND reads (above 30MHz read strobe). After setting this bit, wait 64 GPMI clock cycles for the DLL to lock before performing a NAND read. Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation. DLL_ENABLE must be zero while changing this field. 22 CE2_SEL RW 0x0 21 CE1_SEL RW 0x0 20 CE0_SEL RW 0x0 19 GANGED_RDYBUSY RW 0x0 18 17 BCH_MODE DLL_ENABLE RW 0x0 RW 0x0 16 HALF_PERIOD RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 13-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor GPMI_MODE RDN_DELAY DEV_RESET BCH_MODE BURST_EN CE3_SEL CE2_SEL CE1_SEL CE0_SEL RSVD2 RSVD3 RSVD1 General-Purpose Media Interface (GPMI) Table 13-15. HW_GPMI_CTRL1 Bit Field Descriptions BITS LABEL 15:12 RDN_DELAY RW RESET RW 0x0 DEFINITION This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling. The applied delay (AD) is between 0 and 1.875 times the reference period (RP). RP is one half of the GPMI clock period if HALF_PERIOD=1 otherwise it is the full GPMI clock period. The equation is: AD = RDN_DELAY x 0.125 x RP. This value must not exceed 16ns. This variable is used to achieve faster NAND access. For example if the Read Strobe is asserted from time 0 to 13ns but the read access time is 20ns, then choose AD=12ns will cause the data to be sampled at time 25ns (13+12) giving a 5ns data setup time. If RP=13ns then RDN_DELAY = 12/(0.125 x 13ns) = 7.38 (0111b). DLL_ENABLE must be zero while changing this field. This is mainly for testing HWECC without involving the Nand device. Setting this bit will cause DMA write data to redirected to HWECC module (instead of Nand Device) for encoding or decoding. Program this field to 0x0. This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. Abort a wait for ready command on channel 3. Abort a wait for ready command on channel 2. Abort a wait for ready command on NAND channel 1. Abort a wait for ready command on channel 0. 0= Device Reset pin is held low (asserted). 1= Device Reset pin is held high (de-asserted). ENABLED = 0x0 Device Reset pin is held low (asserted). DISABLED = 0x1 Device Reset pin is held high (de-asserted). 11 DMA2ECC_MODE RW 0x0 10 9 8 7 6 5 4 3 RSVD2 TIMEOUT_IRQ BURST_EN ABORT_WAIT_FOR_READY3 ABORT_WAIT_FOR_READY2 ABORT_WAIT_FOR_READY1 ABORT_WAIT_FOR_READY0 DEV_RESET RW 0x0 RW 0x0 RW 0x0 RW RW RW RW RW 0x0 0x0 0x0 0x0 0x0 2 ATA_IRQRDY_POLARITY RW 0x1 For NAND MODE: 0= External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high. 1= External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low. Note NAND_RDY_BUSY[3:2] are not affected by this bit. ACTIVELOW = 0x0 NAND_RDY_BUSY[1:0] are active low ready. ACTIVEHIGH = 0x1 NAND_RDY_BUSY[1:0] are active high ready. 1 0 RSVD1 GPMI_MODE RW 0x0 RW 0x0 Program this field to 0x0. 0= NAND mode. 1= RESERVED DESCRIPTION: The GPMI control register 1 specifies additional control fields that are not used on a per-transaction basis. EXAMPLE: No Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13-17 General-Purpose Media Interface (GPMI) 13.4.8 GPMI Timing Register 0 Description The GPMI timing register 0 specifies the timing parameters that are used by the cycle state machine to guarantee the various setup, hold and cycle times for the external media type. HW_GPMI_TIMING0 Table 13-16. HW_GPMI_TIMING0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ADDRESS_SETUP 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 DATA_HOLD 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 DATA_SETUP 0 3 0 2 0 1 0 0 0x070 RSVD1 Table 13-17. HW_GPMI_TIMING0 Bit Field Descriptions BITS LABEL 31:24 RSVD1 23:16 ADDRESS_SETUP RW RESET RO 0x0 RW 0x01 DEFINITION Always write zeroes to this bit field. Number of GPMICLK cycles that the CE signals are active before a strobe is asserted. A value of zero is interpreted as 0. Data bus hold time in GPMICLK cycles. Also the time that the data strobe is de-asserted in a cycle. A value of zero is interpreted as 256. Data bus setup time in GPMICLK cycles. Also the time that the data strobe is asserted in a cycle. A value of zero is interpreted as 256. 15:8 DATA_HOLD RW 0x02 7:0 DATA_SETUP RW 0x03 DESCRIPTION: The GPMI timing register 0 specifies the timing parameters that are used by the cycle state machine to guarantee the various setup, hold and cycle times for the external media type. EXAMPLE: No Example. 13.4.9 GPMI Timing Register 1 Description HW_GPMI_TIMING1 0x080 The GPMI timing register 1 specifies the timeouts used when monitoring the NAND READY pin. i.MX23 Applications Processor Reference Manual, Rev. 1 13-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor General-Purpose Media Interface (GPMI) Table 13-18. HW_GPMI_TIMING1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 DEVICE_BUSY_TIMEOUT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 13-19. HW_GPMI_TIMING1 Bit Field Descriptions BITS LABEL 31:16 DEVICE_BUSY_TIMEOUT RW RESET RW 0x0000 DEFINITION Timeout waiting for NAND Ready/Busy. Used in WAIT_FOR_READY mode. This value is the number of GPMI_CLK cycles multiplied by 4096. Always write zeroes to this bit field. 15:0 RSVD1 RO 0x0 DESCRIPTION: The GPMI timing register 1 specifies the timeouts used when monitoring the NAND READY pin. EXAMPLE: No Example. 13.4.10 GPMI DMA Data Transfer Register Description The GPMI DMA data transfer register is used by the DMA to read or write data to or from the NAND control state machine. HW_GPMI_DATA Table 13-20. HW_GPMI_DATA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0A0 DATA Table 13-21. HW_GPMI_DATA Bit Field Descriptions BITS 31:0 DATA LABEL RW RESET RW 0x00000 DEFINITION In 16-bit mode, this register can be accessed in two 16-bit operations, one bus cycle per operation. In 8-bit mode, one, two, three or four bytes can can be accessed to send the same number of bus cycles. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 13-19 General-Purpose Media Interface (GPMI) DESCRIPTION: The GPMI DMA data transfer register is used by the DMA to read or write data to or from the NAND control state machine. EXAMPLE: No Example. 13.4.11 GPMI Status Register Description The GPMI control and status register provides a read back path for various operational states of the GPMI controller. HW_GPMI_STAT Table 13-22. HW_GPMI_STAT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 INVALID_BUFFER_MASK 0 5 0 4 0 3 0 2 0 1 0 0 0x0B0 RDY_TIMEOUT DEV3_ERROR DEV2_ERROR DEV1_ERROR Table 13-23. HW_GPMI_STAT Bit Field Descriptions BITS LABEL 31 PRESENT RW RESET RO 0x1 DEFINITION 0= GPMI is not present in this product. 1= GPMI is present is in this product. UNAVAILABLE = 0x0 GPMI is not present in this product. AVAILABLE = 0x1 GPMI is present in this product. 30:12 11:8 7 6 5 RSVD2 RDY_TIMEOUT RSVD1 INVALID_BUFFER_MASK FIFO_EMPTY RO RO RO RO 0x0 0x0 0x0 0x0 RO 0x1 Always write zeroes to this bit field. Status of the RDY/BUSY Timeout Flags. Program this field to 0x0. 0= ECC Buffer Mask is not invalid. 1= ECC Buffer Mask is invalid. 0= FIFO is not empty. 1= FIFO is empty. NOT_EMPTY = 0x0 FIFO is not empty. EMPTY = 0x1 FIFO is empty. 4 FIFO_FULL RO 0x0 0= FIFO is not full. 1= FIFO is full. NOT_FULL = 0x0 FIFO is not full. FULL = 0x1 FIFO is full. 3 DEV3_ERROR RO 0x0 0= No error condition present on NAND Device 3. 1= An Error has occurred on NAND Device 3 (Timeout or compare failure, depending on COMMAND_MODE). i.MX23 Applications Processor Reference Manual, Rev. 1 13-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor DEV0_ERROR FIFO_EMPTY FIFO_FULL PRESENT RSVD2 RSVD1 General-Purpose Media Interface (GPMI) Table 13-23. HW_GPMI_STAT Bit Field Descriptions BITS LABEL 2 DEV2_ERROR RW RESET RO 0x0 DEFINITION 0= No error condition present on NAND Device 2. 1= An Error has occurred on NAND Device 2 (Timeout or compare failure, depending on COMMAND_MODE). 0= No error condition present on NAND Device 1. 1= An Error has occurred on NAND Device 1 (Timeout or compare failure, depending on COMMAND_MODE). 0= No error condition present on NAND Device 0. 1= An Error has occurred on NAND Device 0 (Timeout or compare failure, depending on COMMAND_MODE). 1 DEV1_ERROR RO 0x0 0 DEV0_ERROR RO 0x0 DESCRIPTION: The GPMI control and status register provides a read back path for various operational states of the GPMI controller. EXAMPLE: No Example. 13.4.12 GPMI Debug Information Register Description The GPMI debug information register provides a read back path for diagnostics to determine the current operating state of the GPMI controller. HW_GPMI_DEBUG Table 13-24. HW_GPMI_DEBUG 3 1 3 0 2 9 2 8 2 7 WAIT_FOR_READY_END3 2 6 WAIT_FOR_READY_END2 2 5 WAIT_FOR_READY_END1 2 4 WAIT_FOR_READY_END0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0C0 UDMA_STATE Table 13-25. HW_GPMI_DEBUG Bit Field Descriptions BITS 31 30 29 28 LABEL READY3 READY2 READY1 READY0 RW RO RO RO RO RESET 0x0 0x0 0x0 0x0 DEFINITION Read-only view of Ready Line 3. Read-only view of Ready Line 2. Read-only view of Ready Line 1. Read-only view of Ready Line 0. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice MAIN_STATE PIN_STATE DMAREQ3 DMAREQ2 DMAREQ1 DMAREQ0 CMD_END READY3 READY2 READY1 READY0 SENSE3 SENSE2 SENSE1 SENSE0 BUSY 13-21 General-Purpose Media Interface (GPMI) Table 13-25. HW_GPMI_DEBUG Bit Field Descriptions BITS LABEL WAIT_FOR_READY_END3 27 RW RESET RO 0x0 DEFINITION Read-only view of WAIT_FOR_READY command end of channel 3. This view sees the toggle state. Read-only view of WAIT_FOR_READY command end of channel 2. This view sees the toggle state. Read-only view of WAIT_FOR_READY command end of channel 1. This view sees the toggle state. Read-only view of WAIT_FOR_READY command end of channel 0. This view sees the toggle state. Read-only view of sense state of channel 3. A value of "1" indicates that a read and compare command failed or a timeout occured. Read-only view of sense state of channel 2. A value of "1" indicates that a read and compare command failed or a timeout occured. Read-only view of sense state of channel 1. A value of "1" indicates that a read and compare command failed or a timeout occured. Read-only view of sense state of channel 0. A value of "1" indicates that a read and compare command failed or a timeout occured. Read-only view of DMA request line for channel 3. This view sees the toggle state. Read-only view of DMA request line for channel 2. This view sees the toggle state. Read-only view of DMA request line for channel 1. This view sees the toggle state. Read-only view of DMA request line for channel 0. This view sees the toggle state. Read Only view of the Command End toggle to DMA. One per channel USM_IDLE = 4'h0, idle USM_DMARQ = 4'h1, DMA req USM_ACK = 4'h2, DMA ACK USM_FIFO_E = 4'h3, Fifo empty USM_WPAUSE = 4'h4, WR DMA Paused by device USM_TSTRB = 4'h5, Toggle HSTROBE USM_CAPTUR = 4'h6, Capture Stage, (data sampled with DSTROBE is valid) USM_DATOUT = 4'h7, Change Burst DATAOUT USM_CRC = 4'h8, Source CRC to Device USM_WAIT_R = 4'h9, Waiting for DDMARDYUSM_END = 4'ha; Negate DMAACK (end of DMA) USM_WAIT_S = 4'hb, Waiting for DSTROBE USM_RPAUSE = 4'hc, Rd DMA Paused by Host USM_RSTOP = 4'hd, Rd DMA Stopped by Host USM_WTERM = 4'he, Wr DMA Termination State USM_RTERM = 4'hf, Rd DMA Termination state When asserted the GPMI is busy. Undefined results may occur if any registers are written when BUSY is asserted. DISABLED = 0x0 The GPMI is not busy. ENABLED = 0x1 The GPMI is busy. 26 25 24 23 WAIT_FOR_READY_END2 WAIT_FOR_READY_END1 WAIT_FOR_READY_END0 SENSE3 RO 0x0 RO 0x0 RO 0x0 RO 0x0 22 SENSE2 RO 0x0 21 SENSE1 RO 0x0 20 SENSE0 RO 0x0 19 18 17 16 DMAREQ3 DMAREQ2 DMAREQ1 DMAREQ0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 15:12 CMD_END 11:8 UDMA_STATE 7 BUSY RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 13-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor General-Purpose Media Interface (GPMI) Table 13-25. HW_GPMI_DEBUG Bit Field Descriptions BITS LABEL 6:4 PIN_STATE RW RESET RO 0x0 DEFINITION parameter PSM_IDLE = 3'h0, PSM_BYTCNT = 3'h1, PSM_ADDR = 3'h2, PSM_STALL = 3'h3, PSM_STROBE = 3'h4, PSM_ATARDY = 3'h5, PSM_DHOLD = 3'h6, PSM_DONE = 3'h7. PSM_IDLE = 0x0 PSM_BYTCNT = 0x1 PSM_ADDR = 0x2 PSM_STALL = 0x3 PSM_STROBE = 0x4 PSM_ATARDY = 0x5 PSM_DHOLD = 0x6 PSM_DONE = 0x7 3:0 MAIN_STATE RO 0x0 parameter MSM_IDLE = 4'h0, MSM_BYTCNT = 4'h1, MSM_WAITFE = 4'h2, MSM_WAITFR = 4'h3, MSM_DMAREQ = 4'h4, MSM_DMAACK = 4'h5, MSM_WAITFF = 4'h6, MSM_LDFIFO = 4'h7, MSM_LDDMAR = 4'h8, MSM_RDCMP = 4'h9, MSM_DONE = 4'hA. MSM_IDLE = 0x0 MSM_BYTCNT = 0x1 MSM_WAITFE = 0x2 MSM_WAITFR = 0x3 MSM_DMAREQ = 0x4 MSM_DMAACK = 0x5 MSM_WAITFF = 0x6 MSM_LDFIFO = 0x7 MSM_LDDMAR = 0x8 MSM_RDCMP = 0x9 MSM_DONE = 0xA DESCRIPTION: The GPMI debug information register provides a read back path for diagnostics to determine the current operating state of the GPMI controller. EXAMPLE: No Example. 13.4.13 GPMI Version Register Description This register reflects the version number for the GPMI. HW_GPMI_VERSION Table 13-26. HW_GPMI_VERSION 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0D0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13-23 General-Purpose Media Interface (GPMI) Table 13-27. HW_GPMI_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x03 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x00 RO 0x0000 DESCRIPTION: This register reflects the version number for the GPMI. EXAMPLE: No Example. 13.4.14 GPMI Debug2 Information Register Description The GPMI Debug2 information register provides a read back path for diagnostics to determine the current operating state of the GPMI controller. HW_GPMI_DEBUG2 Table 13-28. HW_GPMI_DEBUG2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 SYND2GPMI_BE 1 3 1 2 1 1 GPMI2SYND_VALID 1 0 GPMI2SYND_READY 0 9 SYND2GPMI_VALID 0 8 SYND2GPMI_READY 0 7 VIEW_DELAYED_RDN 0 6 UPDATE_WINDOW 0 5 0 4 0 3 0 2 0 1 0 0 0x0E0 Table 13-29. HW_GPMI_DEBUG2 Bit Field Descriptions BITS 31:16 15:12 11 10 9 8 7 LABEL RSVD1 SYND2GPMI_BE GPMI2SYND_VALID GPMI2SYND_READY SYND2GPMI_VALID SYND2GPMI_READY VIEW_DELAYED_RDN RW RO RO RO RO RO RO RW RESET 0x0000 0xf 0x0 0x0 0x0 0x0 0x0 DEFINITION Always write zeroes to this bit field. Data byte enable Input from ECC8 or BCH. Data handshake output to ECC8 or BCH. Data handshake output to ECC8 or BCH. Data handshake Input from ECC8 or BCH. Data handshake Input from ECC8 or BCH. Set to a 1 to select the delayed feedback RDN to drive the GPMI_ADDR[0] (Nand CLE) pin. For debug purposes, this will allow you see if DLL is functioning properly. i.MX23 Applications Processor Reference Manual, Rev. 1 13-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor RDN_TAP RSVD1 General-Purpose Media Interface (GPMI) Table 13-29. HW_GPMI_DEBUG2 Bit Field Descriptions BITS LABEL 6 UPDATE_WINDOW RW RESET RO 0x0 DEFINITION A 1 indicates that the DLL is busy generating the required delay. This is the DLL tap calculated by the DLL controller. The selects the amount of delay form the DLL chain. 5:0 RDN_TAP RO 0x00 DESCRIPTION: The GPMI Debug2 information register provides a read back path for diagnostics to determine the current operating state of the GPMI controller. EXAMPLE: No Example. 13.4.15 GPMI Debug3 Information Register Description The GPMI Debug3 information register provides a read back path for diagnostics to determine the current operating state of the GPMI controller. HW_GPMI_DEBUG3 Table 13-30. HW_GPMI_DEBUG3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 APB_WORD_CNTR 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 DEV_WORD_CNTR 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0F0 Table 13-31. HW_GPMI_DEBUG3 Bit Field Descriptions BITS LABEL 31:16 APB_WORD_CNTR RW RESET RO 0x0000 DEFINITION Reflects the number of words (16 or 8-bit) remains to be transferred on the APB bus. Reflects the number of words (16 or 8-bit) remains to be transferred on the Nand bus. 15:0 DEV_WORD_CNTR RO 0x0000 DESCRIPTION: The GPMI Debug3 information register provides a read back path for diagnostics to determine the current operating state of the GPMI controller. EXAMPLE: No Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13-25 General-Purpose Media Interface (GPMI) GPMI Block v3.0, Revision 2.2 13.4.16 i.MX23 Applications Processor Reference Manual, Rev. 1 13-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 14 8-Symbol Correcting ECC Accelerator (ECC8) This chapter describes the DMA-based hardware ECC accelerator (ECC8) available on the i.MX23. It provides detailed descriptions of how to use the Reed-Solomon ECC accelerator. Programmable registers are described in Section 14.4, "Programmable Registers." 14.1 Overview The hardware ECC accelerator provides a forward error-correction function for improving the reliability of various storage media that may be attached to the i.MX23. For example, modern high-density NAND flash devices presume the existence of forward error-correction algorithms to correct some soft and/or hard bit errors within the device, allowing for higher device yields and, therefore, lower device costs. The hardware ECC8 accelerator uses the Reed-Solomon block codes, a subset of BCH codes, for multi-symbol error corrections. A symbol comprises multiple bits. The ECC8 operates on 9-bit symbols in its computations. A symbol error (and correction) means that any one or all bits of the symbol could be in error. Thus, under a best case scenario, a 4-symbol ECC protection can correct up to 36 bits (= 4 * 9) in error. Under the worst case scenario, only 4 bits (= 4 * 1) can be corrected. In a Reed-Solomon ECC, the fixed data payload to be protected is mapped into data symbols to represent a unique polynomial. The polynomial is divided by a known generator polynomial (that is a function of the number of symbols to be corrected), where the residual remainder polynomial becomes the parity symbols. An ECC codeword is formed by concatenating the data symbols with the parity symbols. This ECC codeword is then written onto the storage media. All arithmetic operations in the Reed-Solomon ECC algorithm operate under Galois fields. The ECC8 supports t=4 symbol correction for 2K page NAND and t=8 symbol correction for 4K page NANDs. Error correction occurs when the ECC codeword is read back from the storage media through the RS decoder. The RS decoder processes the code word in four phases. All phases may not be necessary, for example when no errors are found or when uncorrectable errors are detected. The four phases are: 1. Syndrome Calculation Phase (SC)--This is the process of reading in all of the symbols of the block and continuously dividing the code word by the generator polynomial that is a function of the number of symbols to be corrected. The remainder of this division is the syndrome polynomial. If the remainder is zero, i.e., the syndrome symbols are all zero, then the RS code word is correct and no bit errors were detected in the read NAND data, and an ECC8 interrupt is generated upon completion of this phase. Otherwise, we proceed to the next phase. This phase takes place i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-1 8-Symbol Correcting ECC Accelerator (ECC8) completely on the GPMI clock domain and is fully overlapped with NAND reads from the NAND device. There are approximately two GPMICLK cycles that are not overlapped. The data is passed to the HCLK domain and there are approximately 20 HCLK cycles that are not overlapped on the final block transferred. 2. Key Equation Solver Phase (KES)--After the eight (or sixteen) symbol syndromes have been calculated, a set of eight (or sixteen) linear equations with eight (or sixteen) unknowns is formed. The process of solving these equations and selecting from the numerous possible solutions constitutes the KES phase. The hardware block uses the Berlekamp-Massey algorithm to solve the key equations from the syndrome symbols. The resulting and polynomials are used in the next phase to determine symbol error locations and the respective correction mask. If the hardware detects an uncorrectable scenario while computing the and polynomials, it will terminate and report the appropriate status. This phase takes up to 288 GPMICLK and 20 HCLK cycles, with no planned DMA wait states added. 3. Chien Search and Forney Evaluator Phase (EVAL)--This phase takes the and polynomials from the KES phase and uses Chien's algorithm for finding the locations of the errors based on the polynomial. The method basically involves substituting all 511 nine-bit symbols into the polynomial. All non-zero results of these substitutions represent the locations of the various symbol errors. At this point, another calculation involving the and polynomials determines the error value or the correction to apply at the symbol in the error locations. This phase consumes approximately 550 GPMICLK cycles and no HCLK cycles, with no planned DMA wait states added. 4. Error Correction Phase (CORR)--The CORR phase applies any required read-modify-write cycles to the data payload and/or auxiliary payload to correct any correctable errors. An ECC8 interrupt is generated upon completion of this phase. Firmware examines the error status registers and then clears the interrupt status bit (in that order). The ECC8 block was designed to operate in a pipelined fashion to maximize throughput. Aside from the initial latency to fill the pipeline stages, the ECC8 throughput is faster than the fastest GPMI read rate of 2 cycles/byte. Thus, the bottleneck in performing NAND reads and error corrections is the GPMI read rate. Current GPMI read rates are approximately 3 cycles/byte for the current generation of NANDs. The ECC8 block has an AHB master that allows the CPU to focus on signal processing for enhanced functionality and to operate at lower clock frequencies and voltages for improved battery life. The CPU is not directly involved in generating parity symbols, checking for errors, or correcting them. The hardware ECC8 accelerator is illustrated in Figure 14-1. i.MX23 Applications Processor Reference Manual, Rev. 1 14-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) AHB AHB Slave AHB Master AHB-to-APBH DMA APBH Master GPMI Programmable Registers APBH AHB-to-APBH Bridge ECC8 Programmable Registers 32-Bit Read Data and Stored Parity Write parity GPMI NAND Controller 4-Symbol & 8-Symbol Parity/Syndrome Generator Syndrome Chien Search Syndrome 4-Symbol & 8-Symbol Key Equation Solver (KES) AHB Master and Transfer FSM Forney Evaluator Index, correct error_calc GPMI Clock Domain ECC8 Engine Figure 14-1. Hardware 8-Symbol Correcting ECC Accelerator (ECC8) Block i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-3 8-Symbol Correcting ECC Accelerator (ECC8) 14.2 Operation The data flow for NAND reads passes data directly from the GPMI controller to the ECC8 accelerator without first passing through system memory. This is a much higher bandwidth flow than the APBH DMA transfers used on the previous generations of SoCs. In addition, the copying to and from system memory is eliminated. Because the ECC8 operates on data flowing directly from the GPMI, it handles all error correction operations in an optimized pipelined manner. That is, blocks without errors complete within 20 HCLK cycles of the GPMI completing the read transfer. If errors are present, then the necessary pipeline stages are activated, including error calculation and error correction stages. Unlike the previous generation HWECC, the ECC8 engine directly performs all error corrections in the system memory buffer without CPU intervention, i.e., when the CPU gets an ECC8 interrupt, the error correction process is complete for all blocks of a transaction. A read transaction for a 4K NAND page can consist of up to 9 block transfers, i.e., eight blocks of 512-byte payload and one block of 65-byte auxiliary data. For a 2K NAND page, up to 5 block transfers can be specified for a single transaction, i.e., four blocks of 512-byte payload and one block of 19-byte auxiliary data. For NAND write operations, the GPMI fetches the write data via its DMA interface as usual. However, it forks a copy of the write data to the ECC8 parity/syndrome generator. The ECC8 computes the parity bytes for the transfer on the fly. As soon as the GPMI writes the last data byte to the NAND, it switches its data flow so that the 9 or 18 bytes of Reed-Solomon ECC parity is copied from the ECC8 parity/syndrome generator directly to the NAND. In this case, no extra buffer in system memory is required. The ECC parity generation is fully overlapped with the data write transfer, so that the parity bytes are written immediately after the data is written, with only a few GPMICLK cycles of latency. The ECC8 engine supports both an 8-symbol correcting mode and a 4-symbol correcting mode. The number of parity bytes required for each mode is different. For example, the 8-symbol correcting mode requires 16 parity symbols to be stored with the data. This corresponds to 18 bytes of parity information. Since a 2K page NAND device has only 64 bytes of spare, it cannot hold the required 4*18 =72 bytes of parity data. Recall that a 2K page holds four 512-byte payload blocks. Thus, the 4-symbol correcting mode must be used for 2K page NAND devices. Fortunately, this is consistent with the bit error densities guaranteed for 2K page NAND devices. Figure 14-2 and Figure 14-3 show the organization of the 4-symbol correcting mode 2K page NAND storage, both on the NAND and in the system memory footprint. Figure 14-4 and Figure 14-5 show the NAND image and the system memory footprint used in the 8-symbol correcting mode available for 4K pages only. Notice that the auxiliary data is protected by the 4-symbol error correcting mode, regardless of whether it is stored on a 2K page NAND device or a 4K page NAND device. i.MX23 Applications Processor Reference Manual, Rev. 1 14-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) Total NAND Memory Footprint: 2112 Bytes 2048 Bytes Data + 64 Bytes Redundant Area = 4 * (512B + 9B) + (19 + 9B) 512 bytes 512 bytes in 455 + 1/9 nine-bit symbols (4-symbol correctable) 9 bytes 9 parity bytes cover data only 512 bytes 512 bytes in 455 + 1/9 nine-bit symbols (4-symbol correctable) 9 bytes 9 parity bytes cover data only 2112 bytes 512 bytes 512 bytes in 455 + 1/9 nine-bit symbols (4-symbol correctable) 9 bytes 9 parity bytes cover data only 512 bytes 512 bytes in 455 + 1/9 nine-bit symbols (4-symbol correctable) 9 bytes 19 bytes 9 bytes 9 parity bytes cover data only 19 bytes of auxiliary storage (4-symbol correctable) 9 parity bytes cover auxiliary only Figure 14-2. ECC-Protected 2K NAND Page Data--NAND Memory Footprint i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-5 8-Symbol Correcting ECC Accelerator (ECC8) Total System Memory Footprint: 2236 Bytes 2048 Bytes Data = 4 * 512B 512-Byte Payload A HW_GPMI_PAYLOAD Freescale Semiconductor Preliminary--Subject to Change Without Notice 512-Byte Payload B 2048 bytes 512-Byte Payload C 512-Byte Payload D 68 Bytes Metadata + 120 Bytes ECC Data = 68B + 5 * (12B + 12B) 68 bytes of auxiliary storage (4-symbol correctable) 188 Bytes ECC8 Control Area and Auxiliary Storage Reserved Figure 14-3. ECC-Protected 2K NAND Page Data--System Memory Footprint i.MX23 Applications Processor Reference Manual, Rev. 1 14-6 HW_GPMI_AUXILIARY 8-Symbol Correcting ECC Accelerator (ECC8) Total NAND Memory Footprint: 4314 Bytes 4096 Bytes Data + 218 Bytes Redundant Area = 8 * (512B + 18B) + (65B + 9B) 512 bytes In 455+1/9 nine-bit symbols (8-symbol correctable) 18 parity bytes cover data only 512 bytes In 455+1/9 nine-bit symbols (8-symbol correctable) 18 parity bytes cover data only 512 bytes In 455+1/9 nine-bit symbols (8-symbol correctable) 18 parity bytes cover data only 512 bytes In 455+1/9 nine-bit symbols (8-symbol correctable) 18 parity bytes cover data only 512 bytes In 455+1/9 nine-bit symbols (8-symbol correctable) 18 parity bytes cover data only 512 bytes In 455+1/9 nine-bit symbols (8-symbol correctable) 18 parity bytes cover data only 512 bytes In 455+1/9 nine-bit symbols (8-symbol correctable) 18 parity bytes cover data only 512 bytes In 455+1/9 nine-bit symbols (8-symbol correctable) 18 parity bytes cover data only 65 bytes of auxiliary storage (4-symbol correctable) 9 parity bytes cover auxiliary only 512 bytes 18 bytes 512 bytes 18 bytes 512 bytes 18 bytes 512 bytes 18 bytes 512 bytes 18 bytes 512 bytes 18 bytes 512 bytes 18 bytes 512 bytes 18 bytes 4314 bytes 65B 9 bytes Figure 14-4. ECC-Protected 4K NAND Page Data--NAND Memory Footprint i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-7 8-Symbol Correcting ECC Accelerator (ECC8) Total System Memory Footprint: 4508 Bytes 4096 Bytes Data = 8 * 512B 512-Byte Payload A HW_GPMI_PAYLOAD HW_GPMI_AUXILIARY Freescale Semiconductor Preliminary--Subject to Change Without Notice 512-Byte Payload B 512-Byte Payload C 4096 bytes 512-Byte Payload D 512-Byte Payload E 512-Byte Payload F 512-Byte Payload G 512-Byte Payload H 68 Bytes Metadata + 344 Bytes ECC Data = 68B + (12B + 12B) + 8 * (20B + 20B) 68 bytes of auxiliary storage (4-symbol correctable) 412 Bytes ECC8 Control Area and Auxiliary Storage Reserved Figure 14-5. ECC-Protected 4K NAND Page Data--System Memory Footprint 14.2.1 Reed-Solomon ECC Accelerator The Reed-Solomon algorithm used in ECC8 is capable of correcting up to 8 nine-bit symbols in a 512-byte block. Thus, up to 72 bits in error can be corrected in a 512-byte block, provided they are clustered within no more than 8 nine-bit symbols. * 2K pages have four 512-byte data blocks (+ 9 bytes parity) and one 19-byte auxiliary block (+ 9 bytes parity). i.MX23 Applications Processor Reference Manual, Rev. 1 14-8 8-Symbol Correcting ECC Accelerator (ECC8) * 4K pages have eight 512-byte data blocks (+ 18 bytes parity) and one 65-byte auxiliary block (+ 9 bytes parity). To understand how the Reed-Solomon algorithm is implemented on the i.MX23, consider the case where there are eight 512-byte data blocks located in the on-chip RAM that need to be written to a NAND flash device. Further, assume that there is a 65-byte metadata block that needs to be written to the NAND device. Further assume that the NAND is a 4K page device. Normal DMA channel command word processing in the APBH DMA allows buffers to start on arbitrary byte boundaries within system memory, i.e., buffers are byte-aligned. In operation with the ECC8 engine, the DMA channel command word processing requires the buffers to start on word boundaries within system memory. Specifically, the HW_GPMI_PAYLOAD and HW_GPMI_AUXILIARY pointers need to be word-aligned for proper ECC8 operation. If those pointers are non-word-aligned, then the ECC8 engine will not operate properly and could possibly corrupt system memory in the adjoining memory regions. Assume that the data is stored in system memory in the layout shown in the memory foot print of Figure 14-5. (Note that the data residing in system memory needs to be word-aligned.) In programming the GPMI to write to the NAND, the DMA must be programmed with two DMA descriptors: one that points to the beginning of the PAYLOAD data area and a second to point to the AUXILIARY metadata block. This programming is set up exactly as for the previous generation's version of the GPMI. Program the GPMI to write these blocks to the NAND, and in addition, program the GPMI to run in ECC8 write mode by setting the following: HW_GPMI_ECCCTRL = BV_FLD(GPMI_ECCCTRL,ECC_CMD,ENCODE_8_BIT)| BV_FLD(GPMI_ECCCTRL,ENABLE_ECC,ENABLE)| BF_GPMI_ECCCTRL_BUFFER_MASK (0x1FF); HW_GPMI_ECCCOUNT =BF_GPMI_ECCCOUNT_COUNT (8*(512+18) + (65+9)) NOTE: The buffer mask value is used to specify which data blocks and/or auxiliary block is involved in a transaction. The buffer mask must be contiguous i.e., the data blocks and/or auxiliary block need to be consecutive. For example, a transaction involving only data blocks 0, 1, and 2 (buffer mask value = 0x007) is legal, while a transaction of data blocks 1, 2, 4, 6, plus the auxiliary block (buffer mask value = 0x155) is illegal. Illegal buffer mask values will cause improper and undefined system behavior. Set the first DMA command transfer size to (8*512) bytes. Set the second DMA command transfer size to 65 bytes. In this mode, the GPMI and the ECC8 collaborate to compute the 16-symbol (18-byte) parity values that must be written to the NAND at the end of each of the eight payload data blocks. In addition, the ECC8 calculates the 8-symbol (9-byte) parity value to be appended to the 65-byte metadata block on the NAND device. Programming the ECC8 module for NAND writes consists of clearing the soft reset and clock gates bits (HW_ECC8_CTRL_SFTRST and HW_ECC8_CTRL_CLKGATE) as well as configuring the interrupt enables. The bulk of the programming is actually applied to the GPMI via PIO operations embedded in its i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-9 8-Symbol Correcting ECC Accelerator (ECC8) DMA command structures. This has a subtle implication when writing to the GPMI ECC8 registers: access to the ECC8 registers must be written in progressive register order. Thus, to write to the HW_GPMI_ECCCOUNT register, write first (in order) to registers HW_GPMI_CTRL0, HW_GPMI_COMPARE, and HW_GPMI_ECCCTRL before writing to HW_GPMI_ECCCOUNT. These additional register writes need to be accounted for in the CMDWORDS field of the respective DMA channel command register. See Section 13.4, "Programmable Registers" for the GPMI register descriptions. When the DMA commands complete, the 4K NAND page will have been written in the format shown in Figure 14-4. Except for diagnostic operations, normal transfers would never read or write the NAND in any mode other than its ECC mode. It is possible to bypass the parity generation and write "RAW" data to the NAND by not turning on the ECC functions. To summarize the detailed operation, an 18-byte Reed-Solomon parity field is appended in a 4K page at the end of each of the eight 512-byte blocks. Notice that 4K NAND devices have 4096 byte data areas plus 218-byte spare area for each "4KB" NAND flash page. In addition, a 9-byte parity field is written to the end of the 65-byte metadata block. Assume that the GPMI media interface is used to write the resultant ((8*512)+65) bytes of data from on-chip memory to the NAND flash device. The GPMI and ECC8 then collaborate to generate an additional ((8*18)+9) bytes of parity information. * Channel commands in APBH DMA Channels 4, 5, 6, or 7 are used to point to the data block in either on-chip or off-chip RAM (as shown in Figure 14-8). To program the GPMI and ECC8 to read that same 4K page of NAND data back from the NAND to a buffer in the system memory, first reserve a system memory buffer like the one depicted in Figure 14-5. (Note that the reserved system memory buffers need to be word-aligned.) The GPMI DMA engine is not used for the data transfer, see below. Instead, it is used to convey a sequence of commands to the GPMI as DMA PIO operations. Some of the information conveyed to the GPMI is made available to the ECC8 engine to process the NAND read. In particular, the address of the PAYLOAD BUFFER and the address of the AUXILIARY buffer are written to the GPMI PIO space, not to the ECC8 PIO space. Thus, the normal multi-NAND DMA based device interleaving is preserved, i.e., four NANDs on four separate chip selects can be scheduled for read or write operations using the ECC8. Whichever channel finishes its ready wait first and enters the DMA arbiter with its lock bit set will "own" the GPMI command interface and through it will own the ECC8 resources for the duration of its processing. So, a nearly standard read DMA descriptor chain is used for the NAND read transfer, including the ready wait commands. The DMA command that kicks off the GPMI has a few extra PIO words attached to preload the HW_GPMI_ECCCTRL, HW_GPMI_ECCCOUNT, HW_GPMI_PAYLOADm and HW_GPMI_AUXILIARY registers. i.MX23 Applications Processor Reference Manual, Rev. 1 14-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) When the data is read from the NAND by the GPMI, it is passed to the ECC8. Inside the ECC8, the data is copied to the payload buffer or auxiliary buffer using the AHB bus master in the ECC8. The ECC8 needs some work space in system memory to hold intermediate results. These elements are allocated in the auxiliary buffer pointed to by HW_GPMI_AUXILIARY. Notice that programming the ECC8 for NAND reads consists largely of removing the soft reset and clock gates from HW_ECC8_CTRL and clearing the HW_ECC8_CTRL_COMPLETE_IRQ, since most of the actual programming is accomplished through PIO operations included in GPMI DMA command structures. Set HW_ECC8_CTRL_COMPLETE_IRQ_EN to one, then start the GPMI's DMA, and let it run. The ECC8 interrupts the CPU after completing the entire transaction. This could be a single 512-byte block if desired or the entire 4K page of payload data and the 65 bytes of metadata. It also could be just the metadata block. Note that the metadata is protected by its own 9-byte parity so that reading metadata is very efficient. The ECC8 status registers indicate the quality of the data read into each of the nine blocks with a four-bit code. * * * * * * A value of 0 means no errors occurred on the block. A value of 1-8 means that correctable errors occurred but the data was repaired by the bus master. A value of 0xC means that this block was not specified on the read transaction. A value of 0xE means that an uncorrectable error occurred on that block. A value of 0xF means that this block contains all ones and is therefore considered to be an ERASED block. A summary status quickly tells if any block in the page had an uncorrectable error. 14.2.2 Reed-Solomon ECC Encoding for NAND Writes The RS encoder flowchart in Figure 14-6 shows the detailed steps involved in programming and using the ECC8 encoder. This flowchart shows how to use the ECC8 block with the GPMI. To use the ECC8 encoder with the GPMI's DMA, create a DMA command chain containing ten descriptor structures, as shown in Figure 14-8 and detailed in the DMA structure code example that follows it in Section 14.2.2.1, "DMA Structure Code Example." The ten descriptors perform the following tasks: 1. Disable the ECC8 block (in case it was enabled) and issue NAND write setup command byte (under "CLE") and address bytes (under "ALE"). 2. Configure and enable the ECC8 block and write the data payload. 3. Write the auxiliary payload. 4. Disable the ECC8 block and issue NAND write execute command byte (under "CLE"). 5. Wait for the NAND device to finish writing the data by watching the ready signal. 6. Check for NAND timeout via "DMA_SENSE". Refer to Section 10.2 for a description of DMA SENSE. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-11 8-Symbol Correcting ECC Accelerator (ECC8) 7. Issue NAND status command byte (under "CLE"). 8. Read the status and compare against expected. 9. If status is incorrect/incomplete, branch to error handling descriptor chain. 10. Otherwise, write is complete and emit GPMI interrupt. ECC8 ENCODE & W R IT E N A N D R u n th e p re s c rib e in itia liz a tio n s e q u e n c e . P o in t th e G P M I D M A c h a n n e l 4 (o r 5 o r 6 o r 7 ) a t th e p re s c rib e d s ta tic D M A s e q u e n c e . S ta rt th e D M A . R e tu rn a n d w a it fo r D M A c h a n n e l 4 (o r 5 o r 6 o r 7 ) c o m m a n d c o m p le te in te rru p t. STO P A P B H D M A C H 4 C om m and C o m p le te IS R M u s t u s e S C T c le a r H W _ A P B H _ C T R L 1 _ C H 0 _ C M D C M P L T _ IR Q = 0 S ta rt G P M I D M A c h a in fo r n e x t w rite o r re a d tra n s fe r. STOP Figure 14-6. ECC8 Reed-Solomon Encode Flowchart i.MX23 Applications Processor Reference Manual, Rev. 1 14-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) Descriptor Legend NEXT CMD ADDR CMD HW_GPMI_CTRL0 HW_GPMI_COMPARE HW_GPMI_ECCCTRL <= <= <= <= xfer_count command_mode cmdwords word_length mask ecc_cmd HW_GPMI_ECCCOUNT HW_GPMI_PAYLOAD HW_GPMI_AUXILIARY enable_ecc wait4endcmd lock_cs semaphore BUFFER ADDR CS address address_increment reference buffer_mask xfer_count nandwait4ready nandlock irqoncmplt chain command Note: Refer to this legend when examining Figure 14-8 and Figure 14-11. Figure 14-7. ECC8 DMA Descriptor Legend i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-13 8-Symbol Correcting ECC Accelerator (ECC8) Descriptor 1: Disable ECC8 engine and issue NAND write set-up command and address (CLE/ALE). NEXT CMD ADDR CMD <= 1+5 write ---3 8_bit null disable 1 0 0 101 DMA_READ BUFFER ADDR HW_GPMI_CTRL0 <= HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= enabled 2 NAND_CLE 1 null ---1+5 1 Byte NAND CMD 5 Byte ADDR Descriptor 2: Enable the ECC8 engine and write the data payload. NEXT CMD ADDR CMD <= 8 * 512 write 4 0 0 0 101 DMA_READ 8 * 512 + 65 null enable 8 * (512 + 18) + (65 + 9) Descriptor 3: Write the auxiliary payload. NEXT CMD ADDR CMD <= 65 0 1 0 0 101 DMA_READ BUFFER ADDR Descriptor 4: Disable ECC8 engine and issue NAND write execute command (CLE). NEXT CMD ADDR CMD <= 1 write ---Descriptor 5: Wait for NAND ready. NEXT CMD ADDR CMD <= 0 wait_for_ready 1 1 0 1 0 0 1 NO_DMA_XFER 0 BUFFER ADDR HW_GPMI_CTRL0 <= 8_bit disabled 2 NAND_DATA 0 3 1 0 0 NAND_CLE disable 101 0 null ---DMA_READ 1 BUFFER ADDR HW_GPMI_CTRL0 <= HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= 8_bit enabled 2 null 0x1FF BUFFER ADDR HW_GPMI_CTRL0 <= HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= HW_GPMI_ECCCOUNT<= 8_bit enabled 2 NAND_DATA 0 null encode_8_bit 8*512 Byte Data Payload Buffer 65 Byte Auxiliary Payload Buffer 1 Byte NAND CMD Descriptor 6: PSENSE compare for time-out. NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 001 DMA_SENSE DMA Error Descriptor Chain Descriptor 7: Disable ECC8 engine (if enabled by another thread) and issue NAND status command (CLE). NEXT CMD ADDR CMD <= 1 write ---3 1 0 0 NAND_CLE disable 101 0 null ---DMA_READ BUFFER ADDR HW_GPMI_CTRL0 <= HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= 8_bit enabled 2 null 1 1 Byte NAND CMD Descriptor 8: Read the NAND status and compare against expected value. NEXT CMD ADDR CMD <= 0 2 1 0 0 1 0 1 NO_DMA_XFER 1 BUFFER ADDR HW_GPMI_CTRL0 <= read_and_compare 8_bit disabled 2 NAND_DATA 0 HW_GPMI_COMPARE <= Descriptor 9: PSENSE compare for status comparison check. NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 001 DMA_SENSE Descriptor 10: Emit GPMI DMA interrupt. NEXT CMD ADDR CMD <= 0 0 0 0 0 0 1 0 NO_DMA_XFER BUFFER ADDR Note: To interpret the fields in this diagram, see Figure 14-7 for the descriptor legend. Figure 14-8. ECC8 Reed-Solomon Encode DMA Descriptor Chain i.MX23 Applications Processor Reference Manual, Rev. 1 14-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) 14.2.2.1 DMA Structure Code Example The following code sample illustrates the coding for one write transaction involving 4096 bytes of data payload (eight 512-byte blocks) and 65 bytes of auxiliary payload (also referred to as metadata) to a 4K NAND page sitting on GPMI CS2. //---------------------------------------------------------------------------// generic DMA/GPMI/ECC descriptor struct, order sensitive! //---------------------------------------------------------------------------typedef struct { // DMA related fields unsigned int dma_nxtcmdar; unsigned int dma_cmd; unsigned int dma_bar; // GPMI related fields unsigned int gpmi_ctrl0; unsigned int gpmi_compare; unsigned int gpmi_eccctrl; unsigned int gpmi_ecccount; unsigned int gpmi_data_ptr; unsigned int gpmi_aux_ptr; } GENERIC_DESCRIPTOR; //---------------------------------------------------------------------------// allocate 10 descriptors for doing a NAND ECC Write //---------------------------------------------------------------------------GENERIC_DESCRIPTOR write[10]; //---------------------------------------------------------------------------// DMA descriptor pointer to handle error conditions from psense checks //---------------------------------------------------------------------------unsigned int * dma_error_handler; //---------------------------------------------------------------------------// 8 byte NAND command and address buffer // any alignment is ok, it is read by the GPMI DMA // byte 0 is write setup command // bytes 1-5 is the NAND address // byte 6 is write execute command // byte 7 is status command //---------------------------------------------------------------------------unsigned char nand_cmd_addr_buffer[8]; //---------------------------------------------------------------------------// 4096 byte payload buffer used for reads or writes // needs to be word aligned //---------------------------------------------------------------------------unsigned int write_payload_buffer[(4096/4)]; //---------------------------------------------------------------------------// 65 byte meta-data to be written to NAND // needs to be word aligned //---------------------------------------------------------------------------unsigned int write_aux_buffer[65]; //---------------------------------------------------------------------------// Descriptor 1: issue NAND write setup command (CLE/ALE) //---------------------------------------------------------------------------write[0].dma_nxtcmdar = &write[1]; // point to the next descriptor write[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1 + 5) | BF_APBH_CHn_CMD_CMDWORDS (3) | BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); write[0].dma_bar = &nand_cmd_addr_buffer; // 3 words sent to the GPMI write[0].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT write[0].gpmi_compare = NULL; // 1 byte command, 5 byte address // send 3 words to the GPMI // wait for command to finish before continuing // prevent other DMA channels from taking over // follow chain to next command // read data from DMA, write to NAND // byte 0 write setup, bytes 1 - 5 NAND address WRITE) 8_BIT) ENABLED) (2) NAND_CLE) (1) (1 + 5); | // write to the NAND | | | // must correspond to NAND CS used | | // send command and address // 1 byte command, 5 byte address // field not used but necessary to set eccctrl write[0].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-15 8-Symbol Correcting ECC Accelerator (ECC8) //---------------------------------------------------------------------------// Descriptor 2: write the data payload (DATA) //---------------------------------------------------------------------------write[1].dma_nxtcmdar = &write[2]; // point to the next descriptor write[1].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (8*512) | // BF_APBH_CHn_CMD_CMDWORDS (4) | // BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | // BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); write[1].dma_bar = &write_payload_buffer; NOTE: DMA transfer only the data payload send 4 words to the GPMI DON'T wait to end, wait in the next descriptor maintain resource lock follow chain to next command // read data from DMA, write to NAND // pointer for the 4K byte data area // 4 words sent to the GPMI write[1].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, ENABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) | BF_GPMI_CTRL0_XFER_COUNT (8*512+65); // NOTE: this field contains the total amount // DMA transferred (8 data and 1 aux blocks) // to GPMI! write[1].gpmi_compare = NULL; // field not used but necessary to set eccctrl write[1].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ECC_CMD, ENCODE_8_BIT) | // specify t = 8 mode BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, ENABLE) | // enable ECC module BF_GPMI_ECCCTRL_BUFFER_MASK (0x1FF); // write all 8 data blocks and 1 aux block write[1].gpmi_ecccount = BF_GPMI_ECCCOUNT_COUNT(8*(512+18)+(65+9)); // specify number of bytes written to NAND // NOTE: the extra 8*(18)+9 bytes are // parity bytes generated by the ECC block. //---------------------------------------------------------------------------// Descriptor 3: write the aux payload (DATA) //---------------------------------------------------------------------------write[2].dma_nxtcmdar = &write[3]; // point to the next descriptor write[2].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (65) | BF_APBH_CHn_CMD_CMDWORDS (0) | BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); write[2].dma_bar = &write_aux_buffer; // NOTE: DMA transfer only the aux block // no words sent to GPMI // wait for command to finish before continuing // maintain resource lock // follow chain to next command // read data from DMA, write to NAND // pointer for the 65 byte meta data area //---------------------------------------------------------------------------// Descriptor 4: issue NAND write execute command (CLE) //---------------------------------------------------------------------------write[3].dma_nxtcmdar = &write[4]; // point to the next descriptor write[3].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | BF_APBH_CHn_CMD_CMDWORDS (3) | BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); write[3].dma_bar = &nand_cmd_addr_buffer[6]; // 3 words sent to the GPMI write[3].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT write[3].gpmi_compare = NULL; // 1 byte command // send 3 words to the GPMI // wait for command to finish before continuing // maintain resource lock // follow chain to next command // read data from DMA, write to NAND // point to byte 6, write execute command WRITE) 8_BIT) ENABLED) (2) NAND_CLE) (0) (1); | // write to the NAND | | | // must correspond to NAND CS used | | // 1 byte command // field not used but necessary to set eccctrl write[3].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block //---------------------------------------------------------------------------// Descriptor 5: wait for ready (CLE) //---------------------------------------------------------------------------write[4].dma_nxtcmdar = &write[5]; // point to the next descriptor i.MX23 Applications Processor Reference Manual, Rev. 1 14-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) write[4].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | BF_APBH_CHn_CMD_CMDWORDS (1) | BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(1) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); write[4].dma_bar = NULL; // 1 word sent to the GPMI write[4].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT // no dma transfer // send 1 word to the GPMI wait for command to finish before continuing // wait for nand to be ready // relinquish nand lock // follow chain to next command // no dma transfer // field not used WAIT_FOR_READY) 8_BIT) DISABLED) (2) NAND_DATA) (0) (0); | // wait for NAND ready | | | // must correspond to NAND CS used | | //---------------------------------------------------------------------------// Descriptor 6: psense compare (time out check) //---------------------------------------------------------------------------write[5].dma_nxtcmdar = &write[6]; // point to the next descriptor write[5].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | BF_APBH_CHn_CMD_CMDWORDS (0) | BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE); write[5].dma_bar = dma_error_handler; // no dma transfer // no words sent to GPMI // do not wait to continue // follow chain to next command // perform a sense check // if sense check fails, branch to error handler //---------------------------------------------------------------------------// Descriptor 7: issue NAND status command (CLE) //---------------------------------------------------------------------------write[6].dma_nxtcmdar = &write[7]; // point to the next descriptor write[6].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | BF_APBH_CHn_CMD_CMDWORDS (3) | BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); write[6].dma_bar = &nand_cmd_addr_buffer[7]; write[6].gpmi_compare = NULL; // 1 byte command // send 3 words to the GPMI // wait for command to finish before continuing // prevent other DMA channels from taking over // follow chain to next command // read data from DMA, write to NAND // point to byte 7, status command // field not used but necessary to set eccctrl // disable the ECC block write[6].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // 3 words sent to the GPMI write[6].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT WRITE) 8_BIT) ENABLED) (2) NAND_CLE) (0) (1); | // write to the NAND | | | // must correspond to NAND CS used | | // 1 byte command //---------------------------------------------------------------------------// Descriptor 8: read status and compare (DATA) //---------------------------------------------------------------------------write[7].dma_nxtcmdar = &write[8]; // point to the next descriptor write[7].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // BF_APBH_CHn_CMD_CMDWORDS (2) | // BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); write[7].dma_bar = NULL; // 2 word sent to the GPMI write[7].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ_AND_COMPARE) | BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, 8_BIT) DISABLED) | | no dma transfer send 2 words to the GPMI wait for command to finish before continuing maintain resource lock follow chain to next command // no dma transfer // field not used // read from the NAND and // compare to expect i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-17 8-Symbol Correcting ECC Accelerator (ECC8) BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT write[7].gpmi_compare = // NOTE: mask and reference values are NAND // SPECIFIC to evaluate the NAND status //---------------------------------------------------------------------------// Descriptor 9: psense compare (time out check) //---------------------------------------------------------------------------write[8].dma_nxtcmdar = &write[9]; // point to the next descriptor write[8].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | BF_APBH_CHn_CMD_CMDWORDS (0) | BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE); write[8].dma_bar = dma_error_handler; // no dma transfer // no words sent to GPMI // do not wait to continue // relinquish nand lock // follow chain to next command // perform a sense check // if sense check fails, branch to error handler //---------------------------------------------------------------------------// Descriptor 10: emit GPMI interrupt //---------------------------------------------------------------------------write[9].dma_nxtcmdar = NULL; // not used since this is last descriptor write[9].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | BF_APBH_CHn_CMD_CMDWORDS (0) | BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (1) | BF_APBH_CHn_CMD_CHAIN (0) | BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer // no words sent to GPMI // do not wait to continue // emit GPMI interrupt // terminate DMA chain processing // no dma transfer 14.2.2.2 Using the ECC8 Encoder To use the ECC8 encoder, first turn off the module-wide soft reset bit in both the GPMI and ECC8 blocks before starting any DMA activity. Note that turning off the soft reset must take place by itself, prior to programming the rest of the control registers. Turn off the ECC8 bus master soft reset bit (bit 29). Turn off the clock gate bits. Program the remainder of the GPMI, ECC8 and APBH DMA as follows: // bring APBH out of reset HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_SFRST); HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE); // bring ecc8 out of reset HW_ECC8_CTRL_CLR(BM_ECC8_CTRL_SFTRST); HW_ECC8_CTRL_CLR(BM_ECC8_CTRL_CLKGATE); HW_ECC8_CTRL_CLR(BM_ECC8_CTRL_AHBM_SFTRST); // bring gpmi out of reset HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST); HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE); HW_GPMI_CTRL1_SET(BM_GPMI_CTRL1_DEV_RESET);// deassert in case //anyone's hooked up to the reset pin // enable pinctrl HW_PINCTRL_CTRL_WR(0x00000000); // enable GPMI through alt pin wiring HW_PINCTRL_MUXSEL0_CLR(0xff000000); HW_PINCTRL_MUXSEL0_SET(0xaa000000); // to use the primary pins do the following // HW_PINCTRL_MUXSEL4_CLR(0xff000000); // HW_PINCTRL_MUXSEL4_SET(0x55000000); // enable gpmi pins i.MX23 Applications Processor Reference Manual, Rev. 1 14-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) HW_PINCTRL_MUXSEL0_CLR(0x0000ffff);// data bits HW_PINCTRL_MUXSEL1_CLR(0x000fffff);// control bits Note that for writing NANDs (ECC encoding), only GPMI DMA command complete interrupts are used. The ECC8 engine is used for writing to the NAND but never produces an interrupt. From the sample code in Section 14.2.2.1, "DMA Structure Code Example:" * DMA descriptor 1 prepares the NAND for data write by using the GPMI to issue a write setup command byte under "CLE", then sends a 5-byte address under "ALE". The ECC8 engine is disabled and not used for these commands. DMA descriptor 2 enables the ECC8 engine for t=8 encoding to begin the initial writing of the NAND data by specifying where the data payload is coming from in system memory. DMA descriptor 3 continues the writing of NAND data by specifying where the auxiliary data is coming from in system memory. DMA descriptor 4 issues the write commit command byte under "CLE" to the NAND. DMA descriptor 5 waits for the NAND to complete the write commit/transfer by watching the NAND's ready line status. This descriptor relinquishes the NANDLOCK on the GPMI to enable the other DMA channels to initiate NAND transactions on different NAND CS lines. DMA descriptor 7 issues a NAND status command byte under "CLE" to check the status of the NAND device following the page write. DMA descriptor 8 reads back the NAND status and compares the status with an expected value. If there are differences, then the DMA processing engine follows an error-handling DMA descriptor path. DMA descriptor 9 disables the ECC8 engine and emits a GPMI interrupt to indicate that the NAND write has been completed. * * * * * * * 14.2.3 Reed-Solomon ECC Decoding for NAND Reads When a page is read from NAND flash, RS syndromes will be computed and, if correctable errors are found, they will be corrected on a per block basis within the NAND page. This decoding process is fully overlapped with other NAND data reads and with CPU execution. The RS decoder flowchart in Figure 14-9 shows the steps involved in programming the ECC8 Reed-Solomon decoder. The hardware flow of reading and decoding a 512-byte page encoded for t=8 error correction (18 parity bytes) is shown in Figure 14-10. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-19 8-Symbol Correcting ECC Accelerator (ECC8) R ead N AN D & E C C 8 D e code R u n th e p r e s c r ib e i n it ia l iz a t io n S e q u e n c e P o in t t h e G P M I D M A c h a n n e l 4 ( o r 5 o r 6 o r 7 ) a t t h e p r e s c r i b e d s t a t ic D M A s e q u e n c e S ta rt th e D M A R e tu r n a n d w a i t f o r D M A c h a n n e l 4 ( o r 5 o r 6 o r 7 ) c o m m a n d c o m p le t e in t e r r u p t . STO P APBH D M A C H 4 C om m and C o m p le te IS R M u s t u s e S C T c le a r H W _ A P B H _ C T R L 1 _ C H 0 _ C M D C M P L T _ IR Q = 0 S ta r t G P M I D M A c h a in f o r n e x t w r it e o r r e a d tra n s fe r STOP E C C 8 C o m p l e te I S R R e a d s t a tu s r e g s a n d s t o r e f o r p r o c e s s in g M u s t u s e S C T c le a r H W _ E C C 8 _ C T R L 0 _ C O M P L E T E _ IR Q = 0 STO P Figure 14-9. ECC8 Reed-Solomon Decode Flowchart i.MX23 Applications Processor Reference Manual, Rev. 1 14-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) ECC Check Error (Compute correction) N Good? Y Error Calculator and Error Corrector No Errors (Syndrome = = 0 HW_ECC8_STAT Register and IRQ Payload buffer pointed to by HW_GPMI_PAYLOAD Parity and Syndrome buffer pointed to by HW_GPMI_AUXILIARY NOTES: This diagram describes a decoder for reading and correcting a 512-byte data block encoded with t=8 error correction. ECC8 bus master writes the bytes from the NAND to system memory. The error corrector performs read-modify-writes on these system memory buffers as necessary. Figure 14-10. Conceptually, an APHB DMA Channel 4, 5, 6, or 7 command chain with seven command structures linked together is used to perform the RS decode operation (as shown in Figure 14-11). NOTE: The GPMI's DMA command structures controls the ECC8 decode operation. To use the ECC8 decoder with the GPMI's DMA, create a DMA command chain containing seven descriptor structures, as shown in Figure 14-11 and detailed in the DMA structure code example that follows it in Section 14.2.3.1, "DMA Structure Code Example." The seven DMA descriptors perform the following tasks: Issue NAND read setup command byte (under "CLE") and address bytes (under "ALE"). Issue NAND read execute command byte (under "CLE"). Wait for the NAND device to complete accessing the block data by watching the ready signal. Check for NAND timeout via "DMA_SENSE". Refer to Section 10.2 for a description of DMA SENSE. 5. Configure and enable the ECC8 block and read the NAND block data. 6. Disable the ECC8 block. 7. Descriptor NOP to allow NANDLOCK in the previous descriptor to the thread-safe. 1. 2. 3. 4. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-21 8-Symbol Correcting ECC Accelerator (ECC8) Descriptor 1: Disable ECC8 engine and issue NAND read set-up command and address (CLE/ALE). NEXT CMD ADDR CMD HW_GPMI_CTRL0 <= <= 1+5 write 3 1 0 0 NAND_CLE disable 101 1 null ---DMA_READ BUFFER ADDR 8_bit enabled 2 null ---1+5 HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= 1 Byte NAND CMD 5 Byte ADDR Descriptor 2: NAND read execute command (CLE). NEXT CMD ADDR CMD HW_GPMI_CTRL0 <= <= 1 write 1 1 BUFFER ADDR 0 0 101 DMA_READ 1 Byte NAND CMD NAND_CLE 0 1 8_bit disabled 2 Descriptor 3: Wait for NAND ready. NEXT CMD ADDR CMD HW_GPMI_CTRL0 <= <= 0 wait_for_ready 1 1 0 1 0 0 1 NO_DMA_XFER 0 BUFFER ADDR 8_bit disabled 2 NAND_DATA 0 Descriptor 4: PSENSE compare for time-out. NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 001 DMA_SENSE DMA Error Descriptor Chain Descriptor 5: Enable ECC8 engine and read NAND data. NEXT CMD ADDR CMD HW_GPMI_CTRL0 <= <= 0 read 6 1 0 0 1 0 1 NO_DMA_XFER BUFFER ADDR 8_bit disabled 2 NAND_DATA 0 8 * (512+18) + (65+9) null decode_8_bit enable 8 * (512+18) + (65+9) HW_GPMI_PAYLOAD HW_GPMI_AUXILIARY null 0x1FF HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= HW_GPMI_ECCCOUNT<= 8*512 Byte Data Payload Buffer 412 Byte Auxiliary Payload Buffer Descriptor 6: Disable ECC8 engine (wait for ready is a NOP here). NEXT CMD ADDR CMD HW_GPMI_CTRL0 <= <= 0 wait_for_ready 3 1 0 1 1 0 1 NO_DMA_XFER 0 null disable ---BUFFER ADDR 8_bit disabled 0 NAND_DATA 0 null ---HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= Descriptor 7: NOP to ensure NANDLOCK in previous descriptor. NEXT CMD ADDR CMD <= 0 0 1 BUFFER ADDR 0 0 0 0 0 NO_DMA_XFER Note: To interpret the fields in this diagram, see Figure 14-7 for the descriptor legend. Figure 14-11. ECC8 Reed-Solomon Decode DMA Descriptor Chain i.MX23 Applications Processor Reference Manual, Rev. 1 14-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) 14.2.3.1 DMA Structure Code Example The following sample code illustrates the coding for one read transaction, consisting of a seven DMA command structure chain for reading all 4096 bytes of payload data (eight 512-byte blocks) and 65 bytes of metadata with the associative parity bytes (8 * (18) + 9) from a 4K NAND page sitting on GPMI CS2. //---------------------------------------------------------------------------// generic DMA/GPMI/ECC descriptor struct, order sensitive! //---------------------------------------------------------------------------typedef struct { // DMA related fields unsigned int dma_nxtcmdar; unsigned int dma_cmd; unsigned int dma_bar; // GPMI related fields unsigned int gpmi_ctrl0; unsigned int gpmi_compare; unsigned int gpmi_eccctrl; unsigned int gpmi_ecccount; unsigned int gpmi_data_ptr; unsigned int gpmi_aux_ptr; } GENERIC_DESCRIPTOR; //---------------------------------------------------------------------------// allocate 7 descriptors for doing a NAND ECC Read //---------------------------------------------------------------------------GENERIC_DESCRIPTOR read[7]; //---------------------------------------------------------------------------// DMA descriptor pointer to handle error conditions from psense checks //---------------------------------------------------------------------------unsigned int * dma_error_handler; //---------------------------------------------------------------------------// 7 byte NAND command and address buffer // any alignment is ok, it is read by the GPMI DMA // byte 0 is read setup command // bytes 1-5 is the NAND address // byte 6 is read execute command //---------------------------------------------------------------------------unsigned char nand_cmd_addr_buffer[7]; //---------------------------------------------------------------------------// 4096 byte payload buffer used for reads or writes // needs to be word aligned //---------------------------------------------------------------------------unsigned int read_payload_buffer[(4096/4)]; //---------------------------------------------------------------------------// 412 byte auxiliary buffer used for reads // needs to be word aligned //---------------------------------------------------------------------------unsigned int read_aux_buffer[(412/4)]; //---------------------------------------------------------------------------// Descriptor 1: issue NAND read setup command (CLE/ALE) //---------------------------------------------------------------------------read[0].dma_nxtcmdar = &read[1]; // point to the next descriptor read[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1 + 5) | BF_APBH_CHn_CMD_CMDWORDS (3) | BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); read[0].dma_bar = &nand_cmd_addr_buffer; // 3 words sent to the GPMI read[0].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT read[0].gpmi_compare = NULL; // 1 byte command, 5 byte address // send 3 words to the GPMI // wait for command to finish before continuing // prevent other DMA channels from taking over // follow chain to next command // read data from DMA, write to NAND // byte 0 read setup, bytes 1 - 5 NAND address WRITE) 8_BIT) ENABLED) (2) NAND_CLE) (1) (1 + 5); | // write to the NAND | | | // must correspond to NAND CS used | | // send command and address // 1 byte command, 5 byte address // field not used but necessary to set eccctrl i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-23 8-Symbol Correcting ECC Accelerator (ECC8) read[0].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block //---------------------------------------------------------------------------// Descriptor 2: issue NAND read execute command (CLE) //---------------------------------------------------------------------------read[1].dma_nxtcmdar = &read[2]; // point to the next descriptor read[1].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | BF_APBH_CHn_CMD_CMDWORDS (1) | BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); read[1].dma_bar = &nand_cmd_addr_buffer[6]; // 1 word sent to the GPMI read[1].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT // 1 byte read command // send 1 word to GPMI // wait for command to finish before continuing // prevent other DMA channels from taking over // follow chain to next command // read data from DMA, write to NAND // point to byte 6, read execute command WRITE) 8_BIT) DISABLED) (2) NAND_CLE) (0) (1); | // write to the NAND | | | // must correspond to NAND CS used | | // 1 byte command //---------------------------------------------------------------------------// Descriptor 3: wait for ready (DATA) //---------------------------------------------------------------------------read[2].dma_nxtcmdar = &read[3]; // point to the next descriptor read[2].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | BF_APBH_CHn_CMD_CMDWORDS (1) | BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(1) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); read[2].dma_bar = NULL; // 1 word sent to the GPMI read[2].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT WAIT_FOR_READY) 8_BIT) DISABLED) (2) NAND_DATA) (0) (0); // no dma transfer // send 1 word to GPMI // wait for command to finish before continuing // wait for nand to be ready // relinquish nand lock // follow chain to next command // no dma transfer // field not used | // wait for NAND ready | | | // must correspond to NAND CS used | | //---------------------------------------------------------------------------// Descriptor 4: psense compare (time out check) //---------------------------------------------------------------------------read[3].dma_nxtcmdar = &read[4]; // point to the next descriptor read[3].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | BF_APBH_CHn_CMD_CMDWORDS (0) | BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE); read[3].dma_bar = dma_error_handler; // no dma transfer // no words sent to GPMI // do not wait to continue // follow chain to next command // perform a sense check // if sense check fails, branch to error handler //---------------------------------------------------------------------------// Descriptor 5: read 4K page plus 65 byte meta-data Nand data // and send it to ECC block (DATA) //---------------------------------------------------------------------------read[4].dma_nxtcmdar = &read[5]; // point to the next descriptor read[4].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (6) | // send 6 words to GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // prevent other DMA channels from taking over BF_APBH_CHn_CMD_IRQONCMPLT (0) | // ECC block generates ecc8 interrupt on completion BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no DMA transfer, ECC block handles transfer read[4].dma_bar = NULL; // field not used i.MX23 Applications Processor Reference Manual, Rev. 1 14-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) // 6 words sent to the GPMI read[4].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ) | // read from the NAND BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, DISABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) | BF_GPMI_CTRL0_XFER_COUNT (8*(512+18)+(65+9)); // eight 512 byte data blocks (plus parity, t = 8) // and one 65 byte aux block (plus parity, t = 4) read[4].gpmi_compare = NULL; // field not used but necessary to set eccctrl // GPMI ECCCTRL PIO This launches the 4K byte transfer through ECC8's // bus master. Setting the ECC_ENABLE bit redirects the data flow // within the GPMI so that read data flows to the ECC8 engine instead // of flowing to the GPMI's DMA channel. read[4].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ECC_CMD, DECODE_8_BIT) | // specify t = 8 mode BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, ENABLE) | // enable ECC module BF_GPMI_ECCCTRL_BUFFER_MASK (0X1FF); // read all 8 data blocks and 1 aux block read[4].gpmi_ecccount = BF_GPMI_ECCCOUNT_COUNT(8*(512+18)+(65+9)); // specify number of bytes read from NAND read[4].gpmi_data_ptr = &read_payload_buffer; read[4].gpmi_aux_ptr = &read_aux_buffer; // pointer for the 4K byte data area // pointer for the 65 byte aux area + // parity and syndrome bytes for both // data and aux blocks. //---------------------------------------------------------------------------// Descriptor 6: disable ECC block //---------------------------------------------------------------------------read[5].dma_nxtcmdar = &read[6]; // point to the next descriptor read[5].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (3) | // send 3 words to GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(1) | // wait for nand to be ready BF_APBH_CHn_CMD_NANDLOCK (1) | // need nand lock to be thread safe while turn-off ECC8 BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer read[5].dma_bar = NULL; // 3 words sent to the GPMI read[5].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT read[5].gpmi_compare = NULL; READ) 8_BIT) DISABLED) (2) NAND_DATA) (0) (0); // field not used | | | | // must correspond to NAND CS used | | // field not used but necessary to set eccctrl // disable the ECC block read[5].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); //---------------------------------------------------------------------------// Descriptor 7: deassert nand lock //---------------------------------------------------------------------------read[6].dma_nxtcmdar = NULL; // not used since this is last descriptor read[6].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // BF_APBH_CHn_CMD_CMDWORDS (0) | // BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | // BF_APBH_CHn_CMD_IRQONCMPLT (0) | // BF_APBH_CHn_CMD_CHAIN (0) | // BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); read[6].dma_bar = NULL; no dma transfer no words sent to GPMI wait for command to finish before continuing relinquish nand lock ECC8 engine generates interrupt terminate DMA chain processing // no dma transfer // field not used 14.2.3.2 * Using the Decoder As illustrated in Figure 14-11 and the sample code in Section 14.2.3.1, "DMA Structure Code Example:" DMA descriptor 1 prepares the NAND for data read by using the GPMI to issue a NAND read setup command byte under "CLE", then sends a 5-byte address under "ALE". The ECC8 engine is not used for these commands. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-25 8-Symbol Correcting ECC Accelerator (ECC8) * * * * * * * DMA descriptor 2 issues a one-byte read execute command to the NAND device that triggers its read access. The NAND then goes not ready. DMA descriptor 3 performs a wait for ready operation allowing the DMA chain to remain dormant until the NAND device completes its read access time. DMA descriptor 5 handles the reading and error correction of the NAND data. This command's PIOs activate the ECC8 engine to write the read NAND data to system memory and to process it for any errors that need to be corrected. This DMA descriptor contains two PIO values that are system memory addresses pointing to the PAYLOAD data area and to the AUXILIARY data area. These addresses are used by the ECC8 engine's AHB master to move data into system memory and to correct it. While this example is reading an entire 4K page--payload plus metadata--it is equally possible to read just one 512-byte payload block or just the uniquely protected metadata block in a single 7 DMA structure transfer. DMA descriptor 6 disables the ECC8 engine with the NANDLOCK asserted. This is necessary to ensure that the GPMI resource is not arbitrated to another DMA channel when multiple DMA channels are active concurrently. DMA descriptor 7 deasserts the NANDLOCK to free up the GPMI resource to another channel. The decoder transforms the read NAND data block into an RS code word and computes the codeword syndrome. If no errors are present, then the ECC8 block can immediately report back to firmware. This report is passed as the HW_ECC8_CTRL_COMPLETE_IRQ interrupt status bit and the associated status registers in HW_ECC8_STATUS0/1 registers. If an error is present, then the ECC8 block corrects the necessary data block or parity block bytes, if possible (not all errors are correctable). As the ECC8 block receives data from the GPMI: * As the RS decoder reads the data block and the 9-byte or 18-byte parity block, it records a special condition, i.e., that all of the bits of a payload data block or metadata block are one, including any associated parity bytes. The "all-ones" case for both parity and data indicates an erased block in the NAND device. The HW_ECC8_STATUS0 register contains a 4-bit field that indicates the final status of the auxiliary block. HW_ECC8_STATUS1 contains a similar 4-bit field for each of the 512-byte payload data blocks. * * * * * * A value of 0x0 indicates no errors found for a block. A value of 1 to 8 inclusive indicates that many correctable errors were found and fixed. A value of 0xC is reported for any block that was not actually transferred during a specific transaction, i.e., its BLOCK_MASK bit was a zero for the transaction. A value of 0xE indicates uncorrectable errors detected on the block. A value of 0xF indicates that the block was in the special ALL ONES state and is therefore considered to be an ERASED block. All other values are disallowed by the hardware design. Recall that up to four NAND devices can have DMA chains in-flight at once, i.e. they can all be contending for access to the GPMI data bus. It is impossible to predict which NAND device will enter the ECC8 i.MX23 Applications Processor Reference Manual, Rev. 1 14-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) engine with a transfer first, because each chain includes a wait4ready command structure. As a result, firmware should look at the HW_ECC8_STATUS0_COMPLETED_CE bit field to determine which block is being reported in the status register. There is also a 16 bit HANDLE field in the HW_GPMI_ECCCTRL register that is passed down the pipeline with each transaction. This handle field can be used to speed firmware's detection of which transaction is being reported. These examples of reading and writing have focused on full page transfers of 4K page NAND devices. Set HW_GPMI_ECCCTRL_ECC_CMD to a value of HW_GPMI_ECCCTRL_ECC_CMD_ENCODE_4_BIT or to a value of HW_GPMI_ECCCTRL_ECC_CMD_DECODE_4_BIT to enable encode and decode of up to full page transfers of 2K page NAND devices. To reiterate, you can select a single block to transfer within one transaction by setting only one bit in the HW_GPMI_ECCCTRL_BUFFER_MASK bit field. There is a 1:1 correspondence between a bit in this bit field and a 512-byte buffer address offset into the payload area pointed to by the HW_GPMI_PAYLOAD register. The ECC8 and GPMI blocks are designed to be very efficient at reading single 512-byte pages in one transaction. With no errors, the transaction takes less than 20 HCLKs longer than the time to read the raw data from the NAND. Additionally, you can select multiple contiguous blocks to transfer within one transaction by setting the respective bits in the HW_GPMI_BUFFER_MASK bit fields. The selected bits must represent a contiguous block of data in the NAND. To summarize, the APBH DMA command chain for a Reed-Solomon decode operation is shown in Figure 14-11. Seven DMA command structures must be present for each NAND read transaction decoded by the ECC8. The seven DMA command structures for multiple NAND read transaction blocks can be chained together to make larger units of work for the ECC8, and each will produce an appropriate error report in the ECC8 PIO space. Multiple NAND devices can have such multiple chains scheduled. The results can come back out of order with respect to the multiple chains. If uncorrectable errors occur, it is up to software to determine how to deal with the bad block. One strategy might be to reread the data from NAND flash in the hope that enough soft errors will have been removed to make correction possible on a second pass. 14.2.4 Interrupts There are two interrupt sources used in processing ECC8 protected NAND read and write transfers. Since all ECC8 operations are initiated by GPMI DMA command structures, the DMA completion interrupt for the GPMI is an important ISR. Both of the flow charts of Figure 14-6 and Figure 14-9 show the GPMI DMA complete ISR skeleton. In both reads and writes, the GPMI DMA completion interrupt is used to schedule work INTO the error correction pipeline. As the front end processing completes, the DMA interrupt is generated and additional work, i.e. DMA chains, are passed to the GPMI DMA to keep it i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-27 8-Symbol Correcting ECC Accelerator (ECC8) "fed". For write operations, this is the only interrupt that will be generated for processing the NAND write transfer. For reads, however, two interrupts are needed. Every read is started by a GPMI DMA command chain and the front end queue is fed as described above. The back end of the read pipeline is "drained" by monitoring the ECC8 completion interrupt found in HW_ECC8_CTRL_COMPLETE_IRQ. When the NAND is read using ECC (as configured in the DMA descriptor for that read), the CPU must wait for both the GPMI interrupt and the ECC interrupt, and the interrupts may occur in either order. That is, the GPMI interrupt may happen before the ECC interrupt, or vice-versa. Software needs to wait until both interrupts have occurred to know that the data has been delivered by the DMA. An ECC8 transaction consists of reading or writing all of the blocks requested in the HW_GPMI_ECCCTRL_BUFFER_MASK bit field. As every read transaction completes, it posts the status of all of the blocks to the HW_ECC8_STATUS0 and HW_ECC8_STATUS1 registers and sets the completion interrupt. The five stages of the ECC8 read pipeline completes, one in the GPMI and four in the ECC8, are independently stalled as they complete and try to deliver to the next stage in the data flow. Several of these stages can be skipped if no-errors are found or once an uncorrectable error is found in a block. In any case, the final stage will stall if the status register is busy waiting for the CPU to take status register results. The hardware monitors the state of the HW_ECC8_CTRL_COMPLETE_IRQ bit. If it is still set when the last pipeline stage is ready to post data, then the stage will stall. It follows that the next previous stage will stall when it is ready to hand off work to the final stage, and so on up the pipeline. WARNING: It is important that firmware read the STATUS0/1 results and save them before clearing the interrupt request bit otherwise a transaction and its results could be completely lost. 14.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. 14.4 Programmable Registers The following registers are available for programmer access and control of the ECC8 hardware accelerator. i.MX23 Applications Processor Reference Manual, Rev. 1 14-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) 14.4.1 Hardware ECC Accelerator Control Register Description The Hardware ECC Accelerator Control Register provides overall control of the hardware ECC accelerator. HW_ECC8_CTRL HW_ECC8_CTRL_SET HW_ECC8_CTRL_CLR HW_ECC8_CTRL_TOG Table 14-1. HW_ECC8_CTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 DEBUG_STALL_IRQ_EN 0 9 DEBUG_WRITE_IRQ_EN 0 8 COMPLETE_IRQ_EN 0 7 0 6 0 5 0 4 0 3 0 2 DEBUG_STALL_IRQ 0 1 DEBUG_WRITE_IRQ 0 0 0x000 0x004 0x008 0x00C BM_ERROR_IRQ Table 14-2. HW_ECC8_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION 0 = Normal ECC8 operation. 1 = Disable clocking with the ECC8 and hold it in its reset (lowest power) state (default). This bit can be turned on and then off to reset the ECC8 block to its default state. This bit resets all state machines except for the AHB master state machine. RUN = 0x0 Allow ECC8 to operate normally. RESET = 0x1 Hold ECC8 in reset. 30 CLKGATE RW 0x1 This bit must be cleared to 0 for normal operation. When set to 1, it gates off the clocks to the block. RUN = 0x0 Allow ECC8 to operate normally. NO_CLKS = 0x1 Do not clock ECC8 gates in order to minimize power consumption. 29 AHBM_SFTRST RW 0x1 Resets the AHB state machine. 0 = Normal ECC8 operation. 1 = Disable clocking with the ECC8 and hold it in its reset (lowest power) state (default). This bit can be turned on and then off to reset the ECC8 block to its default state. Do not use this bit for normal device soft-resets unless instructed to do so by Freescale. RUN = 0x0 Allow ECC8 to operate normally. RESET = 0x1 Hold ECC8 in reset. 28 RSRVD2 27:24 THROTTLE 23:11 RSRVD1 DEBUG_STALL_IRQ_EN 10 RO 0x0 RW 0x0 RO 0x0 RW 0x0 Reserved. Non-zero values will hold off that number of HCLKs between success burst requests on the AHB. Reserved. 1 = Interrupt on debug stall mode is enabled. The IRQ is raised on every block i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice COMPLETE_IRQ AHBM_SFTRST THROTTLE CLKGATE RSRVD2 RSRVD1 RSRVD0 SFTRST 14-29 8-Symbol Correcting ECC Accelerator (ECC8) Table 14-2. HW_ECC8_CTRL Bit Field Descriptions BITS LABEL 9 DEBUG_WRITE_IRQ_EN RW RESET RW 0x0 DEFINITION 1 = Interrupt on debug write mode is enabled. The IRQ is raised on every transfer. In this mode, no correction occurs. 1 = Interrupt on completion of correction is enabled. Reserved. AHB Bus Interface Error Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. Debug Stall Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. Debug Write Interrupt Status. Write a 1 to the SCT clear address to clear the interrupt status bit. External Interrupt Line Status. Write a 1 to the SCT clear address to clear the interrupt status bit. Note: Subsequent ECC completions will be held off as long as this bit is set. Be sure to read the data from HW_ECC8_STATUS0/1 before clearing this interrupt bit. 8 7:4 3 2 1 0 COMPLETE_IRQ_EN RSRVD0 BM_ERROR_IRQ DEBUG_STALL_IRQ DEBUG_WRITE_IRQ COMPLETE_IRQ RW 0x0 RO 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 14.4.2 Hardware ECC Accelerator Status Register 0 Description HW_ECC8_STATUS0 Table 14-3. HW_ECC8_STATUS0 The Hardware ECC Accelerator Status Register 0 provides overall status of the hardware ECC accelerator. 0x010 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RS8ECC_ENC_PRESENT 1 4 RS8ECC_DEC_PRESENT 1 3 RS4ECC_ENC_PRESENT 1 2 RS4ECC_DEC_PRESENT 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 UNCORRECTABLE 0 1 0 0 COMPLETED_CE STATUS_AUX CORRECTED ALLONES HANDLE RSVD1 Table 14-4. HW_ECC8_STATUS0 Bit Field Descriptions BITS 31:20 HANDLE LABEL RW RESET RO 0x0 DEFINITION Software supplies a 12-bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction. That handle passes down the pipeline and ends up here at the time the ECC8 interrupt is signaled. Chip enable number corresponding to the NAND device from which this data came. Reserved. Reserved. Reserved. 19:16 COMPLETED_CE 15 14 13 RS8ECC_ENC_PRESENT RS8ECC_DEC_PRESENT RS4ECC_ENC_PRESENT RO 0x0 RO 0x1 RO 0x1 RO 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 14-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSVD0 8-Symbol Correcting ECC Accelerator (ECC8) Table 14-4. HW_ECC8_STATUS0 Bit Field Descriptions BITS LABEL 12 RS4ECC_DEC_PRESENT 11:8 STATUS_AUX RW RESET RO 0x1 RO 0xc DEFINITION Reserved. Count of symbols in error during processing of auxiliary data area. 0xF indicates uncorrectable. NO_ERRORS = 0x0 No errors occurred. ONE_CORRECTABLE = 0x1 One correctable error occurred. TWO_CORRECTABLE = 0x2 Two correctable errors occurred. THREE_CORRECTABLE = 0x3 Three correctable errors occurred. FOUR_CORRECTABLE = 0x4 Four correctable errors occurred. NOT_CHECKED = 0xC This block was not examined by the ECC8. UNCORRECTABLE = 0xE Errors occurred that were uncorrectable. ALL_ONES = 0xF All bits are 1. 7:5 4 3 2 1:0 RSVD1 ALLONES CORRECTED UNCORRECTABLE RSVD0 RO 0x0 RO 0x1 RO 0x0 RO 0x0 RO 0x0 Reserved. 1 = All data bits of this transaction are 1. 1 = At least one correctable error encountered during last processing cycle. 1 = Uncorrectable error encountered during last processing cycle. Reserved. DESCRIPTION: The Hardware ECC Accelerator Status Register 0 provides visibility into the run-time status of the ECC8. The register also reflects the ECC8 configurations supported in this version of the SoC. EXAMPLE: Have8BitRSEncode = HW_ECC8_STAT.B.RS8ENC_PRESENT; 14.4.3 Hardware ECC Accelerator Status Register 1 Description HW_ECC8_STATUS1 Table 14-5. HW_ECC8_STATUS1 The Hardware ECC Accelerator Status Register 1 provides overall status of the hardware ECC accelerator. 0x020 3 1 3 0 STATUS_PAYLOAD7 2 9 2 8 2 7 2 6 STATUS_PAYLOAD6 2 5 2 4 2 3 2 2 STATUS_PAYLOAD5 2 1 2 0 1 9 1 8 STATUS_PAYLOAD4 1 7 1 6 1 5 1 4 STATUS_PAYLOAD3 1 3 1 2 1 1 1 0 STATUS_PAYLOAD2 0 9 0 8 0 7 0 6 STATUS_PAYLOAD1 0 5 0 4 0 3 0 2 STATUS_PAYLOAD0 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-31 8-Symbol Correcting ECC Accelerator (ECC8) Table 14-6. HW_ECC8_STATUS1 Bit Field Descriptions BITS LABEL 31:28 STATUS_PAYLOAD7 RW RESET RO 0xc DEFINITION Count of symbols in error during processing of payload area 7. 0xF indicates uncorrectable. NO_ERRORS = 0x0 No errors occurred. ONE_CORRECTABLE = 0x1 One correctable error occurred. TWO_CORRECTABLE = 0x2 Two correctable errors occurred. THREE_CORRECTABLE = 0x3 Three correctable errors occurred. FOUR_CORRECTABLE = 0x4 Four correctable errors occurred. FIVE_CORRECTABLE = 0x5 Five correctable errors occurred. SIX_CORRECTABLE = 0x6 Six correctable errors occurred. SEVEN_CORRECTABLE = 0x7 Seven correctable errors occurred. EIGHT_CORRECTABLE = 0x8 Eight correctable errors occurred. NOT_CHECKED = 0xC This block was not examined by the ECC8. UNCORRECTABLE = 0xE Errors occurred that were uncorrectable. ALL_ONES = 0xF All bits are 1. 27:24 STATUS_PAYLOAD6 RO 0xc Count of symbols in error during processing of payload area 6. 0xF indicates uncorrectable. NO_ERRORS = 0x0 No errors occurred. ONE_CORRECTABLE = 0x1 One correctable error occurred. TWO_CORRECTABLE = 0x2 Two correctable errors occurred. THREE_CORRECTABLE = 0x3 Three correctable errors occurred. FOUR_CORRECTABLE = 0x4 Four correctable errors occurred. FIVE_CORRECTABLE = 0x5 Five correctable errors occurred. SIX_CORRECTABLE = 0x6 Six correctable errors occurred. SEVEN_CORRECTABLE = 0x7 Seven correctable errors occurred. EIGHT_CORRECTABLE = 0x8 Eight correctable errors occurred. NOT_CHECKED = 0xC This block was not examined by the ECC8. UNCORRECTABLE = 0xE Errors occurred that were uncorrectable. ALL_ONES = 0xF All bits are 1. 23:20 STATUS_PAYLOAD5 RO 0xc Count of symbols in error during processing of payload area 5. 0xF indicates uncorrectable. NO_ERRORS = 0x0 No errors occurred. ONE_CORRECTABLE = 0x1 One correctable error occurred. TWO_CORRECTABLE = 0x2 Two correctable errors occurred. THREE_CORRECTABLE = 0x3 Three correctable errors occurred. FOUR_CORRECTABLE = 0x4 Four correctable errors occurred. FIVE_CORRECTABLE = 0x5 Five correctable errors occurred. SIX_CORRECTABLE = 0x6 Six correctable errors occurred. SEVEN_CORRECTABLE = 0x7 Seven correctable errors occurred. EIGHT_CORRECTABLE = 0x8 Eight correctable errors occurred. NOT_CHECKED = 0xC This block was not examined by the ECC8. UNCORRECTABLE = 0xE Errors occurred that were uncorrectable. ALL_ONES = 0xF All bits are 1. 19:16 STATUS_PAYLOAD4 RO 0xc Count of symbols in error during processing of payload area 4. 0xF indicates uncorrectable. NO_ERRORS = 0x0 No errors occurred. ONE_CORRECTABLE = 0x1 One correctable error occurred. TWO_CORRECTABLE = 0x2 Two correctable errors occurred. THREE_CORRECTABLE = 0x3 Three correctable errors occurred. FOUR_CORRECTABLE = 0x4 Four correctable errors occurred. FIVE_CORRECTABLE = 0x5 Five correctable errors occurred. SIX_CORRECTABLE = 0x6 Six correctable errors occurred. SEVEN_CORRECTABLE = 0x7 Seven correctable errors occurred. EIGHT_CORRECTABLE = 0x8 Eight correctable errors occurred. NOT_CHECKED = 0xC This block was not examined by the ECC8. UNCORRECTABLE = 0xE Errors occurred that were uncorrectable. ALL_ONES = 0xF All bits are 1. 15:12 STATUS_PAYLOAD3 RO 0xc Count of symbols in error during processing of payload area 3. 0xF indicates uncorrectable. NO_ERRORS = 0x0 No errors occurred. ONE_CORRECTABLE = 0x1 One correctable error occurred. TWO_CORRECTABLE = 0x2 Two correctable errors occurred. THREE_CORRECTABLE = 0x3 Three correctable errors occurred. FOUR_CORRECTABLE = 0x4 Four correctable errors occurred. FIVE_CORRECTABLE = 0x5 Five correctable errors occurred. SIX_CORRECTABLE = 0x6 Six correctable errors occurred. SEVEN_CORRECTABLE = 0x7 Seven correctable errors occurred. EIGHT_CORRECTABLE = 0x8 Eight correctable errors occurred. NOT_CHECKED = 0xC This block was not examined by the ECC8. UNCORRECTABLE = 0xE Errors occurred that were uncorrectable. ALL_ONES = 0xF All bits are 1. i.MX23 Applications Processor Reference Manual, Rev. 1 14-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) Table 14-6. HW_ECC8_STATUS1 Bit Field Descriptions BITS LABEL 11:8 STATUS_PAYLOAD2 RW RESET RO 0xc DEFINITION Count of symbols in error during processing of payload area 2. 0xF indicates uncorrectable. NO_ERRORS = 0x0 No errors occurred. ONE_CORRECTABLE = 0x1 One correctable error occurred. TWO_CORRECTABLE = 0x2 Two correctable errors occurred. THREE_CORRECTABLE = 0x3 Three correctable errors occurred. FOUR_CORRECTABLE = 0x4 Four correctable errors occurred. FIVE_CORRECTABLE = 0x5 Five correctable errors occurred. SIX_CORRECTABLE = 0x6 Six correctable errors occurred. SEVEN_CORRECTABLE = 0x7 Seven correctable errors occurred. EIGHT_CORRECTABLE = 0x8 Eight correctable errors occurred. NOT_CHECKED = 0xC This block was not examined by the ECC8. UNCORRECTABLE = 0xE Errors occurred that were uncorrectable. ALL_ONES = 0xF All bits are 1. 7:4 STATUS_PAYLOAD1 RO 0xc Count of symbols in error during processing of payload area 1. 0xF indicates uncorrectable. NO_ERRORS = 0x0 No errors occurred. ONE_CORRECTABLE = 0x1 One correctable error occurred. TWO_CORRECTABLE = 0x2 Two correctable errors occurred. THREE_CORRECTABLE = 0x3 Three correctable errors occurred. FOUR_CORRECTABLE = 0x4 Four correctable errors occurred. FIVE_CORRECTABLE = 0x5 Five correctable errors occurred. SIX_CORRECTABLE = 0x6 Six correctable errors occurred. SEVEN_CORRECTABLE = 0x7 Seven correctable errors occurred. EIGHT_CORRECTABLE = 0x8 Eight correctable errors occurred. NOT_CHECKED = 0xC This block was not examined by the ECC8. UNCORRECTABLE = 0xE Errors occurred that were uncorrectable. ALL_ONES = 0xF All bits are 1. 3:0 STATUS_PAYLOAD0 RO 0xc Count of symbols in error during processing of payload area 0. 0xF indicates uncorrectable. NO_ERRORS = 0x0 No errors occurred. ONE_CORRECTABLE = 0x1 One correctable error occurred. TWO_CORRECTABLE = 0x2 Two correctable errors occurred. THREE_CORRECTABLE = 0x3 Three correctable errors occurred. FOUR_CORRECTABLE = 0x4 Four correctable errors occurred. FIVE_CORRECTABLE = 0x5 Five correctable errors occurred. SIX_CORRECTABLE = 0x6 Six correctable errors occurred. SEVEN_CORRECTABLE = 0x7 Seven correctable errors occurred. EIGHT_CORRECTABLE = 0x8 Eight correctable errors occurred. NOT_CHECKED = 0xC This block was not examined by the ECC8. UNCORRECTABLE = 0xE Errors occurred that were uncorrectable. ALL_ONES = 0xF All bits are 1. DESCRIPTION: The Hardware ECC Accelerator Status Register 1 provides visibility into the run-time status of the ECC8. The register also reflects the ECC8 configurations supported in this version of the SoC. EXAMPLE: if(HW_ECC8_STAT1.B._PAYLOAD0) LifeIsGood(); 14.4.4 Hardware ECC Accelerator Debug Register 0 Description The ECC8 internal state machines and signals can be seen in the Hardware ECC Accelerator Debug Register 0. HW_ECC8_DEBUG0 HW_ECC8_DEBUG0_SET HW_ECC8_DEBUG0_CLR HW_ECC8_DEBUG0_TOG 0x030 0x034 0x038 0x03C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-33 8-Symbol Correcting ECC Accelerator (ECC8) Table 14-7. HW_ECC8_DEBUG0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 KES_DEBUG_SYNDROME_SYMBOL 1 9 1 8 1 7 1 6 1 5 1 4 KES_DEBUG_PAYLOAD_FLAG 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 KES_DEBUG_SHIFT_SYND BM_KES_TEST_BYPASS KES_DEBUG_MODE4K Table 14-8. HW_ECC8_DEBUG0 Bit Field Descriptions BITS LABEL RW RESET 31:25 RSRVD1 RO 0x0 24:16 KES_DEBUG_SYNDROME_S RW 0x0 YMBOL DEFINITION Reserved. The 9-bit value in this bit field will be shifted into the syndrome register array at the input of the KES engine whenever HW_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled. NORMAL = 0x0 Bus master address generator for synd_gen writes operates normally. TEST_MODE = 0x1 Bus master address generator always addresses last four bytes in auxiliary block. 15 KES_DEBUG_SHIFT_SYND RW 0x0 14 KES_DEBUG_PAYLOAD_FLA RW 0x0 G Toggling this bit causes the value in HW_ECC8_DEBUG0_KES_SYNDROME_SYMBOL to be shifted into the syndrome register array at the input to the KES engine. After shifting in 16 symbols, one can kick off both KES and CF cycles by toggling HW_ECC8_DEBUG0_KES_DEBUG_KICK. Be sure to set KES_ECC8_DEBUG0_KES_STANDALONE mode to 1 before kicking. When running the standalone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag. DATA = 0x1 Payload is set for 512 byte data block. AUX = 0x1 Payload is set for 65 or 19 byte auxiliary block. 13 KES_DEBUG_MODE4K RW 0x0 When running the standalone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages). 4k = 0x1 Mode is set for 4K NAND pages. 2k = 0x1 Mode is set for 2K NAND pages. 12 KES_DEBUG_KICK RW 0x0 Toggling causes KES engine FSM to start as if kicked by the bus master. This allows standalone testing of the KES and Chien Search engines. Be sure to set KES_ECC8_DEBUG0_KES_STANDALONE mode to 1 before kicking. i.MX23 Applications Processor Reference Manual, Rev. 1 14-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor DEBUG_REG_SELECT KES_DEBUG_STALL KES_STANDALONE KES_DEBUG_STEP KES_DEBUG_KICK RSRVD1 RSRVD0 8-Symbol Correcting ECC Accelerator (ECC8) Table 14-8. HW_ECC8_DEBUG0 Bit Field Descriptions BITS LABEL 11 KES_STANDALONE RW RESET RW 0x0 DEFINITION Set to 1 to cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and to suppress toggling the CF_BM_DONE signal by the CF engine. NORMAL = 0x0 Bus master address generator for synd_gen writes operates normally. TEST_MODE = 0x1 Bus master address generator always addresses last four bytes in auxiliary block. 10 KES_DEBUG_STEP RW 0x0 9 KES_DEBUG_STALL RW 0x0 Toggling this bit causes the KES FSM to skip past the stall state if it is in DEBUG_STALL mode and it has completed processing a block. Set to 1 to cause KES FSM to stall after notifying the Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete. This allows a diagnostic to stall the FSM after each block's key equations are solved. This also has the effect of stalling the CSFE search engine so its state can be examined after it finishes processing the KES stalled block. NORMAL = 0x0 KES FSM proceeds to next block supplied by bus master. WAIT = 0x1 KES FSM waits after current equations are solved and the search engine is started. 8 BM_KES_TEST_BYPASS RW 0x0 1 = Point all synd_gen writes to dummy area at the end of the auxiliary block so that diagnostics can preload all payload, parity bytes, and computed syndrome bytes for test the KES engine. NORMAL = 0x0 Bus master address generator for synd_gen writes operates normally. TEST_MODE = 0x1 Bus master address generator always addresses last four bytes in auxiliary block. 7:6 5:0 RSRVD0 DEBUG_REG_SELECT RO 0x0 RW 0x0 Reserved. The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine. DESCRIPTION: The Hardware ECC Accelerator Debug Register 0 provides access to various internal state information which might prove useful during hardware debug and validation. EXAMPLE: Value = HW_ECC8_DEBUG0.U; // diagnostic programs can read and act upon various bit fields. 14.4.5 KES Debug Read Register Description The hardware ECC accelerator key equation solver internal state machines and signals can be seen in the KES Debug Read Register. HW_ECC8_DBGKESREAD 0x040 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-35 8-Symbol Correcting ECC Accelerator (ECC8) Table 14-9. HW_ECC8_DBGKESREAD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUES Table 14-10. HW_ECC8_DBGKESREAD Bit Field Descriptions BITS 31:0 VALUES LABEL RW RESET RO 0x0 DEFINITION Reserved. 14.4.6 Chien Search Forney Evaluator Debug Read Register Description The hardware ECC accelerator Chien Search Forney Evaluator (CSFE) internal state machines and signals can be seen in the Chien Search Forney Evaluator Debug Read Register. HW_ECC8_DBGCSFEREAD 0x050 Table 14-11. HW_ECC8_DBGCSFEREAD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUES Table 14-12. HW_ECC8_DBGCSFEREAD Bit Field Descriptions BITS 31:0 VALUES LABEL RW RESET RO 0x0 DEFINITION Reserved. 14.4.7 Syndrome Generator Debug Read Register Description The hardware ECC accelerator syndrome generator internal state machines and signals can be seen in the Syndrome Generator Debug Read Register. HW_ECC8_DBGSYNDGENREAD 0x060 Table 14-13. HW_ECC8_DBGSYNDGENREAD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUES Table 14-14. HW_ECC8_DBGSYNDGENREAD Bit Field Descriptions BITS 31:0 VALUES LABEL RW RESET RO 0x0 DEFINITION Reserved. 14.4.8 AHB Master and ECC8 Controller Debug Read Register Description The hardware ECC accelerator AHB bus master and ECC8 controller internal state machines and signals can be seen in the AHB Master and ECC8 Controller Debug Read Register. i.MX23 Applications Processor Reference Manual, Rev. 1 14-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor 8-Symbol Correcting ECC Accelerator (ECC8) HW_ECC8_DBGAHBMREAD 0x070 Table 14-15. HW_ECC8_DBGAHBMREAD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUES Table 14-16. HW_ECC8_DBGAHBMREAD Bit Field Descriptions BITS 31:0 VALUES LABEL RW RESET RO 0x0 DEFINITION Reserved. 14.4.9 ECC8 Block Name Register Description HW_ECC8_BLOCKNAME Table 14-17. HW_ECC8_BLOCKNAME This register presents a read-only view of the block name string ECC8. 0x080 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 NAME Table 14-18. HW_ECC8_BLOCKNAME Bit Field Descriptions BITS 31:0 NAME LABEL RW RESET RO 0x38434345 DEFINITION Should be the ASCII characters 8, C, C, E. DESCRIPTION: This register presents a fixed-pattern, read-only value for test purposes. It can be read as an ASCII string with the zero termination coming from the first byte of the VERSION register. EXAMPLE: char *cp = ((char *)HW_ECC8_BLOCKNAME_ADDR); reads back ECC8ECC8ECC8ECC8 with zero termination. 14.4.10 ECC8 Version Register Description This register indicates the version of the block for debug purposes. HW_ECC8_VERSION Table 14-19. HW_ECC8_VERSION 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0a0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 14-37 8-Symbol Correcting ECC Accelerator (ECC8) Table 14-20. HW_ECC8_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x01 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x0 RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_ECC8_VERSION.B.MAJOR != 1) Error(); ECC8 Block v1.1, Revision 2.5 i.MX23 Applications Processor Reference Manual, Rev. 1 14-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 15 20-BIT Correcting ECC Accelerator (BCH) This chapter describes the hardware Bose Ray-Choudhury Hocquenghem (BCH) ECC accelerator available on i.MX23. It provides detailed descriptions of how to use the accelerator and programmable registers (described in Section 15.6, "Programmable Registers"). The BCH block is functionally very similar to the Reed-Solomon based ECC8 hardware available in previous chips. The primary difference from a programming standpoint is that all data transfer to/from memory is handled by the BCH directly instead of using DMA for data write operations. DMA is still used in programming the GPMI control registers. 15.1 Overview The hardware ECC accelerator provides a forward error-correction function for improving the reliability of various storage media that may be attached to the i.MX23. For example, modern high-density NAND flash devices presume the existence of forward error-correction algorithms to correct some soft and/or hard bit errors within the device, allowing for higher device yields and, therefore, lower NAND device costs. The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder module is capable of correcting from 2 to 20 single bit errors within a block of data no larger than about 900 bytes (512 bytes is typical) in applications such as protecting data and resources stored on modern NAND flash devices. The correction level in the BCH block is programmable to provide flexibility for varying applications and configurations of flash page size. The design can be programmed to encode protection of 2, 4, 8, 10, 12, 14, 16, 18, or 20 bit errors when writing flash and to correct the corresponding number of errors on decode. The correction level when decoding MUST be programmed to the same correction level as was used during the encode phase. BCH-codes are a type of block-code, which implies that all error-correction is performed over a block of N-symbols. The BCH operation will be performed over GF(213 = 8192), which is the Galois Field consisting of 8191 one-bit symbols. BCH-encoding (or encode for any block-code) can be performed by two algorithms: systematic encoding or multiplicative encoding. Systematic encoding is the process of reading all the symbols which constitute a block, dividing continuously these symbols by the generator polynomial for the GF(8192) and appending the resulting t parity symbols to the block to create a BCH codeword (where t is the number of correctable bits). The BCH encode process creates t 13-bit parity symbols for each data block when the data is written to the flash device. The parity symbols are written to the flash device after the corresponding data block, i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-1 20-BIT Correcting ECC Accelerator (BCH) and together these are collectively called the codeword. The codeword can be used during the decode process to correct errors that occur in either the data or parity blocks. The BCH decoder processes code words in a 4-step fashion: * Syndrome Calculation (SC): This is the process of reading in all of the symbols of the codeword and continuously dividing by the generator polynomial for the field. 2*t syndromes must be calculated for each codeword and inspection of the syndromes determines if there are errors: a non-zero set of syndromes indicates one or more errors. This process is implemented in parallel hardware to minimize processing time since it must be done every time the decode is performed. Key Equation Solver (KES): The syndromes represent 2t-linear equations with 2t-unknown variables. The process of solving these equations and selecting from the numerous solutions constitutes the KES module. When the KES block completes its operations, it generates an error locator polynomial (sigma) that is used in the proceeding block to determine the locations and values of the errors. Chien Search (CS): This block takes input from the KES block and uses the Chien Algorithm for finding the locations of the errors based on the error locator polynomial. The method basically involves substituting all 8191 symbols from the GF(8192) into the locator polynomial. All evaluations that produce a zero solution indicate locations of the various errors. Since each located error corresponds to a single bit, the bit in the original data may be corrected by simply flipping the polarity of the incorrect location. Correction: this block has to convert the symbol index and mask information to memory byte indexes and masks. * * * The BCH block was designed to operate in a pipelined fashion to maximize throughput. Aside from the initial latency to fill the pipeline stages, the BCH throughput is faster than the fastest GPMI read rate of 2 cycles/byte. Thus, the bottleneck in performing NAND reads and error corrections is the GPMI read rate. Current GPMI read rates are approximately 3 cycles/byte for the current generation of NANDs. The CPU is not directly involved in generating parity symbols, checking for errors, or correcting them. i.MX23 Applications Processor Reference Manual, Rev. 1 15-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) The hardware BCH accelerator is illustrated in Figure 15-1. AXI APBH APBH Bridge/DMA GPMI Programmable Registers BCH Programmable Registers BCH Engine Transfer Controls Write Data Parity Generation Write Data GPMI NAND CONTROLLER Read Data synpar Syndrome Calculation syndromes Read Data AXI master & transfer FSM Key Equation Solver error-locator polynomial Chien Search GPMI clock domain corrections Figure 15-1. Hardware BCH Accelerator 15.2 Operation Before performing any NAND flash read or write operations, software should first program the BCH's flash layout registers (see Section 15.2.2, "Flash Page Layout") to specify how data is to be formatted on the flash device. The BCH hardware allows full programmability over the flash page layout to enable users flexibility in balancing ECC correction levels and ever-changing flash page sizes. To initiate a NAND flash write, software will program a GPMI DMA operation. The DMA need only program the GPMI control registers (and handle the requisite flash addressing handshakes) since the BCH will handle all data operations using its AXI bus interface. The BCH will then send the data to the GPMI controller to be written to flash as it computes the parity symbols. At the end of each data block the BCH will insert the parity symbols into the data stream so that the GPMI sees only a continuous stream of data to be written. NAND flash read operations operate in a similar manner. As the GPMI controller reads the device, all data is sent to the BCH hardware for error detection/correction. The BCH controller writes all incoming read data to system memory and in parallel computes the syndromes used to detect bit errors. If errors are i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-3 20-BIT Correcting ECC Accelerator (BCH) detected within a block, the BCH hardware activates the error correction logic to determine where bit errors have occurred and ultimately correct them in the data buffer in system memory. After an entire flash page has been read and corrected, the BCH will signal an interrupt to the CPU. Figure 15-2 indicates how data read from the GPMI is operated on within the BCH hardware. As the BCH receives data from the GPMI (top row) it is written to memory by the BCH's Bus Interface Unit (BIU) (second row). For blocks requiring correction, the KES logic will be activated after the entire block has been received. Once the error locator polynomial has been computed, the corrections are determined by the Chien Search and fed back to the BIU, which performs a read/modify/write operation on the buffer in memory to correct the data. GPMI/ Syndrome Read Block 0 Read Block 1 Read Block 2 Read Block 3 Read Block 4 Read Block 5 Read Block 6 Read Block 7 ECC Done Interrupt BIU Write Block 0 Write Block 1 Write Block 2 / Correct Block 0 KES Block 1 CS Block 0 Write Block 3 / Correct Block 1 Write Block 4 / Correct Block 2 Write Block 5 / Correct Block 3 Write Block 6 / Correct Block 4 Write Block 7 / Correct Block 5 Correct Block 6 Correct Block 7 KES KES Block 0 KES Block 2 CS Block 1 KES Block 3 CS Block 2 KES Block 4 CS Block 3 KES Block 5 CS Block 4 KES Block 6 CS Block 5 KES Block 7 CS Block 6 CS Block 7 Chien Search Figure 15-2. Block Pipeline while Reading Flash 15.2.1 * * * * * * * * BCH Limitations and Assumptions The BCH is programmable to support 2, 4, 6, 8, 10, 12, 14, 16, 18, and 20 bit error correction. ECC0 is supported as a passthrough, non-correcting mode. Data block sizes must be a multiple of 4 bytes and must be 4-byte aligned in system memory. The BCH supports a programmable number of metadata/auxiliary data bytes, from 0 to 255. Metadata will be written at the beginning of the flash page to facilitate fast access for filesystem operations. Metadata may be treated as an independent block for ECC purposes or combined with the first data block to conserve bits in the flash. The BCH does not support a partial page write. Flash read operations can read the entire page or the first block on the page. The BCH also supports a memory-to-memory mode of operation that does not require the use of DMA or the GPMI. 15.2.2 Flash Page Layout The BCH supports a fully programmable flash page layout, versus the hardwired modes supported in the former ECC8 engine. The BCH maintains 4 independent layout registers that can describe four completely different NAND devices or layouts. When the BCH initiates an operation, it selects one of the layi.MX23 Applications Processor Reference Manual, Rev. 1 15-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) outs by using the chip select as an index into the HW_BCH_LAYOUTSELECT register the determines which layout should be used for the operation. Three possible (generic) flash layout schemes are supported, as indicated in Figure 15-3. (In each case, the metadata size may also be programmed to 0 bytes). Metadata may either be combined with the first block of data or the size of the first data block can be programmed to 0 to allow the metadata to be protected by its own ECC parity bits. Separate ECC over Metadata parity parity parity parity parity parity parity parity meta 10B d0 512B d1 512B d2 512B dn-1 512B dn 512B Block 0 Size=10B ECC=4 Block 1 Size=512B ECC=14 Block 2 Size=512B ECC=14 Combined Metadata & Block 0, unbalanced ECC coverage parity parity parity parity meta 10B d0 512B d1 512B d2 512B dn-1 512B dn 512B Block 0 Size=522B ECC=16 Block 1 Size=512B ECC=16 Block 2 Size=512B ECC=16 Combined Metadata & Block 0, balanced ECC coverage parity parity parity parity meta 32B d0 484B d1 516B d2 516B dn-1 516B dn 516B Block 0 Size=516B ECC=14 Block 1 Size=516B ECC=14 Block 2 Size=516B ECC=14 Figure 15-3. FLASH Page Layout Options Each layout is determined by a pair of registers that define the following parameters: * DATA0_SIZE: Indicates the number of data bytes in the first block on the page (this should not include parity or metadata bytes). This should be set to 0 when the metadata is to be covered separately with its own ECC. This MUST be a multiple of 4 bytes. ECC0: Indicates the ECC level to be used for the first block on the flash (data0+metadata). META_SIZE: indicates the number of bytes (from 0-255) that are stored as metadata. NBLOCKS: Indicates the number of subsequent "DATAN" blocks on the flash, or the number of blocks following the DATA0 block. DATAN_SIZE: Indicates the number of data bytes in all subsequent data blocks. This MUST be a multiple of 4 bytes. ECCN: Indicates the ECC level to be used for the subsequent data blocks. PAGE_SIZE: Indicates the total number of bytes available per page on the physical flash device. This includes the spare area and is typically 4096+128, 4096+218, or 2048+64 bytes. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-5 * * * * * * 20-BIT Correcting ECC Accelerator (BCH) 15.2.3 Determining the ECC layout for a device Since the BCH is programmable, a system can trade off ECC levels for flash size and layout configurations. The following examples indicate how to determine a valid layout based on the required storage space and flash size. For all cases, the size of the parity will be 13*ECC level bits-- thus for ECC8, 13 bytes are required (per block). 15.2.3.1 4K+218 flash, 10 bytes metadata, 512 byte data blocks, separate metadata In this case, we have 8 data blocks each consisting of 512 bytes. Since the flash has 218 "spare" bytes (1744 bits), we first estimate an ECC level for the data blocks by first subtracting the number of metadata bytes from the spare bytes (218-10=208 bytes = 1664 bits) then dividing the number of bits by 8 (number of blocks) and then by 13 (bits per ECC level). 1664 ( 218 - 10 ) x 8 = ------------- = 16 13 ( 8 ) Thus all the data blocks could be covered by ECC16 if the metadata had no parity. This isn't acceptable, so assume ECC14 for all the data blocks. We now calculate the number of free bits for the metadata parity as: 1664 - ( 14 ) x 13 x 8 = 208 Thus 208 bits remain for metadata parity. Dividing by 13 (bits/ECC) gives 16, thus the metadata can be covered with ECC16. The settings for this device would then be Table 15-1. Settings for 4K+218 FLASH Setting PAGE_SIZE META_SIZE DATA0_SIZE ECC0 DATAN_SIZE ECCN NBLOCKS Value 4096+218=4314=0x10DA 10=0x0A 0 16=0x10 512=0x200 14=0x0E 8 15.2.3.2 4K+128 flash, 10 bytes metadata, 512 byte data blocks, separate metadata This flash will have 118 bytes available for ECC (after subtracting the metadata size), thus 944 bits. Dividing by 8*13 (number of blocks * bits per ECC level) we get 9.07, thus we can support ECC8 on the data blocks. The number of free spare bits becomes 944-8*8*13=944-832=112, divided by 13 = 8.6, thus the metadata can be also covered by ECC8. i.MX23 Applications Processor Reference Manual, Rev. 1 15-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) Table 15-2. Settings for 4K+128 FLASH Setting PAGE_SIZE META_SIZE DATA0_SIZE ECC0 DATAN_SIZE ECCN NBLOCKS Value 4096+128=4224=0x1080 10=0x0A 0 8 512=0x200 8 8 In this case, there will be additional unused spare bits, with the BCH will pad out with zeros. 15.2.4 Data buffers in system memory While the data on the flash is interleaved with parity symbols, the BCH assumes that the data buffers in memory are contiguous. Metadata read from the flash will be stored to the location pointed to by the HW_GPMI_AUXILIARY register and data will be written to the address specified in the HW_GPMI_PAYLOAD register. Since the number of blocks on a flash page is programmable, the BCH also writes individual block correction status to the auxiliary pointer at the word-aligned address following the end of the metadata. Optionally, the computed syndromes may also be written to the auxiliary area if the DEBUGSYNDROME bit is set in the control register. As blocks complete processing, the bus master will accumulate the status for each block and write it to the auxiliary data buffer following the metadata. The metadata area will be padded with 0's until the next word boundary and the status for blocks 0-3 will be written to the next word. Status for subsequent blocks will then be written to the buffer. Status for the first block (metadata block) is also stored in the STATUS_BLK0 register in the BCH_STATUS register. The completion codes for the blocks are indicated in the Table 15-3. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-7 20-BIT Correcting ECC Accelerator (BCH) Minimum System Memory Footprint: 512 byte Payload A HW_GPMI_PAYLOAD 512 byte Payload B 512 byte Payload C 512 byte Payload D HW_GPMI_AUXILIARY META_SIZE bytes of auxiliary storage (programmable - block is padded w/ 0's to word boundary) Status for each block. (Optional n bytes syndromes for Payload A) (Optional n bytes syndrome for Payload B) (Optional n bytes syndrome for Payload C) (Optional n bytes syndrome for Payload D) Computed syndrome area consists of 2*t 13-bit symbols written as 16-bit halfwords. Figure 15-4. BCH Data Buffers in Memory Table 15-3. Status Block Completion Codes Code 0xFF 0xFE 0x00 0x01-0x14 Description Block is erased Block is uncorrectable No errors found Number of errors corrected Figure 15-5 shows the layout of the bytes within the status field. i.MX23 Applications Processor Reference Manual, Rev. 1 15-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) 3 2 1 0 Metadata 0 Block 3 Status Block 7 Status 0 0 Block 2 Status Block 6 Status 0 Block 1 Status Block 5 Status 0 block 0 Status Block 4 Status Block 8 Status Status bytes are allocated based on the NBLOCKS programmed into the flash format register. The number of status bytes will be computed by the NBLOCKS+1. The status area will be padded with zeros to the next word boundary. Syndrome data written for debug purposes will follow the end of the status block. Figure 15-5. Memory-to-Memory Operations 15.3 Memory to Memory (Loopback) Operation The BCH supports a memory-to-memory mode of operation where both the encoded and decoded buffers reside in system memory. This can be useful for applications where data must be protected by ECC, but the storage device does not reside on the GPMI bus. The BCH operation in memory to memory mode is much simpler than in GPMI mode since DMAs are not required to manage the operation. Instead software simply writes the HW_BCH_DATAPTR and HW_BCH_METAPTR with the addresses of the data and metadata (auxiliary) buffers and the HW_BCH_ENCODEPTR with the address of the buffer for encoded data. To initiate the operation, software simply sets the M2M_ENCODE and M2M_ENABLE bits in the control register. The BCH can be programmed to either issue an interrupt at the end of the operation or software may poll the status bits for completion. Memory to memory decode operations work in a similar manner. The encoded data address is written to the HW_BCH_ENCODEPTR and the data and meta pointers are written to buffers that correspond to the i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-9 20-BIT Correcting ECC Accelerator (BCH) desired decoded data addresses. To initiate a decode, software must set the M2M_ENCODE bit to 0 while writing the M2M_ENABLE bit. 15.4 Programming the BCH/GPMI Interfaces Programming the BCH for NAND operations consists largely of disabling the soft reset and clock bits (SFTRST and CLKGATE) from the HW_BCH_CTRL register and then programming the flash layout registers to correspond to the format of the attached NAND device(s). The HW_BCH_LAYOUTSELECT register should also be programmed to map the chip select of each attached device into one of the four layout registers. The bulk of the programming is actually applied to the GPMI via PIO operations embedded in DMA command structures. The DMA will perform all the requisite handshaking with the GPMI interface to negotiate the address portion of the transfer, then the BCH will handle all the movement of data from memory to the GPMI (writes) or the GPMI to memory (reads). The BCH will direct all data blocks to the buffer pointed to by the PAYLOAD_BUFFER and the metadata will be written to the AUXILIARY_BUFFER. Both of these registers are located in the GPMI PIO data space and are communicated to the BCH hardware at the beginning of the transfer. Thus, the normal multi-NAND DMA based device interleaving is preserved, i.e., four NANDs on four separate chip selects can be scheduled for read or write operations using the BCH. Whichever channel finishes its ready wait first and enters the DMA arbiter with its lock bit set will "own" the GPMI command interface and through it will own the BCH resources for the duration of its processing. 15.4.1 BCH Encoding for NAND Writes The BCH encoder flowchart in Figure 15-6 shows the detailed steps involved in programming and using the BCH encoder. This flowchart shows how to use the BCH block with the GPMI. To use the BCH encoder with the GPMI's DMA, create a DMA command chain containing nine descriptor structures, as shown in Figure 15-8 and detailed in the DMA structure code example that follows it in Section 15.4.1.1, "DMA Structure Code Example." The nine descriptors perform the following tasks: 1. Disable the BCH block (in case it was enabled) and issue NAND write setup command byte (under "CLE") and address bytes (under "ALE"). 2. Configure and enable the BCH and GPMI blocks to perform the NAND write. 3. Disable the BCH block and issue NAND write execute command byte (under "CLE"). 4. Wait for the NAND device to finish writing the data by watching the ready signal. 5. Check for NAND timeout via "PSENSE". 6. Issue NAND status command byte (under "CLE"). 7. Read the status and compare against expected. 8. If status is incorrect/incomplete, branch to error handling descriptor chain. 9. Otherwise, write is complete and emit GPMI interrupt. i.MX23 Applications Processor Reference Manual, Rev. 1 15-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) BCH ENCODE & WRITE NAND Run the prescribe initialization sequence. Point the GPMI DMA channel 4 (or 5 or 6 or 7) at the prescribed static DMA sequence. Start the DMA. Return and wait for DMA channel 4 (or 5 or 6 or 7) command complete interrupt. STOP APBH DMA CH4 Command Complete ISR Must use SCT clear HW _APBH_CTRL1_CH0_CMDCMPLT_IRQ = 0 Start GPMI DMA chain for next write or read transfer. STOP Figure 15-6. BCH Encode Flowchart Descriptor Legend NEXT CMD ADDR CMD HW_GPMI_CTRL0 HW_GPMI_COMPARE HW_GPMI_ECCCTRL <= <= <= <= xfer_count command_mode cmdwords word_length mask ecc_cmd HW_GPMI_ECCCOUNT HW_GPMI_PAYLOAD HW_GPMI_AUXILIARY enable_ecc wait4endcmd lock_cs semaphore BUFFER ADDR CS address address_increment reference buffer_mask xfer_count nandwait4ready nandlock irqoncmplt chain command Note: Refer to this legend when examining Figure 15-8 and Figure 15-10. Figure 15-7. BCH DMA Descriptor Legend i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-11 20-BIT Correcting ECC Accelerator (BCH) Descriptor 1: Disable BCH engine and issue NAND write set-up command and address (CLE/ALE). NEXT CMD ADDR CMD <= 1+5 write ---3 1 0 0 101 DMA_READ BUFFER ADDR HW_GPMI_CTRL0 <= HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= 8_bit enabled 2 null disable NAND_CLE 1 null ---1+5 1 Byte NAND CMD 5 Byte ADDR Descriptor 2: Enable the BCH engine and write the data payload. NEXT CMD ADDR CMD <= 0 write 4 1 0 0 1 0 1 NO_DMA_XFER 0 null enable 4096+218 (flash page size) HW_GPMI_PAYLOAD HW_GPMI_AUXILIARY NOTE: No DMA data transferred to GPMI when using BCH BUFFER ADDR HW_GPMI_CTRL0 <= HW_GPMI_COMPARE<= HW_GPMI_ECCCTRL <= HW_GPMI_ECCCOUNT<= 8_bit enabled 2 NAND_DATA 0 null encode_8_bit 0x1FF 8*512 Byte Data Payload Buffer Auxiliary Payload Buffer Descriptor 3: Disable BCH engine and issue NAND write execute command (CLE). NEXT CMD ADDR CMD <= 1 write ---Descriptor 4: Wait for NAND ready. NEXT CMD ADDR CMD <= 0 wait_for_ready 1 1 0 1 0 0 1 NO_DMA_XFER 0 BUFFER ADDR HW_GPMI_CTRL0 <= 8_bit disabled 2 NAND_DATA 0 3 1 0 0 101 0 null disable ---DMA_READ 1 BUFFER ADDR HW_GPMI_CTRL0 <= HW_GPMI_COMPARE<= HW_GPMI_ECCCTRL <= 8_bit enabled 2 NAND_CLE null 1 Byte NAND CMD Descriptor 5: PSENSE compare for time-out. NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 001 DMA_SENSE DMA Error Descriptor Chain Descriptor 6: Disable BCH engine (if enabled by another thread) and issue NAND status command (CLE). NEXT CMD ADDR CMD <= 1 write ---3 1 0 0 101 DMA_READ BUFFER ADDR HW_GPMI_CTRL0 <= HW_GPMI_COMPARE<= HW_GPMI_ECCCTRL <= 8_bit enabled 2 null disable NAND_CLE 0 null ---1 1 Byte NAND CMD Descriptor 7: Read the NAND status and compare against expected value. NEXT CMD ADDR CMD <= 0 2 1 0 0 1 0 1 NO_DMA_XFER 1 BUFFER ADDR HW_GPMI_CTRL0 <= read_and_compare 8_bit disabled 2 NAND_DATA 0 HW_GPMI_COMPARE<= Descriptor 8: PSENSE compare for status comparison check. NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 001 DMA_SENSE Descriptor 9: Emit GPMI DMA interrupt. NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 0 1 0 NO_DMA_XFER Note: To interpret the fields in this diagram, see Figure 15-7 for the descriptor legend. Figure 15-8. BCH Encode DMA Descriptor Chain i.MX23 Applications Processor Reference Manual, Rev. 1 15-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) 15.4.1.1 DMA Structure Code Example The following code sample illustrates the coding for one write transaction involving 4096 bytes of data payload (eight 512-byte blocks) and 10 bytes of auxiliary payload (also referred to as metadata) to a 4K NAND page sitting on GPMI CS2. //---------------------------------------------------------------------------// generic DMA/GPMI/ECC descriptor struct, order sensitive! //---------------------------------------------------------------------------typedef struct { // DMA related fields unsigned int dma_nxtcmdar; unsigned int dma_cmd; unsigned int dma_bar; // GPMI related fields unsigned int gpmi_ctrl0; unsigned int gpmi_compare; unsigned int gpmi_eccctrl; unsigned int gpmi_ecccount; unsigned int gpmi_data_ptr; unsigned int gpmi_aux_ptr; } GENERIC_DESCRIPTOR; //---------------------------------------------------------------------------// allocate 9 descriptors for doing a NAND ECC Write //---------------------------------------------------------------------------GENERIC_DESCRIPTOR write[9]; //---------------------------------------------------------------------------// DMA descriptor pointer to handle error conditions from psense checks //---------------------------------------------------------------------------unsigned int * dma_error_handler; //---------------------------------------------------------------------------// 8 byte NAND command and address buffer // any alignment is ok, it is read by the GPMI DMA // byte 0 is write setup command // bytes 1-5 is the NAND address // byte 6 is write execute command // byte 7 is status command //---------------------------------------------------------------------------unsigned char nand_cmd_addr_buffer[8]; //---------------------------------------------------------------------------// 4096 byte payload buffer used for reads or writes // needs to be word aligned //---------------------------------------------------------------------------unsigned int write_payload_buffer[(4096/4)]; //---------------------------------------------------------------------------// 65 byte meta-data to be written to NAND // needs to be word aligned //---------------------------------------------------------------------------unsigned int write_aux_buffer[65]; //---------------------------------------------------------------------------// Descriptor 1: issue NAND write setup command (CLE/ALE) //---------------------------------------------------------------------------write[0].dma_nxtcmdar = &write[1]; // point to the next descriptor write[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1 + 5)| BF_APBH_CHn_CMD_CMDWORDS (3) | BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); write[0].dma_bar = &nand_cmd_addr_buffer; // 3 words sent to the GPMI write[0].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT write[0].gpmi_compare = NULL; // 1 byte command, 5 byte address // send 3 words to the GPMI // wait for command to finish before continuing // prevent other DMA channels from taking over // follow chain to next command // read data from DMA, write to NAND // byte 0 write setup, bytes 1 - 5 NAND address WRITE) 8_BIT) ENABLED) (2) NAND_CLE) (1) (1 + 5); | // write to the NAND | | | // must correspond to NAND CS used | | // send command and address // 1 byte command, 5 byte address // field not used but necessary to set eccctrl i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-13 20-BIT Correcting ECC Accelerator (BCH) write[0].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block //---------------------------------------------------------------------------// Descriptor 2: write the data payload (DATA) //---------------------------------------------------------------------------write[1].dma_nxtcmdar = &write[2]; // point to the next descriptor write[1].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0)| // NOTE: No DMA data transfer BF_APBH_CHn_CMD_CMDWORDS (6)| // send 6 words to the GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1)| // Wait to end BF_APBH_CHn_CMD_SEMAPHORE (0)| BF_APBH_CHn_CMD_NANDWAIT4READY (0)| BF_APBH_CHn_CMD_NANDLOCK (1)| // maintain resource lock BF_APBH_CHn_CMD_IRQONCMPLT (0)| BF_APBH_CHn_CMD_CHAIN (1)| // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, DMA_NO_XFER); // No data transferred write[1].dma_bar = &write_payload_buffer; // 4 words sent to the GPMI write[1].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT // pointer for the 4K byte data area WRITE) | // write to the NAND 8_BIT) | ENABLED) | (2) | // must correspond to NAND CS used NAND_DATA)| (0) | (0); // NOTE: this field contains // the total amount // DMA transferred to GPMI via DMA (0)! // field not used but necessary to set eccctrl write[1].gpmi_compare = NULL; write[1].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ECC_CMD, ENCODE_8_BIT) | // specify t = 8 mode BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, ENABLE) | // enable ECC module BF_GPMI_ECCCTRL_BUFFER_MASK (0x1FF); // write all 8 data blocks and 1 aux block write[1].gpmi_ecccount = BF_GPMI_ECCCOUNT_COUNT(4096+218); write[1].gpmi_data_pointer = &write_payload_pointer; write[1].gpmi_aux_pointer = &write_aux_pointer; // specify number of bytes written to NAND // data buffer address // metadata pointer //---------------------------------------------------------------------------// Descriptor 3: issue NAND write execute command (CLE) //---------------------------------------------------------------------------write[2].dma_nxtcmdar = &write[3]; // point to the next descriptor write[2].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | // BF_APBH_CHn_CMD_CMDWORDS (3) | // BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); write[2].dma_bar = &nand_cmd_addr_buffer[6]; // 3 words sent to the GPMI write[2].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT write[2].gpmi_compare = NULL; 1 byte command send 3 words to the GPMI wait for command to finish before continuing maintain resource lock follow chain to next command // read data from DMA, write to NAND // point to byte 6, write execute command WRITE) 8_BIT) ENABLED) (2) NAND_CLE) (0) (1); | // write to the NAND | | | // must correspond to NAND CS used | | // 1 byte command // field not used but necessary to set eccctrl write[2].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block //---------------------------------------------------------------------------// Descriptor 4: wait for ready (CLE) //---------------------------------------------------------------------------write[3].dma_nxtcmdar = &write[4]; // point to the next descriptor write[3].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (1) | // send 1 word to the GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(1) | // wait for nand to be ready BF_APBH_CHn_CMD_NANDLOCK (0) | // relinquish nand lock BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer write[3].dma_bar = NULL; // 1 word sent to the GPMI // field not used i.MX23 Applications Processor Reference Manual, Rev. 1 15-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) write[3].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT WAIT_FOR_READY) | // wait for NAND ready 8_BIT) | DISABLED) | (2) | // must correspond to NAND CS used NAND_DATA) | (0) | (0); //---------------------------------------------------------------------------// Descriptor 5: psense compare (time out check) //---------------------------------------------------------------------------write[4].dma_nxtcmdar = &write[5]; // point to the next descriptor write[4].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | BF_APBH_CHn_CMD_CMDWORDS (0) | BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE); write[4].dma_bar = dma_error_handler; // no dma transfer // no words sent to GPMI // do not wait to continue // follow chain to next command // perform a sense check // if sense check fails, branch to error handler //---------------------------------------------------------------------------// Descriptor 6: issue NAND status command (CLE) //---------------------------------------------------------------------------write[5].dma_nxtcmdar = &write[6]; // point to the next descriptor write[5].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | // 1 byte command BF_APBH_CHn_CMD_CMDWORDS (3) | // send 3 words to the GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // prevent other DMA channels from taking over BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); // read data from DMA, write to NAND write[5].dma_bar = &nand_cmd_addr_buffer[7]; write[5].gpmi_compare = NULL; // point to byte 7, status command // field not used but necessary to set eccctrl write[5].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block // 3 words sent to the GPMI write[5].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT WRITE) 8_BIT) ENABLED) (2) NAND_CLE) (0) (1); | // write to the NAND | | | // must correspond to NAND CS used | | // 1 byte command //---------------------------------------------------------------------------// Descriptor 7: read status and compare (DATA) //---------------------------------------------------------------------------write[6].dma_nxtcmdar = &write[7]; // point to the next descriptor write[6].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (2) | // send 2 words to the GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // maintain resource lock BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer write[6].dma_bar = NULL; // 2 word sent to the GPMI write[6].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, // BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT write[6].gpmi_compare = //---------------------------------------------------------------------------// Descriptor 8: psense compare (time out check) //---------------------------------------------------------------------------write[7].dma_nxtcmdar = &write[8]; // point to the next descriptor i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-15 20-BIT Correcting ECC Accelerator (BCH) write[7].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | BF_APBH_CHn_CMD_CMDWORDS (0) | BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE); write[7].dma_bar = dma_error_handler; // no dma transfer // no words sent to GPMI // do not wait to continue // relinquish nand lock // follow chain to next command // perform a sense check // if sense check fails, branch to error handler //---------------------------------------------------------------------------// Descriptor 9: emit GPMI interrupt //---------------------------------------------------------------------------write[8].dma_nxtcmdar = NULL; // not used since this is last descriptor write[8].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | BF_APBH_CHn_CMD_CMDWORDS (0) | BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (1) | BF_APBH_CHn_CMD_CHAIN (0) | BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer // no words sent to GPMI // do not wait to continue // emit GPMI interrupt // terminate DMA chain processing // no dma transfer 15.4.1.2 Using the BCH Encoder To use the BCH encoder, first turn off the module-wide soft reset bit in both the GPMI and BCH blocks before starting any DMA activity. Note that turning off the soft reset must take place by itself, prior to programming the rest of the control registers. Turn off the BCH bus master soft reset bit (bit 29). Turn off the clock gate bits. Program the remainder of the GPMI, BCH and APBH DMA as follows: // bring APBH out of reset HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_SFRST); HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE); // bring BCH out of reset HW_BCH_CTRL_CLR(BM_BCH_CTRL_SFTRST); HW_BCH_CTRL_CLR(BM_BCH_CTRL_CLKGATE); // bring gpmi out of reset HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST); HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE); HW_GPMI_CTRL1_SET(BM_GPMI_CTRL1_DEV_RESET | // deassert reset BM_GPMI_CTRL1_BCH_MODE );// enable BCH mode // enable pinctrl HW_PINCTRL_CTRL_WR(0x00000000); // enable GPMI through alt pin wiring HW_PINCTRL_MUXSEL0_CLR(0xff000000); HW_PINCTRL_MUXSEL0_SET(0xaa000000); // to use the primary pins do the following // HW_PINCTRL_MUXSEL4_CLR(0xff000000); // HW_PINCTRL_MUXSEL4_SET(0x55000000); // enable gpmi pins HW_PINCTRL_MUXSEL0_CLR(0x0000ffff);// data bits HW_PINCTRL_MUXSEL1_CLR(0x000fffff);// control bits Note that for writing NANDs (ECC encoding), only GPMI DMA command complete interrupts are used. The BCH engine is used for writing to the NAND but may optionally produce an interrupt. From the sample code in Section 15.4.1.1, "DMA Structure Code Example": i.MX23 Applications Processor Reference Manual, Rev. 1 15-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) * * * * * * * DMA descriptor 1 prepares the NAND for data write by using the GPMI to issue a write setup command byte under "CLE", then sends a 5-byte address under "ALE". The BCH engine is disabled and not used for these commands. DMA descriptor 2 enables the BCH engine for encoding to begin the initial writing of the NAND data by specifying where the data and auxiliary payload are coming from in system memory. DMA descriptor 3 issues the write commit command byte under "CLE" to the NAND. DMA descriptor 4 waits for the NAND to complete the write commit/transfer by watching the NAND's ready line status. This descriptor relinquishes the NANDLOCK on the GPMI to enable the other DMA channels to initiate NAND transactions on different NAND CS lines. DMA descriptor 6 issues a NAND status command byte under "CLE" to check the status of the NAND device following the page write. DMA descriptor 7 reads back the NAND status and compares the status with an expected value. If there are differences, then the DMA processing engine follows an error-handling DMA descriptor path. DMA descriptor 8 disables the BCH engine and emits a GPMI interrupt to indicate that the NAND write has been completed. 15.4.2 BCH Decoding for NAND Reads When a page is read from NAND flash, BCH syndromes will be computed and, if correctable errors are found, they will be corrected on a per block basis within the NAND page. This decoding process is fully overlapped with other NAND data reads and with CPU execution. The BCH decoder flowchart in Figure 15-9 shows the steps involved in programming the decoder. The hardware flow of reading and decoding a 4096-byte page is shown in Figure 15-10. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-17 20-BIT Correcting ECC Accelerator (BCH) R ead N AN D & B C H D ecode R u n th e p r e s c r ib e i n it ia l iz a t io n S e q u e n c e P o in t t h e G P M I D M A c h a n n e l 4 ( o r 5 o r 6 o r 7 ) a t t h e p r e s c r i b e d s t a t ic D M A s e q u e n c e S ta rt th e D M A R e tu r n a n d w a i t f o r D M A c h a n n e l 4 ( o r 5 o r 6 o r 7 ) c o m m a n d c o m p le t e in t e r r u p t . STO P APBH D M A C H 4 C om m and C o m p le te IS R M u s t u s e S C T c le a r H W _ A P B H _ C T R L 1 _ C H 0 _ C M D C M P L T _ IR Q = 0 S ta r t G P M I D M A c h a in f o r n e x t w r it e o r r e a d tra n s fe r STOP BCH C o m p le t e I S R R e a d s t a tu s r e g s a n d s t o r e f o r p r o c e s s in g M u s t u s e S C T c le a r H W _ B C H _ C T R L _ C O M P L E T E _ IR Q = 0 STO P Figure 15-9. BCH Decode Flowchart Conceptually, an APBH DMA Channel 4, 5, 6, or 7 command chain with seven command structures linked together is used to perform the BCH decode operation (as shown in Figure 15-10). NOTE: The GPMI's DMA command structures controls the BCH decode operation. To use the BCH decoder with the GPMI's DMA, create a DMA command chain containing seven descriptor structures, as shown in Figure 15-10 and detailed in the DMA structure code example that fol- i.MX23 Applications Processor Reference Manual, Rev. 1 15-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) lows it in Section 15.4.2.1, "DMA Structure Code Example." The seven DMA descriptors perform the following tasks: 1. 2. 3. 4. 5. 6. 7. Issue NAND read setup command byte (under "CLE") and address bytes (under "ALE"). Issue NAND read execute command byte (under "CLE"). Wait for the NAND device to complete accessing the block data by watching the ready signal. Check for NAND timeout via "PSENSE". Configure and enable the BCH block and read the NAND block data. Disable the BCH block. Descriptor NOP to allow NANDLOCK in the previous descriptor to the thread-safe. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-19 20-BIT Correcting ECC Accelerator (BCH) Descriptor 1: Disable BCH engine and issue NAND read set-up command and address (CLE/ALE). NEXT CMD ADDR CMD HW_GPMI_CTRL0 <= <= 1+5 write ---3 1 0 0 NAND_CLE disable 101 1 null ---DMA_READ BUFFER ADDR 8_bit enabled 2 null 1+5 HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= 1 Byte NAND CMD 5 Byte ADDR Descriptor 2: NAND read execute command (CLE). NEXT CMD ADDR CMD HW_GPMI_CTRL0 <= <= 1 write 1 1 0 0 101 DMA_READ BUFFER ADDR 8_bit disabled 2 NAND_CLE 0 1 1 Byte NAND CMD Descriptor 3: Wait for NAND ready. NEXT CMD ADDR CMD HW_GPMI_CTRL0 <= <= 0 wait_for_ready 1 1 0 1 0 0 1 NO_DMA_XFER 0 BUFFER ADDR 8_bit disabled 2 NAND_DATA 0 Descriptor 4: PSENSE compare for time-out. NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 001 DMA_SENSE DMA Error Descriptor Chain Descriptor 5: Enable BCH engine and read NAND data. NEXT CMD ADDR CMD HW_GPMI_CTRL0 <= <= 0 read 6 1 0 0 1 0 1 NO_DMA_XFER 4096+218 null enable 4096+218 (flash page size) HW_GPMI_PAYLOAD HW_GPMI_AUXILIARY 0x1FF BUFFER ADDR 8_bit disabled 2 NAND_DATA 0 null decode_8_bit HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= HW_GPMI_ECCCOUNT<= 8*512 Byte Data Payload Buffer 412 Byte Auxiliary Payload Buffer Descriptor 6: Disable BCH engine (wait for ready is a NOP here). NEXT CMD ADDR CMD HW_GPMI_CTRL0 <= <= 0 wait_for_ready ---3 1 0 1 1 0 1 NO_DMA_XFER 0 null disable ---BUFFER ADDR 8_bit disabled 0 NAND_DATA 0 null HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= Descriptor 7: NOP to ensure NANDLOCK in previous descriptor. NEXT CMD ADDR CMD <= 0 0 1 BUFFER ADDR 0 0 0 0 0 NO_DMA_XFER Note: To interpret the fields in this diagram, see Figure 15-7 for the descriptor legend. Figure 15-10. BCH Decode DMA Descriptor Chain 15.4.2.1 DMA Structure Code Example The following sample code illustrates the coding for one read transaction, consisting of a seven DMA command structure chain for reading all 4096 bytes of payload data (eight 512-byte blocks) and 65 bytes of metadata with the associative parity bytes (8 * (18) + 9) from a 4K NAND page sitting on GPMI CS2. i.MX23 Applications Processor Reference Manual, Rev. 1 15-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) //---------------------------------------------------------------------------// generic DMA/GPMI/ECC descriptor struct, order sensitive! //---------------------------------------------------------------------------typedef struct { // DMA related fields unsigned int dma_nxtcmdar; unsigned int dma_cmd; unsigned int dma_bar; // GPMI related fields unsigned int gpmi_ctrl0; unsigned int gpmi_compare; unsigned int gpmi_eccctrl; unsigned int gpmi_ecccount; unsigned int gpmi_data_ptr; unsigned int gpmi_aux_ptr; } GENERIC_DESCRIPTOR; //---------------------------------------------------------------------------// allocate 7 descriptors for doing a NAND ECC Read //---------------------------------------------------------------------------GENERIC_DESCRIPTOR read[7]; //---------------------------------------------------------------------------// DMA descriptor pointer to handle error conditions from psense checks //---------------------------------------------------------------------------unsigned int * dma_error_handler; //---------------------------------------------------------------------------// 7 byte NAND command and address buffer // any alignment is ok, it is read by the GPMI DMA // byte 0 is read setup command // bytes 1-5 is the NAND address // byte 6 is read execute command //---------------------------------------------------------------------------unsigned char nand_cmd_addr_buffer[7]; //---------------------------------------------------------------------------// 4096 byte payload buffer used for reads or writes // needs to be word aligned //---------------------------------------------------------------------------unsigned int read_payload_buffer[(4096/4)]; //---------------------------------------------------------------------------// 412 byte auxiliary buffer used for reads // needs to be word aligned //---------------------------------------------------------------------------unsigned int read_aux_buffer[(412/4)]; //---------------------------------------------------------------------------// Descriptor 1: issue NAND read setup command (CLE/ALE) //---------------------------------------------------------------------------read[0].dma_nxtcmdar = &read[1]; // point to the next descriptor read[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1 + 5) | BF_APBH_CHn_CMD_CMDWORDS (3) | BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); read[0].dma_bar = &nand_cmd_addr_buffer; // 3 words sent to the GPMI read[0].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT read[0].gpmi_compare = NULL; // 1 byte command, 5 byte address // send 3 words to the GPMI // wait for command to finish before continuing // prevent other DMA channels from taking over // follow chain to next command // read data from DMA, write to NAND // byte 0 read setup, bytes 1 - 5 NAND address WRITE) 8_BIT) ENABLED) (2) NAND_CLE) (1) (1 + 5); | // write to the NAND | | | // must correspond to NAND CS used | | // send command and address // 1 byte command, 5 byte address // field not used but necessary to set eccctrl read[0].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block //---------------------------------------------------------------------------// Descriptor 2: issue NAND read execute command (CLE) //---------------------------------------------------------------------------read[1].dma_nxtcmdar = &read[2]; // point to the next descriptor read[1].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) BF_APBH_CHn_CMD_CMDWORDS (1) BF_APBH_CHn_CMD_WAIT4ENDCMD (1) BF_APBH_CHn_CMD_SEMAPHORE (0) BF_APBH_CHn_CMD_NANDWAIT4READY(0) | | | | | // 1 byte read command // send 1 word to GPMI // wait for command to finish before continuing i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-21 20-BIT Correcting ECC Accelerator (BCH) BF_APBH_CHn_CMD_NANDLOCK BF_APBH_CHn_CMD_IRQONCMPLT BF_APBH_CHn_CMD_CHAIN BV_FLD(APBH_CHn_CMD, COMMAND, read[1].dma_bar = &nand_cmd_addr_buffer[6]; // 1 word sent to the GPMI read[1].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT WRITE) 8_BIT) DISABLED) (2) NAND_CLE) (0) (1); (1) | // prevent other DMA channels from taking over (0) | (1) | // follow chain to next command DMA_READ); // read data from DMA, write to NAND // point to byte 6, read execute command | // write to the NAND | | | // must correspond to NAND CS used | | // 1 byte command //---------------------------------------------------------------------------// Descriptor 3: wait for ready (DATA) //---------------------------------------------------------------------------read[2].dma_nxtcmdar = &read[3]; // point to the next descriptor read[2].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // BF_APBH_CHn_CMD_CMDWORDS (1) | // BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(1) | // BF_APBH_CHn_CMD_NANDLOCK (0) | // BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); read[2].dma_bar = NULL; // 1 word sent to the GPMI read[2].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT no dma transfer send 1 word to GPMI wait for command to finish before continuing wait for nand to be ready relinquish nand lock follow chain to next command // no dma transfer // field not used WAIT_FOR_READY) 8_BIT) DISABLED) (2) NAND_DATA) (0) (0); | // wait for NAND ready | | | // must correspond to NAND CS used | | //---------------------------------------------------------------------------// Descriptor 4: psense compare (time out check) //---------------------------------------------------------------------------read[3].dma_nxtcmdar = &read[4]; // point to the next descriptor read[3].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | BF_APBH_CHn_CMD_CMDWORDS (0) | BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE); read[3].dma_bar = dma_error_handler; // no dma transfer // no words sent to GPMI // do not wait to continue // follow chain to next command // perform a sense check // if sense check fails, branch to error handler //---------------------------------------------------------------------------// Descriptor 5: read 4K page plus 65 byte meta-data Nand data // and send it to ECC block (DATA) //---------------------------------------------------------------------------read[4].dma_nxtcmdar = &read[5]; // point to the next descriptor read[4].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (6) | // send 6 words to GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // prevent other DMA channels from taking over BF_APBH_CHn_CMD_IRQONCMPLT (0) | // ECC block generates BCH interrupt on completion BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no DMA transfer, // ECC block handles transfer read[4].dma_bar = NULL; // 6 words sent to the GPMI read[4].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT READ) 8_BIT) DISABLED) (2) NAND_DATA) (0) (4096+218); // field not used | | | | | | // read from the NAND // must correspond to NAND CS used // eight 512 byte data blocks // metadata, and parity read[4].gpmi_compare = NULL; // field not used but necessary to set eccctrl i.MX23 Applications Processor Reference Manual, Rev. 1 15-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) // GPMI ECCCTRL PIO This launches the 4K byte transfer through BCH's // bus master. Setting the ECC_ENABLE bit redirects the data flow // within the GPMI so that read data flows to the BCH engine instead // of flowing to the GPMI's DMA channel. read[4].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ECC_CMD, DECODE_8_BIT) | // specify t = 8 mode BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, ENABLE) | // enable ECC module BF_GPMI_ECCCTRL_BUFFER_MASK (0X1FF); // read all 8 data blocks and 1 aux block read[4].gpmi_ecccount = BF_GPMI_ECCCOUNT_COUNT(4096+218); read[4].gpmi_data_ptr = &read_payload_buffer; read[4].gpmi_aux_ptr = &read_aux_buffer; // specify number of bytes read from NAND // pointer for the 4K byte data area // pointer for the 65 byte aux area + // parity and syndrome bytes for both // data and aux blocks. //---------------------------------------------------------------------------// Descriptor 6: disable ECC block //---------------------------------------------------------------------------read[5].dma_nxtcmdar = &read[6]; // point to the next descriptor read[5].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) BF_APBH_CHn_CMD_CMDWORDS (3) BF_APBH_CHn_CMD_WAIT4ENDCMD (1) BF_APBH_CHn_CMD_SEMAPHORE (0) BF_APBH_CHn_CMD_NANDWAIT4READY(1) BF_APBH_CHn_CMD_NANDLOCK (1) | | | | | | // no dma transfer // send 3 words to GPMI // wait for command to finish before continuing // wait for nand to be ready // need nand lock to be // thread safe while turn-off BCH BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer read[5].dma_bar = NULL; // 3 words sent to the GPMI read[5].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, BV_FLD(GPMI_CTRL0, WORD_LENGTH, BV_FLD(GPMI_CTRL0, LOCK_CS, BF_GPMI_CTRL0_CS BV_FLD(GPMI_CTRL0, ADDRESS, BF_GPMI_CTRL0_ADDRESS_INCREMENT BF_GPMI_CTRL0_XFER_COUNT read[5].gpmi_compare = NULL; READ) 8_BIT) DISABLED) (2) NAND_DATA) (0) (0); // field not used | | | | // must correspond to NAND CS used | | // field not used but necessary to set eccctrl // disable the ECC block read[5].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); //---------------------------------------------------------------------------// Descriptor 7: deassert nand lock //---------------------------------------------------------------------------read[6].dma_nxtcmdar = NULL; // not used since this is last descriptor read[6].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // BF_APBH_CHn_CMD_CMDWORDS (0) | // BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | // BF_APBH_CHn_CMD_IRQONCMPLT (0) | // BF_APBH_CHn_CMD_CHAIN (0) | // BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); read[6].dma_bar = NULL; no dma transfer no words sent to GPMI wait for command to finish before continuing relinquish nand lock BCH engine generates interrupt terminate DMA chain processing // no dma transfer // field not used 15.4.2.2 * Using the Decoder As illustrated in Figure 15-10 and the sample code in Section 15.4.2.1, "DMA Structure Code Example": DMA descriptor 1 prepares the NAND for data read by using the GPMI to issue a NAND read setup command byte under "CLE", then sends a 5-byte address under "ALE". The BCH engine is not used for these commands. DMA descriptor 2 issues a one-byte read execute command to the NAND device that triggers its read access. The NAND then goes not ready. DMA descriptor 3 performs a wait for ready operation allowing the DMA chain to remain dormant until the NAND device completes its read access time. * * i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-23 20-BIT Correcting ECC Accelerator (BCH) * * * * * DMA descriptor 5 handles the reading and error correction of the NAND data. This command's PIOs activate the BCH engine to write the read NAND data to system memory and to process it for any errors that need to be corrected. This DMA descriptor contains two PIO values that are system memory addresses pointing to the PAYLOAD data area and to the AUXILIARY data area. These addresses are used by the BCH engine's AHB master to move data into system memory and to correct it. While this example is reading an entire 4K page--payload plus metadata--it is equally possible to read just one 512-byte payload block or just the uniquely protected metadata block in a single 7 DMA structure transfer. DMA descriptor 6 disables the BCH engine with the NANDLOCK asserted. This is necessary to ensure that the GPMI resource is not arbitrated to another DMA channel when multiple DMA channels are active concurrently. DMA descriptor 7 deasserts the NANDLOCK to free up the GPMI resource to another channel. The decoder transforms the read NAND data block into an BCH code word and computes the codeword syndrome. If no errors are present, then he BCH block can immediately report back to firmware. This report is passed as the HW_BCH_CTRL_COMPLETE_IRQ interrupt status bit and the associated status bits in the HW_BCH_STATUS0 register. If an error is present, then the BCH block corrects the necessary data block or parity block bytes, if possible (not all errors are correctable). As the BCH block receives data from the GPMI: * As the BCH decoder reads the data and parity blocks, it records a special condition, i.e., that all of the bits of a payload data block or metadata block are one, including any associated parity bytes. The "all-ones" case for both parity and data indicates an erased block in the NAND device. The erased block detection mechanism can be tuned to allow a maximum number of bit errors on an erased page (i.e. zero bits). Write the HW_BCH_MODE_ERASE_THRESHOLD field to a non-zero setting to allow a certain number of zero bits to be read within a block and still consider the block "erased". The HW_BCH_STATUS0 register contains a 4-bit field that indicates the final status of the auxiliary block. A value of 0x0 indicates no errors found for a block. * * * * A value of 1 to 20 inclusive indicates that many correctable errors were found and fixed. A value of 0xFE indicates uncorrectable errors detected on the block. A value of 0xFF indicates that the block was in the special ALL ONES state and is therefore considered to be an ERASED block. All other values are disallowed by the hardware design. Recall that up to four NAND devices can have DMA chains in-flight at once, i.e. they can all be contending for access to the GPMI data bus. It is impossible to predict which NAND device will enter the BCH engine with a transfer first, because each chain includes a wait4ready command structure. As a result, firmware should look at the HW_BCH_STATUS0_COMPLETED_CE bit field to determine which block is being reported in the status register. There is also a 16 bit HANDLE field in the i.MX23 Applications Processor Reference Manual, Rev. 1 15-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) HW_GPMI_ECCCTRL register that is passed down the pipeline with each transaction. This handle field can be used to speed firmware's detection of which transaction is being reported. These examples of reading and writing have focused on full page transfers of 4K page NAND devices. Other device configurations can be specified by changing the ECCOUNT field in the GPMI registers and reprogramming the BCH's HW_FLASHnLAYOUTm registers. The BCH and GPMI blocks are designed to be very efficient at reading single 512-byte pages in one transaction. With no errors, the transaction takes less than 20 HCLKs longer than the time to read the raw data from the NAND. To summarize, the APBH DMA command chain for a BCH decode operation is shown in Figure 15-10. Seven DMA command structures must be present for each NAND read transaction decoded by the BCH. The seven DMA command structures for multiple NAND read transaction blocks can be chained together to make larger units of work for the BCH, and each will produce an appropriate error report in the BCH PIO space. Multiple NAND devices can have such multiple chains scheduled. The results can come back out of order with respect to the multiple chains. 15.4.3 Interrupts There are two interrupt sources used in processing BCH protected NAND read and write transfers. Since all BCH operations are initiated by GPMI DMA command structures, the DMA completion interrupt for the GPMI is an important ISR. Both of the flow charts of Section Figure 15-6., "BCH Encode Flowchart," and Figure 15-9 show the GPMI DMA complete ISR skeleton. In both reads and writes, the GPMI DMA completion interrupt is used to schedule work INTO the error correction pipeline. As the front end processing completes, the DMA interrupt is generated and additional work, i.e. DMA chains, are passed to the GPMI DMA to keep it "fed". For write operations, this is the only interrupt that will be generated for processing the NAND write transfer. For reads, however, two interrupts are needed. Every read is started by a GPMI DMA command chain and the front end queue is fed as described above. The back end of the read pipeline is "drained" by monitoring the BCH completion interrupt found int HW_BCH_CTRL_COMPLETE_IRQ. An BCH transaction consists of reading or writing all of the blocks requested in the HW_GPMI_ECCCTRL_BUFFER_MASK bit field. As every read transaction completes, it posts the status of all of the blocks to the HW_BCH_STATUS0 register and sets the completion interrupt. The five stages of the BCH read pipeline completes, one in the GPMI and four in the BCH, are independently stalled as they complete and try to deliver to the next stage in the data flow. Several of these stages can be skipped if no-errors are found or once an uncorrectable error is found in a block. In any case, the final stage will stall if the status register is busy waiting for the CPU to take status register results. The hardware monitors the state of the HW_BCH_CTRL_COMPLETE_IRQ bit. If it is still i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-25 20-BIT Correcting ECC Accelerator (BCH) set when the last pipeline stage is ready to post data, then the stage will stall. It follows that the next previous stage will stall when it is ready to hand off work to the final stage, and so on up the pipeline. WARNING: It is important that firmware read the STATUS0/1 results and save them before clearing the interrupt request bit otherwise a transaction and its results could be completely lost. 15.5 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. 15.6 Programmable Registers The following registers are available for programmer access and control of the BCH hardware accelerator. 15.6.1 Hardware BCH ECC Accelerator Control Register Description HW_BCH_CTRL HW_BCH_CTRL_SET HW_BCH_CTRL_CLR HW_BCH_CTRL_TOG Table 15-4. HW_BCH_CTRL The BCH CTRL provides overall control of the hardware ECC accelerator 0x000 0x004 0x008 0x00C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 DEBUGSYNDROME 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 DEBUG_STALL_IRQ_EN 0 9 0 8 COMPLETE_IRQ_EN 0 7 0 6 0 5 0 4 0 3 0 2 DEBUG_STALL_IRQ 0 1 0 0 BM_ERROR_IRQ i.MX23 Applications Processor Reference Manual, Rev. 1 15-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor COMPLETE_IRQ M2M_ENCODE M2M_ENABLE M2M_LAYOUT CLKGATE SFTRST RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVD0 20-BIT Correcting ECC Accelerator (BCH) Table 15-5. HW_BCH_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Set this bit to zero to enable normal BCH operation. Set this bit to one (default) to disable clocking with the BCH and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the BCH block to its default state. This bit resets all state machines except for the AHB master state machine. IMPORTANT: Due to an on-chip bug, BCH SFTRST use is not recommended. If the BCH is soft-reset after any transfers, then the AXI master will be locked up until a hard reset. Even if the AXI master is idle, the AXI state machine will be locked up. Soft resets after hard-reset should be safe, but once you perform any BCH transfer, then any subsequent attempts to soft reset the BCH will almost always lock up the BCH. The only way to recover from a BCH lock-up is hard-reset. There should not be any reason to soft reset the BCH. The BCH should finish every transfer properly and be ready for the next operation no matter the state of the page (correctable, uncorrectable, erased, etc.). RUN = 0x0 Allow BCH to operate normally. RESET = 0x1 Hold BCH in reset. 30 CLKGATE RW 0x1 This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. RUN = 0x0 Allow BCH to operate normally. NO_CLKS = 0x1 Do not clock BCH gates in order to minimize power consumption. 29:23 RSVD5 DEBUGSYNDROME 22 RO 0x0 RW 0x0 21:20 RSVD4 19:18 M2M_LAYOUT RO 0x0 RW 0x0 17 16 M2M_ENCODE M2M_ENABLE RW 0x0 RW 0x0 15:11 RSVD3 DEBUG_STALL_IRQ_EN 10 9 8 7:4 RO 0x0 RW 0x0 RO 0x0 RW 0x0 RO 0x0 RSVD2 COMPLETE_IRQ_EN RSVD1 Reserved, always set this bit to zero. (For debug purposes only). Enable write of computed syndromes to memory on BCH decode operations. Computed syndromes will be written to the auxiliary buffer after the status block. Syndromes will be written as padded 16-bit values. Reserved, always set these bits to zero. Selects the flash page format (by indexing into one of the HW_BCH_FLASHnLAYOUT register banks) for memory-to-memory operations. Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. WARNING! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION. The BCH module must be inactive (not processing data from the GPMI) when this bit is set. The M2M_ENCODE and M2M_LAYOUT bits as well as the ENCODEPTR, DATAPTR, and METAPTR registers are used for memory-to-memory operations and must be correctly programmed before writing this bit. Reserved, always set these bits to zero. 1 = interrupt on debug stall mode is enabled. The irq is raised on every block Reserved, always set these bits to zero. 1 = interrupt on completion of correction is enabled. Reserved, always set these bits to zero. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-27 20-BIT Correcting ECC Accelerator (BCH) Table 15-5. HW_BCH_CTRL Bit Field Descriptions BITS LABEL 3 BM_ERROR_IRQ RW RESET RW 0x0 DEFINITION AHB Bus interface Error Interrupt Status. Write a one to the SCT clear address to clear the interrupt status bit. DEBUG STALL Interrupt Status. Write a one to the SCT clear address to clear the interrupt status bit. Reserved, always set these bits to zero. This bit indicates the state of the external interrupt line. Write a one to the SCT clear address to clear the interrupt status bit. NOTE: subsequent ECC completions will be held off as long as this bit is set. Be sure to read the data from HW_BCH_STATUS0 before clearing this interrupt bit. 2 1 0 DEBUG_STALL_IRQ RSVD0 COMPLETE_IRQ RW 0x0 RO 0x0 RW 0x0 15.6.2 Hardware BCH ECC Accelerator Status Register 0 Description HW_BCH_STATUS0 Table 15-6. HW_BCH_STATUS0 The BCH STAT provides overall status of the hardware ECC accelerator 0x010 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 COMPLETED_CE 1 7 1 6 1 5 1 4 1 3 1 2 STATUS_BLK0 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 CORRECTED 0 2 UNCORRECTABLE 0 1 0 0 ALLONES HANDLE RSVD1 Table 15-7. HW_BCH_STATUS0 Bit Field Descriptions BITS 31:20 HANDLE LABEL RW RESET RO 0x0 DEFINITION Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction. That handle passes down the pipeline and ends up here at the time the BCH interrupt is signaled. This is the chip enable number corresponding to the NAND device from which this data came. Count of symbols in error during processing of first block of flash (metadata block). The number of errors reported will be in the range of 0 to the ECC correction level for block 0. ZERO = 0x00 No errors found on block. ERROR1 = 0x01 One error found on block. ERROR2 = 0x02 One errors found on block. ERROR3 = 0x03 One errors found on block. ERROR4 = 0x04 One errors found on block. UNCORRECTABLE = 0xFE Block exhibited uncorrectable errors. ERASED = 0xFF Page is erased. 19:16 COMPLETED_CE 15:8 RO 0x0 RO 0x0 STATUS_BLK0 7:5 4 RSVD1 ALLONES RO 0x0 RO 0x1 Reserved, always set these bits to zero. 1 = All data bits of this transaction are ONE. i.MX23 Applications Processor Reference Manual, Rev. 1 15-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSVD0 20-BIT Correcting ECC Accelerator (BCH) Table 15-7. HW_BCH_STATUS0 Bit Field Descriptions BITS LABEL 3 CORRECTED 2 1:0 RW RESET RO 0x0 RO 0x0 RO 0x0 UNCORRECTABLE RSVD0 DEFINITION 1 = At least one correctable error encountered during last processing cycle. 1 = Uncorrectable error encountered during last processing cycle. Reserved, always set these bits to zero. DESCRIPTION: The BCH STAT register provides visibility into the run-time status of the BCH and status information when processing is complete. 15.6.3 Hardware BCH ECC Accelerator Mode Register Description HW_BCH_MODE Table 15-8. HW_BCH_MODE The BCH MODE register provides additional mode controls. 0x020 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ERASE_THRESHOLD 0 3 0 2 0 1 0 0 Table 15-9. HW_BCH_MODE Bit Field Descriptions BITS LABEL 31:8 RSVD ERASE_THRESHOLD 7:0 RW RESET RO 0x0 RW 0x00 DEFINITION Reserved, always set these bits to zero. This value indicates the maximum number of zero bits on a flash block for it to be considered erased. For SLC NAND devices, this value should be programmed to 0 (meaning that the entire block should consist of bytes of 0xFF. For MLC NAND devices, bit errors may occur on reads (even on blank block), so this threshold can be used to tune the erased block checking algorithm. DESCRIPTION: Contains additional global mode controls for the BCH engine. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-29 RSVD 20-BIT Correcting ECC Accelerator (BCH) 15.6.4 Hardware BCH ECC Loopback Encode Buffer Register Description When performing memory to memory operations, indicates the address of the encode buffer. This register should be programmed before writing a 1 to the M2M_ENABLE bit in the CTRL register. This value must be aligned on a 4-byte boundary. HW_BCH_ENCODEPTR Table 15-10. HW_BCH_ENCODEPTR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x030 ADDR Table 15-11. HW_BCH_ENCODEPTR Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x00000000 DEFINITION Address pointer to encode buffer. This is the source for decode operations and the destination for encode operations. DESCRIPTION: For memory to memory operations, this register is used as the pointer to the encoded data, which is an output when encoding and an input while decoding. 15.6.5 Hardware BCH ECC Loopback Data Buffer Register Description HW_BCH_DATAPTR Table 15-12. HW_BCH_DATAPTR When performing memory to memory operations, indicates the address of the data buffer. 0x040 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ADDR Table 15-13. HW_BCH_DATAPTR Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x00000000 DEFINITION Address pointer to data buffer. This is the source for encode operations and the destination for decode operations. This register should be programmed before writing a 1 to the M2M_ENABLE bit in the CTRL register. This value must be aligned on a 4-byte boundary. DESCRIPTION: For memory to memory operations, this register is used as the pointer to the data to encode or the destination buffer for decode operations. i.MX23 Applications Processor Reference Manual, Rev. 1 15-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) 15.6.6 Hardware BCH ECC Loopback Metadata Buffer Register Description HW_BCH_METAPTR Table 15-14. HW_BCH_METAPTR When performing memory to memory operations, indicates the address of the metadata buffer. 0x050 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ADDR Table 15-15. HW_BCH_METAPTR Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x00000000 DEFINITION Address pointer to metadata buffer. This is the source for encode metadata read operations and the destination for metadata decode operations. This register should be programmed before writing a 1 to the M2M_ENABLE bit in the CTRL register. This value must be aligned on a 4-byte boundary. DESCRIPTION: For memory to memory operations, this register is used as the pointer to the metadata to encode or the extracted metadata for decode operations. 15.6.7 Hardware BCH ECC Accelerator Layout Select Register Description HW_BCH_LAYOUTSELECT 0x070 The BCH LAYOUTSELECT register provides a mapping of chip selects to layout registers. Table 15-16. HW_BCH_LAYOUTSELECT 3 1 CS15_SELECT 3 0 2 9 CS14_SELECT 2 8 2 7 CS13_SELECT 2 6 2 5 CS12_SELECT 2 4 2 3 CS11_SELECT 2 2 2 1 CS10_SELECT 2 0 1 9 CS9_SELECT 1 8 1 7 CS8_SELECT 1 6 1 5 CS7_SELECT 1 4 1 3 CS6_SELECT 1 2 1 1 CS5_SELECT 1 0 0 9 CS4_SELECT 0 8 0 7 CS3_SELECT 0 6 0 5 CS2_SELECT 0 4 0 3 CS1_SELECT 0 2 0 1 CS0_SELECT 0 0 Table 15-17. HW_BCH_LAYOUTSELECT Bit Field Descriptions BITS 31:30 29:28 27:26 25:24 23:22 21:20 19:18 LABEL CS15_SELECT CS14_SELECT CS13_SELECT CS12_SELECT CS11_SELECT CS10_SELECT CS9_SELECT RW RW RW RW RW RW RW RW RESET 0x3 0x2 0x1 0x0 0x3 0x2 0x1 DEFINITION Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip select 15. select 14. select 13. select 12. select 11. select 10. select 9. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-31 20-BIT Correcting ECC Accelerator (BCH) Table 15-17. HW_BCH_LAYOUTSELECT Bit Field Descriptions BITS 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 LABEL CS8_SELECT CS7_SELECT CS6_SELECT CS5_SELECT CS4_SELECT CS3_SELECT CS2_SELECT CS1_SELECT CS0_SELECT RW RW RW RW RW RW RW RW RW RW RESET 0x0 0x3 0x2 0x1 0x0 0x3 0x2 0x1 0x0 DEFINITION Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip Selects which layout is used for chip select 8. select 7. select 6. select 5. select 4. select 3. select 2. select 1. select 0. DESCRIPTION: When the BCH engine receives a request to process a data block from the GPMI interface, it will use this register to map the incoming chip select to one of the four possible flash layout registers 15.6.8 Hardware BCH ECC Flash 0 Layout 0 Register Description The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjuction with the FLASH0LAYOUT1 register to control the format for the devices selecting layout 0 in the LAYOUTSELECT register. HW_BCH_FLASH0LAYOUT0 0x080 Table 15-18. HW_BCH_FLASH0LAYOUT0 3 1 3 0 2 9 2 8 NBLOCKS 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 META_SIZE 1 9 1 8 1 7 1 6 1 5 1 4 ECC0 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DATA0_SIZE 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 15-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) Table 15-19. HW_BCH_FLASH0LAYOUT0 Bit Field Descriptions BITS LABEL 31:24 NBLOCKS RW RESET RW 0x07 DEFINITION Number of subsequent blocks on the flash page (excluding the data0 block). A value of 0 indicates that only the DATA0 block is present and a value of 8 indicates that 8 subsequent blocks are present for a total of 9 blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by the hardware. Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design support from 0 to 255 bytes for metadata -- if set to zero, no metadata will be stored. Metadata is stored before the associated data in block 0. If the DATA0_SIZE field is programmed to a zero, then metadata effectively be stored with its own parity. When both the metadata and data0 fields are programmed with non-zero values, the first block will contain both portions of data and will be covered by a single parity block. Indicates the ECC level for the first block on the flash page. The first block covers metadata plus the associated data from the DATA0_SIZE field. NONE = 0x0 No ECC to be performed ECC2 = 0x1 ECC 2 to be performed ECC4 = 0x2 ECC 4 to be performed ECC6 = 0x3 ECC 6 to be performed ECC8 = 0x4 ECC 8 to be performed ECC10 = 0x5 ECC 10 to be performed ECC12 = 0x6 ECC 12 to be performed ECC14 = 0x7 ECC 14 to be performed ECC16 = 0x8 ECC 16 to be performed ECC18 = 0x9 ECC 18 to be performed ECC20 = 0xA ECC 20 to be performed 23:16 META_SIZE RW 0x0A 15:12 ECC0 RW 0x8 11:0 DATA0_SIZE RW 0x200 Indicates the size of the data 0 block (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. If set to zero, the first block will only contain metadata. DESCRIPTION: Each pair of layout registers describes one of four supported flash configurations. Software should program the LAYOUTSELECT register for each supported GPMI chip select to select from one of the fourlayout values. Each pair of registers contains settings that are used by the BCH block while reading/writing the flash page to control data, metadata, and flash page sizes as well as the ECC correction level. The first block written to flash can be programmed to have different ECC, metadata, and data sizes from subsequent data blocks on the device. In addition, the number of blocks stored on a page of flash is not fixed, but instead is determined by the number of bytes consumed by the initial (block 0) and subsequent data blocks. See the BCH programming reference manual for more information on setting up the flash layout registers. EXAMPLE: HW_BCH_FLASH0LAYOUT0_WR(0x020C8000); HW_BCH_FLASH0LAYOUT1_WR(0x04408200); i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-33 20-BIT Correcting ECC Accelerator (BCH) 15.6.9 Hardware BCH ECC Flash 0 Layout 1 Register Description The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjuction with the FLASH0LAYOUT0 register to control the format for the device on chip select 0. HW_BCH_FLASH0LAYOUT1 0x090 Table 15-20. HW_BCH_FLASH0LAYOUT1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 PAGE_SIZE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 ECCN 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DATAN_SIZE 0 5 0 4 0 3 0 2 0 1 0 0 Table 15-21. HW_BCH_FLASH0LAYOUT1 Bit Field Descriptions BITS LABEL 31:16 PAGE_SIZE RW RESET RW 0x10DA DEFINITION Indicates the total size of the flash page (in bytes). This should be set to the page size including spare area. The page size is programmable to accomodate different flash configurations that may be available in the future. Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n). Subsequent blocks only contain data (no metadata). NONE = 0x0 No ECC to be performed ECC2 = 0x1 ECC 2 to be performed ECC4 = 0x2 ECC 4 to be performed ECC6 = 0x3 ECC 6 to be performed ECC8 = 0x4 ECC 8 to be performed ECC10 = 0x5 ECC 10 to be performed ECC12 = 0x6 ECC 12 to be performed ECC14 = 0x7 ECC 14 to be performed ECC16 = 0x8 ECC 16 to be performed ECC18 = 0x9 ECC 18 to be performed ECC20 = 0xA ECC 20 to be performed 15:12 ECCN RW 0x8 11:0 DATAN_SIZE RW 0x200 Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. The size of subsequent data blocks does not have to match the data size for block 0, which is important when metadata is stored separately or for balancing the amount of data stored in each block. EXAMPLE: HW_BCH_FLASH0LAYOUT0_WR(0x020C8000); HW_BCH_FLASH0LAYOUT1_WR(0x04408200); 15.6.10 Hardware BCH ECC Flash 1 Layout 0 Register Description The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjuction with the FLASH0LAYOUT1 register to control the format for the devices selecting layout 0 in the LAYOUTSELECT register. i.MX23 Applications Processor Reference Manual, Rev. 1 15-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) HW_BCH_FLASH1LAYOUT0 0x0a0 Table 15-22. HW_BCH_FLASH1LAYOUT0 3 1 3 0 2 9 2 8 NBLOCKS 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 META_SIZE 1 9 1 8 1 7 1 6 1 5 1 4 ECC0 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DATA0_SIZE 0 5 0 4 0 3 0 2 0 1 0 0 Table 15-23. HW_BCH_FLASH1LAYOUT0 Bit Field Descriptions BITS LABEL 31:24 NBLOCKS RW RESET RW 0x07 DEFINITION Number of subsequent blocks on the flash page (excluding the data0 block). A value of 0 indicates that only the DATA0 block is present and a value of 8 indicates that 8 subsequent blocks are present for a total of 9 blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by the hardware. Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design support from 0 to 255 bytes for metadata -- if set to zero, no metadata will be stored. Metadata is stored before the associated data in block 0. If the DATA0_SIZE field is programmed to a zero, then metadata will effectively be stored with its own parity. When both the metadata and data0 fields are programmed with non-zero values, the first block will contain both portions of data and will be covered by a single parity block. Indicates the ECC level for the first block on the flash page. The first block covers metadata plus the associated data from the DATA0_SIZE field. NONE = 0x0 No ECC to be performed ECC2 = 0x1 ECC 2 to be performed ECC4 = 0x2 ECC 4 to be performed ECC6 = 0x3 ECC 6 to be performed ECC8 = 0x4 ECC 8 to be performed ECC10 = 0x5 ECC 10 to be performed ECC12 = 0x6 ECC 12 to be performed ECC14 = 0x7 ECC 14 to be performed ECC16 = 0x8 ECC 16 to be performed ECC18 = 0x9 ECC 18 to be performed ECC20 = 0xA ECC 20 to be performed 23:16 META_SIZE RW 0x0A 15:12 ECC0 RW 0x8 11:0 DATA0_SIZE RW 0x200 Indicates the size of the data 0 block (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. If set to zero, the first block will only contain metadata. DESCRIPTION: Each pair of layout registers describes one of four supported flash configurations. Software should program the LAYOUTSELECT register for each supported GPMI chip select to select from one of the fourlayout values. Each pair of registers contains settings that are used by the BCH block while reading/writing the flash page to control data, metadata, and flash page sizes as well as the ECC correction i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-35 20-BIT Correcting ECC Accelerator (BCH) level. The first block written to flash can be programmed to have different ECC, metadata, and data sizes from subsequent data blocks on the device. In addition, the number of blocks stored on a page of flash is not fixed, but instead is determined by the number of bytes consumed by the initial (block 0) and subsequent data blocks. See the BCH programming reference manual for more information on setting up the flash layout registers. EXAMPLE: HW_BCH_FLASH1LAYOUT0_WR(0x020C8000); HW_BCH_FLASH1LAYOUT1_WR(0x04408200); 15.6.11 Hardware BCH ECC Flash 1 Layout 1 Register Description The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjuction with the FLASH0LAYOUT0 register to control the format for the device on chip select 0. HW_BCH_FLASH1LAYOUT1 0x0b0 Table 15-24. HW_BCH_FLASH1LAYOUT1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 PAGE_SIZE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 ECCN 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DATAN_SIZE 0 5 0 4 0 3 0 2 0 1 0 0 Table 15-25. HW_BCH_FLASH1LAYOUT1 Bit Field Descriptions BITS LABEL 31:16 PAGE_SIZE RW RESET RW 0x10DA DEFINITION Indicates the total size of the flash page (in bytes). This should be set to the page size including spare area. The page size is programmable to accomodate different flash configurations that may be available in the future. i.MX23 Applications Processor Reference Manual, Rev. 1 15-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) Table 15-25. HW_BCH_FLASH1LAYOUT1 Bit Field Descriptions BITS 15:12 ECCN LABEL RW RESET RW 0x8 DEFINITION Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n). Subsequent blocks only contain data (no metadata). NONE = 0x0 No ECC to be performed ECC2 = 0x1 ECC 2 to be performed ECC4 = 0x2 ECC 4 to be performed ECC6 = 0x3 ECC 6 to be performed ECC8 = 0x4 ECC 8 to be performed ECC10 = 0x5 ECC 10 to be performed ECC12 = 0x6 ECC 12 to be performed ECC14 = 0x7 ECC 14 to be performed ECC16 = 0x8 ECC 16 to be performed ECC18 = 0x9 ECC 18 to be performed ECC20 = 0xA ECC 20 to be performed 11:0 DATAN_SIZE RW 0x200 Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. The size of subsequent data blocks does not have to match the data size for block 0, which is important when metadata is stored separately or for balancing the amount of data stored in each block. EXAMPLE: HW_BCH_FLASH1LAYOUT0_WR(0x020C8000); HW_BCH_FLASH1LAYOUT1_WR(0x04408200); 15.6.12 Hardware BCH ECC Flash 2 Layout 0 Register Description The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjuction with the FLASH0LAYOUT1 register to control the format for the devices selecting layout 0 in the LAYOUTSELECT register. HW_BCH_FLASH2LAYOUT0 0x0c0 Table 15-26. HW_BCH_FLASH2LAYOUT0 3 1 3 0 2 9 2 8 NBLOCKS 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 META_SIZE 1 9 1 8 1 7 1 6 1 5 1 4 ECC0 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DATA0_SIZE 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-37 20-BIT Correcting ECC Accelerator (BCH) Table 15-27. HW_BCH_FLASH2LAYOUT0 Bit Field Descriptions BITS LABEL 31:24 NBLOCKS RW RESET RW 0x07 DEFINITION Number of subsequent blocks on the flash page (excluding the data0 block). A value of 0 indicates that only the DATA0 block is present and a value of 8 indicates that 8 subsequent blocks are present for a total of 9 blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by the hardware. Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design support from 0 to 255 bytes for metadata -- if set to zero, no metadata will be stored. Metadata is stored before the associated data in block 0. If the DATA0_SIZE field is programmed to a zero, then metadata effectively be stored with its own parity. When both the metadata and data0 fields are programmed with non-zero values, the first block will contain both portions of data and will be covered by a single parity block. Indicates the ECC level for the first block on the flash page. The first block covers metadata plus the associated data from the DATA0_SIZE field. NONE = 0x0 No ECC to be performed ECC2 = 0x1 ECC 2 to be performed ECC4 = 0x2 ECC 4 to be performed ECC6 = 0x3 ECC 6 to be performed ECC8 = 0x4 ECC 8 to be performed ECC10 = 0x5 ECC 10 to be performed ECC12 = 0x6 ECC 12 to be performed ECC14 = 0x7 ECC 14 to be performed ECC16 = 0x8 ECC 16 to be performed ECC18 = 0x9 ECC 18 to be performed ECC20 = 0xA ECC 20 to be performed 23:16 META_SIZE RW 0x0A 15:12 ECC0 RW 0x8 11:0 DATA0_SIZE RW 0x200 Indicates the size of the data 0 block (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. If set to zero, the first block will only contain metadata. DESCRIPTION: Each pair of layout registers describes one of four supported flash configurations. Software should program the LAYOUTSELECT register for each supported GPMI chip select to select from one of the fourlayout values. Each pair of registers contains settings that are used by the BCH block while reading/writing the flash page to control data, metadata, and flash page sizes as well as the ECC correction level. The first block written to flash can be programmed to have different ECC, metadata, and data sizes from subsequent data blocks on the device. In addition, the number of blocks stored on a page of flash is not fixed, but instead is determined by the number of bytes consumed by the initial (block 0) and subsequent data blocks. See the BCH programming reference manual for more information on setting up the flash layout registers. EXAMPLE: HW_BCH_FLASH2LAYOUT0_WR(0x020C8000); HW_BCH_FLASH2LAYOUT1_WR(0x04408200); i.MX23 Applications Processor Reference Manual, Rev. 1 15-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) 15.6.13 Hardware BCH ECC Flash 2 Layout 1 Register Description The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjuction with the FLASH0LAYOUT0 register to control the format for the device on chip select 0. HW_BCH_FLASH2LAYOUT1 0x0d0 Table 15-28. HW_BCH_FLASH2LAYOUT1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 PAGE_SIZE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 ECCN 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DATAN_SIZE 0 5 0 4 0 3 0 2 0 1 0 0 Table 15-29. HW_BCH_FLASH2LAYOUT1 Bit Field Descriptions BITS LABEL 31:16 PAGE_SIZE RW RESET RW 0x10DA DEFINITION Indicates the total size of the flash page (in bytes). This should be set to the page size including spare area. The page size is programmable to accomodate different flash configurations that may be available in the future. Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n). Subsequent blocks only contain data (no metadata). NONE = 0x0 No ECC to be performed ECC2 = 0x1 ECC 2 to be performed ECC4 = 0x2 ECC 4 to be performed ECC6 = 0x3 ECC 6 to be performed ECC8 = 0x4 ECC 8 to be performed ECC10 = 0x5 ECC 10 to be performed ECC12 = 0x6 ECC 12 to be performed ECC14 = 0x7 ECC 14 to be performed ECC16 = 0x8 ECC 16 to be performed ECC18 = 0x9 ECC 18 to be performed ECC20 = 0xA ECC 20 to be performed 15:12 ECCN RW 0x8 11:0 DATAN_SIZE RW 0x200 Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. The size of subsequent data blocks does not have to match the data size for block 0, which is important when metadata is stored separately or for balancing the amount of data stored in each block. EXAMPLE: HW_BCH_FLASH2LAYOUT0_WR(0x020C8000); HW_BCH_FLASH2LAYOUT1_WR(0x04408200); 15.6.14 Hardware BCH ECC Flash 3 Layout 0 Register Description The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjuction with the FLASH0LAYOUT1 register to control the format for the devices selecting layout 0 in the LAYOUTSELECT register. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-39 20-BIT Correcting ECC Accelerator (BCH) HW_BCH_FLASH3LAYOUT0 0x0e0 Table 15-30. HW_BCH_FLASH3LAYOUT0 3 1 3 0 2 9 2 8 NBLOCKS 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 META_SIZE 1 9 1 8 1 7 1 6 1 5 1 4 ECC0 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DATA0_SIZE 0 5 0 4 0 3 0 2 0 1 0 0 Table 15-31. HW_BCH_FLASH3LAYOUT0 Bit Field Descriptions BITS LABEL 31:24 NBLOCKS RW RESET RW 0x07 DEFINITION Number of subsequent blocks on the flash page (excluding the data0 block). A value of 0 indicates that only the DATA0 block is present and a value of 8 indicates that 8 subsequent blocks are present for a total of 9 blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by the hardware. Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design support from 0 to 255 bytes for metadata -- if set to zero, no metadata will be stored. Metadata is stored before the associated data in block 0. If the DATA0_SIZE field is programmed to a zero, then metadata effectively be stored with its own parity. When both the metadata and data0 fields are programmed with non-zero values, the first block will contain both portions of data and will be covered by a single parity block. Indicates the ECC level for the first block on the flash page. The first block covers metadata plus the associated data from the DATA0_SIZE field. NONE = 0x0 No ECC to be performed ECC2 = 0x1 ECC 2 to be performed ECC4 = 0x2 ECC 4 to be performed ECC6 = 0x3 ECC 6 to be performed ECC8 = 0x4 ECC 8 to be performed ECC10 = 0x5 ECC 10 to be performed ECC12 = 0x6 ECC 12 to be performed ECC14 = 0x7 ECC 14 to be performed ECC16 = 0x8 ECC 16 to be performed ECC18 = 0x9 ECC 18 to be performed ECC20 = 0xA ECC 20 to be performed 23:16 META_SIZE RW 0x0A 15:12 ECC0 RW 0x8 11:0 DATA0_SIZE RW 0x200 Indicates the size of the data 0 block (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. If set to zero, the first block will only contain metadata. DESCRIPTION: Each pair of layout registers describes one of four supported flash configurations. Software should program the LAYOUTSELECT register for each supported GPMI chip select to select from one of the fourlayout values. Each pair of registers contains settings that are used by the BCH block while reading/writing the flash page to control data, metadata, and flash page sizes as well as the ECC correction i.MX23 Applications Processor Reference Manual, Rev. 1 15-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) level. The first block written to flash can be programmed to have different ECC, metadata, and data sizes from subsequent data blocks on the device. In addition, the number of blocks stored on a page of flash is not fixed, but instead is determined by the number of bytes consumed by the initial (block 0) and subsequent data blocks. See the BCH programming reference manual for more information on setting up the flash layout registers. EXAMPLE: HW_BCH_FLASH3LAYOUT0_WR(0x020C8000); HW_BCH_FLASH3LAYOUT1_WR(0x04408200); 15.6.15 Hardware BCH ECC Flash 3 Layout 1 Register Description The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjuction with the FLASH0LAYOUT0 register to control the format for the device on chip select 0. HW_BCH_FLASH3LAYOUT1 0x0f0 Table 15-32. HW_BCH_FLASH3LAYOUT1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 PAGE_SIZE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 ECCN 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DATAN_SIZE 0 5 0 4 0 3 0 2 0 1 0 0 Table 15-33. HW_BCH_FLASH3LAYOUT1 Bit Field Descriptions BITS LABEL 31:16 PAGE_SIZE RW RESET RW 0x10DA DEFINITION Indicates the total size of the flash page (in bytes). This should be set to the page size including spare area. The page size is programmable to accomodate different flash configurations that may be available in the future. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-41 20-BIT Correcting ECC Accelerator (BCH) Table 15-33. HW_BCH_FLASH3LAYOUT1 Bit Field Descriptions BITS 15:12 ECCN LABEL RW RESET RW 0x8 DEFINITION Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n). Subsequent blocks only contain data (no metadata). NONE = 0x0 No ECC to be performed ECC2 = 0x1 ECC 2 to be performed ECC4 = 0x2 ECC 4 to be performed ECC6 = 0x3 ECC 6 to be performed ECC8 = 0x4 ECC 8 to be performed ECC10 = 0x5 ECC 10 to be performed ECC12 = 0x6 ECC 12 to be performed ECC14 = 0x7 ECC 14 to be performed ECC16 = 0x8 ECC 16 to be performed ECC18 = 0x9 ECC 18 to be performed ECC20 = 0xA ECC 20 to be performed 11:0 DATAN_SIZE RW 0x200 Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. The size of subsequent data blocks does not have to match the data size for block 0, which is important when metadata is stored separately or for balancing the amount of data stored in each block. EXAMPLE: HW_BCH_FLASH3LAYOUT0_WR(0x020C8000); HW_BCH_FLASH3LAYOUT1_WR(0x04408200); 15.6.16 Hardware BCH ECC Debug Register0 Description The hardware BCH accelerator internal state machines and signals can be seen in the ECC debug register. HW_BCH_DEBUG0 HW_BCH_DEBUG0_SET HW_BCH_DEBUG0_CLR HW_BCH_DEBUG0_TOG Table 15-34. HW_BCH_DEBUG0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 KES_DEBUG_SYNDROME_SYMBOL 0x100 0x104 0x108 0x10C 1 9 1 8 1 7 1 6 1 5 1 4 KES_DEBUG_PAYLOAD_FLAG 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 KES_DEBUG_SHIFT_SYND BM_KES_TEST_BYPASS ROM_BIST_COMPLETE KES_DEBUG_MODE4K i.MX23 Applications Processor Reference Manual, Rev. 1 15-42 Preliminary--Subject to Change Without Notice Freescale Semiconductor DEBUG_REG_SELECT KES_DEBUG_STALL ROM_BIST_ENABLE KES_STANDALONE KES_DEBUG_STEP KES_DEBUG_KICK RSVD1 RSVD0 20-BIT Correcting ECC Accelerator (BCH) Table 15-35. HW_BCH_DEBUG0 Bit Field Descriptions BITS LABEL 31:27 RSVD1 ROM_BIST_ENABLE 26 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved, always set these bits to zero. Software may initiate a ROM BIST operation by toggling this bit from a zero to a one. When the operation is complete, the ROM_BIST_COMPLETE bit will be set and the ROM's CRC value will be available in the DEBUG data register. This bit will be set after a BIST operation completes, at which time the ROM CRC is available in the DBGKESREAD register. The CRC value will be cleared after the BIST_ENABLE bit is cleared. The 9 bit value in this bit field will be shifted into the syndrome register array at the input of the KES engine whenever HW_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled. NORMAL = 0x0 Bus master address generator for synd_gen writes operates normally. TEST_MODE = 0x1 Bus master address generator always addresses last four bytes in Auxilliary block. 25 ROM_BIST_COMPLETE RW 0x0 24:16 KES_DEBUG_SYNDROME_S RW 0x0 YMBOL 15 KES_DEBUG_SHIFT_SYND RW 0x0 14 KES_DEBUG_PAYLOAD_FLA RW 0x0 G Toggling this bit causes the value in HW_BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine. After shifting in 16 symbols, one can kick off both KES and CF cycles by toggling HW_BCH_DEBUG0_KES_DEBUG_KICK. Be sure to set KES_BCH_DEBUG0_KES_STANDALONE mode to 1 before kicking. When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input payload flag. DATA = 0x1 Payload is set for 512 byte data block. AUX = 0x1 Payload is set for 65 or 19 byte auxilliary block. 13 KES_DEBUG_MODE4K RW 0x0 When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages). 4k = 0x1 Mode is set for 4K NAND pages. 2k = 0x1 Mode is set for 2K NAND pages. 12 KES_DEBUG_KICK RW 0x0 11 KES_STANDALONE RW 0x0 Toggling causes KES engine FSM to start as if kicked by the Bus Master. This allows stand alone testing of the KES and Chien Search engines. Be sure to set KES_BCH_DEBUG0_KES_STANDALONE mode to 1 before kicking. Set to one to cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and to suppress toggling the CF_BM_DONE signal by the CF engine. NORMAL = 0x0 Bus master address generator for synd_gen writes operates normally. TEST_MODE = 0x1 Bus master address generator always addresses last four bytes in Auxilliary block. 10 KES_DEBUG_STEP RW 0x0 Toggling this bit causes the KES FSM to skip past the stall state if it is in DEBUG_STALL mode and it has completed processing a block. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-43 20-BIT Correcting ECC Accelerator (BCH) Table 15-35. HW_BCH_DEBUG0 Bit Field Descriptions BITS LABEL 9 KES_DEBUG_STALL RW RESET RW 0x0 DEFINITION Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete. This allows a diagnostic to stall the FSM after each block's key equations are solved. This also has the effect of stalling the CSFE search engine so it's state can be examined after it finishes processing the KES stalled block. NORMAL = 0x0 KES FSM proceeds to next block supplied by bus master. WAIT = 0x1 KES FSM waits after current equations are solved and the search engine is started. 8 BM_KES_TEST_BYPASS RW 0x0 1 = Point all synd_gen writes to dummy area at the end of the AUXILIARY block. With this data diagnostics can preload all payload, parity bytes and computed syndrome bytes for testing the KES engine. NORMAL = 0x0 Bus master address generator for synd_gen writes operates normally. TEST_MODE = 0x1 Bus master address generator always addresses last four bytes in Auxilliary block. 7:6 5:0 RSVD0 DEBUG_REG_SELECT RO 0x0 RW 0x0 Reserved, always set these bits to zero. The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine. DESCRIPTION: The HW_BCH_DEBUG0 register provides access to various internal state information which might prove useful during hardware debug and validation. EXAMPLE: // perform BIST operation HW_BCH_DEBUG0_SET(BM_BCH_DEBUG0_ROM_BIST_ENABLE); // enable BIST operation // poll until BIST_DONE while( (HW_BCH_DEBUG0_RD() & BM_BCH_DEBUG0_ROM_BIST_COMPLETE) == 0 ); i=HW_BCH_DBGKESREAD(); if(HW_BCH_DBGKESREAD_RD() != 0x7AA3792F) { // BIST FAILED err++; } HW_BCH_DEBUG0_CLR(BM_BCH_DEBUG0_ROM_BIST_ENABLE | BM_BCH_DEBUG0_ROM_BIST_COMPLETE); // clear bist status 15.6.17 Hardware BCH ECC KES Debug Read Register Description The hardware ECC 8 accelerator key equation solver internal state machines and signals can be seen in the ECC debug registers. HW_BCH_DBGKESREAD Table 15-36. HW_BCH_DBGKESREAD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x110 VALUES i.MX23 Applications Processor Reference Manual, Rev. 1 15-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) Table 15-37. HW_BCH_DBGKESREAD Bit Field Descriptions BITS 31:0 VALUES LABEL RW RESET RO 0x0 DEFINITION This register will return the ROM BIST CRC value after a BIST test. 15.6.18 Hardware BCH ECC Chien Search Debug Read Register Description The hardware ECC 8 accelerator Chien Search internal state machines and signals can be seen in the ECC debug registers. HW_BCH_DBGCSFEREAD 0x120 Table 15-38. HW_BCH_DBGCSFEREAD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUES Table 15-39. HW_BCH_DBGCSFEREAD Bit Field Descriptions BITS 31:0 VALUES LABEL RW RESET RO 0x0 DEFINITION Reserved 15.6.19 Hardware BCH ECC Syndrome Generator Debug Read Register Description The hardware ECC 8 accelerator syndrome generator internal state machines and signals can be seen in the ECC debug registers. HW_BCH_DBGSYNDGENREAD 0x130 Table 15-40. HW_BCH_DBGSYNDGENREAD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUES Table 15-41. HW_BCH_DBGSYNDGENREAD Bit Field Descriptions BITS 31:0 VALUES LABEL RW RESET RO 0x0 DEFINITION Reserved 15.6.20 Hardware BCH ECC AXI Master Debug Read Register Description The hardware BCH ECC 8 AXI bus master internal state machines and signals can be seen in the ECC debug registers. HW_BCH_DBGAHBMREAD 0x140 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-45 20-BIT Correcting ECC Accelerator (BCH) Table 15-42. HW_BCH_DBGAHBMREAD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUES Table 15-43. HW_BCH_DBGAHBMREAD Bit Field Descriptions BITS 31:0 VALUES LABEL RW RESET RO 0x0 DEFINITION Reserved 15.6.21 Hardware BCH ECC Block Name Register Description Read only view of the block name string BCH. HW_BCH_BLOCKNAME Table 15-44. HW_BCH_BLOCKNAME 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x150 NAME Table 15-45. HW_BCH_BLOCKNAME Bit Field Descriptions BITS 31:0 NAME LABEL RW RESET RO 0x20484342 DEFINITION Should be the ascii characters "BCH " (0x20, H, C, B). DESCRIPTION: Fixed pattern read only value for test puposes. Can be read as an ASCII string with the zero termination coming from the first byte of the BLOCKVERSION register. EXAMPLE: char *cp = ((char *)HW_BCH_BLOCKNAME_ADDR); reads back "BCH ". 15.6.22 Hardware BCH ECC Version Register Description This register always returns a known read value for debug purposes. The read value indicates the version of the block. HW_BCH_VERSION 0x160 i.MX23 Applications Processor Reference Manual, Rev. 1 15-46 Preliminary--Subject to Change Without Notice Freescale Semiconductor 20-BIT Correcting ECC Accelerator (BCH) Table 15-46. HW_BCH_VERSION 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 15-47. HW_BCH_VERSION Bit Field Descriptions BITS 31:24 MAJOR 23:16 MINOR 15:0 LABEL RW RESET RO 0x01 RO 0x0 RO 0x0000 STEP DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_BCH_VERSION.B.MAJOR != 1) Error(); BCH Block v1.0, Revision 2.5 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15-47 20-BIT Correcting ECC Accelerator (BCH) i.MX23 Applications Processor Reference Manual, Rev. 1 15-48 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 16 Data Co-Processor (DCP) This chapter describes the data co-processor (DCP) block included on the i.MX23 and how to use it. It includes sections on memory copy functionality, Advanced Encryption Standard (AES), hashing, color-space conversion, and arbitration. Sections on programming channel operations and the color-space converter are also provided, along with example code. Programmable registers are described in Section 16.3, "Programmable Registers." 16.1 Overview AXI Bus Master Hash Dual-Port FIFO Control Cipher APBH Slave Figure 16-1. Data Co-Processor (DCP) Block Diagram The DCP module provides support for general encryption and hashing functions typically used for security functions. Because its basic job is moving data from memory to memory, it also incorporates memory-copy (memcopy) function for both debugging and as a more efficient method of copying data between memory blocks than the DMA-based approach. The memcopy function also has a "blit" mode of operation where it can transfer a rectangular block of data to a video frame buffer. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-1 Data Co-Processor (DCP) The DCP has been designed to support a wide variety of encryption and hashing algorithms, and the control structures have been designed to allow flexibility in adding additional algorithms and modes in the future. It supports up to 16 encryption algorithms (for example DES, TDEA, AES-128, etc.) with 16 different modes of operation (ECB, CBC, etc.) as well as 16 hashing algorithms (for example MD5, SHA-1, SHA-2, etc.). While the DCP module has been designed to support numerous algorithms, only a subset may be implemented in any given implementation (see the Capability Register). The DCP module processes data based on chained command structures written to system memory by software (in a manner similar to the DMA engine). The control block maintains registers to support four independent and concurrent chains, allowing software to virtualize access to the DCP block. Each command in a chain represents a work unit that the module will process to completion. At the end of each work unit, the control logic arbitrates among chains with outstanding commands and processes a command from that chain. Arbitration among the channels is round-robin, allowing all active channels equal access to the data engine. Each channel also supports a "high-priority" mode that allows it to have priority over the remaining channels. If multiple channels are selected as high-priority, the channel arbiter selects among the high-priority channels in round-robin fashion. The data flow through the DCP module can be configured in one of five fashions, depending on the functionality activated by the control packet: * Memcopy/Blit Mode--Data is moved unchanged from one memory buffer to another. AHB FIFO AH B * Encryption Only--Data from source buffer is encrypted/decrypted into the destination buffer AHB FIFO Encrypt ion D ecryption FIFO AH B * Hashing Only--Data from source buffer is read, and a hash is generated. AHB Has h * Encryption and Input Hashing--Data from source buffer is encrypted/decrypted into destination, and source buffer is hashed. i.MX23 Applications Processor Reference Manual, Rev. 1 16-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) AHB FIFO Encryption D ecryption FIFO AH B Has h * Encryption and Output Hashing--Data from source buffer is encrypted/decrypted into destination, and output data is hashed. AHB FIFO Encryption D ecryption FIFO AH B H ash 16.1.1 DCP Limitations for Software While the DCP module has been designed to be as flexible as possible, there are a few limitations to which software must adhere: * Buffer sizes for all operations MUST be aligned to the natural size of the transfer algorithm used. Memcopy operations can transfer any number of bytes (one-byte granularity) and AES operations must be multiples of 16 bytes (four-word granularity). For all operations, if the byte count is not a word granularity, the hardware rounds up to the next word. Hashing is supported at a byte granularity. The DCP module supports buffer operations to any byte alignment, but performance will be improved if buffers are aligned to a four-byte boundary, since fetch/store operations can be performed without having to do byte operations to accommodate the misaligned addresses. Hash operations are limited to a 512-Mbyte buffer size. The hardware only implements a 32-bit hash length counter instead of the 64-bit counter supported by the SHA-1 algorithm (counter counts bits, not bytes, therefore a total of 512 Mbytes). For chained hashing operations (operations involving multiple descriptors), every descriptor except the last must have a byte count that is a 16-word multiple (granularity of the hash algorithm). Key values cannot be written while the AES block is active. This limitation exists because the key RAM is in use while AES is operational. Any writes from the APB cannot be held in wait states; therefore, the RAM must be accessible during key writes. The byte-swap controls can only be used with modulo-4 length buffers. For non-modulo-4 lengths, the final partial word will contain incorrect data. Any address alignment can be used with byte swapping, however. * * * * * i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-3 Data Co-Processor (DCP) * The word-swap controls are only useful with cipher operations, because the logic forms the 128-bit cipher data from four words from system memory. The word-swap controls are ignored for memcopy or hashing operations. 16.2 Operation The top-level DCP module contains the AXI master, APB slave bus interface units, the main control block and FIFO, and any encryption or hashing blocks included with the design. The controller manages the fetching of work blocks, the fetching/storing of context information when switching between chain pointers, and the managing of the data flow through the FIFO, SHA, and AES blocks. Data entering the block from the AXI master is placed in the FIFO for consumption by the cipher block. After the cipher module has finished its operation, data is placed back into the FIFO and stored back to memory via the AXI master. When hashing is enabled, the SHA block takes its inputs from the bus side of the FIFO to allow it to operate without waiting for the cipher block to complete. The APB slave provides all register controls and interfaces mainly with the control block. 16.2.1 Memory Copy, Blit, and Fill Functionality In its most basic operation, the DCP supports moving unmodified data from one place in system memory to another. This functionality is referred to as "memcopy", because it operates only on memory and it copies data from one place to another. Typical uses for memcopy might be for fast virtual memory page moves or repositioning data blocks in memory. Memcopy buffers can be aligned to any memory address and can be of any length (byte granularity). For best performance, buffers should be word-aligned, although the DCP includes enhancements to improve performance for unaligned cases. The DCP also has the ability to do basic "blit" operations that are typical in graphics operations. To specify a blit, the control packet must have the ENABLE_BLIT bit set in the packet control register. Blit source buffers must be contiguous. The output destination buffer for a blit operation is defined as a "M runs of N bytes" that define a rectangular region in a frame buffer. For blit operations, each line of the blit may consist of any number of bytes. After performing a "run", the DCP updates the destination pointer such that the next destination address falls on the pixel below the start of the previous run operation. This is done by incrementing the starting pointer by the frame buffer width, which is specified in the Control1 field. In addition to being able to copy data within memory, the DCP also provides a "fill" operation, where source data comes not from another memory location, but from an internal register (the source buffer address in the control packet). This is done whenever the CONSTANT_FILL flag is set in the packet control register. This feature may be used with memcopy to prefill memory with a specified value or during a blit operation to fill a rectangular region with a constant color. i.MX23 Applications Processor Reference Manual, Rev. 1 16-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) 16.2.2 Advanced Encryption Standard (AES) The AES block implements a 128-bit key/data encryption/decryption block as defined by the National Institute of Standards and Technology (NIST) as US FIPS PUB 197, dated November 2001 (see references for specifications and toolkits)1. There are three variations of AES, each corresponding to the key size used: AES-128, AES-192 or AES-256. AES always operates on 128 bits of data at a time. Only the AES-128 algorithm is implemented at this time. 16.2.2.1 Key Storage The DCP implements four SRAM-based keys that may be used by software to securely store keys on a semi-permanent basis. The keys may be written via the PIO interface by specifying a key index to specify which key to load and a subword pointer that indicates which word to write within the key. After a subword is written, the logic automatically increments the subword pointer so that software can program the higher-order words of the key without rewriting the key index. Keys written into the key storage are not readable. To use a key in the key storage, the cipher descriptor packet should select the key by setting the KEY_SELECT field in the Control1 descriptor field without setting the OTP_KEY or PAYLOAD_KEY fields in the Control0 register. 16.2.2.2 OTP Key After a system reset, the OTP controller reads the e-fuse devices and provides OTP key information over a parallel 128-bit interface. The key transfer interface runs on HCLK and provides the key over the serialized otp_data signal. The otp_crypto_key_smpl signal indicates when the key value is valid and causes the control logic to capture the key into the key RAM. To use the OTP key, the descriptor packet should set the OTP_KEY field in the Control1 register. 16.2.2.3 Encryption Modes The most basic form of encryption is the Electronic Code Book (ECB) mode. In this mode, the encryption output is a function only of the key and the plaintext, thus it can be visualized as a giant lookup table. While this provides a great deal of security, there are a few limitations. For instance, if the same plaintext appears more than once in a block of data, the same ciphertext will also appear. This can be very evident if the plaintext contains large blocks of constant data (0s for example) and can be used to formulate attacks against a key. 1. The AES core used in the design was derived from the AES design available from OpenCores.org under a modified BSD license as described here: http://www.opencores.org/projects.cgi/web/aes_core/overview The license for this code is documented on page 56 for compliance. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-5 Data Co-Processor (DCP) In order to make ciphers stronger, several modes of operation can be implemented around the basic ECB cipher to provide additional security. One such mode is CBC mode (Cipher Block Chaining), which takes the previous encrypted data and logically XORs it with the next incoming plaintext before performing the encryption. During decryption, the process is reversed and the previous encrypted data is XORed with the decrypted ECB data to provide the plaintext again. The AES engine supports handling the various modes of operation. The core AES block supports ECB mode, and other algorithms are handled in the wrapper around the encryption blocks. The DCP module supports Cipher Block Chaining (CBC), which chains the data blocks by XORing the previously encrypted data with the plaintext before encryption. Cipher block chaining encryption is illustrated in Figure 16-2. Plaintext Plaintext Plaintext Initialization Vector (IV) Key Block Cipher Encryption Key Block Cipher Encryption Key Block Cipher Encryption Ciphertext Ciphertext Ciphertext Figure 16-2. Cipher Block Chaining (CBC) Mode Encryption Decryption (shown in Figure 16-3) works in a similar manner, where the cipher text is first decrypted and then XORed with the previous ciphertext. For the first encryption/decryption operation, an initialization vector (IV) is used to seed the operation. The IV must be the same for both the encryption and decryption steps; otherwise, decrypted data will not match the original plaintext. i.MX23 Applications Processor Reference Manual, Rev. 1 16-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) Ciphertext Ciphertext Ciphertext Initialization Vector (IV) Key Block Cipher Decryption Key Block Cipher Decryption Key Block Cipher Decryption Plaintext Plaintext Plaintext Figure 16-3. Cipher Block Chaining (CBC) Mode Decryption 16.2.3 Hashing The hashing module implements the SHA-1 hashing algorithm and a modified CRC-32 checksum algorithm. These algorithms produce a signature for a block of data that can be used to determine whether the data is intact. The CRC-32 algorithm implements a 32-bit CRC algorithm similar to the one used by Ethernet and many other protocols. The CRC differs from the Unix cksum() function in three ways: * * * The CRC is initialized as 0xFFFFFFFF instead of 0x00000000. Logic pads zeros to a 32-bit boundary for trailing bytes. Logic does not post-pend the file length. The SHA-1 block implements a 160-bit hashing algorithm that operates on 512-bit (64-byte) blocks as defined by US FIPS PUB 180-1 in 1995. The purpose of the hashing module is to generate a unique signature for a block of data that can be used to validate the integrity of the data by comparing the resulting "digest" with the original digest. Results from hash operations are written to the beginning of the payload for the descriptor. The DCP also has the ability to check the resulting hash against a value in the payload and issue an interrupt if a mismatch occurs. 16.2.4 Managing DCP Channel Arbitration and Performance The DCP can have four channels compete for DCP resources to complete their operations. Depending on the situation, critical operations may need to be prioritized above less important operations to ensure smooth system operation. To help software achieve this goal, the DCP implements a programmable arbi- i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-7 Data Co-Processor (DCP) ter for internal DCP operations and provides "recovery" timers on each channel to throttle channel activity. 16.2.4.1 DCP Arbitration The DCP implements a multi-tiered arbitration policy that allows software a lot of flexibility in scheduling DCP operations. Figure 16-4 illustrates the arbitration levels and where each channel fits into the arbitration scheme. Channels 2 1 1 1 0 High 1 3 1 Priority Level Medium Low 0 0 0 0 Figure 16-4. DCP Arbitration Each channel can be programmed as being in either the high-priority or low-priority arbitration pool, depending on the setting in the HIGH_PRIORITY_CHANNEL field of the HW_DCP_CHANNELCTRL register. When the corresponding bit is programmed as a 1, the channel arbitrates in the high-priority pool; otherwise it arbitrates in the low-priority pool. Once a channel has been selected, it completes one packet and then the arbiter re-arbitrates. The channel that just completed participates in the new arbitration round. Each arbitration pool is arbitrated independently in a round-robin fashion. This ensures that the arbiter is perfectly fair in its distribution of resources. For each arbitration cycle, any pending requests in the high-priority pool are serviced first, followed by requests in the medium and low pools. 16.2.4.2 Channel Recovery Timers Each channel also contains a channel recovery timer in its HW_DCP_CHnOPTS register. The purpose of the recovery timer is to keep the channel inactive for a period of time after it completes an operation. This capability could be used for a high-priority channel to ensure that at least some lower-priority requests get serviced between packets or to simply allow more timeslices for other channels to perform operations. The value programmed into the recovery timers register delays the channel from operations until 16 times i.MX23 Applications Processor Reference Manual, Rev. 1 16-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) the programmed value. Any non-zero value should prevent the channel from participating in the next arbitration cycle. 16.2.5 Programming Channel Operations The control logic block maintains the channel pointers and manages arbitration and context switching between the different channels. It also manages the fetching of work packets and data fetch/store operations from the AXI master interface and coordinates the actions of the hashing and encryption blocks. The control logic maintains four channels that allow software to effectively create four independent work sets for the DCP module. Software can construct chained control packets in memory that describe encryption/hashing/memcopy operations to the hardware unit. The address for this first control packet can be written to one of the four virtual channels and enabled. When one or more of the channels is enabled, the controller fetches the control packet pointed to by that channel and initiate data fetches from the source buffer. Data is then processed as described in the control packet and stored back to system memory. Once the processing for a control packet is complete, the controller writes completion status information back to the control packet, and optionally stores relevant state information to the context buffer. If the control packet specifies a subsequent control packet, the channel's pointer is updated to the address for the next packet and an optional interrupt can be issued to the processor. At this point, the DCP module arbitrates among the virtual channels for the next operation and processes its control packet. If a subsequent operation is continued from a previous operation, the controller automatically loads the context from the previous session into the working registers before resuming operation for that channel. 16.2.5.1 Virtual Channels The DCP module processes data via work packets stored in memory. Each of the channels contains a pointer to the current work packet and enough control logic to determine whether the channel is active and to provide status to the processor. Each channel also provides a recovery timer to help throttle processing by a particular channel. After processing a packet, the channel enables its 16-bit recovery timer (if the recovery time is set to a non-zero value). The channel will not become active again until its recovery timer has expired. The recovery timer timebase is 16 HCLK cycles, so the timer acts as a 20-bit timer with the bottom four bits implicitly tied to 0. This provides an effective range of zero to 220-1 clocks or 0 ns to 7.8 ms at 133 MHz. A channel is activated any time its semaphore is non-zero and its recovery timer is cleared. The semaphore can be incremented by software to indicate that the chain pointer has been loaded with a valid pointer. As the hardware completes the work packets, it decrements the semaphore if the Decrement Semaphore flag in the Control 0 field set. Work packets may be chained together using the CHAIN or CHAIN_CONTIGUOUS bits in the Control0 field, which causes the channel to automatically update the i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-9 Data Co-Processor (DCP) work packet pointer to the value in the NEXT_COMMAND_ADDRESS field at the end of the current work packet. All channels have the same capabilities, but channel 0 is special in that it has a private interrupt line (dcp_vmi_irq). This allows software to use it for VMI (virtual memory) page-copy operations and have a dedicated interrupt vector to reduce latency. All other channels (and the color-space converter) share the other interrupt (dcp_irq). 16.2.5.2 Context Switching The control logic maintains four virtual channels that allow the DCP block to time-multiplex encryption, hashing, and memcopy operations, it must also retain state information when changing channels so that when a channel is resumed, it can resume the operation from where it left off. This process is called context-switching. To minimize the number of registers used in the design, the controller saves context information from each channel into a private context area in system memory. When initializing the DCP module, software must allocate memory for the context buffer and write the address into the Context Buffer Pointer register. As the DCP module processes packets, it saves the context information for each channel to the buffer after completing each control packet. When the channel is subsequently activated, the DCP module's internal registers are then reloaded with the proper context before resuming the operation. Each channel reserves one-fourth the context buffer area for its context storage. The context buffer consumes 160 bytes of system memory and is formatted as shown in Table 16-1. Table 16-1. DCP Context Buffer Layout Range 0x00-0x0C 0x10-0x24 0x28-0x34 0x38-0x4C 0x50-0x5C 0x60-0x74 0x78-0x84 0x88-0x9C 0 1 2 Channel 3 Data Cipher Context Hash Context Cipher Context Hash Context Cipher Context Hash Context Cipher Context Hash Context Size 16 bytes 24 bytes 16 bytes 24 bytes 16 bytes 24 bytes 16 bytes 24 bytes The control logic writes to the context buffer only if the function is being used. This effectively means that the cipher context is stored for CBC encryption/decryption operations only, and the hash context is written only if SHA-1 is utilized. If neither of these modes are used for a given channel, the memory for the context buffer need not be allocated by software. i.MX23 Applications Processor Reference Manual, Rev. 1 16-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) Since channel 0 is likely to be used for VMI in an SDRAM-based system-to-page data from the SDRAM to on-chip SRAM, the buffer allocation table has been organized so that the highest numbered channel uses the lowest area in the context buffer. For this reason, software should allocate the higher numbered channels for encryption/hashing operations and the lower numbered channels for memcopy operations to reduce the size of the context buffer. If only a single channel is used for CBC mode operations or hashing operations, the controller provides a bit in the control register to disable context switching. In this scenario, context switching is not required, because other channels will not corrupt the state of the hashing or cipher modes. Thus, when the channel resumes, a context load is not required. Additionally, the control logic monitors the use of CBC/hashing, so that a context reload is not done if the previous channel resumes an operation without an intermediate operation from another channel. 16.2.5.3 Working with Semaphores Each channel has a semaphore register to indicate that control packets are ready to be processed. Several techniques can be used when programming the semaphores to control the execution of packets within a channel. The channel will continue to execute packets as long as the semaphore is non-zero, a chain bit is set in the descriptor, and no error has occurred. * Software can write the number of pending packets into the semaphore register with the Decrement Semaphore bit in each control packet set. In this scenario, the channel simply decrements the semaphore for each packet set and terminates at the end of the packet chain. The benefit of this method is that software can easily determine how many packets have executed by reading the semaphore status register. Software can create a packet chain with the Decrement Semaphore bit set only in the last packet. In this case, software would write a 1 to the semaphore register to start the chains and the DCP will terminate after executing the last packet. Software can create a packet chain with the Decrement Semaphore bit set for each packet and write either a 1 or a number less than the number of packets to the semaphore register. This can be useful when debugging, because it allows the channel to execute only a portion of the packets and software can inspect intermediate values before restarting the channel again. * * If an error occurs, the channel issues an interrupt and clears the semaphore register. The channel does not perform any further operations until the error bits in the status register have been cleared. Software can manually clear a non-zero semaphore by writing 0xFF to the CLR (clear) address of the semaphore register. 16.2.5.4 Work Packet Structure Work packets for the DCP module are created in memory by the processor. Each work packet includes all information required for the hardware to process the data. The general structure of the packet is shown in Figure 16-5. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-11 Data Co-Processor (DCP) Word 0 Next Cmd Addr Word 1 Word 2 Control 0 Control 1 Word 3 Source Buffer Addr Word 4 Word 5 Destination Buffer Addr Buffer Size Word 6 Payload Pointer Word 7 Status Figure 16-5. DCP Work Packet Structure For some operations, additional information is required to process the data in the packet. This additional information is provided in the variable-sized payload buffer, which can be found at the address specified in the payload pointer field. When encryption is specified, the payload may include the encryption key (if the key selected resides in the packet), an initialization vector (for modes of operation such as CBC), and expected hash values when data hashing is indicated. The hardware can automatically compare the expected hash with the actual hash and interrupt the processor only on a mismatch. The payload area is used by software to store the calculated hash value at the end of hashing operations (when the HASH_TERM control bit is set). 16.2.5.4.1 Next Command Address Field The NEXT_COMMAND_ADDRESS field (as shown in Table 16-2) is used to point to the next work packet in the chain. This field is loaded into the channel's command pointer after the current packet has completed processing if the CHAIN bit in the CONTROL0 field (see Table 16-3) is set. The Next Command Address field should be programmed to a non-zero value when the CHAIN bit is set; otherwise, the channel will flag an invalid setup error. Table 16-2. DCP Next Command Address Field 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 111111111 987654321 NEXT_COMMAND_ADDRESS 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 16.2.5.4.2 Control0 Field The main functions of the DCP module are enabled with the ENABLE_MEMCOPY, ENABLE_BLIT, ENABLE_CIPHER, and ENABLE_HASH bits from the Control0 field in the work packet. The combii.MX23 Applications Processor Reference Manual, Rev. 1 16-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) nations of these bits determine the function performed by the DCP. Table 16-4 summarizes the function performed for each combination. Table 16-3. DCP Control0 Field 3 1 3 0 2 9 22 87 TAG 2 6 2 5 2 4 2 3 OUTPUT_WORDSWAP 2 2 OUTPUT_BYTESWAP 2 1 INPUT_WORDSWAP 2 0 INPUT_BYTESWAP 1 9 KEY_WORDWRAP 1 8 KEY_BYTEWRAP 1 7 TEST_SEMA_IRQ 1 6 CONSTANT_FILL 1 5 HASH_OUTPUT 1 4 HASH_CHECK 1 3 1 2 1 1 1 0 0 9 0 8 CIPHER_ENCRYPT 0 7 0 6 ENABLE_HASH 0 5 ENABLE_CIPHER 0 4 ENABLE_MEMCOPY 0 3 CHAIN_CONTINUOUS 0 2 0 1 DECR_SEMAPHORE 0 0 INTERRUPT_ENABLE PAYLOAD_KEY ENABLE_BLIT CIPHER_INIT HASH_TERM HASH_INIT OTP_KEY Table 16-4. DCP Function Enable Bits Hash 0 0 0 1 1 1 Cipher 0 0 1 0 0 1 Blit 0 1 0 0 0 0 All Others Memcopy X 0 0 0 1 0 Description Simple memcopy operation. Blit operation. Simple encrypt/decrypt operation. Simple hash. Only reads performed. Memcopy and hash operation. Hash with encryption/decryption. Invalid setup. The CHAIN bit should be set if the NEXT_COMMAND_ADDRESS field has a valid pointer to the next work packet. When set, this bit causes the channel to update its pointer to the next packet. The CHAIN_CONTINUOUS bit is similar, but it indicates that the next packet follows immediately after the current packet. This allows software to generate templates of operations without regard to the actual physical addresses used, which makes programming easier, especially in a virtual memory environment. If the INTERRUPT_ENABLE bit is set, the channel generates an interrupt to the processor after completing the work for this packet. When the interrupt is issued, the packet will have been completely processed, including the update of the status/payload fields in the work packet. Each channel contains an eight-bit counting semaphore that controls whether it is in the run or idle state. When the semaphore in non-zero, the channel is ready to run and process commands. Whenever a command finishes its operation, it checks the DECR_SEMAPHORE bit. If set, it decrements the counting semaphore. If the semaphore goes to 0 as a result, then the channel enters the idle state and remains there until the semaphore is incremented by software. When the semaphore goes to non-zero and the channel is in its idle state, it then uses the value in the NEXT_COMMAND_ADDRESS field to begin processing. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-13 CHAIN Data Co-Processor (DCP) If the ENABLE_CIPHER bit is set, the data is encrypted or decrypted based on the CIPHER_ENCRYPT bit using the key/encryption settings from the Control1 field. The OTP_KEY and PAYLOAD_KEY indicate the source of the keys for the operation. If the OTP_KEY value is set, the KEY_SELECT field from the Control1 register indicates which OTP key is to be used. If the PAYLOAD_KEY bit is set, the first entry in the payload is the key to be used for the operation. If neither bit is set, the KEY_SELECT field indicates an index in the key RAM that contains the key to be used. (For cases when both the OTP_KEY and PAYLOAD_KEY bits are set, the PAYLOAD_KEY takes precedence.) The HASH_ENABLE enables hashing of the data with the HASH_OUTPUT bit controlling whether the input data (HASH_OUTPUT=0) or output data (HASH_OUTPUT=1) is hashed. In addition, the hardware can be programmed to automatically check the hashed data if the HASH_CHECK bit is set. If the hash does not match, an interrupt is generated and the channel terminates operation on the current chain. The hashing algorithms also require two additional fields in order to operate properly. The HASH_INIT bit should be set for the first block in a hashing pass to properly initialize the hashing function. The HASH_TERM bit must be set on the final block of a hash to notify the hardware that the hashing operation is complete so that it can properly pad the tail of the buffer according to the hashing algorithm. This flag also triggers the write-back of the hash output to the work packet's payload area. The CONSTANT_FILL flag may be used for both memcopy and blit operations. When this is set, the source address field is used instead as a constant that is written to all locations in the output buffer. The WORDSWAP and BYTESWAP bits enable muxes around the FIFO to swap data to handle little-endian and big-endian storage of data in system memory. When these bits are cleared, data is assumed to be in little-endian format. When all bits are set, data is assumed to be in big-endian format. The TAG field is used to identify the work packet and the associated completion status. As each packet is completed, the channel provides the status and tag information for the last packet processed. 16.2.5.4.3 Control1 Field The Control1 field (shown in Table 16-5) provides additional values used when hashing or encrypting/decrypting data. For blit operations, this field indicates the number of bytes in a frame buffer line, which is used to calculate the address for successive lines in each blit operation. Table 16-5. DCP Control1 Field 3 1 3 0 22222 98765 CIPHER_CONFIG 2 4 2 3 2 2 2 1 2 0 1 9 111 876 HASH_ SELECT 1 5 1 4 0000000 6543210 CIPHER_ CIPHER_ MODE SELECT FRAMEBUFFER_LENGTH (in bytes, blit mode) 11110 32109 KEY_SELECT 0 8 0 7 The CIPHER_SELECT field selects from one of sixteen possible encryption algorithms (0=AES128). The CIPHER_MODE selects the mode of operation for that cipher (0=ECB, 1=CBC). i.MX23 Applications Processor Reference Manual, Rev. 1 16-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) The KEY_SELECT field allows key selection for one of several sources. Keys can be included in the packet payload or may come from OTP or write-only registers. The HASH_SELECT field selects a hashing algorithm for the operation (0=SHA-1, 1=CRC32). The CIPHER_CONFIG field provides optional configuration information for the selected cipher. An example would be a key length for the RC4 algorithm. 16.2.5.4.4 Source Buffer The SOURCE_BUFFER pointer (shown in Table 16-6) specifies the location of the source buffer in memory. The buffer may reside at any byte alignment and should refer to an on-chip SRAM of off-chip SDRAM location. For optimal performance, buffers should be word aligned. When the CONSTANT_FILL flag is set in the Control0 field, the value in this field is used as the data written to all destination buffer locations. Table 16-6. DCP Source Buffer Field 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 111111111 876543210 SOURCE_BUFFER CONSTANT (CONSTANT_FILL mode) 2 0 1 9 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 16.2.5.4.5 Destination Buffer The DESTINATION_BUFFER (shown in Table 16-7) specifies the location of the destination buffer in on-chip SRAM or off-chip SDRAM memory and may be set to any byte alignment. For in-place encryption, the destination buffer and source buffer should be the same value. For optimal performance, the buffer location should be word-aligned. Table 16-7. DCP Destination Buffer Field 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1111111 8765432 DESTINATION_BUFFER 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 16.2.5.4.6 Buffer Size Field The BUFFER_SIZE field (shown in Table 16-8) indicates the size of the buffers for memcopy, encryption, and hashing modes. For memcopy and hashing operations, the value may be any number of bytes (byte granularity), and for encryption modes, the length must be a multiple of the selected encryption algorithm's natural data size (16 bytes for AES). Table 16-8. DCP Buffer Size Field 3 1 3 0 2 9 2 8 2222222211111111110000000 7654321098765432109876543 NUMBER_LINES (blit mode) BLIT_WIDTH (in bytes, blit mode) BUFFER_SIZE (in bytes, memcopy, encryption, hashing modes) 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-15 Data Co-Processor (DCP) For blit operations, the buffer size field is split into two portions, a BLIT_WIDTH value, which specifies the number of bytes in each "line" of the blit operation, and a NUMBER_LINES value, which specifies how many vertical rows of pixels are in the image buffer. 16.2.5.4.7 Payload Pointer Some operations require additional control values that are stored in a Payload Buffer (shown in Table 16-9), which is pointed to by this field. After the DCP reads the control packet, it examines the Control0 register and determines whether any payload information is required. If so, the DCP loads the payload from the address specified in this field. (See Section 16.2.5.4.9, "Payload" for more details.) Table 16-9. DCP Payload Buffer Pointer 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 111111 876543 PAYLOAD_POINTER 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 The payload area is also written to by the DCP at the completion of a hash operation (when the HASH_TERM) bit is set. Software must allocate the appropriate amount of storage (20 bytes for SHA-1 and 4 bytes for CRC32) in the payload or risk having the DCP write to an unallocated address. 16.2.5.4.8 Status After the DCP engine has completed processing of a descriptor, it writes the packet status (shown in Table 16-10) back to the descriptor In the Status field. The packet status is the value of the channel status register at the time the packet completed processing. Table 16-10. DCP Status Field 3 1 3 0 2 9 22 87 TAG 2 6 2 5 2 4 2 3 2 2 22111 10987 ERROR_CODE 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 ERROR_DST 0 4 ERROR_SRC 0 3 ERROR_PACKET 0 2 ERROR_SETUP 0 1 HASH_MISMATCH 0 0 COMPLETE For various error conditions, the DCP encodes additional error information in the ERROR_CODE field. See Section 16.3, "Programmable Registers." for more details on assignments of error codes. For any completion codes besides the COMPLETE flag, the channel suspends processing of the command chain until the error status values are cleared in the channel status register. The format for this field is the same as for the channel status register, with the exception that the COMPLETE bit is written to the payload status but is not present in the channel status register. i.MX23 Applications Processor Reference Manual, Rev. 1 16-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) 16.2.5.4.9 Payload The payload is a variable-length field that is used to provide key, initialization values, and expected results from hashing operations. The payload may consist of the data fields listed in Table 16-11. Table 16-11. DCP Payload Field Field Name Cipher Key Cipher IV Hash Check Size 16 bytes 16 bytes 20 bytes Description AES key CBC initialization vector Hash completion value Condition Cipher enable with PAYLOAD_KEY Cipher enable with CBC mode. Hash enabled with HASH_TERM fields set. If fields are not used, they do not appear in the payload and the other payload values move upwards in the payload area. For instance, if only hashing is used, then the HASH_CHECK value would appear at offset 0 in the payload area. Table 16-12 should be used by software to determine the amount of payload to allocate and initialize. Table 16-12. DCP Payload Allocation by Software Control Bits Present Payload Size Hash_Check 0 0 0 0 1 1 1 1 Cipher_Init 0 0 1 1 0 0 1 1 Payload_Key 0 1 0 1 0 1 0 1 0 words / 0 bytes 4 words / 16 bytes 4 words / 16 bytes 8 words / 32 bytes 5 words / 20 bytes 9 words / 36 bytes 9 words / 36 bytes 13 words / 52 bytes For hashing operations, the DCP module writes the final hash value back to the start of the payload area for descriptors with the HASH_TERM bit set in the control packet. It is important that software allocate the required payload space, even though it is not required to set up the payload for control purposes. 16.2.6 16.2.6.1 Programming Other DCP Functions Basic Memory Copy Programming Example To perform a basic memcopy operation, only a single descriptor is required. The DCP simply copies data from the source to the destination buffer. This process is illustrated in Figure 16-6. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-17 Data Co-Processor (DCP) Next Ctrl0 Ctrl1 Src Dst Bytes Payld Stat 0x13 = Memcopy | DecrSema | Interrupt Source Buffer Address Destination Buffer Address Byte Count Tag 0x13 Source Buffer Destination Buffer Figure 16-6. Basic Memory Copy Operation typedef struct _dcp_descriptor { u32 *next; hw_dcp_packet1_t ctrl0; hw_dcp_packet2_t ctrl1; u32 *src, *dst, buf_size, *payload, stat; } DCP_DESCRIPTOR; DCP_DESCRIPTOR dcp1; u32 *srcbuffer, *dstbuffer; // set up control packet dcp1.next = 0; // single packet in chain dcp1.ctrl0.U = 0; // clear ctrl0 field dcp1.ctrl0.B.ENABLE_MEMCOPY = 1; // enable memcopy dcp1.ctrl0.B.DECR_SEMAPHORE = 1; // decrement semaphore dcp1.ctrl0.B.INTERRUPT = 1; // interrupt dcp1.ctrl1.U = 0; // clear ctrl1 dcp1.src = srcbuffer; // source buffer dcp1.dst = dstbuffer; // destination buffer dcp1.buf_size = 512; // 512 bytes dcp1.payload = NULL; // not required dcp1.status = 0; // clear status // Enable channel 0 HW_DCP_CHnCMDPTR_WR(0, dcp1); HW_DCP_CHnSEMA_WR(0, 1); // write packet address to pointer register // increment semaphore by 116.2.6.2 Basic Hash Operation Programming Example To perform a basic hash operation, only a single descriptor is required. The DCP simply reads data from the source buffer and computes the hash value on the contents. This process is illustrated in Figure 16-7. i.MX23 Applications Processor Reference Manual, Rev. 1 16-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) Next Ctrl0 Ctrl1 Src Dst Bytes Payld Stat 0x70 = Hash Check | Hash Term | Hash Init 0x43 = Hash Enable | DecrSema | Interrupt Byte Count Payload Addrses Tag SHA1 0x70 0x43 Source Buffer Source Buffer Address Payload Expected Hash Figure 16-7. Basic Hash Operation typedef struct _dcp_descriptor { u32 *next; hw_dcp_packet1_t ctrl0; hw_dcp_packet2_t ctrl1; u32 *src, *dst, buf_size, *payload, stat; } DCP_DESCRIPTOR; DCP_DESCRIPTOR dcp1; u32 *srcbuffer; u32 payload[5]; // set up expected hash check value payload[0]=0x01234567; payload[1]=0x89ABCDEF; payload[2]=0x00112233; payload[3]=0x44556677; payload[4]=0x8899aabb; // set up control packet dcp1.next = 0; // single packet in chain dcp1.ctrl0.U = 0; // clear ctrl0 field dcp1.ctrl0.B.HASH_CHECK = 1; // check hash when complete dcp1.ctrl0.B.HASH_INIT = 1; // initialize hash with this block dcp1.ctrl0.B.HASH_TERM = 1; // terminate hash with this block dcp1.ctrl0.B.ENABLE_HASH = 1; // enable hash dcp1.ctrl0.B.DECR_SEMAPHORE = 1; // decrement semaphore dcp1.ctrl0.B.INTERRUPT = 1; // interrupt dcp1.ctrl1.U = 0; // clear ctrl1 dcp1.src = srcbuffer; // source buffer dcp1.dst = 0; // no destination buffer dcp1.buf_size = 512; // 512 bytes dcp1.payload = payload; // holds expected hash value dcp1.status = 0; // clear status // Enable channel 0 HW_DCP_CHnCMDPTR_WR(0, dcp1); HW_DCP_CHnSEMA_WR(0, 1); // write packet address to pointer register // increment semaphore by 116.2.6.3 Basic Cipher Operation Programming Example To perform a basic cipher operation, only a single descriptor is required. The DCP reads data from the source buffer, encrypts it, and writes it to the destination buffer. For this example, the key is provided in the payload and the algorithm uses the AES CBC mode of operation. This requires a payload with both the key and CBC initialization value. This process is illustrated in Figure 16-8. Next Ctrl0 Ctrl1 Src Dst Bytes Payld Stat 0x0B = Payload Key | Cipher Init | Encrypt 0x23 = Cipher Enable | DecrSema | Interrupt Payload Key CBC Init Source Buffer Address Destination Buffer Address Byte Count Payload Address Tag 0x0B 0x23 CBC AES Source Buffer Destination Buffer Figure 16-8. Basic Cipher Operation typedef struct _dcp_descriptor { u32 *next; hw_dcp_packet1_t ctrl0; hw_dcp_packet2_t ctrl1; u32 *src, *dst, buf_size, *payload, stat; } DCP_DESCRIPTOR; DCP_DESCRIPTOR dcp1; u32 *srcbuffer; u32 *dstbuffer; u32 payload[8]; // set up key/CBC init in the payload payload[0]=0x01234567; // key payload[1]=0x89ABCDEF; payload[2]=0xfedcba98; payload[3]=0x76543210; payload[4]=0x00112233; // CBC initialization payload[5]=0x44556677; payload[6]=0x8899aabb; payload[7]=0xccddeeff; // set up control packet16.2.6.4 Multi-Buffer Scatter/Gather Cipher and Hash Operation Programming Example For this example, three separate buffers are encrypted and hashed with the results being directed to a unified buffer (gather operation). Three descriptors are used for the operation because there are three separate source buffer pointers. The DCP reads data from the source buffer and computes a hash on the unencrypted data. It then encrypts the data and writes it to the destination buffer. For this example, the key is located in the key RAM, and the algorithm uses the AES CBC mode of operation with a SHA-1 hash. The payload for the first operation contains the CBC initialization value, and the payload for the last packet contains the expected hash value. The middle packet requires no payload. This process is illustrated in Figure 16-9. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-21 Data Co-Processor (DCP) Next Ctrl0 Ctrl1 Src Dst Bytes Payld Stat Tag Packet 1 Address 0x00 SHA1 0x13 Key# 0x66 CBC AES Source Buffer 0 Source Buffer 0 Address Destination Buffer 0 Address Byte Count Payload 0 Address Payload CBC Init 0x13 = Hash Init | Cipher Init | Encrypt 0x66 = Hash Enable | Cipher Enable | Chain | DecrSema Next Ctrl0 Ctrl1 Src Dst Bytes Payld Stat Tag Packet 2 Address 0x00 SHA1 0x01 Key# 0x66 CBC AES Source Buffer 1 Dest Buffer 0 Source Buffer 1 Address Destination Buffer 1 Address Byte Count Dest Buffer 1 0x01 = Encrypt 0x66 = Hash Enable | Cipher Enable | Chain | DecrSema Dest Buffer 2 Next Ctrl0 Ctrl1 Src Dst Bytes Payld Stat 0x61 = Hash Check | Hash Term | Encrypt 0x63 = Hash Enable | Cipher Enable | DecrSema | Interrupt Tag 0x00 SHA1 0x61 Key# 0x63 CBC AES Source Buffer 2 Source Buffer 2 Address Destination Buffer 2 Address Byte Count Payload 2 Address Payload Hash Check Figure 16-9. Multi-Buffer Scatter/Gather Cipher and Hash Operation typedef struct _dcp_descriptor { u32 *next; hw_dcp_packet1_t ctrl0; hw_dcp_packet2_t ctrl1; u32 *src, *dst, buf_size, *payload, stat; } DCP_DESCRIPTOR;16.3 Programmable Registers The following registers are available for programmer access and control of the DCP. 16.3.1 DCP Control Register 0 Description HW_DCP_CTRL HW_DCP_CTRL_SET HW_DCP_CTRL_CLR HW_DCP_CTRL_TOG Table 16-13. HW_DCP_CTRL The CTRL register contains controls for the DCP module. 0x000 0x004 0x008 0x00C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 GATHER_RESIDUAL_WRITES 2 2 ENABLE_CONTEXT_CACHING 2 1 ENABLE_CONTEXT_SWITCHING 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 CHANNEL_INTERRUPT_ENABLE 0 3 0 2 0 1 0 0 PRESENT_CRYPTO CLKGATE SFTRST RSVD1 RSVD3 RSVD2 Table 16-14. HW_DCP_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Set this bit to zero to enable normal DCP operation. Set this bit to one (default) to disable clocking with the DCP and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the DCP block to its default state. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. 30 CLKGATE RW 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 16-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSVD0 Data Co-Processor (DCP) Table 16-14. HW_DCP_CTRL Bit Field Descriptions BITS LABEL 29 PRESENT_CRYPTO RW RESET RO 0x1 DEFINITION Indicates whether the crypto (Cipher/Hash) functions are present. Present = 0x1 Absent = 0x0 28 RSVD3 27:24 RSVD2 GATHER_RESIDUAL_WRITE 23 S RO 0x000000 RO 0x000000 RW 0x1 22 ENABLE_CONTEXT_CACHIN RW 0x0 G 21 ENABLE_CONTEXT_SWITCH RW 0x0 ING 20:9 8 7:0 RSVD1 RO 0x000000 RSVD0 RO 0x000000 CHANNEL_INTERRUPT_ENA RW 0x0 BLE Reserved Reserved, always set to zero. Software should set this bit to enable ragged writes to unaligned buffers to be gathered between multiple write operations. This improves performance by removing several byte operations between write bursts. Trailing byte writes are held in a residual write data buffer and combined with a subsequent write to the buffer to form a word write. Software should set this bit to enable caching of contexts between operations. If only a single channel is used for encryption/hashing, enabling caching causes the context to not be reloaded if the channel was the last to be used. Enable automatic context switching for the channels. Software should set this bit if more than one channel is doing hashing or cipher operations that require context to be saved (for instance, when CBC mode is enabled). By disabling context switching, software can save the 160 bytes used for the context buffer. Reserved, always set to zero. Reserved Per-channel interrupt enable bit. When set, the channel's interrupt will get routed to the interrupt controller. Channel 0 is routed to the dcp_vmi_irq signal and the other channels are combined (along with the CRC interrupt) into the dcp_irq signal. CH0 = 0x01 CH1 = 0x02 CH2 = 0x04 CH3 = 0x08 DESCRIPTION: The Control register contains the primary controls for the DCP block. The present bits indicate which of the sub-features of the block are present in the hardware. The context control bits control how the DCP utilizes it's context buffer and the gather residual writes bit controls how the master handles writing misaligned data to the bus. Each channel and the color-space converter contains an independent interrupt enable. EXAMPLE: HW_DCP_CTRL_SET(BM_DCP_CTRL_SFTRST); HW_DCP_CTRL_CLR(BM_DCP_CTRL_SFTRST | BM_DCP_CTRL_CLKGATE); 16.3.2 DCP Status Register Description HW_DCP_STAT HW_DCP_STAT_SET 0x010 0x014 The DCP Interrupt Status register provides channel interrupt status information. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-25 Data Co-Processor (DCP) HW_DCP_STAT_CLR HW_DCP_STAT_TOG Table 16-15. HW_DCP_STAT 3 1 3 0 2 9 2 8 OTP_KEY_READY 0x018 0x01C 2 7 2 6 CUR_CHANNEL 2 5 2 4 2 3 2 2 2 1 2 0 READY_CHANNELS 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSVD2 RSVD1 RSVD3 RSVD0 Table 16-16. HW_DCP_STAT Bit Field Descriptions BITS LABEL 31:29 RSVD3 OTP_KEY_READY 28 27:24 CUR_CHANNEL RW RESET RO 0x000000 RO 0x1 RO 0x0 DEFINITION Reserved, always set to zero. When set, indicates that the OTP key has been shifted from the fuse block and is ready for use. Current (active) channel (encoded). None = 0x0 CH0 = 0x1 CH1 = 0x2 CH2 = 0x3 CH3 = 0x4 CSC = 0x8 23:16 READY_CHANNELS RO 0x0 Indicates which channels are ready to proceed with a transfer (active channel also included). Each bit is a one-hot indicating the request status for the associated channel. CH0 = 0x01 CH1 = 0x02 CH2 = 0x04 CH3 = 0x08 15:9 8 7:4 3:0 RSVD2 RSVD1 RSVD0 IRQ RO RO RO RW 0x000000 0x000000 0x000000 0x0 Reserved, always set to zero. Reserved Reserved, always set to zero. Indicates which channels have pending interrupt requests. Channel 0's interrupt is routed through the dcp_vmi_irq and the other interrupt bits are routed through the dcp_irq. DESCRIPTION: This register provides status feedback indicating the channel currently performing an operation and which channels have pending operations. EXAMPLE: HW_DCP_STAT_CLR(BM_DCP_STAT_CSCIRQ); // clear CSC interrupt 16.3.3 DCP Channel Control Register Description The DCP Channel Control register provides controls for channel arbitration and channel enables. i.MX23 Applications Processor Reference Manual, Rev. 1 16-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor IRQ Data Co-Processor (DCP) HW_DCP_CHANNELCTRL HW_DCP_CHANNELCTRL_SET HW_DCP_CHANNELCTRL_CLR HW_DCP_CHANNELCTRL_TOG 0x020 0x024 0x028 0x02C Table 16-17. HW_DCP_CHANNELCTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 HIGH_PRIORITY_CHANNEL 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 16-18. HW_DCP_CHANNELCTRL Bit Field Descriptions BITS LABEL 31:19 RSVD 18:17 RSVD1 CH0_IRQ_MERGED 16 RW RESET RO 0x0000 RO 0x000000 RW 0x0 DEFINITION Reserved, always set to zero. Reserved Indicates that the interrupt for channel 0 should be merged with the other interrupts on the shared dcp_irq interrupt. When set to 0, channel 0's interrupt will be routed to the separate dcp_vmi_irq. When set to 1, the interrupt will be routed to the shared DCP interrupt. Setting a bit in this field causes the corresponding channel to have high-priority arbitration. High priority channels will be arbitrated round-robin and will take precedence over other channels that are not marked as high priority. CH0 = 0x01 CH1 = 0x02 CH2 = 0x04 CH3 = 0x08 15:8 HIGH_PRIORITY_CHANNEL RW 0x0 7:0 ENABLE_CHANNEL RW 0x0 Setting a bit in this field will enabled the DMA channel associated with it. This field is a direct input to the DMA channel arbiter. When not enabled, the channel is denied access to the central DMA resources. CH0 = 0x01 CH1 = 0x02 CH2 = 0x04 CH3 = 0x08 DESCRIPTION: This register provides status feedback indicating the channel currently performing an operation and which channels have pending operations. EXAMPLE: BW_DCP_CHANNELCTRL_ENABLE_CHANNEL(BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0); // enable channel 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-27 ENABLE_CHANNEL CH0_IRQ_MERGED RSVD1 RSVD Data Co-Processor (DCP) 16.3.4 DCP Capability 0 Register Description HW_DCP_CAPABILITY0 Table 16-19. HW_DCP_CAPABILITY0 This register contains additional information about the DCP module implementation parameters. 0x030 3 1 DISABLE_DECRYPT 3 0 ENABLE_TZONE 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 NUM_CHANNELS 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 16-20. HW_DCP_CAPABILITY0 Bit Field Descriptions BITS LABEL 31 DISABLE_DECRYPT RW RESET RW 0x0 DEFINITION Write to a 1 to disable decryption. This bit can only be written by secure software and the value can only be cleared by a reset. Write to a 1 enable trustzone support. Channel operations initiated by secure operations will be protected from non-secure operations and the secure channel interrupts will be routed to the secure DCP interrupt. This bit can only be written by secure software and the value can only be cleared by a reset. Reserved, always set to zero. Encoded value indicating the number of channels implemented in the design. Encoded value indicating the number of key storage locations implemented in the design. 30 ENABLE_TZONE RW 0x0 29:12 RSVD 11:8 NUM_CHANNELS 7:0 RO 0x000000 RO 0x4 RO 0x4 NUM_KEYS DESCRIPTION: This register provides capability information for the DCP block. It indicates the number of channels implemented as well as the number of key storage locations available for software use. EXAMPLE: Empty Example 16.3.5 DCP Capability 1 Register Description HW_DCP_CAPABILITY1 0x040 This register contains information about the algorithms available on the implementation. i.MX23 Applications Processor Reference Manual, Rev. 1 16-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor NUM_KEYS RSVD Data Co-Processor (DCP) Table 16-21. HW_DCP_CAPABILITY1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 HASH_ALGORITHMS 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 CIPHER_ALGORITHMS 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 16-22. HW_DCP_CAPABILITY1 Bit Field Descriptions BITS LABEL 31:16 HASH_ALGORITHMS RW RESET RO 0x1 DEFINITION One-hot field indicating which hashing algorithms are available. SHA1 = 0x0001 CRC32 = 0x0002 15:0 CIPHER_ALGORITHMS RO 0x1 One-hot field indicating which cipher algorithms are available. AES128 = 0x0001 DESCRIPTION: This register provides capability information for the DCP block. It contains two fields indicating which encryption and hashing algorithms are present in the design. Each bit set indicates that support for the associated function is present. EXAMPLE: Empty Example. 16.3.6 DCP Context Buffer Pointer Description HW_DCP_CONTEXT Table 16-23. HW_DCP_CONTEXT This register contains a pointer to the memory region to be used for DCP context swap operations. 0x050 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ADDR Table 16-24. HW_DCP_CONTEXT Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Context pointer address. Address should be located in system RAM and should be word-aligned for optimal performance. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-29 Data Co-Processor (DCP) DESCRIPTION: This register contains a pointer to the start of the context pointer memory in on-chip SRAM or off-chip SDRAM. This buffer will be used to store state information when the DCP module changes from one channel to another. EXAMPLE: Empty Example. 16.3.7 DCP Key Index Description HW_DCP_KEY Table 16-25. HW_DCP_KEY This register contains a pointer to the key location to be written. 0x060 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 RSVD_INDEX 0 6 0 5 0 4 0 3 RSVD_SUBWORD 0 2 0 1 0 0 Table 16-26. HW_DCP_KEY Bit Field Descriptions BITS 31:8 7:6 5:4 3:2 1:0 LABEL RSVD RSVD_INDEX INDEX RSVD_SUBWORD SUBWORD RW RO RO RW RO RW RESET 0x000000 0x000000 0x0 0x0 0x0 DEFINITION Reserved, always set to zero. Reserved, always set to zero. Key index pointer. Valid indices are 0-[number_keys]. Reserved, always set to zero. Key subword pointer. Valid indices are 0-3. After each write to the key data register, this field will increment. DESCRIPTION: The DCP module maintains a set of write-only keys that may be used by software. To write a key, software must first write the desired key index/subword to this register and then write the key values to the key registers (below). After each write to the key data register, the SUBWORD field will increment to allow software to write the subsequent key to be written without having to rewrite the key index. EXAMPLE: // write key 0 to 0x00112233_44556677_8899aabb_ccddeeff HW_DCP_KEY_WR(BF_DCP_KEY_INDEX(0) | BF_DCP_KEY_SUBWORD(0)); HW_DCP_KEYDATA_WR(0xccddeeff); // write key values (subword HW_DCP_KEYDATA_WR(0x8899aabb); // write key values (subword HW_DCP_KEYDATA_WR(0x44556677); // write key values (subword HW_DCP_KEYDATA_WR(0x00112233); // write key values (subword // set key index to key 0, subword 0 0) 1) 2) 3) i.MX23 Applications Processor Reference Manual, Rev. 1 16-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor SUBWORD INDEX RSVD Data Co-Processor (DCP) 16.3.8 DCP Key Data Description HW_DCP_KEYDATA Table 16-27. HW_DCP_KEYDATA This register provides write access to the key/key subword specified by the Key Index Register. 0x070 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DATA Table 16-28. HW_DCP_KEYDATA Bit Field Descriptions BITS 31:0 DATA LABEL RW RESET RW 0x0 DEFINITION Word 0 data for key. This is the least-significant word. DESCRIPTION: Writing this location updates the selected subword for the key located at the index specified by the Key Index Register. A write also triggers the SUBWORD field of the KEY register to increment to the next higher word in the key. EXAMPLE: // write key 0 to 0x00112233_44556677_8899aabb_ccddeeff HW_DCP_KEY_WR(BF_DCP_KEY_INDEX(0) | BF_DCP_KEY_SUBWORD(0)); HW_DCP_KEYDATA_WR(0xccddeeff); // write key values (subword HW_DCP_KEYDATA_WR(0x8899aabb); // write key values (subword HW_DCP_KEYDATA_WR(0x44556677); // write key values (subword HW_DCP_KEYDATA_WR(0x00112233); // write key values (subword // set key index to key 0, subword 0 0) 1) 2) 3) 16.3.9 DCP Work Packet 0 Status Register Description HW_DCP_PACKET0 Table 16-29. HW_DCP_PACKET0 This register displays the values for the current work packet offset 0x00 (Next Command) field. 0x080 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ADDR Table 16-30. HW_DCP_PACKET0 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RO 0x0 DEFINITION Next Pointer Register, DESCRIPTION: The Work Packet Status Registers show the contents of the currently executing packet. When the channels are inactive (or the CSC is active), the packet status register return 0. The register bits are fully documented here to document the packet structure in memory. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-31 Data Co-Processor (DCP) EXAMPLE: Empty Example. 16.3.10 DCP Work Packet 1 Status Register Description This register displays the values for the current work packet offset 0x04 (control) field. HW_DCP_PACKET1 Table 16-31. HW_DCP_PACKET1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 OUTPUT_WORDSWAP 0x090 2 2 OUTPUT_BYTESWAP 2 1 INPUT_WORDSWAP 2 0 INPUT_BYTESWAP 1 9 KEY_WORDSWAP 1 8 KEY_BYTESWAP 1 7 TEST_SEMA_IRQ 1 6 CONSTANT_FILL 1 5 HASH_OUTPUT 1 4 1 3 1 2 1 1 1 0 0 9 0 8 CIPHER_ENCRYPT 0 7 0 6 ENABLE_HASH 0 5 ENABLE_CIPHER 0 4 ENABLE_MEMCOPY 0 3 CHAIN_CONTIGUOUS 0 2 0 1 DECR_SEMAPHORE 0 0 PAYLOAD_KEY CHECK_HASH ENABLE_BLIT HASH_TERM CIPHER_INIT Table 16-32. HW_DCP_PACKET1 Bit Field Descriptions BITS LABEL 31:24 TAG OUTPUT_WORDSWAP 23 22 21 20 19 18 17 16 RW RESET RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 DEFINITION Packet Tag Reflects whether the DCP engine will wordswap output data (big-endian data). Reflects whether the DCP engine will byteswap output data (big-endian data). Reflects whether the DCP engine will wordswap input data (big-endian data). Reflects whether the DCP engine will byteswap input data (big-endian data). Reflects whether the DCP engine will swap key words (big-endian key). Reflects whether the DCP engine will swap key bytes (big-endian key). This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY! When this bit is set (MEMCOPY and BLIT modes only), the DCP will simply fill the destination buffer with the value found in the Source Address field. When hashing is enabled, this bit controls whether the input or output data is hashed. INPUT = 0x00 OUTPUT = 0x01 OUTPUT_BYTESWAP INPUT_WORDSWAP INPUT_BYTESWAP KEY_WORDSWAP KEY_BYTESWAP TEST_SEMA_IRQ CONSTANT_FILL 15 HASH_OUTPUT RO 0x0 14 13 CHECK_HASH HASH_TERM RO 0x0 RO 0x0 Reflects whether the calculated hash value should be compared against the hash provided in the payload. Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding should be applied by hardware. i.MX23 Applications Processor Reference Manual, Rev. 1 16-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor INTERRUPT HASH_INIT OTP_KEY CHAIN TAG Data Co-Processor (DCP) Table 16-32. HW_DCP_PACKET1 Bit Field Descriptions BITS LABEL 12 HASH_INIT RW RESET RO 0x0 DEFINITION Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers should be initialized before the operation. When set, indicates the payload contains the key. This bit takes precedence over the OTP_KEY control Reflects whether a hardware-based key should be used. The KEY_SELECT field from the Control1 field is used to select from multiple hardware keys. The PAYLOAD_KEY bit takes precedence over the OTP_KEY bit. Reflects whether the cipher block should load the initialization vector from the payload for this operation. When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption. ENCRYPT = 0x01 DECRYPT = 0x00 11 10 PAYLOAD_KEY OTP_KEY RO 0x0 RO 0x0 9 8 CIPHER_INIT CIPHER_ENCRYPT RO 0x0 RO 0x0 7 ENABLE_BLIT RO 0x0 6 5 4 3 2 ENABLE_HASH ENABLE_CIPHER ENABLE_MEMCOPY CHAIN_CONTIGUOUS CHAIN RO 0x0 RO 0x0 RO 0x0 RO 0x000000 RO 0x0 1 DECR_SEMAPHORE RO 0x0 0 INTERRUPT RO 0x0 Reflects whether the DCP should perform a blit operation. Source data is always continuous and the destination buffer is written in run/stride format. When set, the BUFFER_SIZE field is treated as two 16-bit values for the X-Y extents of the blit operation. Reflects whether the selected hashing function should be enabled for this operation. Reflects whether the selected cipher function should be enabled for this operation. Reflects whether the selected hashing function should be enabled for this operation. Reflects whether the next packet's address is located following this packet's payload. Reflects whether the next command pointer register should be loaded into the channel's current descriptor pointer. Reflects whether the channel's semaphore should be decremented at the end of the current operation. When the semaphore reaches a value of zero, no more operations will be issued from the channel. Reflects whether the channel should issue an interrupt upon completion of the packet. DESCRIPTION: This register shows the contents of the Control0 register from the packet being processed. EXAMPLE: Empty Example. 16.3.11 DCP Work Packet 2 Status Register Description This register displays the values for the current work packet offset 0x08 (Control1) field. HW_DCP_PACKET2 0x0A0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-33 Data Co-Processor (DCP) Table 16-33. HW_DCP_PACKET2 3 1 3 0 2 9 2 8 CIPHER_CFG 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 HASH_SELECT 1 7 1 6 1 5 1 4 1 3 1 2 KEY_SELECT 1 1 1 0 0 9 0 8 0 7 0 6 CIPHER_MODE 0 5 0 4 0 3 0 2 CIPHER_SELECT 0 1 0 0 Table 16-34. HW_DCP_PACKET2 Bit Field Descriptions BITS LABEL 31:24 CIPHER_CFG 23:20 RSVD 19:16 HASH_SELECT 15:8 7:4 RSVD RW RESET RO 0x0 RO 0x0 RO 0x0 RO 0x0 RO 0x0 DEFINITION Cipher configuration bits. Optional configuration bits required for ciphers Reserved, always set to zero. Hash Selection Field SHA1 = 0x00 CRC32 = 0x01 KEY_SELECT CIPHER_MODE Key Selection Field. The value here reflects the key index for the cipher operation. Cipher Mode Selection Field. Reflects the mode of operation for cipher operations. ECB = 0x00 CBC = 0x01 3:0 CIPHER_SELECT RO 0x0 Cipher Selection Field AES128 = 0x00 DESCRIPTION: This register shows the contents of the Control0 register from the packet being processed. EXAMPLE: Empty Example. 16.3.12 DCP Work Packet 3 Status Register Description This register displays the values for the current work packet offset 0x0C (Source Address) field. HW_DCP_PACKET3 Table 16-35. HW_DCP_PACKET3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0B0 ADDR i.MX23 Applications Processor Reference Manual, Rev. 1 16-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) Table 16-36. HW_DCP_PACKET3 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RO 0x0 DEFINITION Source Buffer Address Pointer. This value is the working value and will update as the operation proceeds. DESCRIPTION: This register shows the contents of the Source Address register from the packet being processed. When the CONSTANT_FILL bit in the Control 0 field is set, this field contains the data written to the destination buffer. EXAMPLE: Empty Example. 16.3.13 DCP Work Packet 4 Status Register Description This register displays the values for the current work packet offset 0x10 (Destination Address) field. HW_DCP_PACKET4 Table 16-37. HW_DCP_PACKET4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0C0 ADDR Table 16-38. HW_DCP_PACKET4 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RO 0x0 DEFINITION Destination Buffer Address Pointer. This value is the working value and will update as the operation proceeds. DESCRIPTION: This register shows the contents of the Destination Address register from the packet being processed. EXAMPLE: Empty Example. 16.3.14 DCP Work Packet 5 Status Register Description This register displays the values for the current work packet offset 0x14 (Buffer Size) field. HW_DCP_PACKET5 Table 16-39. HW_DCP_PACKET5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0D0 COUNT i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-35 Data Co-Processor (DCP) Table 16-40. HW_DCP_PACKET5 Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RO 0x0 DEFINITION Byte Count register. This value is the working value and will update as the operation proceeds. DESCRIPTION: This register shows the contents of the bytecount register from the packet being processed. The field can be considered either a byte count or a buffer size. The logic treats this as a decrmenting count of bytes from the buffer size programmed into the field. As the transaction proceeds, the logic will decrement the bytecount as data is written to the destination buffer. For blit operations, the top 16-bits of this field represents the number of lines (y size) in the blit and the lower 16-bits represent the number of bytes in a line (x size). EXAMPLE: Empty Example. 16.3.15 DCP Work Packet 6 Status Register Description This register displays the values for the current work packet offset 0x1C (Payload Pointer) field. HW_DCP_PACKET6 Table 16-41. HW_DCP_PACKET6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0E0 ADDR Table 16-42. HW_DCP_PACKET6 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RO 0x0 DEFINITION This regiser reflects the payload pointer for the current control packet. DESCRIPTION: This register shows the contents of the payload pointer fieldr from the packet being processed. EXAMPLE: Empty Example. 16.3.16 DCP Channel 0 Command Pointer Address Register Description The DCP channel 0 current command address register points to the multiword descriptor that is to be executed (or currently being executed). The channel may be activated by writing the command pointer address to a valid descriptor in memory and then updating the semaphore to a non-zero value. After the i.MX23 Applications Processor Reference Manual, Rev. 1 16-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) engine completes processing of a descriptor, the "next_ptr" field from the descriptor is moved into this register to enable processing of the next descriptor. All channels with a non-zero semaphore value will arbitrate for access to the engine for the subsequent operation. HW_DCP_CH0CMDPTR Table 16-43. HW_DCP_CH0CMDPTR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x100 ADDR Table 16-44. HW_DCP_CH0CMDPTR Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x00000000 DEFINITION Pointer to descriptor structure to be processed for channel 0. DESCRIPTION: DCP Channel 0 is controlled by a variable sized command structure. This register points to the command structure to be executed. EXAMPLE: HW_DCP_CHnCMDPTR_WR(0, v); // Write channel 0 command pointer pCurptr = (hw_DCP_chncmdptr_t *) HW_DCP_CHnCMDPTR_RD(0); // Read current command pointer 16.3.17 DCP Channel 0 Semaphore Register Description The DCP Channel 0 semaphore register is used to synchronize the CPU instruction stream and the DMA chain processing state. After a command chain has been generated in memory, software should write the address of the first command descriptor to the CMDPTR register and then write a non-zero value to the semaphore register to indicate that the channel is active. Each command packet has a chaining bit which indicates that another descriptor should be loaded into the channel upon completion of the current descriptor. If the chaining bit is not set, the next address will not be loaded into the CMDPTR register. Each packet also contains a "decrement semaphore" bit, which indicates that the counting semaphore should be decremented after the operation. A channel is considered active when the semaphore is a non-zero value. When programming a series operations, software must properly program the semaphore values in conjuction with the "decrement_semaphore" bits in the control packets to ensure that the proper number of descriptors are activated. A semaphore may be cleared by software by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. The logic will also clear the semaphore if an error has occurred. HW_DCP_CH0SEMA 0x110 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-37 Data Co-Processor (DCP) Table 16-45. HW_DCP_CH0SEMA 3 1 3 0 2 9 2 8 RSVD2 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 VALUE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RSVD1 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT 0 3 0 2 0 1 0 0 Table 16-46. HW_DCP_CH0SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 VALUE 15:8 7:0 LABEL RW RESET RO 0x0 RO 0x0 RO 0x0 RW 0x00 RSVD1 INCREMENT DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP channel decrements the count on the same clock, then the count is incremented by a net one. The semaphore may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. DESCRIPTION: Each DCP channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DCP chain processing. After processing each control packet, the DCP decrements the semaphore if it is non-zero. The channel will continue processing packets as long as the semaphore contains a non-zero value and the CHAIN or CHAIN_CONTIGOUS control bits in the Control0 field are set. EXAMPLE: Empty Example. 16.3.18 DCP Channel 0 Status Register Description The DCP Channel 0 Interrupt Status register contains the interrupt status bit and the tag of the last completed operation from the command chain. If an error occurs during processing, the ERROR bit is set and an interrupt is generated. HW_DCP_CH0STAT HW_DCP_CH0STAT_SET HW_DCP_CH0STAT_CLR HW_DCP_CH0STAT_TOG 0x120 0x124 0x128 0x12C i.MX23 Applications Processor Reference Manual, Rev. 1 16-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) Table 16-47. HW_DCP_CH0STAT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ERROR_CODE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 ERROR_DST 0 4 ERROR_SRC 0 3 ERROR_PACKET 0 2 ERROR_SETUP 0 1 HASH_MISMATCH 0 0 RSVD3 RSVD2 Table 16-48. HW_DCP_CH0STAT Bit Field Descriptions BITS 31:24 TAG LABEL RW RESET RO 0x00 RW 0x0 23:16 ERROR_CODE DEFINITION Indicates the tag from the last completed packet in the command structure Indicates additional error codes for some error conditions. NEXT_CHAIN_IS_0 = 0x01 Error signalled because the next pointer is 0x00000000 NO_CHAIN = 0x02 Error signalled because the semaphore is nonzero and neither chain bit is set CONTEXT_ERROR = 0x03 Error signalled because an error was reported reading/writing the context buffer PAYLOAD_ERROR = 0x04 Error signalled because an error was reported reading/writing the payload INVALID_MODE = 0x05 Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 15:7 6 5 RSVD3 RSVD2 ERROR_DST RO 0x0000 RW 0x0 RW 0x0 4 ERROR_SRC RW 0x0 3 ERROR_PACKET RW 0x0 2 ERROR_SETUP RW 0x0 Reserved, always set to zero. Program this field to 0x0. This bit indicates a bus error occurred when storing to the destination buffer. When an error is detected, the channel's processing will stop until the error handled by software. This bit indicates a bus error occurred when reading from the source buffer. When an error is detected, the channel's processing will stop until the error handled by software. This bit indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload. When an error is detected, the channel's processing will stop until the error is handled by software. This bit indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation. When an error is detected, the channel's processing will stop until the error is handled by software. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-39 RSVD1 TAG Data Co-Processor (DCP) Table 16-48. HW_DCP_CH0STAT Bit Field Descriptions BITS LABEL 1 HASH_MISMATCH RW RESET RW 0x0 DEFINITION The bit indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit. When an error is detected, the channel's processing will stop until the error is handled by software. This bit will always read 0 in the status register, but will be set to 1 in the packet status field after processing of the packet has completed. This was done so that software can verify that each packet completed properly in a chain of commands for cases when an interrupt is issued only for the last item in a packet. The completion bit for the channel is effectively the channel interrupt status bit. 0 RSVD1 RO 0x0 DESCRIPTION: The interrupt status register is updated at the end of each work packet. If the interrupt bit is set in the command packet's command field, an interrupt will be generated once the packet has completed. In addition, the tag value from the command is stored in the TAG field so that software can identify which command structure was the last to complete. If an error occurs, the ERROR bit is set and processing of the command chain is halted. EXAMPLE: Empty Example. 16.3.19 DCP Channel 0 Options Register Description The DCP Channel 0 Options Status register contains optional control information that may be used to further tune the behavior of the channel. HW_DCP_CH0OPTS HW_DCP_CH0OPTS_SET HW_DCP_CH0OPTS_CLR HW_DCP_CH0OPTS_TOG Table 16-49. HW_DCP_CH0OPTS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 RECOVERY_TIMER 0x130 0x134 0x138 0x13C 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSVD i.MX23 Applications Processor Reference Manual, Rev. 1 16-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) Table 16-50. HW_DCP_CH0OPTS Bit Field Descriptions BITS LABEL 31:16 RSVD 15:0 RECOVERY_TIMER RW RESET RO 0x0 RW 0x0 DEFINITION Reserved, always set to zero. This field indicates the recovery time for the channel. After each operation, the recover timer for the channel is initiallized with this value and then decremented until the timer reaches zero. The channel will not initiate another operation for the next packet in the chain until the recovery time has been satisfied. The timebase for the recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation. DESCRIPTION: The options register can be used to control optional features of the channels. EXAMPLE: Empty Example. 16.3.20 DCP Channel 1 Command Pointer Address Register Description The DCP channel 1 current command address register points to the multiword descriptor that is to be executed (or currently being executed). The channel may be activated by writing the command pointer address to a valid descriptor in memory and then updating the semaphore to a non-zero value. After the engine completes processing of a descriptor, the "next_ptr" field from the descriptor is moved into this register to enable processing of the next descriptor. All channels with a non-zero semaphore value will arbitrate for access to the engine for the subsequent operation. HW_DCP_CH1CMDPTR Table 16-51. HW_DCP_CH1CMDPTR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x140 ADDR Table 16-52. HW_DCP_CH1CMDPTR Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x00000000 DEFINITION Pointer to descriptor structure to be processed for channel 1. DESCRIPTION: DCP Channel 1 is controlled by a variable sized command structure. This register points to the command structure to be executed. EXAMPLE: HW_DCP_CHn_CMDPTR_WR(1, v); // Write channel 1 command pointer pCurptr = (hw_DCP_chn_cmdptr_t *) HW_DCP_CHn_CMDPTR_RD(1); // Read current command pointer i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-41 Data Co-Processor (DCP) 16.3.21 DCP Channel 1 Semaphore Register Description The DCP Channel 1 semaphore register is used to synchronize the CPU instruction stream and the DMA chain processing state. After a command chain has been generated in memory, software should write the address of the first command descriptor to the CMDPTR register and then write a non-zero value to the semaphore register to indicate that the channel is active. Each command packet has a chaining bit which indicates that another descriptor should be loaded into the channel upon completion of the current descriptor. If the chaining bit is not set, the next address will not be loaded into the CMDPTR register. Each packet also contains a "decrement semaphore" bit, which indicates that the counting semaphore should be decremented after the operation. A channel is considered active when the semaphore is a non-zero value. When programming a series operations, software must properly program the semaphore values in conjuction with the "decrement_semaphore" bits in the control packets to ensure that the proper number of descriptors are activated. A semaphore may be cleared by software by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. The logic will also clear the semaphore if an error has occurred. HW_DCP_CH1SEMA Table 16-53. HW_DCP_CH1SEMA 3 1 3 0 2 9 2 8 RSVD2 0x150 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 VALUE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RSVD1 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT 0 3 0 2 0 1 0 0 Table 16-54. HW_DCP_CH1SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 VALUE 15:8 7:0 LABEL RW RESET RO 0x0 RO 0x0 RO 0x0 RW 0x00 RSVD1 INCREMENT DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP channel decrements the count on the same clock, then the count is incremented by a net one. The semaphore may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. DESCRIPTION: Each DCP channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DCP chain processing. DCP processing continues until the engine attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DCP channel is stalled until software increments the semaphore count. i.MX23 Applications Processor Reference Manual, Rev. 1 16-42 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) EXAMPLE: Empty Example. 16.3.22 DCP Channel 1 Status Register Description The DCP Channel 1 Interrupt Status register contains the interrupt status bit and the tag of the last completed operation from the command chain. If an error occurs during processing, the ERROR bit is set and an interrupt is generated. HW_DCP_CH1STAT HW_DCP_CH1STAT_SET HW_DCP_CH1STAT_CLR HW_DCP_CH1STAT_TOG Table 16-55. HW_DCP_CH1STAT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ERROR_CODE 0x160 0x164 0x168 0x16C 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 ERROR_DST 0 4 ERROR_SRC 0 3 ERROR_PACKET 0 2 ERROR_SETUP 0 1 HASH_MISMATCH 0 0 RSVD3 RSVD2 Table 16-56. HW_DCP_CH1STAT Bit Field Descriptions BITS 31:24 TAG LABEL RW RESET RO 0x00 RW 0x0 23:16 ERROR_CODE DEFINITION Indicates the tag from the last completed packet in the command structure Indicates additional error codes for some error conditions. NEXT_CHAIN_IS_0 = 0x01 Error signalled because the next pointer is 0x00000000 NO_CHAIN = 0x02 Error signalled because the semaphore is nonzero and neither chain bit is set CONTEXT_ERROR = 0x03 Error signalled because an error was reported reading/writing the context buffer PAYLOAD_ERROR = 0x04 Error signalled because an error was reported reading/writing the payload INVALID_MODE = 0x05 Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 15:7 6 5 RSVD3 RSVD2 ERROR_DST RO 0x0000 RW 0x0 RW 0x0 4 ERROR_SRC RW 0x0 Reserved, always set to zero. Program this field to 0x0. This bit indicates a bus error occurred when storing to the destination buffer. When an error is detected, the channel's processing will stop until the error handled by software. This bit indicates a bus error occurred when reading from the source buffer. When an error is detected, the channel's processing will stop until the error handled by software. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-43 RSVD1 TAG Data Co-Processor (DCP) Table 16-56. HW_DCP_CH1STAT Bit Field Descriptions BITS LABEL 3 ERROR_PACKET RW RESET RW 0x0 DEFINITION This bit indicates that a bus error occurs when reading the packet or payload or when writing status back to the packet paylaod. When an error is detected, the channel's processing will stop until the error is handled by software. This bit indicates that the hardware detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation. When an error is detected, the channel's processing will stop until the error is handled by software. The bit indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit. When an error is detected, the channel's processing will stop until the error is handled by software. This bit will always read 0 in the status register, but will be set to 1 in the packet status field after processing of the packet has completed. This was done so that software can verify that each packet completed properly in a chain of commands for cases when an interrupt is issued only for the last item in a packet. The completion bit for the channel is effectively the channel interrupt status bit. 2 ERROR_SETUP RW 0x0 1 HASH_MISMATCH RW 0x0 0 RSVD1 RO 0x0 DESCRIPTION: The interrupt status register is updated at the end of each work packet. If the interrupt bit is set in the command packet's command field, an interrupt will be generated once the packet has completed. In addition, the tag value from the command is stored in the TAG field so that software can identify which command structure was the last to complete. If an error occurs, the ERROR bit is set and processing of the command chain is halted. EXAMPLE: Empty Example. 16.3.23 DCP Channel 1 Options Register Description The DCP Channel 1 Options Status register contains optional control information that may be used to further tune the behavior of the channel. HW_DCP_CH1OPTS HW_DCP_CH1OPTS_SET HW_DCP_CH1OPTS_CLR HW_DCP_CH1OPTS_TOG 0x170 0x174 0x178 0x17C i.MX23 Applications Processor Reference Manual, Rev. 1 16-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) Table 16-57. HW_DCP_CH1OPTS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 RECOVERY_TIMER 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 16-58. HW_DCP_CH1OPTS Bit Field Descriptions BITS LABEL 31:16 RSVD 15:0 RECOVERY_TIMER RW RESET RO 0x0 RW 0x0 DEFINITION Reserved, always set to zero. This field indicates the recovery time for the channel. After each operation, the recover timer for the channel is initiallized with this value and then decremented until the timer reaches zero. The channel will not initiate operation on the next packet in the chain until the recovery time has been satisfied. The timebase for the recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation. DESCRIPTION: The options register can be used to control optional features of the channels. EXAMPLE: Empty Example. 16.3.24 DCP Channel 2 Command Pointer Address Register Description The DCP channel 2 current command address register points to the multiword descriptor that is to be executed (or currently being executed). The channel may be activated by writing the command pointer address to a valid descriptor in memory and then updating the semaphore to a non-zero value. After the engine completes processing of a descriptor, the "next_ptr" field from the descriptor is moved into this register to enable processing of the next descriptor. All channels with a non-zero semaphore value will arbitrate for access to the engine for the subsequent operation. HW_DCP_CH2CMDPTR Table 16-59. HW_DCP_CH2CMDPTR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSVD 0x180 ADDR i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-45 Data Co-Processor (DCP) Table 16-60. HW_DCP_CH2CMDPTR Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x00000000 DEFINITION Pointer to descriptor structure to be processed for channel 2. DESCRIPTION: DCP Channel 2 is controlled by a variable sized command structure. This register points to the command structure to be executed. EXAMPLE: HW_DCP_CHn_CMDPTR_WR(2, v); // Write channel 2 command pointer pCurptr = (hw_DCP_chn_cmdptr_t *) HW_DCP_CHn_CMDPTR_RD(2); // Read current command pointer 16.3.25 DCP Channel 2 Semaphore Register Description The DCP Channel 2 semaphore register is used to synchronize the CPU instruction stream and the DMA chain processing state. After a command chain has been generated in memory, software should write the address of the first command descriptor to the CMDPTR register and then write a non-zero value to the semaphore register to indicate that the channel is active. Each command packet has a chaining bit which indicates that another descriptor should be loaded into the channel upon completion of the current descriptor. If the chaining bit is not set, the next address will not be loaded into the CMDPTR register. Each packet also contains a "decrement semaphore" bit, which indicates that the counting semaphore should be decremented after the operation. A channel is considered active when the semaphore is a non-zero value. When programming a series operations, software must properly program the semaphore values in conjuction with the "decrement_semaphore" bits in the control packets to ensure that the proper number of descriptors are activated. A semaphore may be cleared by software by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. The logic will also clear the semaphore if an error has occurred. HW_DCP_CH2SEMA Table 16-61. HW_DCP_CH2SEMA 3 1 3 0 2 9 2 8 RSVD2 0x190 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 VALUE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RSVD1 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT 0 3 0 2 0 1 0 0 Table 16-62. HW_DCP_CH2SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 VALUE LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. i.MX23 Applications Processor Reference Manual, Rev. 1 16-46 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) Table 16-62. HW_DCP_CH2SEMA Bit Field Descriptions BITS LABEL 15:8 RSVD1 INCREMENT 7:0 RW RESET RO 0x0 RW 0x00 DEFINITION Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP channel decrements the count on the same clock, then the count is incremented by a net one. The semaphore may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. DESCRIPTION: Each DCP channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DCP chain processing. DCP processing continues until the engine attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DCP channel is stalled until software increments the semaphore count. EXAMPLE: Empty Example. 16.3.26 DCP Channel 2 Status Register Description The DCP Channel 2 Interrupt Status register contains the interrupt status bit and the tag of the last completed operation from the command chain. If an error occurs during processing, the ERROR bit is set and an interrupt is generated. HW_DCP_CH2STAT HW_DCP_CH2STAT_SET HW_DCP_CH2STAT_CLR HW_DCP_CH2STAT_TOG Table 16-63. HW_DCP_CH2STAT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ERROR_CODE 0x1A0 0x1A4 0x1A8 0x1AC 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 ERROR_DST 0 4 ERROR_SRC 0 3 ERROR_PACKET 0 2 ERROR_SETUP 0 1 HASH_MISMATCH 0 0 RSVD3 RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-47 RSVD1 TAG Data Co-Processor (DCP) Table 16-64. HW_DCP_CH2STAT Bit Field Descriptions BITS 31:24 TAG LABEL RW RESET RO 0x00 RW 0x0 23:16 ERROR_CODE DEFINITION Indicates the tag from the last completed packet in the command structure Indicates additional error codes for some error conditions. NEXT_CHAIN_IS_0 = 0x01 Error signalled because the next pointer is 0x00000000 NO_CHAIN = 0x02 Error signalled because the semaphore is nonzero and neither chain bit is set CONTEXT_ERROR = 0x03 Error signalled because an error was reported reading/writing the context buffer PAYLOAD_ERROR = 0x04 Error signalled because an error was reported reading/writing the payload INVALID_MODE = 0x05 Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 15:7 6 5 RSVD3 RSVD2 ERROR_DST RO 0x0000 RW 0x0 RW 0x0 4 ERROR_SRC RW 0x0 3 ERROR_PACKET RW 0x0 2 ERROR_SETUP RW 0x0 1 HASH_MISMATCH RW 0x0 0 RSVD1 RO 0x0 Reserved, always set to zero. Program this field to 0x0. This bit indicates a bus error occurred when storing to the destination buffer. When an error is detected, the channel's processing will stop until the error handled by software. This bit indicates a bus error occurred when reading from the source buffer. When an error is detected, the channel's processing will stop until the error handled by software. This bit indicates that a bus error occurred when reading the packet or payload or when writing status back to the packet paylaod. When an error is detected, the channel's processing will stop until the error is handled by software. This bit indicates that the hardware detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation. When an error is detected, the channel's processing will stop until the error is handled by software. The bit indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit. When an error is detected, the channel's processing will stop until the error is handled by software. This bit will always read 0 in the status register, but will be set to 1 in the packet status field after processing of the packet has completed. This was done so that software can verify that each packet completed properly in a chain of commands for cases when an interrupt is issued only for the last item in a packet. The completion bit for the channel is effectively the channel interrupt status bit. DESCRIPTION: The interrupt status register is updated at the end of each work packet. If the interrupt bit is set in the command packet's command field, an interrupt will be generated once the packet has completed. In addition, the tag value from the command is stored in the TAG field so that software can identify which i.MX23 Applications Processor Reference Manual, Rev. 1 16-48 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) command structure was the last to complete. If an error occurs, the ERROR bit is set and processing of the command chain is halted. EXAMPLE: Empty Example. 16.3.27 DCP Channel 2 Options Register Description The DCP Channel 2 Options Status register contains optional control information that may be used to further tune the behavior of the channel. HW_DCP_CH2OPTS HW_DCP_CH2OPTS_SET HW_DCP_CH2OPTS_CLR HW_DCP_CH2OPTS_TOG Table 16-65. HW_DCP_CH2OPTS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 RECOVERY_TIMER 0x1B0 0x1B4 0x1B8 0x1BC 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 16-66. HW_DCP_CH2OPTS Bit Field Descriptions BITS LABEL 31:16 RSVD 15:0 RECOVERY_TIMER RW RESET RO 0x0 RW 0x0 DEFINITION Reserved, always set to zero. This field indicates the recovery time for the channel. After each operation, the recover timer for the channel is initiallized with this value and then decremented until the timer reaches zero. The channel will not initiate operation on the next packet in the chain until the recovery time has been satisfied. The timebase for the recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation. DESCRIPTION: The options register can be used to control optional features of the channels. EXAMPLE: Empty Example. RSVD i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-49 Data Co-Processor (DCP) 16.3.28 DCP Channel 3 Command Pointer Address Register Description The DCP channel 3 current command address register points to the multiword descriptor that is to be executed (or currently being executed). The channel may be activated by writing the command pointer address to a valid descriptor in memory and then updating the semaphore to a non-zero value. After the engine completes processing of a descriptor, the "next_ptr" field from the descriptor is moved into this register to enable processing of the next descriptor. All channels with a non-zero semaphore value will arbitrate for access to the engine for the subsequent operation. HW_DCP_CH3CMDPTR Table 16-67. HW_DCP_CH3CMDPTR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x1C0 ADDR Table 16-68. HW_DCP_CH3CMDPTR Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x00000000 DEFINITION Pointer to descriptor structure to be processed for channel 3. DESCRIPTION: DCP Channel 3 is controlled by a variable sized command structure. This register points to the command structure to be executed. EXAMPLE: HW_DCP_CHn_CMDPTR_WR(3, v); // Write channel 3 command pointer pCurptr = (hw_DCP_chn_cmdptr_t *) HW_DCP_CHn_CMDPTR_RD(3); // Read current command pointer 16.3.29 DCP Channel 3 Semaphore Register Description The DCP Channel 3 semaphore register is used to synchronize the CPU instruction stream and the DMA chain processing state. After a command chain has been generated in memory, software should write the address of the first command descriptor to the CMDPTR register and then write a non-zero value to the semaphore register to indicate that the channel is active. Each command packet has a chaining bit which indicates that another descriptor should be loaded into the channel upon completion of the current descriptor. If the chaining bit is not set, the next address will not be loaded into the CMDPTR register. Each packet also contains a "decrement semaphore" bit, which indicates that the counting semaphore should be decremented after the operation. A channel is considered active when the semaphore is a non-zero value. When programming a series operations, software must properly program the semaphore values in conjuction with the "decrement_semaphore" bits in the control packets to ensure that the proper number of descriptors are activated. A semaphore may be cleared by software by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. The logic will also clear the semaphore if an error has occurred. HW_DCP_CH3SEMA 0x1D0 i.MX23 Applications Processor Reference Manual, Rev. 1 16-50 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) Table 16-69. HW_DCP_CH3SEMA 3 1 3 0 2 9 2 8 RSVD2 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 VALUE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RSVD1 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INCREMENT 0 3 0 2 0 1 0 0 Table 16-70. HW_DCP_CH3SEMA Bit Field Descriptions BITS 31:24 RSVD2 23:16 VALUE 15:8 7:0 LABEL RW RESET RO 0x0 RO 0x0 RO 0x0 RW 0x00 RSVD1 INCREMENT DEFINITION Reserved, always set to zero. This read-only field shows the current (instantaneous) value of the semaphore counter. Reserved, always set to zero. The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP channel decrements the count on the same clock, then the count is incremented by a net one. The semaphore may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. DESCRIPTION: Each DCP channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DCP chain processing. DCP processing continues until the engine attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DCP channel is stalled until software increments the semaphore count. EXAMPLE: Empty Example. 16.3.30 DCP Channel 3 Status Register Description The DCP Channel 3 Interrupt Status register contains the interrupt status bit and the tag of the last completed operation from the command chain. If an error occurs during processing, the ERROR bit is set and an interrupt is generated. HW_DCP_CH3STAT HW_DCP_CH3STAT_SET HW_DCP_CH3STAT_CLR HW_DCP_CH3STAT_TOG 0x1E0 0x1E4 0x1E8 0x1EC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-51 Data Co-Processor (DCP) Table 16-71. HW_DCP_CH3STAT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ERROR_CODE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 ERROR_DST 0 4 ERROR_SRC 0 3 ERROR_PACKET 0 2 ERROR_SETUP 0 1 HASH_MISMATCH 0 0 RSVD3 RSVD2 Table 16-72. HW_DCP_CH3STAT Bit Field Descriptions BITS 31:24 TAG LABEL RW RESET RO 0x00 RW 0x0 23:16 ERROR_CODE DEFINITION Indicates the tag from the last completed packet in the command structure Indicates additional error codes for some error conditions. NEXT_CHAIN_IS_0 = 0x01 Error signalled because the next pointer is 0x00000000 NO_CHAIN = 0x02 Error signalled because the semaphore is nonzero and neither chain bit is set CONTEXT_ERROR = 0x03 Error signalled because an error was reported reading/writing the context buffer PAYLOAD_ERROR = 0x04 Error signalled because an error was reported reading/writing the payload INVALID_MODE = 0x05 Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 15:7 6 5 RSVD3 RSVD2 ERROR_DST RO 0x0000 RW 0x0 RW 0x0 4 ERROR_SRC RW 0x0 3 ERROR_PACKET RW 0x0 2 ERROR_SETUP RW 0x0 Reserved, always set to zero. Program this field to 0x0. This bit indicates a bus error occurred when storing to the destination buffer. When an error is detected, the channel's processing will stop until the error handled by software. This bit indicates a bus error occurred when reading from the source buffer. When an error is detected, the channel's processing will stop until the error handled by software. This bit indicates that a bus error occurred when reading the packet or payload or when writing status back to the packet paylaod. When an error is detected, the channel's processing will stop until the error is handled by software. This bit indicates that the hardware detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation. When an error is detected, the channel's processing will stop until the error is handled by software. i.MX23 Applications Processor Reference Manual, Rev. 1 16-52 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSVD1 TAG Data Co-Processor (DCP) Table 16-72. HW_DCP_CH3STAT Bit Field Descriptions BITS LABEL 1 HASH_MISMATCH RW RESET RW 0x0 DEFINITION The bit indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit. When an error is detected, the channel's processing will stop until the error is handled by software. This bit will always read 0 in the status register, but will be set to 1 in the packet status field after processing of the packet has completed. This was done so that software can verify that each packet completed properly in a chain of commands for cases when an interrupt is issued only for the last item in a packet. The completion bit for the channel is effectively the channel interrupt status bit. 0 RSVD1 RO 0x0 DESCRIPTION: The interrupt status register is updated at the end of each work packet. If the interrupt bit is set in the command packet's command field, an interrupt will be generated once the packet has completed. In addition, the tag value from the command is stored in the TAG field so that software can identify which command structure was the last to complete. If an error occurs, the ERROR bit is set and processing of the command chain is halted. EXAMPLE: Empty Example. 16.3.31 DCP Channel 3 Options Register Description The DCP Channel 3 Options Status register contains optional control information that may be used to further tune the behavior of the channel. HW_DCP_CH3OPTS HW_DCP_CH3OPTS_SET HW_DCP_CH3OPTS_CLR HW_DCP_CH3OPTS_TOG Table 16-73. HW_DCP_CH3OPTS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 RECOVERY_TIMER 0x1F0 0x1F4 0x1F8 0x1FC 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSVD i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-53 Data Co-Processor (DCP) Table 16-74. HW_DCP_CH3OPTS Bit Field Descriptions BITS LABEL 31:16 RSVD 15:0 RECOVERY_TIMER RW RESET RO 0x0 RW 0x0 DEFINITION Reserved, always set to zero. This field indicates the recovery time for the channel. After each operation, the recover timer for the channel is initiallized with this value and then decremented until the timer reaches zero. The channel will not initiate operation on the next packet in the chain until the recovery time has been satisfied. The timebase for the recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation. DESCRIPTION: The options register can be used to control optional features of the channels. EXAMPLE: Empty Example. 16.3.32 DCP Debug Select Register Description This register selects a debug register to view. HW_DCP_DBGSELECT Table 16-75. HW_DCP_DBGSELECT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 RSVD 0x400 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INDEX 0 3 0 2 0 1 0 0 Table 16-76. HW_DCP_DBGSELECT Bit Field Descriptions BITS 31:8 RSVD INDEX 7:0 LABEL RW RESET RO 0x00 RW 0x0 DEFINITION Reserved, always set to zero. Selects a value to read via the debug data register. CONTROL = 0x01 OTPKEY0 = 0x10 OTPKEY1 = 0x11 OTPKEY2 = 0x12 OTPKEY3 = 0x13 DESCRIPTION: This register selects debug information to return in the debug data register. EXAMPLE: Empty Example. 16.3.33 DCP Debug Data Register Description Reading this register returns the debug data value from the selected index. i.MX23 Applications Processor Reference Manual, Rev. 1 16-54 Preliminary--Subject to Change Without Notice Freescale Semiconductor Data Co-Processor (DCP) HW_DCP_DBGDATA Table 16-77. HW_DCP_DBGDATA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0x410 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DATA Table 16-78. HW_DCP_DBGDATA Bit Field Descriptions BITS 31:0 DATA LABEL RW RESET RO 0x0 DEFINITION Debug Data DESCRIPTION: This register returns the debug data from the selected debug index source. EXAMPLE: Empty Example. 16.3.34 DCP Version Register Description Read-only register indicating implemented version of the DCP. HW_DCP_VERSION Table 16-79. HW_DCP_VERSION 3 1 3 0 2 9 2 8 MAJOR 0x430 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 16-80. HW_DCP_VERSION Bit Field Descriptions BITS 31:24 MAJOR 23:16 MINOR 15:0 LABEL RW RESET RO 0x2 RO 0x0 RO 0x0 STEP DEFINITION Fixed read-onlyl value reflecting the MAJOR version of the design implementation. Fixed read-onlyl value reflecting the MINOR version of the design implementation. Fixed read-onlyl value reflecting the stepping of version of the design implementation. DESCRIPTION: This register returns the debug data from the selected debug index source. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 16-55 Data Co-Processor (DCP) DCP Block v2.0, Revision 1.57 The license for the AEC code is documented here for compliance: Copyright (C) 2000-2003, ASICS World Services, LTD., AUTHORS All rights reserved. Redistribution and use in source, netlist, binary and silicon forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of ASICS World Services, the Authors and/or the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE i.MX23 Applications Processor Reference Manual, Rev. 1 16-56 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 17 Pixel Pipeline (PXP) This chapter describes the pixel pipeline (PXP) included on the i.MX23 SoC and how to operate it. Programmable registers are described in Section 17.4, "Programmable Registers." 17.1 Overview The pixel pipeline is used to perform alpha blending of graphic or video buffers with graphics data before sending to an LCD display or TV encoder. The PXP provides a performance-optimized engine that can meet the needs of both SDRAM and SDRAM-less systems. The PXP also supports image rotation for hand-held devices that require both portrait and landscape image support. AXI APBH APBH Bridge/DMA PXP PXP Programmable Registers S0/ Colorspace /Scaling S0 Data S1/Overlay RGB RGB S1 RGB Data AXI Interface Control Logic Colorkey/ Alpha Blend RGB Rotation Buffers RGB Write Data Figure 17-1. Pixel Pipeline (PXP) Block Diagram i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-1 Pixel Pipeline (PXP) The PXP is organized as having a background image (S0) and one or more overlay images that can be blended with the background. Each overlay image must be a multiple of eight pixels in both height and width and the offset of the overlay into the background image must be a multiple of eight pixels. As the PXP processes data, it reads each 8x8 block from the background image and finds the highest priority (lowest numbered) overlay that is co-located at that block coordinate. The PXP then fetches the overlay and performs the alpha blending and color key operations on the two blocks. The resulting 8x8 pixel block is then written to the corresponding block in the output buffer. For the S0 plane, the PXP supports RGB images (unscaled) or colorspace conversion (YUV->RGB) and scaling of YUV images. The S1 plane consists of up to eight overlay regions consisting of 16 or 32-bit RGB data. The S0 and S1 planes may then be combined by alpha blending, color key substitution, or raster operations (ROPs) to form the output image. Finally the resulting image may be clock-wise rotated in 90 degree increments or flipped horizontally or vertically. The PXP also supports letterboxing and interlacing of progressive content (by writing alternate lines to different frame buffers). The flow of data through the PXP is shown in Figure 17-2. Overlay Overlay Overlay Overlay Overlay Overlay Overlay Overlay S1 RGB alpha blending/ color key S3 rotation Y U V Scaler CSC S0 Figure 17-2. Pixel Pipeline (PXP) Data Flow 17.1.1 * * * * * Image Support The PXP's S0 buffer supports the following image formats: 24-bit unpacked RGB (32bpp) 16-bit RGB in either 555 or 565 format 3-plane YUV/YCbCr in 4:2:0 or 4:2:2 format 32-bit RGB (with or without alpha) 16-bit RGB in either 555, 565, or 1555 (alpha) The PXP's S1 buffer supports the following image formats: i.MX23 Applications Processor Reference Manual, Rev. 1 17-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) The PXP's output buffer supports * 32-bit RGB (with alpha) * 24-bit packed RGB (24bpp) * 16-bit RGB in either 565, 555, or 1555 format Internally, all image data is handled as 32bpp data for all steps after the colorspace conversion. Input RGB images are always converted to the equivalent 32bpp format before processing. 17.1.2 * * * PXP Limitations/Issues * * * * The PXP's scalar uses a bilinear scaling algorithm and can scale YUV images from 0.5x to 4096x in 12-bit fractional steps. The default YUV coefficient register value is incorrect. The C2/C3 field values are reversed. When using the NEXT register, the interrupt enable setting should remain the same for all frames. If not, the PXP will change the interrupt enable register value and possibly cause the loss of an interrupt. The PXP cannot rotate/flip video in the interlaced modes. When performing input interlacing, the input image and overlays must be multiples of 8x16 pixels. Overlays must also reside on 8x16 boundaries. The PXP will support images up to 1024 pixels in either the X or Y coordinates. The PXP does not support inplace processing when rotation is enabled. 17.2 Operation The PXP operates by rendering the output frame buffer in 8x8 pixel macroblocks in display order (left to right, then top to bottom). At each output macroblock location the PXP determines whether the S0 buffer is visible based on the cropping register and S0 offset parameters. If the S0 plane is visible, the PXP will fetch and process the required data from the S0 image, otherwise the S0's contribution to the output macroblock will be the S0BACKGROUND register value. This value is effectively the color of the letterboxed region or background color. The PXP will also determine if an overlay is present for that macroblock location, and if so, instruct the S1 buffer to fetch the required data. If multiple overlays cover the macroblock, the PXP will select only the lowest numbered overlay and direct the S1 buffer to load the data for this overlay. For areas with no overlays the S1 buffer contributes nothing to the rendered image. Figure 17-3 shows the order in which the output blocks are generated (blocks 0, 1, 2) and indicates how various blocks are rendered (blocks A-E). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-3 Pixel Pipeline (PXP) rgb_width S0_yoffset 0 1 2 8x8 macroblock rendering order S0_xoffset B A C OL1 crop_height rgb_height D OL0 E S0 image crop_width Background (letterbox) region 0,1,2: Pixel blocks rendered with the background color . The numbering and arrow indicate the order of macroblock rendering . A: S0 Image rendered B: Overlay 1 blended with background C: Overlay 1 blended with S0 image D: Overlay 0 blended with S0 image E: Overlay 0 blended with S0 image (OL0 takes precedence over OL1) Figure 17-3. Pixel Pipeline (PXP) Macro Blocks It is important to understand how the PXP renders each output macroblock to properly understand how it accomplishes cropping, letterboxing, and overlay blending. The following sections will provide more details on these operations. The PXP also has the ability to rotate/flip images for cases when the pixel scan order is not in the traditional left-to-right/top-to-bottom raster scan (landscape raster). This can occur when a handheld device with a traditional landscape scan is rotated into a portrait orientation (in which the scan order is now bottom-to-top/left-to-right or vice versa) or when a cell phone oriented display (portrait raster) is rotated into a landscape orientation for viewing videos. In these cases, the PXP still renders the image in scan-order format (as sent to the device), but it will traverse the input images based on the transformations required. The following sections detail each of the PXP's functional capabilities. 17.2.1 Pixel Handling All pixels are internally represented as 24-bit RGB values with an 8-bit alpha value at all stages in the PXP after the colorspace converter. Input pixels are converted into this format using the following rules: * * * 32-bit ARGB8888 pixels are read directly with no conversion for both the S0 and overlay images. 32-bit RGB888 pixels are assumed to have an alpha value of 0xFF (full opaque). 16-bit RGB565 and RGB555 values are expanded into the corresponding 24-bit colorspace and assigned an alpha value of 0xFF (opaque). The expansion process replicates the upper pixel bits i.MX23 Applications Processor Reference Manual, Rev. 1 17-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) * into the lower pixel bits (for instance a 16-bit RGB565 triplet of 0x1F/0x20/0x07 would be expanded to 0xFF/0x82/0x39). 16-bit RGB1555 values are expanded into the corresponding 24-bit colorspace and assigned an alpha value of either 0x00 or 0xFF, based on the 1-bit alpha value in the pixel. The ALPHA_MULTIPLY function is useful in this scenario to allow scaling of the opaque pixels to a semi-transparent value. Output pixels will retain the effective alpha value of the overlay or can be set to a programmed alpha value using the ALPHA field of the S0PARAM register. 16-bit pixels values are formed from the most significant bits of the 24-bit pixel values. 17.2.2 S0 Cropping/Masking The PXP's cropping operation should be viewed as a mask on the output image through which the background S0 plane can be viewed. Using this definition clarifies a subtlety on the usage of cropping an image when the image is scaled. When scaling is not used, the input and output image sizes are the same, thus the operation is analogous to cropping the input source image. The background output image can be cropped to a width and height independent of the image size at a given offset into the image (all sizes are in terms of 8 pixel units) using the values in the S0CROP register. The XBASE and YBASE provide the coordinates of the first block to be displayed from the source image and the WIDTH and HEIGHT parameters specify an effective size of the resulting image in the output buffer. Cropping must be enabled by setting the CROP bit in the CTRL register to a 1. When not set, the visible portions of the S0 image will be rendered based on the WIDTH and HEIGHT specified in the S0SIZE field. Figure 17-4 indicates how the various cropping parameters relate to the source and RGB images (non-scaled case). S0 width clip ybase s0 xbase RGB width s0 ybase clip xbase S0 height clip height clip height clip width clip width RGB Buffer S0 Buffer Figure 17-4. Pixel Pipeline (PXP) Cropping It is important to note that when scaling an image, software must specify a valid cropping region since the PXP will default to using the source image size. When downscaling, this is not an issue, but with i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-5 RGB height Pixel Pipeline (PXP) upscaling the resulting image will be a scaled up version of the source, but cropped to the same size as the source image as shown in Figure 17-5. 320 240 When upscaling, the CROP register should be used to properly mask the resulting scaled image. Boundary of rendered image 480 Resulting image when upscaling if the CROP register is not used (default cropping is based on input image size) 320 240 Source Image 640 Resulting image when CROP register is programmed to the RGB Buffer size (CTRL_CROP=1, CROP_XBASE=0, CROP_YBASE=0 CROP_WIDTH=RGB Width CROP_HEIGHT=RGB Height) Figure 17-5. Pixel Pipeline (PXP) Scaling and Cropping Example The cropping extents should fall completely within the S0 buffer to avoid displaying incorrect data. The PXP hardware does not check for these conditions and will render the image as shown in the following two diagrams. (Note that the cropping width and height can be viewed as applying to the input buffer only because it is not scaled. In actuality, it is applied to the output buffer). i.MX23 Applications Processor Reference Manual, Rev. 1 17-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) S0 width S0 Buffer s0 xbase crop ybase RGB width s0 ybase crop width S0 height crop height crop xbase crop width crop height RGB Buffer If the clipping extents fall outside the S0 buffer (vertically), data beyond the S0 buffer will be fetched when rendering the S0 plane. S0 width S0 Buffer s0 xbase crop ybase RGB width s0 ybase crop width S0 height crop height crop xbase crop width crop height data aliases to here RGB Buffer If the clipping area extends outside the S0 buffer in the horizontal direction, the data read will effectively "wrap" to the next lines in the S0 buffer. Figure 17-6. Invalid PXP Cropping Examples 17.2.3 Scaling The PXP can scale YUV images from 1/2x to about 4096x (although the upper range is technically unlimited) using a bilinear scaling algorithm. The hardware is capable of scaling with 12-bit fractional resolution, or in 1/4096th pixel increments with independent scaling ratios for the X and Y direction. The scaler also implements an initial offset, which can be useful when scaling by powers of 2 in order to ensure that the resulting pixels are averages of the source pixels instead of producing a decimated or replicated image. The scaling parameter is specified to the hardware in terms of the inverse of the scaling ratio desired. This can also be viewed as the step size between computed sample values. For instance, when scaling by 2x the inverse is 1/2, thus the scaler will increment by 1/2 pixel steps across the input image and compute the bilinear average for each sample point. The scaling values are represented by 12-bit fractional values in the scaling register and hardware. The scaling ratios are computed as the input size divided by the output size. The resulting decimal value must then be converted into a 12-bit fixed point value by multiplying by 212 or 4096 to produce the value programmed into the scaling registers. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RGB height RGB height 17-7 Pixel Pipeline (PXP) To scale an image from 400x300 to 320x200, the horizontal XSCALE factor is computed as Input Size 400 XSCALE = --------------------------- x 4096 = -------- x 4096 = 1.25 x 4096 = 0x1400 Output Size 320 The vertical YSCALE can be similarly computed as Input Size 300 YSCALE = --------------------------- x 4096 = -------- x 4096 = 1.5 x 4096 = 0x1800 Output Size 200 The scaler will use the CROP_XBASE and CROP_YBASE values as an offset into the source S0 image for the origin of the input image to be scaled. The CROP_WIDTH and CROP_HEIGHT parameters will be used to determine the extent of the scaled image in the output buffer. It is tempting to view the cropping width and height as being applied to the input buffer, but this is incorrect -- the PXP uses these values as a mask on the output buffer to determine which regions of the output buffer require data from the scaled input image. To enable scaling, the HW_PXP_CTRL_SCALE bit must be set and the desired scaling ratios written into the HW_PXP_S0SCALE registers. Initial offsets should be programmed into the HW_PXP_S0OFFSET register. 17.2.3.1 Scaling Operation The scaling engine operates on YUV (or YCbCr) 422 or 420 formatted pixels. The scaled output image is presented to the CSC module as YUV444 pixels with a single byte for each the Y, U, and V channels. The scaler can reduce an input image by a maximum factor of 2. In this case, the output image will be 1/2 the dimension of the input image in each of the X and Y axis. There are no limits, essentially, on increasing the source image size. The theoretical maximum increase is 4096 since a 12 bit fractional step function is used when scaling an input image. Scaling in either axis, X or Y is independent, so a source image can appear stretched in either direction. All source images using YUV/YCbCr pixels must pass through the scale engine. The PXP alpha blend module and Overlay pixel streams are in the RGB888 format, so S0 pixel buffers must be converted to the RGB888 format for alpha blending, the final transform just before rotation. Even when the S0 image is passed without scaling, or 1:1 scaling is selected, the scaling engine is required to convert the incoming pixels from 422/420 format to YUV444. This is the format required by the CSC engine to convert to the RGB color space, The scaling engine works with the CSC module to translate YUV/YCbCr pixel formats to RGB888 for output frame buffer compositing using the alpha blender. NOTE RGB S0 source images cannot use the scaling engine. Scaling is not supported on RGB pixel formats and the scale and CSC modules are bypassed in this case. i.MX23 Applications Processor Reference Manual, Rev. 1 17-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) 17.2.3.1.1 Bilinear Image Scaling Filter The PXP implements a bilinear scaling filter to resize an input image to a different resolution for display output. The bilinear filter is a weighted average of the four nearest pixels that can be sourced to approximate the pixel in the output frame buffer. To compute the output pixel value at position as indicated by P, consider the diagram in Figure 17-7. 4 source image pixel: p00, p1 0, p01, p11 p00 Px0 p10 Figure 17-7. Computing Pixel Value in Output Frame Buffer A step function is used to indicate the position of the pixel "P" in the output frame. This position may not coincide with a single pixel position in the input frame buffer. In this case, the four closest pixels in the input frame are used to approximate the value of the pixel in the output frame. The PXP scaler first computes a linear filter in the X axis to create the two intermediate pixel values Px0 and Px1. The step function's X fractional component is used to provide the weighting factor for blending p00 with p10 to provide Px0. Likewise, Px1 is also derived from a linear filter using p01 and p11. The equations for Px0 and Px1 are as follows: Px0 = p00*(1-Rx) + p10*Rx Px1 = p01*(1-Rx) + p11*Rx The PXP scaler uses the intermediate X pixels Px0 and Px1 and implements a bilinear filter on these two pixel values to produce the final pixel value at position P. The remainder of the step function for the Y axis is used to compute the weighted average pixel result. The equation for the final filtered pixel follows: P = Px0*(1-Ry) + Px1*Ry i.MX23 Applications Processor Reference Manual, Rev. 1 Ry P 1 destina tion image p ixe l: P, bilin ear filter (1-Ry) p01 Px1 p11 Rx (1-Rx) Eqn. 17-1 Eqn. 17-2 Eqn. 17-3 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-9 Pixel Pipeline (PXP) 17.2.3.1.2 YUV 4:2:2 Image Scaling Figure 17-8 illustrates the positioning of YUV samples for the 4:2:2 formats. There are twice as many Y luma samples as U and V chroma samples horizontally. Pixel Column 0 0 Ps 1 Scan Lines 2 1 2 3 4 5 3 Y, U, V Sampl e Y Sample Only Figure 17-8. YUV Samples for 4:2:2 Formats Consider the scaled output pixel Ps (pixel scaled) which has an accumulated step function of X=1.5 and Y=0.5. The remainder for the step function is Rx = 0.5 and Ry = 0.5. Or, the sub pixel position of output pixel Ps is half way between line 0 and 1 and half way between column 1 and 2. The Y output component of Ps is simply the bilinear function of the four nearest Y samples from the input image. Specifically, the Y values at [1,0], [2,0], [1,1], and [2,1] are used to compute the Y for Ps. For the U and V components of Ps, there are no samples present in the column position 1. The bilinear filter uses chroma components located at [0,0], [2,0], [0,1] and [2,1]. Since the chroma components are not sub sampled vertically, the remainder used to combine pixels vertically is Ry=0.5 (the same as for Y). However, horizontally, the scaling engine shifts the remainder by a factor of 2. So an X axis step function value of X=1.5 has a remainder Rx=0.75. Source chroma values are not replicated, they are completely interpolated using the four nearest chroma samples to approximate U and V at Ps. i.MX23 Applications Processor Reference Manual, Rev. 1 17-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) 17.2.3.1.3 YUV 4:2:0 Image Scaling Figure 17-9 illustrates the positioning of YUV samples for the 4:2:0 formats. Chroma is sub sampled both horizontally and vertically. In this format, the chroma frame buffers contain 1/4 the data that the luma frame buffers store. Pixel Column 0 0 Chro ma Shift /Copy 1 Scan Lines 2 Ps 1 2 3 4 5 3 U, V Sample Y Sample Only Figure 17-9. YUV Samples for 4:2:0 Formats The Y output component for all scaled pixels in 4:2:0 formats are the same as for the 4:2:2 pixel formats. The U and V output components have two considerations when computing the output pixel Ps. 1. All chroma samples from the input source image are shifted left and up by 1/2 a sample position of the input pixel matrix. 2. Odd scan lines are replicated using the previous even chroma scan line values. So, output image chroma values that map between even to odd scan lines are replicated in the vertical axis. In contrast, output image chroma values between odd to even scan lines are interpolated vertically. The chroma values are interpolated horizontally as in the 4:2:2 pixel format. As an example, consider the interpolated pixel Ps in the 4:2:0 diagram above. For the Y component, the interpolated output luma is a function of the Y values in the source frame buffer at position [1,0], [2,0], [1,1], [2,1]. For the U and V interpolated samples, the chroma values on scan line position 0.5 are shifted so that they coincide with the even luma sample points. They are also replicated so that a single chroma scan line is used twice. The chroma scan line at 0.5 is replicated to represent the 4:2:2 sample points for scan line 0 and 1. The chroma scan line at 2.5 is replicated to represent the 4:2:2 sample points for scan line 2 and 3. This pattern of chroma replication occurs for the entire source frame buffer during the scaling operation. Figure 17-10 has two examples for the computation of the scaled chroma output pixel. For chroma at output position PsA (vertical position 0.5), interpolation occurs in the X axis using chroma values at col- i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-11 Pixel Pipeline (PXP) umn 0 and column 2. However, since line 0 and line 1 have equal chroma values due to chroma line replication, scaling in the Y axis results in replication of chroma values. Pixel Column 0 Ch roma shift/copy to line 0,1 0 PsA 0.5 1 PsB Scan Lines 2 2.5 1.5 1 2 3 Figure 17-10. Examples for Scaled Chroma Output Pixel For chroma at output position PsB (vertical position 1.5), interpolation occurs in both the X and Y axis. The Y axis is an interpolation since the chroma values for scan line 1 and 2 and not replicated respectfully. In summary, any output image pixels that map to an odd scan line above and an even scan line below are interpolated vertically. Output image pixels that map to an even scan line above and an odd scan line below are replicated vertically. 17.2.3.1.4 Out-of-Range Image Access An important note with respect to the scaling engine is that there are no provisions for accessing data that is out of range with respect to the source image. Under some circumstances (even typical use scenarios), it would appear that the data should exist. The important note is that the resolution of the Y luma plane is not the same as the resolution of the U and V chroma planes. Also, all pixels are interpolated horizontally with respect to their nearest neighbors. Figure 17-11. Scan Line Sample Positions i.MX23 Applications Processor Reference Manual, Rev. 1 17-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) An easy example of this would be sourcing an 8x8 YUV 422 input image and displaying it as an 8x8 output image. In this scenario, an obvious but incorrect scaling ratio would be 1:1. Horizontally, there are 8 Y values and only 4 chroma values. In a given scan line, there are Y samples at positions 0 - 7 as indicated in Figure 17-11. Also, the 4 UV samples are at positions 0, 2, 4, and 6. A UV sample does not exist at position 7. The scaling engine will interpolate the UV sample at position 7 from the UV sample at position 6 and 8. From Figure 17-11, it can be observed that position 8 is not a valid sample for the displayed scan line. The step function would be initialized to 0 to interpolate the pixel at position 0. The step function would increment 7 times thereafter to produce 8 output pixels as follows: Step 0: 100% Y0, 100% U0V0 Step 1: 100% Y1, 50% U0V0, 50% U2V2 Step 2: 100% Y2, 100% U2V2 Step 3: 100% Y3, 50% U2V2, 50% U4V4 Step 4: 100% Y4, 100% U4V4 Step 5: 100% Y5, 50% U4V4, 50% U6V6 Step 6: 100% Y6, 100% U6V6 Step 7: 100% Y7, 50% U6V6, 50% U8V8 Since the resolution of the UV plane is half of the Y plane, there are valid UV samples at pixel position 0, 2, 4, and 6. At pixel position 7, the final pixel is interpolated with a UV value that apparently does not exist in position 8 for this provided S0 image. An artifact could be visible when programming the scale engine to scale 1:1 for this simple example. The UV data at position 8 is likely the first UV sample on the next line. Interpolating the pixel at (x,y) = 7,0 using the UV sample at 0,1 likely would produce an artifact on the right side of the "scaled" image. "Scaled" is quoted in this case, since the scale factor is 1:1 which is used to convert the YUV422 input image to YUV444 in preparation for color space conversion. There are several methods to compensate for this anomaly. Also, similar cases of scaling factors that are not equal to 1:1 could produce a similar scenario on the bottom horizontal line of pixels. The user should take care to understand the nature of the source image data and the scaling algorithm implemented in the PXP to account for potential out of range image access. 17.2.4 Colorspace Conversion The CSC module receives scaled YUV/YCbCr444 pixels from the scale engine and converts the pixels to the RGB888 color space. These pixels are loaded into the pixel FIFO for processing by the alpha blend module. The following equations are used to perform YUV/YCbCr -> RGB conversion. The constants will be stored in the PXP control registers as two's compliment values to allow flexibility in the implementation and to allow for differences in the video encode and decode operations. In addition, this provides a software mechanism to manipulate brightness or contrast. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-13 Pixel Pipeline (PXP) R = C0(Y+Yoffset) + C1(V+UVoffset) G = C0(Y+Yoffset) + C3(U+UVoffset) + C2(V+UVoffset) B = C0(Y+Yoffset) + C4(U+UVoffset) Note: In the equations above, U and V are synonymous with Cb and Cr in regards to the color space format of the source frame buffer. Since UV values have been converted into an unsigned integer representation before entering the scaler, the Coffset for both UV and CbCr modes should be 0x180 (-0x80 or -128). Saturation of each color channel is checked and corrected for excursions outside the nominal YUV/YCbCr color spaces. Overflow for the three channels are saturated at 0x255 and underflow is saturated at 0x00. Table 17-1 indicates the expected coefficients for YUV and YCbCr modes of operation: Table 17-1. Coefficients for YUV and YCbCr Operation Coefficient YUV YCbCr Yoffset UVoffset C0 C1 C2 C3 C4 0x000 0x180 (-128) 0x100 (1.00) 0x123 (1.140) 0x76B (-0.581) 0x79B (-0.394) 0x208 (2.032) 0x1F0 (-16) 0x180 (-128) 0x12A (1.164) 0x198 (1.596) 0x730 (-0.813) 0x79C (-0.392) 0x204 (2.017) By default, the PXP colorspace coefficients are set to support the conversion of YUV data to RGB data. If YCbCr input is present, software must change the coefficient registers appropriately (see the register definitions for values). Software must also set the YCBCR_MODE bit in the COEFF0 register to ensure proper conversion of YUV versus YCBCR data. 17.2.5 Overlays The PXP supports up to eight overlays that can be used to merge graphic data with video (or other graphic data). Each overlay consists of a rectangular area that is a multiple of eight pixels in both the vertical and horizontal directions. Overlays must also be located on 8x8 boundaries within the output image. As the PXP processes each 8x8 macroblock, it determines if any of the enabled overlays cover the block and then merges the overlay data with the background image as specified in the overlay's control registers. If multiple overlays overlap for a given 8x8 block, the PXP will select the lowest numbered one for the blending operation. If the desired affect is to blend the overlays together, this can be accomplished as a multi-step process using the IN_PLACE functionality (see Section 17.2.10, "In-place Rendering") i.MX23 Applications Processor Reference Manual, Rev. 1 17-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Output Buffer 0,0 1,0 2,0 3,0 4,0 5,0 0,1 1,1 2,1 3,1 4,1 5,1 0,2 1,2 S0 Buffer WIDTH=6 2,2 HEIGHT=3 3,2 XBASE=0 YBASE=1 OL2 WIDTH=1 HEIGHT=5 4,2 XBASE=4 YBASE=0 5,2 0,3 1,3 OL0 WIDTH=2 HEIGHT=2 XBASE=1 YBASE=3 2,3 OL1 3,3 4,3 WIDTH=4 HEIGHT=1 XBASE=2 YBASE=3 5,3 0,4 1,4 2,4 3,4 4,4 5,4 Background Color The S0 buffer and each overlay can be placed within the output buffer using their XBASE and YBASE registers and the dimensions of each region are set using their WIDTH and HEIGHT parameters. Overlay 0 has the highest priority (effectively it is the highest in the stacking order) and the S0 buffer and background color have the lowest priority. Overlays can be blended with the background or S0 planes, but not with each other. Effectively only a single overlay is active for each 8x8 pixel block. Figure 17-12. Pixel Pipeline Overlay Support Each overlay can perform one of three classes of operations between the overlay and the underlying background (S0) image: alpha blending, color keying, or raster operations. An overlay can be enabled by writing the address of the overlay image to the OLn register, the overlay's size and location information into the OLnSIZE register, and then setting the OLnPARAM_ENABLE bit. The OLnPARAM registers also contain further controls to select the modes of operation (below). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-15 Pixel Pipeline (PXP) 17.2.6 Alpha Blending The alpha value for an individual pixel represents a mathematical weighting factor applied to the S1 pixel. An alpha value of 0x00 corresponds to a transparent pixel and a value of 0xFF corresponds to an opaque pixel. The effective alpha value for an overlay pixel is determined by the ALPHA bit-field and the two ALPHA control bits in the OLnPARAM register. If the ALPHA_CTRL field is set to ALPHA_OVERRIDE, the alpha value for the pixel is taken from the ALPHA bit-field. This can be useful for applying a constant alpha to an entire image or for image formats that don't include an alpha value. If ALPHA_MULTIPLY is selected, the pixel's alpha value will be multiplied by the ALPHA value in order to allow scaling of the pixel's alpha or to provide better control for pixel formats such as RGB1555, which only contains a single bit of alpha. For each color channel, the equation used to blend two source pixels is defined below: E = Embedded alpha associated with S1 pixel = G x E + 0x80 G = PIO programmed global alpha (8-bit value) The result for the red channel as an example * Y r [ 7:0 ] = ( x S1.r ) + ( ( 1 - ) x S0.r ) When alpha is 0xff, the S1 pixel will not be blended with S0, but S1 will be passed as the output pixel and will not be blended with S0. In this case, S0 will be discarded. Likewise, if alpha is 0x00 for a given pixel, S0 will be loaded as the output pixel. Alpha values in the overlays are loaded from the source image for all pixel formats. For formats that do not support an alpha value, the pixel is assigned an alpha value of 0xFF (opaque). This can be modified by the overlay processing by setting either the ALPHA_MULTIPLY or ALPHA_OVERRIDE bit in the associated OLnPARAM register. 17.2.7 Color Key Pixels may be made transparent to the corresponding overlay by using the S0 colorkey registers. If an S0 pixel matches the range specified by the S0COLORKEYLOW and S0COLORKEYHIGH registers, the pixel from the associated overlay will be displayed. If no overlay is present for that block, a black pixel will be generated since the default overlay pixel is 0x00000000 (transparent black pixel). The most common use for this is when a bitmap does not support an alpha-field or for applications such as "green screen" where an image is substituted for a solid background color as shown in Figure 17-13. i.MX23 Applications Processor Reference Manual, Rev. 1 17-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Figure 17-13. Pixel Pipeline (PXP) Colorkey Example The green portion of the overlay image can be colorkeyed to display the contents of the S0 buffer for locations that match the color range. For this example, the color range is OL COLORKEY: 00 17.2.8 Raster Operations (ROPs) In addition to alpha blending and color keying, the PXP's alpha blender also supports a set of raster operations that may be performed between the active overlay and the background image. The operations are done on a per-pixel basis and are performed using the 24-bit overlay and background image values. The following table lists the supported ROP operations : Table 17-2. Supported ROP Operations Mnemonic Value Operation MASKOL MASKNOTOL MASKOLNOT MERGEOL MERGEOLNET MERGEOLNOT 0x0 0x1 0x2 0x3 0x4 0x5 i.MX23 Applications Processor Reference Manual, Rev. 1 OL & S0 ~OL & S0 OLL & ~S0 OL | S0 ~OL | S0 OL | ~S0 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-17 Pixel Pipeline (PXP) Table 17-2. Supported ROP Operations (continued) Mnemonic Value Operation NOTCOPYOL NOT NOTMASKOL NOTMERGEOL XOROL NOTXOROL 0x6 0x7 0x8 0x9 0xA 0xB ~OL ~S0 ~(OL & S0) (nand) ~(OL | S0) (nor) OL ^ S0 (xor) ~(OL ^ S0) (xnor) These operations are specified in the overlay's PARAM register and must be enabled by setting the ALPHA_CTRL field to ROPs. 17.2.9 Rotation Rotation is an inherently inefficient operation, especially for a graphics device operating in a raster-scan fashion since the resulting memory fetches would be non-contiguous. The PXP solves this problem by operating on 8x8 pixel blocks. This allows the PXP to rotate a subportion of the image, where it can fetch 8 lines of pixels, process them, and then write 8 lines of pixels regardless of the rotation orientation. Rotation is mainly useful for reorganizing the frame buffer for handheld LCD displays for cases when the user rotates the device from a portrait to landscape orientation. Consider the following scenario: Raster Scan Direction On Screen Text Display On Screen Text Display Landscape Format Raster Scan Direction Portrait Format Figure 17-14. Pixel Pipeline (PXP) Rotation Example 1 While this looks like a trivial operation, consider what the frame buffer must look like in memory before being sent to the LCD in raster-scan format i.MX23 Applications Processor Reference Manual, Rev. 1 17-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Raster Scan Direction Figure 17-15. Pixel Pipeline (PXP) Rotation Example 2 Not only must the image be rotated, but any on-screen graphics must also be rendered in a different orientation. By building rotation into the rendering process, the PXP allows software to construct the image in the traditional portrait format and simply rotate the image/overlays for the LCD interface during composition. The rotation operations are defined as rotations in a clockwise direction and the flip operations will flip the pixels in the specified direction. On Screen Text Display Portrait Format Frame Buffer Vertical Flip 270 Rotation Figure 17-16. Pixel Pipeline (PXP) Rotation and Flip Definition i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice no081 R it a o t 90 Rotation Source Image Horizontal Flip 17-19 Pixel Pipeline (PXP) The PXP supports rotation in 90 degree increments as well as horizontal and vertical flip operations. These can be done in any combination (for example, 90 degree rotation with both vertical and horizontal flip). When a flip operation is specified in combination with a rotation operation, the PXP will render the output such that the effect of the flip operation(s) occur BEFORE the rotation operation. Horizontal Flip Rotate 90 Figure 17-17. Pixel Pipeline (PXP) Rotation Plus Flip Definition Rotations and flip operations are enabled by setting the VFLIP, HFLIP, and ROTATE fields of the HW_PXP_CTRL register. 17.2.10 In-place Rendering The PXP also has the ability to process an image and write the resulting buffer back to the original S0 buffer. This is referred to as "in place" rendering. This scenario may be useful when software wishes to alpha blend multiple images where the overlays effectively overlap each other. When the IN_PLACE control bit is set to 1, the control logic will optimize the PXP's operations to only process the blocks that match an overlay region since all other pixels will be unmodified. This considerably reduces processing time as well as memory bandwidth used. In place rendering is enabled by setting the IN_PLACE bit in the HW_PXP_CTRL registers. Note the following restrictions when rendering in place: * * The source buffer is used as the destination buffer (RGBBUF is not used), Only RGB S0 images are supported (not YUV) i.MX23 Applications Processor Reference Manual, Rev. 1 17-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) * The output RGB format must be programmed to the same value as the input RGB format. 17.2.11 Interlaced Video Support The PXP has some minimal ability to generate interlaced video content from a progressive source. There are two available options, based on the bandwidth requirements and how software is managing video frames. The PXP can either interlace on the input side (by reading every other line of input data) or on the output side (by writing the individual lines of video into two separate fields). Generally, output interleaving should be used since it is the most flexible mode (it allows scaling and full overlay support) and it only requires a single pass of the PXP to generate two separate output fields. Input interleaving can be beneficial in cases where the PXP is running at 60fps, since it requires fewer fetches to produce the output data. The PXP will perform input interlacing when the INTERLACED_INPUT field is programmed to either FIELD0 or FIELD1 (to select the desired field). When performing output interlacing, the PXP will write field0 data to the RGBBUF pointer and the field1 data to the RGBBUF2 pointer. The OUTPUT_INTERLACING field of the HW_PXP_CTRL register controls which of these fields (or both) are generated. 17.2.12 Queueing Frame Operations The PXP supports a primitive ability to queue up one operation while the current operation is running. This is enabled through the use of the HW_PXP_NEXT register. When this register is written, it enables the PXP to reload its current register contents with the data found at the location pointed to by this address (when it completes processing of the current frame. This feature may be useful in helping to reduce the interrupt latency in servicing the PXP. If the PXP is idle when the HW_PXP_NEXT register is written, the PXP treats this as an indication that it should immediately load the values at the pointer and begin processing the frame. This ability should allow software to use the same routines when programming the PXP (so that the first frame doesn't differ from subsequent frames). When loading values from the NEXT register, nearly all registers in the PXP are reloaded, including the interrupt enable bit in the control register. It is recommended that the interrupt enable value not be changed when using queued operations to ensure that interrupts are not spuriously lost or generated. The following table indicates the registers that are affected and the offset into the block address in memory. Table 17-3. Registers and Offsets Offset Register OFFSET REGISTER 0x00 0x04 0x08 0x0C CTRL RGBBUF RGBBUF2 RGBSIZE 0x60 0x64 0x68 0x6C OL2 OL2SIZE OL2PARAM OL2PARAM2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-21 Pixel Pipeline (PXP) Table 17-3. Registers and Offsets (continued) Offset Register OFFSET REGISTER 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C S0BUF S0UBUF S0VBUF S0PARAM S0BACKGROUND S0CROP S0SCALE S0OFFSET S0COLORKEYLOW S0COLORKEYHIGH OLCOLORKEYLOW OLCOLORKEYHIGH OL0 OL0SIZE OL0PARAM OL0PARAM2 OL1 OL1SIZE OL1PARAM OL1PARAM2 0x70 0x74 0x78 0x7C 0x70 0x84 0x88 0x8C 0x90 0x94 0x98 0x9A 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC OL3 OL3SIZE OL3PARAM OL3PARAM2 OL4 OL4SIZE OL4PARAM OL4PARAM2 OL5 OL5SIZE OL5PARAM OL5PARAM2 OL6 OL6SIZE OL6PARAM OL6PARAM2 OL7 OL7SIZE OL7PARAM OL7PARAM2 17.3 Examples This section includes several examples of programming the PXP to render an output image. The image could be either a still image or one frame of a sequence of video images. For each case, the input and output images will be shown along with a table of PXP register settings. In all examples, pointers to the data structures with image data will be referred to in the following notation: *imagename_type, where imagename indicates which image is being used and type indicates either luma (y), chroma (u, v) or RGB data (rgb). All register names are assumed to have the HW_PXP_ register prefix. The registers can be written in any order except the HW_PXP_CTRL register, which must be written last since it enables the PXP's operation. 17.3.1 Basic QVGA Example This example shows how to perform basic colorspace conversion of a 3-plane YUV image into an RGB image suitable for an LCD device. i.MX23 Applications Processor Reference Manual, Rev. 1 17-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Table 17-4. Register Use for Conversion Register Value Description RGBBUF RGBSIZE *example1_rgb 0xFF1400F0 Pointer to the output buffer. ALPHA=0xFF WIDTH=0x140=320 HEIGHT=0x0F0=240 Pointer to input Y buffer Pointer to input U buffer Pointer to input V buffer WIDTH=0x28=40 (40*8=320 pixels) HEIGHT=0x1E=30 (30*8=240 pixels) Black background region No Cropping YUV->RGB Coefficient Values S0BUF S0UBUF SOVBUF S0PARAM S0BACKGROUND S0CROP S0CSCCOEFF0 S0CSCCOEFF1 S0CSCCOEFF2 OL0PARAM OL1PARAM OL2PARAM OL3PARAM OL4PARAM OL5PARAM OL6PARAM OL7PARAM CTRL *morraine_y *morraine_u *morraine_v 0x0000281E 0x00000000 0x00000000 0x04030000 0x01230208 0x076b079b 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00009003 Overlay 0 disabled Overlay 1 disabled Overlay 2 disabled Overlay 3 disabled Overlay 4 disabled Overlay 5 disabled Overlay 6 disabled Overlay 7 disabled S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 The resulting image is simply the RGB equivalent of the YUV image: Figure 17-18. Example: RGB Equivalent of YUV image i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-23 Pixel Pipeline (PXP) 17.3.2 Basic QVGA with Overlays This example is similar to the last, but adds two overlay images, one for a logo and the other as a time counter/control bar. The two overlay images are shown in Figure 17-19. (Note that the black background is actually transparent in the real image). Figure 17-19. Example: QVGA with Overlays Changes from the previous example are in bold. Table 17-5. Register Use for Conversion Register Value Description RGBBUF RGBSIZE *example1_rgb 0xFF1400F0 Pointer to the output buffer. ALPHA=0xFF WIDTH=0x140=320 HEIGHT=0x0F0=240 Pointer to input Y buffer Pointer to input U buffer Pointer to input V buffer WIDTH=0x28=40 (40*8=320 pixels) HEIGHT=0x1E=30 (30*8= 240 pixels) Black background region No Cropping YUV->RGB Coefficient Values S0BUF S0UBUF SOVBUF S0PARAM S0BACKGROUND S0CROP S0CSCCOEFF0 S0CSCCOEFF1 S0CSCCOEFF2 OL0 OL0SIZE OL0PARAM *morraine_y *morraine_u *morraine_v 0x0000281E 0x00000000 0x00000000 0x04030000 0x01230208 0x076b079b *overlay1_rgb 0x00000A02 0x0000FF01 Pointer to control graphic WIDTH=0x0A=80 pixels HEIGHT=0x02=16pixels ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 Pointer to logo graphic XBASE=0x0A=80pixels YBASE=0x18=192pixels WIDTH=0x1D=232pixels HEIGHT=0x06=48pixels ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 OL1 OL1SIZE *logo_rgb 0x0A181D06 OL1PARAM 0x0000FF01 OL2PARAM OL3PARAM OL4PARAM 0x00000000 0x00000000 0x00000000 Overlay 2 disabled Overlay 3 disabled Overlay 4 disabled i.MX23 Applications Processor Reference Manual, Rev. 1 17-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Table 17-5. Register Use for Conversion (continued) Register Value Description OL5PARAM OL6PARAM OL7PARAM CTRL 0x00000000 0x00000000 0x00000000 0x00009003 Overlay 5 disabled Overlay 6 disabled Overlay 7 disabled S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 The resulting image is shown below. Note the presence of the overlays in the upper left and lower right corners of the image. Figure 17-20. Example: QVGA with Overlays 17.3.3 Cropped QVGA Example This example displays the same image as the first example, but does so on a portrait-oriented display (240x320) without the overlays. Changes from the first example are shown in bold. Table 17-6. Register Use for Conversion Register Value Description RGBBUF RGBSIZE *example1_rgb 0xFF0F0140 Pointer to the output buffer. ALPHA=0xFF WIDTH=0x0F0=240 pixels HEIGHT=0x140=320 pixels Pointer to input Y buffer Pointer to input U buffer Pointer to input V buffer YBASE=0x05=40pixels WIDTH=0x28=40 (40*8=320 pixels) HEIGHT=0x1E=30 (30*8= 240 pixels) S0BUF S0UBUF SOVBUF S0PARAM *morraine_y *morraine_u *morraine_v 0x0005281E S0BACKGROUND 0x00000000 Black background region i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-25 Pixel Pipeline (PXP) Table 17-6. Register Use for Conversion (continued) Register Value Description S0CROP 0x05001E1E XBASE=0x05=40 pixels YBASE=00=0pixels WIDTH=0x1E=240pixels HEIGHT=0x1E=240 pixels YUV->RGB Coefficient Values S0CSCCOEFF0 S0CSCCOEFF1 S0CSCCOEFF2 OL0PARAM OL1PARAM OL2PARAM OL3PARAM OL4PARAM OL5PARAM OL6PARAM OL7PARAM CTRL 0x04030000 0x01230208 0x076b079b 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00089003 Overlay 0 disabled Overlay 1 disabled Overlay 2 disabled Overlay 3 disabled Overlay 4 disabled Overlay 5 disabled Overlay 6 disabled Overlay 7 disabled CROP=1 S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 In this case, we have now changed the RGB size to reflect the portrait nature of the display. The S0PARAM_YBASE has been changed to 0x05 (40 pixels) to place the S0 plane down 40 pixels from the top of the screen. The cropping register is now also used to control the cropping extents. The CROP_XBASE is set to 0x05 (40 pixels) to move the origin of the S0 buffer to the (40,0) location within the buffer. The CROP_WIDTH/CROP_HEIGHT are also programmed to ensure that the resulting image in the output buffer is cropped to 240x240 pixels. Since the image no longer covers the entire output buffer, the S0BACKGROUND register is used to letterbox the image in black. The resulting image is shown below. i.MX23 Applications Processor Reference Manual, Rev. 1 17-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Figure 17-21. Example: Cropped QVGA 17.3.4 Upscale QVGA to VGA with Overlays In this example, the image will be upscaled from QVGA to VGA resolution and displayed with the two overlays from the second example. Changes from the second example are shown in bold. Table 17-7. Register Use for Conversion Register Value Description RGBBUF RGBSIZE *example1_rgb 0xFF2801E0 Pointer to the output buffer. ALPHA=0xFF WIDTH=0x280=640 HEIGHT=0x1E0=480 Pointer to input Y buffer Pointer to input U buffer Pointer to input V buffer WIDTH=0x28=40 (40*8=320 pixels) HEIGHT=0x1E=30 (30*8= 240 pixels) Black background region WIDTH=0x50=640pixels HEIGHT=0x3C=320pixels XSCALE=0x0800=2x scale YSCALE=0x0800=2x scale S0BUF S0UBUF SOVBUF S0PARAM S0BACKGROUND S0CROP S0SCALE *morraine_y *morraine_u *morraine_v 0x0000281E 0x00000000 0x0000503C 0x08000800 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-27 Pixel Pipeline (PXP) Table 17-7. Register Use for Conversion (continued) Register Value Description S0CSCCOEFF0 S0CSCCOEFF1 S0CSCCOEFF2 OL0 OL0SIZE 0x04030000 0x01230208 0x076b079b *overlay1_rgb 0x23000A02 YUV->RGB Coefficient Values Pointer to control graphic XBASE=0x23=280pixels WIDTH=0x0A=80 pixels HEIGHT=0x02=16pixels OL0PARAM 0x0000FF01 ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 Pointer to logo graphic XBASE=0x19=200pixels YBASE=0x36=432pixels WIDTH=0x1D=232pixels HEIGHT=0x06=48pixels OL1 OL1SIZE *logo_rgb 0x19361D06 OL1PARAM 0x0000FF01 ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 Overlay 2 disabled Overlay 3 disabled Overlay 4 disabled Overlay 5 disabled Overlay 6 disabled Overlay 7 disabled SCALE=1 CROP=1 S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 OL2PARAM OL3PARAM OL4PARAM OL5PARAM OL6PARAM OL7PARAM CTRL 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x000c9003 The resulting image is shown in the figure below. Note that the overlays have moved in this image and that the overall image size is now larger than before. i.MX23 Applications Processor Reference Manual, Rev. 1 17-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Figure 17-22. Example: Upscale QVGA to VGA with Overlays 17.3.5 Downscale VGA to WQVGA (480x272) to fill screen In this example, a VGA image will be downscaled to fix the extents of a 480x272 WQVGA display. This means that the aspect ratio of the resulting image will not match that of the source image, thus the scaling factors in the horizontal and vertical directions will differ from each other. Table 17-8. Register Use for Conversion Register Value Description RGBBUF RGBSIZE *example_rgb 0xFFf1E0110 Pointer to the output buffer. ALPHA=0xFF WIDTH=0x1E0=480 HEIGHT=0x110=272 Pointer to input Y buffer Pointer to input U buffer Pointer to input V buffer WIDTH=0x50=80=640 pixels HEIGHT=0x3C=60=480 pixels Black background region WIDTH=0x3C=480 pixels HEIGHT=0x22=272 pixels YSCALE=0x1C3C=1/1.765x XSCALE=0x1555=1/1.333x YUV->RGB Coefficient Values S0BUF S0UBUF SOVBUF S0PARAM S0BACKGROUND S0CROP S0SCALE S0CSCCOEFF0 S0CSCCOEFF1 S0CSCCOEFF2 OL0PARAM OL1PARAM *garden_y *garden_u *garden_v 0x0000503C 0x00000000 0x00003C22 0x1C3C1555 0x04030000 0x01230208 0x076b079b 0x00000000 0x00000000 Overlay 0 disabled Overlay 1 disabled i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-29 Pixel Pipeline (PXP) Table 17-8. Register Use for Conversion (continued) Register Value Description OL2PARAM OL3PARAM OL4PARAM OL5PARAM OL6PARAM OL7PARAM CTRL 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x000C9003 Overlay 2 disabled Overlay 3 disabled Overlay 4 disabled Overlay 5 disabled Overlay 6 disabled Overlay 7 disabled SCALE=1 CROP=1 S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 Note that the scaling factors are computed as (source/dest)*4096, thus in the horizontal direction 640/480*4096=5461=0x1555. In the vertical direction, the scaling factor is computed as 480/272*4096=7228=0x1C3C. The original source image and resulting scaled images are shown below: i.MX23 Applications Processor Reference Manual, Rev. 1 17-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Original Image (640x480) Scaled Image (480x272) Figure 17-23. Example: Downscale VGA to WQVGA (480x272) to fill screen 17.3.6 Downscale VGA to QVGA with Overlapping Overlays The final example will perform a 1/2x scaling of a VGA image to QVGA to maintain the aspect ratio. It will also add four overlays to present the image as if it were a photo album application. Table 17-9. Register Use for Conversion Register Value Description RGBBUF RGBSIZE *example_rgb 0xFF1400F0 Pointer to the output buffer. ALPHA=0xFF WIDTH=0x1E0=320 HEIGHT=0x110=240 Pointer to input Y buffer Pointer to input U buffer Pointer to input V buffer S0BUF S0UBUF SOVBUF *garden_y garden_u garden_v i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-31 Pixel Pipeline (PXP) Table 17-9. Register Use for Conversion (continued) Register Value Description S0PARAM S0BACKGROUND S0CROP S0SCALE S0OFFSET S0CSCCOEFF0 S0CSCCOEFF1 S0CSCCOEFF2 OL0 OL0SIZE 0x0000503C 0x00000040 0x0000281E 0x20002000 0x08000800 0x04030000 0x01230208 0x076b079b *prev_rgb 0x0B1B0402 WIDTH=0x50=80=640 pixels HEIGHT=0x3C=60=480 pixels Dark Blue background region WIDTH=0x28=320 pixels HEIGHT=0x1E=240 pixels YSCALE=0x2000=1/2x XSCALE=0x1555=1/2x XOFFSET=0x0800 (1/2 pixel) YOFFSET=0x0800 (1/2 pixel) YUV->RGB Coefficient Values Pointer to "previous" graphic XBASE=0x0B=88pixels YBASE=0x1B=216pixels WIDTH=0x04=32 pixels HEIGHT=0x02=16pixels ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 Pointer to "next" graphic XBASE=0x2D=360pixels YBASE=0x1B=216pixels WIDTH=0x04=32 pixels HEIGHT=0x02=16pixels ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 Pointer to text graphic XBASE=0x00=0pixels YBASE=0x00=0pixels WIDTH=0x0A=80pixels HEIGHT=0x1E=240pixels ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 Pointer to rectangular border graphic XBASE=0x0A=80pixels YBASE=0x00=0pixels WIDTH=0x28=320pixels HEIGHT=0x1E=240pixels ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 Overlay 4 disabled OL0PARAM 0x0000FF01 OL1 OL1SIZE *next_rgb 0x2D1B0402 OL1PARAM 0x0000FF01 OL2 OL2SIZE *text_overlay 0x00000A1E OL2PARAM 0x0000FF01 OL3 OL3SIZE *border_rgb 0x0A00281E OL3PARAM 0x0000FF01 OL4PARAM 0x00000000 i.MX23 Applications Processor Reference Manual, Rev. 1 17-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Table 17-9. Register Use for Conversion (continued) Register Value Description OL5PARAM OL6PARAM OL7PARAM CTRL 0x00000000 0x00000000 0x00000000 0x000C9003 Overlay 5 disabled Overlay 6 disabled Overlay 7 disabled SCALE=1 CROP=1 S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 The resulting image is shown below. Note that the "text" is rendered in a transparent overlay (overlay #2)on the right side of the screen. The background color (#000040) is dark blue and shows through the overlay as the background color. Overlay #3 applies a thin white alpha-blended border around the image to frame it. Overlays #0 and #1 generate the "Next>" and " 17.4 Programmable Registers This section includes the programmable registers supported. 17.4.1 PXP Control Register 0 Description HW_PXP_CTRL 0x000 The CTRL register contains controls for the PXP module. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-33 Pixel Pipeline (PXP) HW_PXP_CTRL_SET HW_PXP_CTRL_CLR HW_PXP_CTRL_TOG Table 17-10. HW_PXP_CTRL 3 1 3 0 2 9 2 8 2 7 INTERLACED_OUTPUT 0x004 0x008 0x00C 2 6 2 5 INTERLACED_INPUT 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 OUTPUT_RGB_FORMAT 0 5 0 4 0 3 0 2 0 1 0 0 ALPHA_OUTPUT IRQ_ENABLE SUBSAMPLE S0_FORMAT UPSAMPLE IN_PLACE CLKGATE Table 17-11. HW_PXP_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Set this bit to zero to enable normal PXP operation. Set this bit to one (default) to disable clocking with the PXP and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the PXP block to its default state. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. Reserved, always set to zero. Determines how the PXP writes it's output RGB data. Output interlacing should not be used in conjunction with input interlacing. Splitting frames into fields is most efficient using output interlacing. PROGRESSIVE = 0x0 All data written in progressive format to the RGBBUF Pointer. FIELD0 = 0x1 Interlaced output: only data for field 0 is written to the RGBBUF Pointer. FIELD1 = 0x2 Interlaced output: only data for field 1 is written to the RGBBUF2 Pointer. INTERLACED = 0x3 Interlaced output: data for field 0 is written to RGBBUF and data for field 1 is written to RGBBUF2. 30 CLKGATE RW 0x1 RO 0x0 RW 0x0 29:28 RSVD4 27:26 INTERLACED_OUTPUT 25:24 INTERLACED_INPUT RW 0x0 When set, causes the fetch side of the PXP to fetch every other line from the source buffers. This effectively produces one field of interlaced output data. Scaling should NOT be enabled for interlaced operation and only overlays with boundaries on 8x16 multiples are supported. PROGRESSIVE = 0x0 All data will be read and processed in progressive format. FIELD0 = 0x2 Interlaced, Field 0: only data for field 0 (even lines) is read/processed. FIELD1 = 0x3 Interlaced, Field 1: only data for field 1 (odd lines) is read/processed. 23 22 RSVD3 ALPHA_OUTPUT RO 0x0 RW 0x0 Reserved, always set to zero. Indicates, if 0, that the output buffer pixels should retain their alpha value from the computed alpha for that pixel. If 1, then the ALPHA field from the output buffer parameters register will be used. i.MX23 Applications Processor Reference Manual, Rev. 1 17-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor ENABLE ROTATE SFTRST SCALE RSVD3 RSVD2 RSVD4 RSVD1 DELTA HFLIP CROP VFLIP Pixel Pipeline (PXP) Table 17-11. HW_PXP_CTRL Bit Field Descriptions BITS LABEL 21 IN_PLACE RW RESET RW 0x0 DEFINITION When set, this enables the PXP to perform an alpha blend operation on an existing buffer (output buffer is set to S0 buffer). In this case, the PXP will perform the alpha blending of the overlays into the source buffer. Since only pixels containing an overlay are processed, the PXP does this very efficiently. Reserved for future use. Indicates that the S0 plane should use the cropping register to provide the extents for the output S0 buffer cropping. If not set, the input video cropping extents will be inferred from the S0 WIDTH and HEIGHT fields. When scaling, the CROP bit and controls should be used to specify the scaled image size in the RGB buffer. Indicates that the output image should be scaled (only YUV/YCbCr images may be scaled -- RGB scaling is not supported). The XSCALE and YSCALE registers should be programmed accordingly. In addition, the CROP bit and the S0CROP registers should be programmed to ensure that the scaled image is properly cropped in the output buffer. When this bit is zero, the contents of the scaling registers are ignored. Reserved for future use. Reserved for future use. Source 0 buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSCCOEFF0 register. RGB888 = 0x1 32-bit pixels (unpacked 24-bit format) RGB565 = 0x4 16-bit pixels RGB555 = 0x5 16-bit pixels YUV422 = 0x8 16-bit pixels YUV420 = 0x9 16-bit pixels 20 19 DELTA CROP RO 0x0 RW 0x0 18 SCALE RW 0x0 17 UPSAMPLE SUBSAMPLE 16 15:12 S0_FORMAT RO 0x0 RO 0x0 RW 0x0 11 10 9:8 VFLIP HFLIP ROTATE RW 0x0 RW 0x0 RW 0x0 Indicates that the output buffer should be flipped vertically (effect applied before rotation). Indicates that the output buffer should be flipped horizontally (effect applied before rotation). Indicates the clockwise rotation to be applied at the output buffer. The rotation effect is defined as occurring after the FLIP_X and FLIP_Y permutation. ROT_0 = 0x0 ROT_90 = 0x1 ROT_180 = 0x2 ROT_270 = 0x3 7:4 OUTPUT_RGB_FORMAT RW 0x0 Target RGB framebuffer format. ARGB8888 = 0x0 32-bit pixels RGB888 = 0x1 32-bit pixels (unpacked 24-bit format) RGB888P = 0x2 24-bit pixels (packed 24-bit format) ARGB1555 = 0x3 16-bit pixels RGB565 = 0x4 16-bit pixels RGB555 = 0x5 16-bit pixels 3 2 RSVD2 RSVD1 RO 0x0 RW 0x0 Reserved, always set to zero. Program this field to 0x0. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-35 Pixel Pipeline (PXP) Table 17-11. HW_PXP_CTRL Bit Field Descriptions BITS LABEL 1 IRQ_ENABLE RW RESET RW 0x0 DEFINITION Interrupt enable. NOTE: When using the HW_PXP_NEXT functionality to reprogram the PXP, the new value of this bit will be used and may therefore enable or disable an interrupt unintentionally. Enables PXP operation with specified parameters. The ENABLE bit will remain set while the PXP is active and will be cleared once the current operation completes. Software should use the IRQ bit in the HW_PXP_STAT when polling for PXP completion. 0 ENABLE RW 0x0 DESCRIPTION: The Control register contains the primary controls for the PXP block. The present bits indicate which of the sub-features of the block are present in the hardware. EXAMPLE: HW_PXP_CTRL_SET(BM_PXP_CTRL_SFTRST); HW_PXP_CTRL_CLR(BM_PXP_CTRL_SFTRST | BM_PXP_CTRL_CLKGATE); 17.4.2 PXP Status Register Description HW_PXP_STAT HW_PXP_STAT_SET HW_PXP_STAT_CLR HW_PXP_STAT_TOG Table 17-12. HW_PXP_STAT The PXP Interrupt Status register provides interrupt status information. 0x010 0x014 0x018 0x01C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 AXI_ERROR_ID 0 5 0 4 0 3 0 2 AXI_READ_ERROR 0 1 AXI_WRITE_ERROR 0 0 BLOCKX BLOCKY RSVD2 RSVD1 Table 17-13. HW_PXP_STAT Bit Field Descriptions BITS 31:24 BLOCKX LABEL RW RESET RO 0x00 DEFINITION Indicates the X coordinate of the block currently being rendered. Indicates the X coordinate of the block currently being rendered. Reserved, always set to zero. Indicates the AXI ID of the failing bus operation. Reserved, always set to zero. 23:16 BLOCKY 15:8 7:4 3 RSVD2 AXI_ERROR_ID RSVD1 RO 0x00 RO 0x000000 RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 17-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor IRQ Pixel Pipeline (PXP) Table 17-13. HW_PXP_STAT Bit Field Descriptions BITS LABEL 2 AXI_READ_ERROR RW RESET RW 0x0 DEFINITION Indicates PXP encountered an AXI read error and processing has been terminated. Indicates PXP encountered an AXI write error and processing has been terminated. Indicates current PXP interrupt status. The IRQ is routed through the pxp_irq when the IRQ_ENABLE bit in the control register is set. 1 0 AXI_WRITE_ERROR IRQ RW 0x0 RW 0x0 DESCRIPTION: This register provides PXP interrupt status and the current X/Y block coordinate that is being processed. EXAMPLE: HW_PXP_STAT_CLR(BM_PXP_STAT_IRQ); // clear CSC interrupt 17.4.3 RGB Output Frame Buffer Pointer Description RGB Output Framebuffer Pointer. This register points to the beginning of the RGB output frame buffer. This pointer is used for progressive format and field 0 when generating interlaced output. HW_PXP_RGBBUF Table 17-14. HW_PXP_RGBBUF 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x020 ADDR Table 17-15. HW_PXP_RGBBUF Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Current address pointer for the output frame buffer. The address MUST be word-aligned for proper PXP operation. DESCRIPTION: This register is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE: HW_PXP_RGBBUF_WR( buffer ); 17.4.4 RGB Output Frame Buffer Pointer #2 Description RGB Output Framebuffer Pointer #2. This register points to the beginning of the RGB output frame buffer for field 1 when generating interlaced output. HW_PXP_RGBBUF2 0x030 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-37 Pixel Pipeline (PXP) Table 17-16. HW_PXP_RGBBUF2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ADDR Table 17-17. HW_PXP_RGBBUF2 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Current address pointer for the output frame buffer. The address MUST be word-aligned for proper PXP operation. DESCRIPTION: This register is used by the logic to point to the current output location for the field 1 RGB frame buffer. EXAMPLE: HW_PXP_RGBBUF_WR( field0 ); // buffer for interlaced field 0 HW_PXP_RGBBUF2_WR( field1 ); // buffer for interlaced field 1 17.4.5 PXP Output Buffer Size Description This register contains framebuffer size information for the output RGB buffer (independent of the rotation). When rotating the framebuffer, the PXP will automatically modify the output WIDTH/HEIGHT to accomodate the rotated size. HW_PXP_RGBSIZE Table 17-18. HW_PXP_RGBSIZE 3 1 3 0 2 9 2 8 ALPHA 0x040 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 WIDTH 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 HEIGHT 0 5 0 4 0 3 0 2 0 1 0 0 Table 17-19. HW_PXP_RGBSIZE Bit Field Descriptions BITS 31:24 ALPHA LABEL RW RESET RW 0x00 DEFINITION When generating an output RGB buffer with an alpha component, the value in this field will be used. Indicates number of horizontal PIXELS in the image (non-rotated). The image size IS required to be a multiple of 8 pixels. The PXP will handle clipping the pixel output at this boundary. Indicates the number of vertical PIXELS in the image (non-rotated). The image size IS required to be a multiple of 8 pixels. The PXP will handle clipping the pixel output at this boundary. 23:12 WIDTH RW 0x0 11:0 HEIGHT RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 17-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) DESCRIPTION: This register sets the size of the output frame buffer. The frame buffer need not be a multiple of 8x8 pixels. Partial 8x8 blocks will be written for blocks that extend beyond the extents of the frame buffer. EXAMPLE: HW_PXP_RGBSIZE.U.WIDTH=320; // set width HW_PXP_RGBSIZE.U.HEIGHT=240; // set height HW_PX_RGBSIZE_WR( BF_PXP_RGBSIZE_WIDTH(320) | BF_PXP_RGBSIZE_HEIGHT(240) ); 17.4.6 PXP Source 0 (video) Input Buffer Pointer Description S0 Input Buffer Pointer. This should be programmed to the starting address of the RGB data or Y (luma) data for the S0 plane. HW_PXP_S0BUF Table 17-20. HW_PXP_S0BUF 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x050 ADDR Table 17-21. HW_PXP_S0BUF Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Address pointer for the S0 RGB or Y (luma) input buffer. The address MUST be word-aligned for proper PXP operation. DESCRIPTION: This register contains the pointer to the Luma/RGB buffer. EXAMPLE: HW_PXP_S0BUF_WR(image_rgb); // RGB image HW_PXP_S0BUF_WR(image_y); // Y (luma) image data HW_PXP_S0UBUF_WR(image_u); // U (Cb) image data HW_PXP_S0VBUF_WR(image_v); // V (Cr) image data 17.4.7 Source 0 U/Cb Input Buffer Pointer Description S0 Chroma (U/Cb) Input Buffer Pointer. This register points to the beginning of the Source 0 U/Cb input buffer. HW_PXP_S0UBUF Table 17-22. HW_PXP_S0UBUF 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x060 ADDR i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-39 Pixel Pipeline (PXP) Table 17-23. HW_PXP_S0UBUF Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Address pointer for the S0 (video) U/Cb Chroma input buffer. The address MUST be word-aligned for proper PXP operation. DESCRIPTION: This register contains the pointer to the Chroma U/Cb buffer when performing colorspace conversion. This register is unused when processing RGB data. EXAMPLE: HW_PXP_S0BUF_WR(image_y); // Y (luma) image data HW_PXP_S0UBUF_WR(image_u); // U (Cb) image data HW_PXP_S0VBUF_WR(image_v); // V (Cr) image data 17.4.8 Source 0 V/Cr Input Buffer Pointer Description S0 Chroma (V/Cr) Input Buffer Pointer. This register points to the beginning of the Source 0 V/Cr input buffer. HW_PXP_S0VBUF Table 17-24. HW_PXP_S0VBUF 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x070 ADDR Table 17-25. HW_PXP_S0VBUF Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Address pointer for the S0 (video) V/Cr Chroma input buffer. The address MUST be word-aligned for proper PXP operation. DESCRIPTION: This register contains the pointer to the Chroma V/Cr buffer when performing colorspace conversion. This register is unused when processing RGB data. EXAMPLE: HW_PXP_S0BUF_WR(image_y); // Y (luma) image data HW_PXP_S0UBUF_WR(image_u); // U (Cb) image data HW_PXP_S0VBUF_WR(image_v); // V (Cr) image data 17.4.9 PXP Source 0 (video) Buffer Parameters Description HW_PXP_S0PARAM 0x080 This register contains buffer information for the S0 input RGB/YUV buffer. i.MX23 Applications Processor Reference Manual, Rev. 1 17-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Table 17-26. HW_PXP_S0PARAM 3 1 3 0 2 9 2 8 XBASE 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 YBASE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 WIDTH 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 HEIGHT 0 3 0 2 0 1 0 0 Table 17-27. HW_PXP_S0PARAM Bit Field Descriptions BITS 31:24 XBASE LABEL RW RESET RW 0x00 DEFINITION This field indicates the horizontal offset location (in 8x8 block) of the S0 buffer within the output frame buffer. This field indicates the vertical offset location (in 8x8 block) of the S0 buffer within the output frame buffer. Indicates number of horizontal 8x8 blocks in the image (non-rotated). Indicates the number of vertical 8x8 blocks in the image (non-rotated). 23:16 YBASE 15:8 7:0 WIDTH HEIGHT RW 0x00 RW 0x0 RW 0x0 DESCRIPTION: The S0 Parameter register contains the size of the S0 input buffer (WIDTH, HEIGHT) as well as provides an offset for the display of this buffer within the output frame buffer (XBASE,YBASE). All four values are in terms of 8x8 pixel blocks. EXAMPLE: HW_PXP_S0PARAM_WR(0x0101281E); // S0 buffer will appear at offset (8,8) in the RGB buffer. // the size is 0x28 (40*8=320 pixels) by 0x1E (30*8=240 pixels) 17.4.10 Source 0 Background Color Description S0 Background Pixel Color. This register provides a pixel value used when processing blocks outside of the region specified by the S0SIZE register. This value can effectively be used to set the color of the letterboxing region around a video image. HW_PXP_S0BACKGROUND 0x090 Table 17-28. HW_PXP_S0BACKGROUND 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COLOR Table 17-29. HW_PXP_S0BACKGROUND Bit Field Descriptions BITS 31:0 COLOR LABEL RW RESET RW 0x0 DEFINITION Background color (in 32bpp format) for any pixels not in the S0 buffer range specified in the S0SIZE register. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-41 Pixel Pipeline (PXP) DESCRIPTION: This register contains a pixel value to be used for any S0 blocks that fall outside the S0 extents. This is effectively a background or letterbox color. EXAMPLE: HW_PXP_S0BACKGROUND_WR(0x00000000); HW_PXP_S0BACKGROUND_WR(0x00800000); HW_PXP_S0BACKGROUND_WR(0x00008000); HW_PXP_S0BACKGROUND_WR(0x00000080); // // // // letterbox letterbox letterbox letterbox is is is is black dark red dark green dark blue 17.4.11 Source 0 Cropping Register Description This register contains controls for image/video cropping. XBASE and YBASE select the origin of the S0 buffer for PXP operations. The WIDTH and HEIGHT determine the visible size of the selected region in the output frame buffer. Software should program the input framebuffer cropped width/height values into these fields. Cropping is applied in the output buffer, therefore after any scaling operations. Scaled regions may need to be cropped to avoid artifacts at the edge of a scaled region. HW_PXP_S0CROP Table 17-30. HW_PXP_S0CROP 3 1 3 0 2 9 2 8 XBASE 0x0A0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 YBASE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 WIDTH 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 HEIGHT 0 3 0 2 0 1 0 0 Table 17-31. HW_PXP_S0CROP Bit Field Descriptions BITS 31:24 XBASE LABEL RW RESET RW 0x00 DEFINITION This field indicates the horizontal offset (in terms of 8-pixel blocks) into the S0 buffer which is considered the origin of the image. This allows selection of a subset of a source image for processing. This field indicates the vertical offset (in terms of 8-pixel blocks) into the S0 buffer which is considered the origin of the image. This allows selection of a subset of a source image for processing. 23:16 YBASE RW 0x00 i.MX23 Applications Processor Reference Manual, Rev. 1 17-42 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Table 17-31. HW_PXP_S0CROP Bit Field Descriptions BITS 15:8 WIDTH LABEL RW RESET RW 0x00 DEFINITION Ouput buffer cropped video width (in terms of 8 pixel blocks). This field should be programmed to the desired cropped width of the S0 plane in the output buffer. When scaling is not used, this value is effectively the width of the input buffer that should appear in the output buffer. For scaling operations, it's important that this field be programmed to the width of the scaled size of the S0 output image. Input buffer cropped video height (in terms of 8 pixel blocks). This field should be programmed to the desired cropped height of the S0 plan in the output buffer. When scaling is not used, this value is effectively the height of the input buffer that should appear in the output buffer. For scaling operations, it's important that this field be programmed to the height of the scaled size of the S0 output image. 7:0 HEIGHT RW 0x00 DESCRIPTION: The cropping register can be used to specify cropping extents for S0 plane in the output buffer. It is only used if the CROP bit is set in the PXP_CTRL register is set. When this bit is not set, no cropping of the input image will be performed and the PXP will default to using the S0 WIDTH and HEIGHT parameters. Cropping should always be used when scaling images since the PXP cannot determine the scaled image size. EXAMPLE: HW_PXP_S0CROP_WR(0x02021810); // S0 origin is at (16,16) -- 0x0202 // output width is 192 (0x18->24*8=192 pixels) // output height is 128 (0x10->16*8=128 pixels) 17.4.12 Source 0 Scale Factor Register Description S0 Scale Factor. This register provides the scale factor for the S0 (video) buffer. HW_PXP_S0SCALE Table 17-32. HW_PXP_S0SCALE 3 1 RSVD2 0x0B0 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 YSCALE 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 RSVD1 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 XSCALE 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 17-33. HW_PXP_S0SCALE Bit Field Descriptions BITS 31:30 RSVD2 29:16 YSCALE LABEL RW RESET RO 0x00 RW 0x1000 DEFINITION Reserved, always set to zero. This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the S0 source buffer. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-43 Pixel Pipeline (PXP) Table 17-33. HW_PXP_S0SCALE Bit Field Descriptions BITS 15:14 RSVD1 13:0 XSCALE LABEL RW RESET RO 0x00 RW 0x1000 DEFINITION Reserved, always set to zero. This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the S0 source buffer. DESCRIPTION: The maximum down scaling factor is 1/2 such that the output image in either axis is half the size of the source. The maximum up scaling factor is 2^12 for either axis. The reciprocal of the scale factor should be loaded into this register. To reduce the S0 buffer by a factor of two in the output frame buffer, a value of 10.0000_0000_0000 should be loaded into this register. The scale up by a factor of 4, the value of 1/4, or 00.0100_0000_0000, should be loaded into this register. To scale up by 8/5, the value of 00.1010_0000_0000 should be loaded. EXAMPLE: HW_PXP_S0SCALE_WR(0x10001000); // 1:1 scaling (0x1.000) HW_PXP_S0SCALE_WR(0x08000800); // 2x scaling (0x0.800) HW_PXP_S0SCALE_WR(0x20002000); // 1/2x scaling (0x2.000) 17.4.13 Source 0 Scale Offset Register Description S0 Scale Offset. This register provides the initial scale offset for the S0 (video) buffer. HW_PXP_S0OFFSET Table 17-34. HW_PXP_S0OFFSET 3 1 3 0 RSVD2 0x0C0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 YOFFSET 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 RSVD1 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 XOFFSET 0 5 0 4 0 3 0 2 0 1 0 0 Table 17-35. HW_PXP_S0OFFSET Bit Field Descriptions BITS LABEL 31:28 RSVD2 27:16 YOFFSET RW RESET RO 0x00 RW 0x000 DEFINITION Reserved, always set to zero. This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed block offset which gets added to the scaled block address to determine source data for the scaling engine. Reserved, always set to zero. This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed block offset which gets added to the scaled block address to determine source data for the scaling engine. 15:12 RSVD1 11:0 XOFFSET RO 0x00 RW 0x000 i.MX23 Applications Processor Reference Manual, Rev. 1 17-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) DESCRIPTION: The X and Y offset provides the ability to access the source image with a per pixel or per sub-pixel granularity. To shift the source input image by a single pixel, for example, a value of 0x200 would be loaded into this offset field. Since a pixel block is 8x8 pixels, 0x200 (or 1/8), will provide a fixed offset of 1 pixel for the entire PXP operation. The fixed offset values can also be used for sub-pixel adjustments in the bilinear scaling filter. For example, when scaling an image down by a factor of 2, an initial offset of 0x0 would result in sub-sampling every other pixel. If a fixed offset of 0x100 (1/16) is programmed, all pixels are used in scaling the final output pixel value. EXAMPLE: Empty Example. HW_PXP_S0SCALE_WR(0x20002000); // 1/2x scaling (0x2.000) HW_PXP_S0OFFSET_WR(0x01000100); // half-pixel offset in both X and Y to ensure averaging versus pixel replication 17.4.14 Color Space Conversion Coefficient Register 0 Description This register contains color space conversion coefficients in two's compliment notation. HW_PXP_CSCCOEFF0 Table 17-36. HW_PXP_CSCCOEFF0 3 1 YCBCR_MODE 0x0D0 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 UV_OFFSET 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 Y_OFFSET 0 3 0 2 0 1 0 0 RSVD1 Table 17-37. HW_PXP_CSCCOEFF0 Bit Field Descriptions BITS LABEL 31 YCBCR_MODE RW RESET RW 0x0 DEFINITION Set to 1 when performing YCbCr conversion to RGB. Set to 0 when converting YUV to RGB data. This bit changes the behavior of the scaler when performing U/V scaling. Reserved, always set to zero. Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) Two's compliment phase offset implicit for UV data. YUV=YCbCr=0x180 (typically -128 or 0x180 to indicate a -0.5 to 0.5 range) Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is typically -16 (0x1F0) C0 30:29 RSVD1 28:18 C0 17:9 UV_OFFSET RO 0x00 RW 0x100 RW 0x180 8:0 Y_OFFSET RW 0x000 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-45 Pixel Pipeline (PXP) DESCRIPTION: The Coeffient 0 register contains coeffients used in the color space conversion algorithm. The Y and UV offsets are added to the source buffer to normalize them before the conversion. C0 is the coeffient that is used to multiply the luma component of the data for all three RGB components. EXAMPLE: // The equations used for Colorspace conversion are: // R = C0*(Y+YOFFSET) + C1(V+UV_OFFSET) // G = C0*(Y+YOFFSET) + C3(U+UV_OFFSET) + C2(V+UV_OFFSET) // R = C0*(Y+YOFFSET) + C4(U+UV_OFFSET) HW_PXP_CSCCOEFF0_WR(0x04030000); // YUV coefficients: C0, Yoffset, UVoffset HW_PXP_CSCCOEFF1_WR(0x01230208); // YUV coefficients: C1, C4 HW_PXP_CSCCOEFF2_WR(0x076B079b); // YUV coefficients: C2, C3 17.4.15 Color Space Conversion Coefficient Register 1 Description This register contains color space conversion coefficients in two's compliment notation. HW_PXP_CSCCOEFF1 Table 17-38. HW_PXP_CSCCOEFF1 3 1 3 0 2 9 RSVD1 0x0E0 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 C1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSVD0 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 C4 0 4 0 3 0 2 0 1 0 0 Table 17-39. HW_PXP_CSCCOEFF1 Bit Field Descriptions BITS 31:27 RSVD1 26:16 C1 LABEL RW RESET RO 0x00 RW 0x123 DEFINITION Reserved, always set to zero. Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596) Reserved, always set to zero. Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017) 15:11 RSVD0 10:0 C4 RO 0x00 RW 0x208 DESCRIPTION: The Coeffient 1 register contains coeffients used in the color space conversion algorithm. C1 is the coeffient that is used to multiply the chroma (Cr/V) component of the data for the red component. C4 is the coeffient that is used to multiply the chroma (Cb/U) component of the data for the blue component. Both values should be coded as a two's compliment fixed point number with 8 bits right of the decimal. EXAMPLE: HW_PXP_CSCCOEFF0_WR(0x04030000); // YUV coefficients: C0, Yoffset, UVoffset HW_PXP_CSCCOEFF1_WR(0x01230208); // YUV coefficients: C1, C4 HW_PXP_CSCCOEFF2_WR(0x076B079b); // YUV coefficients: C2, C3 i.MX23 Applications Processor Reference Manual, Rev. 1 17-46 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) 17.4.16 Color Space Conversion Coefficient Register 2 Description This register contains color space conversion coefficients in two's compliment notation. HW_PXP_CSCCOEFF2 Table 17-40. HW_PXP_CSCCOEFF2 3 1 3 0 2 9 RSVD1 0x0F0 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 C2 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSVD0 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 C3 0 4 0 3 0 2 0 1 0 0 Table 17-41. HW_PXP_CSCCOEFF2 Bit Field Descriptions BITS 31:27 RSVD1 26:16 C2 LABEL RW RESET RO 0x00 RW 0x79b DEFINITION Reserved, always set to zero. Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813) Reserved, always set to zero. Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392) 15:11 RSVD0 10:0 C3 RO 0x00 RW 0x76c DESCRIPTION: The Coeffient 2 register contains coeffients used in the color space conversion algorithm. C2 is the coeffient that is used to multiply the chroma (Cr/V) component of the data for the green component. C3 is the coeffient that is used to multiply the chroma (Cb/U) component of the data for the green component. Both values should be coded as a two's compliment fixed point number with 8 bits right of the decimal. EXAMPLE: // NOTE: The default values for the CSCCOEFF2 register are incorrect. C2 should be 0x76B and C3 should be 0x79C for proper operation. HW_PXP_CSCCOEFF0_WR(0x04030000); // YUV coefficients: C0, Yoffset, UVoffset HW_PXP_CSCCOEFF1_WR(0x01230208); // YUV coefficients: C1, C4 HW_PXP_CSCCOEFF2_WR(0x076B079b); // YUV coefficients: C2, C3 17.4.17 PXP Next Frame Pointer Description This register contains a pointer to a data structure used to reload the PXP registers at the end of the current frame. HW_PXP_NEXT HW_PXP_NEXT_SET HW_PXP_NEXT_CLR HW_PXP_NEXT_TOG 0x100 0x104 0x108 0x10C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-47 Pixel Pipeline (PXP) Table 17-42. HW_PXP_NEXT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 POINTER 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 RSVD 0 0 ENABLED Table 17-43. HW_PXP_NEXT Bit Field Descriptions BITS LABEL 31:2 POINTER RW RESET RW 0x0 DEFINITION A pointer to a data structure containing register values to be used when processing the next frame. The pointer must be 32-bit aligned and should reside in on-chip or off-chip memory. Reserved, always set to zero. Indicates that the "next frame" functionality has been enabled. This bit reflects the status of the hardware semaphore indicating that a reload operation is pending at the end of the current frame. 1 0 RSVD ENABLED RO 0x0 RO 0x0 DESCRIPTION: To enable this functionality, software must write this register while the PXP is processing the current data frame (if the PXP is currently idle, this will also initiate an immediate load of registers from the pointer). The process of writing this register (WRITE operation) will set a semaphore in hardware to notify the control logic that a register reload operation must be performed when the current frame processing is complete. At the end of a frame, the PXP will fetch the register settings from this location, signal an interrupt to software, then proceed with rendering the next frame of data. Software may cancel the reload operation by issuing a CLEAR operation to this register. SET and TOGGLE operations should not be used when addressing this register. All registers will be reloaded with the exception of the following: STAT, CSCCOEFFn, NEXT, VERSION. All other registers will be loaded in the order they appear in the register map. EXAMPLE: // create register command structure in memory u32* pxp_commands0[48], pxp_commands1; u32 rc; // initialize control structure for frame 0 pxp_commands0[0] = ...; // CTRL pxp_commands0[1] = ...; // RGB Buffer ... pxp_commands0[47] = ..; // Overlay7 param2 // initialize control structure for frame 1 pxp_commands1[0] = ...; // CTRL pxp_commands1[1] = ...; // RGB Buffer ... pxp_commands1[47] = ..; // Overlay7 param2 // poll until a command isn't queued while (rc=HW_PXP_NEXT_RD() & BM_PXP_NEXT_ENABLED ); HW_PXP_NEXT_WR(pxp_commands0); // enable PXP operation 0 via command pointer i.MX23 Applications Processor Reference Manual, Rev. 1 17-48 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) // poll until first command clears while (rc=HW_PXP_NEXT_RD() & BM_PXP_NEXT_ENABLED ); HW_PXP_NEXT_WR(pxp_commands1); // enable PXP operation 1 via command pointer 17.4.18 PXP S0 Color Key Low Description This register contains the color key low value for the S0 buffer. HW_PXP_S0COLORKEYLOW 0x180 Table 17-44. HW_PXP_S0COLORKEYLOW 3 1 3 0 2 9 2 8 RSVD1 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 PIXEL 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 17-45. HW_PXP_S0COLORKEYLOW Bit Field Descriptions BITS 31:24 RSVD1 23:0 PIXEL LABEL RW RESET RO 0x00 RW 0xFFFFFF DEFINITION Reserved, always set to zero. Low range of RGB color key applied to S0 buffer. To disable S0 colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. DESCRIPTION: When processing an image, the if the PXP finds a pixel in the background image with a color that falls in the range from the S0COLORKEYLOW to S0COLORKEYHIGH range, it will substitute the color found in the matching overlay. If no overlay is present or if the overlay also matches its colorkey range, the s0background color is used. EXAMPLE: // colorkey values between HW_PXP_S0COLORKEYLOW_WR (0x008000); // medium green and HW_PXP_S0COLORKEYHIGH_WR(0x00FF00); // light green 17.4.19 PXP S0 Color Key High Description This register contains the color key high value for the S0 buffer. HW_PXP_S0COLORKEYHIGH 0x190 Table 17-46. HW_PXP_S0COLORKEYHIGH 3 1 3 0 2 9 2 8 RSVD1 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 PIXEL 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-49 Pixel Pipeline (PXP) Table 17-47. HW_PXP_S0COLORKEYHIGH Bit Field Descriptions BITS 31:24 RSVD1 23:0 PIXEL LABEL RW RESET RO 0x00 RW 0x0 DEFINITION Reserved, always set to zero. High range of RGB color key applied to S0 buffer. To disable S0 colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. DESCRIPTION: When processing an image, the if the PXP finds a pixel in the background image with a color that falls in the range from the S0COLORKEYLOW to S0COLORKEYHIGH range, it will substitute the color found in the matching overlay. If no overlay is present or if the overlay also matches its colorkey range, the s0background color is used. EXAMPLE: // colorkey values between HW_PXP_S0COLORKEYLOW_WR (0x008000); // medium green and HW_PXP_S0COLORKEYHIGH_WR(0x00FF00); // light green 17.4.20 PXP Overlay Color Key Low Description This register contains the color key low value for the OL buffer. HW_PXP_OLCOLORKEYLOW 0x1A0 Table 17-48. HW_PXP_OLCOLORKEYLOW 3 1 3 0 2 9 2 8 RSVD1 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 PIXEL 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 17-49. HW_PXP_OLCOLORKEYLOW Bit Field Descriptions BITS 31:24 RSVD1 23:0 PIXEL LABEL RW RESET RO 0x00 RW 0xFFFFFF DEFINITION Reserved, always set to zero. Low range of RGB color key applied to OL buffer. Each overlay has an independent colorkey enable. DESCRIPTION: When processing an image, the if the PXP finds a pixel in the current overlay image with a color that falls in the range from the OLCOLORKEYLOW to OLCOLORKEYHIGH range, it will use the S0 pixel value for that location. If no S0 image is present or if the S0 image also matches its colorkey range, the s0background color is used. Colorkey operations are higher priority than alpha or ROP operations. EXAMPLE: // colorkey values between HW_PXP_OLCOLORKEYLOW_WR (0x000000); // black and i.MX23 Applications Processor Reference Manual, Rev. 1 17-50 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) HW_PXP_OLCOLORKEYHIGH_WR(0x800000); // medium red 17.4.21 PXP Overlay Color Key High Description This register contains the color key high value for the OL buffer. HW_PXP_OLCOLORKEYHIGH 0x1B0 Table 17-50. HW_PXP_OLCOLORKEYHIGH 3 1 3 0 2 9 2 8 RSVD1 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 PIXEL 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 17-51. HW_PXP_OLCOLORKEYHIGH Bit Field Descriptions BITS 31:24 RSVD1 23:0 PIXEL LABEL RW RESET RO 0x00 RW 0x0 DEFINITION Reserved, always set to zero. High range of RGB color key applied to OL buffer. Each overlay has an independent colorkey enable. DESCRIPTION: When processing an image, the if the PXP finds a pixel in the current overlay image with a color that falls in the range from the OLCOLORKEYLOW to OLCOLORKEYHIGH range, it will use the S0 pixel value for that location. If no S0 image is present or if the S0 image also matches its colorkey range, the s0background color is used. Colorkey operations are higher priority than alpha or ROP operations. EXAMPLE: // colorkey values between HW_PXP_OLCOLORKEYLOW_WR (0x000000); // black and HW_PXP_OLCOLORKEYHIGH_WR(0x800000); // medium red 17.4.22 PXP Debug Control Register Description This register controls the debug features of the PXP. HW_PXP_DEBUGCTRL Table 17-52. HW_PXP_DEBUGCTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 RSVD2 0x1D0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 RSVD1 0 7 0 6 0 5 0 4 SELECT 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-51 Pixel Pipeline (PXP) Table 17-53. HW_PXP_DEBUGCTRL Bit Field Descriptions BITS 31:9 RSVD2 RSVD1 8 SELECT 7:0 LABEL RW RESET RO 0x0 RW 0x0 RW 0x00 DEFINITION Reserved, always set to zero. Program this field to 0x0. Index into one of the PXP debug registers. The data for the selected register will be returned NONE = 0x0 None CTRL = 0x1 Control Debug S0REGS = 0x2 S0 Debug S0BAX = 0x3 S0 BA X Scale S0BAY = 0x4 S0 BA Y Scale PXBUF = 0x5 PXBUF Debug ROTATION = 0x6 Rotation Debug ROTBUF0 = 0x7 Rotation Buffer 0 ROTBUF1 = 0x8 Rotation Buffer 1 DESCRIPTION: This register controls the PXP Debug features. This register is not intended for customer use. EXAMPLE: NA 17.4.23 PXP Debug Register Description This register returns selected debug register values. HW_PXP_DEBUG Table 17-54. HW_PXP_DEBUG 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x1E0 DATA Table 17-55. HW_PXP_DEBUG Bit Field Descriptions BITS 31:0 DATA LABEL RW RESET RO 0x000000 DEFINITION Debug data DESCRIPTION: Debug register. Select the appropriate register in debug control and the values are returned here. EXAMPLE: NA 17.4.24 PXP Version Register Description This register always returns a known read value for debug purposes it indicates the version of the block. HW_PXP_VERSION 0x1F0 i.MX23 Applications Processor Reference Manual, Rev. 1 17-52 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Table 17-56. HW_PXP_VERSION 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 17-57. HW_PXP_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x02 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x0 RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_PXP_VERSION.B.MAJOR != 2) Error(); 17.4.25 PXP Overlay 0 Buffer Pointer Description Overlay 0 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 0 input buffer. HW_PXP_OL0 Table 17-58. HW_PXP_OL0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x200 ADDR Table 17-59. HW_PXP_OL0 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Address pointer for the overlay 0 buffer. The address MUST be word-aligned for proper PXP operation. DESCRIPTION: This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE: u32* overlay_ptr; HW_PXP_OLn_WR(0,overlay_ptr); i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-53 Pixel Pipeline (PXP) 17.4.26 PXP Overlay 0 Size Description This register contains buffer size/location information for the Overlay 0 input buffer. HW_PXP_OL0SIZE Table 17-60. HW_PXP_OL0SIZE 3 1 3 0 2 9 2 8 XBASE 0x210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 YBASE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 WIDTH 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 HEIGHT 0 3 0 2 0 1 0 0 Table 17-61. HW_PXP_OL0SIZE Bit Field Descriptions BITS 31:24 XBASE LABEL RW RESET RW 0x00 DEFINITION This field indicates the X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. This field indicates the Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. Indicates number of horizontal 8x8 blocks in the image (non-rotated). Indicates the number of vertical 8x8 blocks in the image (non-rotated). 23:16 YBASE RW 0x00 15:8 7:0 WIDTH HEIGHT RW 0x0 RW 0x0 DESCRIPTION: This register contains information about Overlay 0 indicating the size of the overlay (in 8x8 blocks) and the overlay's location within the output frame buffer (in 8x8 blocks). EXAMPLE: HW_PXP_OLnSIZE_WR(0,0x10000401); // 32x8 overlay at offset +128+0 17.4.27 PXP Overlay 0 Parameters Description This register contains buffer parameters for the Overlay 0 input buffer. HW_PXP_OL0PARAM 0x220 i.MX23 Applications Processor Reference Manual, Rev. 1 17-54 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Table 17-62. HW_PXP_OL0PARAM 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ENABLE_COLORKEY 0 2 0 1 0 0 ALPHA_CNTL FORMAT Table 17-63. HW_PXP_OL0PARAM Bit Field Descriptions BITS 31:20 RSVD1 19:16 ROP LABEL RW RESET RO 0x0000 RW 0x0 DEFINITION Reserved, always set to zero. Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. MASKOL = 0x0 OL AND S0 MASKNOTOL = 0x1 nOL AND S0 MASKOLNOT = 0x2 OL AND nS0 MERGEOL = 0x3 OL OR S0 MERGENOTOL = 0x4 nOL OR S0 MERGEOLNOT = 0x5 OL OR nS0 NOTCOPYOL = 0x6 nOL NOT = 0x7 nS0 NOTMASKOL = 0x8 OL NAND S0 NOTMERGEOL = 0x9 OL NOR S0 XOROL = 0xA OL XOR S0 NOTXOROL = 0xB OL XNOR S0 15:8 ALPHA RW 0x0 7:4 FORMAT RW 0x0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. ARGB8888 = 0x0 32-bit pixels with alpha RGB888 = 0x1 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 = 0x3 16-bit pixels with alpha RGB565 = 0x4 16-bit pixels without alpha RGB555 = 0x5 16-bit pixels without alpha 3 ENABLE_COLORKEY RW 0x0 2:1 ALPHA_CNTL RW 0x0 Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Embedded = 0x0 Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override = 0x1 Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply = 0x2 Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs = 0x3 Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0 ENABLE RW 0x0 Indicates that the overlay is active for this operation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice ENABLE ALPHA RSVD1 ROP 17-55 Pixel Pipeline (PXP) DESCRIPTION: The S1 Overlay 0 Parameter register provides additional controls for Overlay 0. EXAMPLE: u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(0,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay 17.4.28 PXP Overlay 0 Parameters 2 Description This register contains buffer parameters for the Overlay 0 input buffer. HW_PXP_OL0PARAM2 Table 17-64. HW_PXP_OL0PARAM2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x230 RSVD Table 17-65. HW_PXP_OL0PARAM2 Bit Field Descriptions BITS 31:0 RSVD LABEL RW RESET RO 0x00000000 DEFINITION Reserved, always set to zero. DESCRIPTION: The Overlay 0 Parameter 2 register is reserved for future use. EXAMPLE: Empty Example. 17.4.29 PXP Overlay 1 Buffer Pointer Description Overlay 1 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 1 input buffer. HW_PXP_OL1 Table 17-66. HW_PXP_OL1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x240 ADDR Table 17-67. HW_PXP_OL1 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Address pointer for the overlay 1 buffer. The address MUST be word-aligned for proper PXP operation. i.MX23 Applications Processor Reference Manual, Rev. 1 17-56 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) DESCRIPTION: This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE: u32* overlay_ptr; HW_PXP_OLn_WR(1,overlay_ptr); 17.4.30 PXP Overlay 1 Size Description This register contains buffer size/location information for the Overlay 1 input buffer. HW_PXP_OL1SIZE Table 17-68. HW_PXP_OL1SIZE 3 1 3 0 2 9 2 8 XBASE 0x250 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 YBASE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 WIDTH 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 HEIGHT 0 3 0 2 0 1 0 0 Table 17-69. HW_PXP_OL1SIZE Bit Field Descriptions BITS 31:24 XBASE LABEL RW RESET RW 0x00 DEFINITION This field indicates the X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. This field indicates the Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. Indicates number of horizontal 8x8 blocks in the image (non-rotated). Indicates the number of vertical 8x8 blocks in the image (non-rotated). 23:16 YBASE RW 0x00 15:8 7:0 WIDTH HEIGHT RW 0x0 RW 0x0 DESCRIPTION: This register contains information about Overlay 1 indicating the size of the overlay (in 8x8 blocks) and the overlay's location within the output frame buffer (in 8x8 blocks). EXAMPLE: HW_PXP_OLnSIZE_WR(1,0x10000401); // 32x8 overlay at offset +128+0 17.4.31 PXP Overlay 1 Parameters Description This register contains buffer parameters for the Overlay 1 input buffer. HW_PXP_OL1PARAM 0x260 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-57 Pixel Pipeline (PXP) Table 17-70. HW_PXP_OL1PARAM 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ENABLE_COLORKEY 0 2 0 1 0 0 ALPHA_CNTL FORMAT Table 17-71. HW_PXP_OL1PARAM Bit Field Descriptions BITS 31:20 RSVD1 19:16 ROP LABEL RW RESET RO 0x0000 RW 0x0 DEFINITION Reserved, always set to zero. Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. MASKOL = 0x0 OL AND S0 MASKNOTOL = 0x1 nOL AND S0 MASKOLNOT = 0x2 OL AND nS0 MERGEOL = 0x3 OL OR S0 MERGENOTOL = 0x4 nOL OR S0 MERGEOLNOT = 0x5 OL OR nS0 NOTCOPYOL = 0x6 nOL NOT = 0x7 nS0 NOTMASKOL = 0x8 OL NAND S0 NOTMERGEOL = 0x9 OL NOR S0 XOROL = 0xA OL XOR S0 NOTXOROL = 0xB OL XNOR S0 15:8 ALPHA RW 0x0 7:4 FORMAT RW 0x0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. ARGB8888 = 0x0 32-bit pixels with alpha RGB888 = 0x1 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 = 0x3 16-bit pixels with alpha RGB565 = 0x4 16-bit pixels without alpha RGB555 = 0x5 16-bit pixels without alpha 3 ENABLE_COLORKEY RW 0x0 2:1 ALPHA_CNTL RW 0x0 Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Embedded = 0x0 Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override = 0x1 Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply = 0x2 Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs = 0x3 Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0 ENABLE RW 0x0 Indicates that the overlay is active for this operation. i.MX23 Applications Processor Reference Manual, Rev. 1 17-58 Preliminary--Subject to Change Without Notice Freescale Semiconductor ENABLE ALPHA RSVD1 ROP Pixel Pipeline (PXP) DESCRIPTION: The S1 Overlay 1 Parameter register provides additional controls for Overlay 1. EXAMPLE: u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(1,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay 17.4.32 PXP Overlay 1 Parameters 2 Description This register contains buffer parameters for the Overlay 1 input buffer. HW_PXP_OL1PARAM2 Table 17-72. HW_PXP_OL1PARAM2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x270 RSVD Table 17-73. HW_PXP_OL1PARAM2 Bit Field Descriptions BITS 31:0 RSVD LABEL RW RESET RO 0x00000000 DEFINITION Reserved, always set to zero. DESCRIPTION: The Overlay 1 Parameter 2 register is reserved for future use. EXAMPLE: Empty Example. 17.4.33 PXP Overlay 2 Buffer Pointer Description Overlay 2 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 2 input buffer. HW_PXP_OL2 Table 17-74. HW_PXP_OL2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x280 ADDR Table 17-75. HW_PXP_OL2 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Address pointer for the overlay 2 buffer. The address MUST be word-aligned for proper PXP operation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-59 Pixel Pipeline (PXP) DESCRIPTION: This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE: u32* overlay_ptr; HW_PXP_OLn_WR(2,overlay_ptr); 17.4.34 PXP Overlay 2 Size Description This register contains buffer size/location information for the Overlay 2 input buffer. HW_PXP_OL2SIZE Table 17-76. HW_PXP_OL2SIZE 3 1 3 0 2 9 2 8 XBASE 0x290 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 YBASE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 WIDTH 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 HEIGHT 0 3 0 2 0 1 0 0 Table 17-77. HW_PXP_OL2SIZE Bit Field Descriptions BITS 31:24 XBASE LABEL RW RESET RW 0x00 DEFINITION This field indicates the X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. This field indicates the Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. Indicates number of horizontal 8x8 blocks in the image (non-rotated). Indicates the number of vertical 8x8 blocks in the image (non-rotated). 23:16 YBASE RW 0x00 15:8 7:0 WIDTH HEIGHT RW 0x0 RW 0x0 DESCRIPTION: This register contains information about Overlay 2 indicating the size of the overlay (in 8x8 blocks) and the overlay's location within the output frame buffer (in 8x8 blocks). EXAMPLE: HW_PXP_OLnSIZE_WR(2,0x10000401); // 32x8 overlay at offset +128+0 17.4.35 PXP Overlay 2 Parameters Description This register contains buffer parameters for the Overlay 2 input buffer. HW_PXP_OL2PARAM 0x2a0 i.MX23 Applications Processor Reference Manual, Rev. 1 17-60 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Table 17-78. HW_PXP_OL2PARAM 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ENABLE_COLORKEY 0 2 0 1 0 0 ALPHA_CNTL FORMAT Table 17-79. HW_PXP_OL2PARAM Bit Field Descriptions BITS 31:20 RSVD1 19:16 ROP LABEL RW RESET RO 0x0000 RW 0x0 DEFINITION Reserved, always set to zero. Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. MASKOL = 0x0 OL AND S0 MASKNOTOL = 0x1 nOL AND S0 MASKOLNOT = 0x2 OL AND nS0 MERGEOL = 0x3 OL OR S0 MERGENOTOL = 0x4 nOL OR S0 MERGEOLNOT = 0x5 OL OR nS0 NOTCOPYOL = 0x6 nOL NOT = 0x7 nS0 NOTMASKOL = 0x8 OL NAND S0 NOTMERGEOL = 0x9 OL NOR S0 XOROL = 0xA OL XOR S0 NOTXOROL = 0xB OL XNOR S0 15:8 ALPHA RW 0x0 7:4 FORMAT RW 0x0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. ARGB8888 = 0x0 32-bit pixels with alpha RGB888 = 0x1 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 = 0x3 16-bit pixels with alpha RGB565 = 0x4 16-bit pixels without alpha RGB555 = 0x5 16-bit pixels without alpha 3 ENABLE_COLORKEY RW 0x0 2:1 ALPHA_CNTL RW 0x0 Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Embedded = 0x0 Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override = 0x1 Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply = 0x2 Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs = 0x3 Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0 ENABLE RW 0x0 Indicates that the overlay is active for this operation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice ENABLE ALPHA RSVD1 ROP 17-61 Pixel Pipeline (PXP) DESCRIPTION: The S1 Overlay 2 Parameter register provides additional controls for Overlay 2. EXAMPLE: u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(2,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay 17.4.36 PXP Overlay 2 Parameters 2 Description This register contains buffer parameters for the Overlay 2 input buffer. HW_PXP_OL2PARAM2 Table 17-80. HW_PXP_OL2PARAM2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x2b0 RSVD Table 17-81. HW_PXP_OL2PARAM2 Bit Field Descriptions BITS 31:0 RSVD LABEL RW RESET RO 0x00000000 DEFINITION Reserved, always set to zero. DESCRIPTION: The Overlay 2 Parameter 2 register is reserved for future use. EXAMPLE: Empty Example. 17.4.37 PXP Overlay 3 Buffer Pointer Description Overlay 3 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 3 input buffer. HW_PXP_OL3 Table 17-82. HW_PXP_OL3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x2c0 ADDR Table 17-83. HW_PXP_OL3 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Address pointer for the overlay 3 buffer. The address MUST be word-aligned for proper PXP operation. i.MX23 Applications Processor Reference Manual, Rev. 1 17-62 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) DESCRIPTION: This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE: u32* overlay_ptr; HW_PXP_OLn_WR(3,overlay_ptr); 17.4.38 PXP Overlay 3 Size Description This register contains buffer size/location information for the Overlay 3 input buffer. HW_PXP_OL3SIZE Table 17-84. HW_PXP_OL3SIZE 3 1 3 0 2 9 2 8 XBASE 0x2d0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 YBASE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 WIDTH 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 HEIGHT 0 3 0 2 0 1 0 0 Table 17-85. HW_PXP_OL3SIZE Bit Field Descriptions BITS 31:24 XBASE LABEL RW RESET RW 0x00 DEFINITION This field indicates the X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. This field indicates the Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. Indicates number of horizontal 8x8 blocks in the image (non-rotated). Indicates the number of vertical 8x8 blocks in the image (non-rotated). 23:16 YBASE RW 0x00 15:8 7:0 WIDTH HEIGHT RW 0x0 RW 0x0 DESCRIPTION: This register contains information about Overlay 3 indicating the size of the overlay (in 8x8 blocks) and the overlay's location within the output frame buffer (in 8x8 blocks). EXAMPLE: HW_PXP_OLnSIZE_WR(3,0x10000401); // 32x8 overlay at offset +128+0 17.4.39 PXP Overlay 3 Parameters Description This register contains buffer parameters for the Overlay 3 input buffer. HW_PXP_OL3PARAM 0x2e0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-63 Pixel Pipeline (PXP) Table 17-86. HW_PXP_OL3PARAM 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ENABLE_COLORKEY 0 2 0 1 0 0 ALPHA_CNTL FORMAT Table 17-87. HW_PXP_OL3PARAM Bit Field Descriptions BITS 31:20 RSVD1 19:16 ROP LABEL RW RESET RO 0x0000 RW 0x0 DEFINITION Reserved, always set to zero. Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. MASKOL = 0x0 OL AND S0 MASKNOTOL = 0x1 nOL AND S0 MASKOLNOT = 0x2 OL AND nS0 MERGEOL = 0x3 OL OR S0 MERGENOTOL = 0x4 nOL OR S0 MERGEOLNOT = 0x5 OL OR nS0 NOTCOPYOL = 0x6 nOL NOT = 0x7 nS0 NOTMASKOL = 0x8 OL NAND S0 NOTMERGEOL = 0x9 OL NOR S0 XOROL = 0xA OL XOR S0 NOTXOROL = 0xB OL XNOR S0 15:8 ALPHA RW 0x0 7:4 FORMAT RW 0x0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. ARGB8888 = 0x0 32-bit pixels with alpha RGB888 = 0x1 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 = 0x3 16-bit pixels with alpha RGB565 = 0x4 16-bit pixels without alpha RGB555 = 0x5 16-bit pixels without alpha 3 ENABLE_COLORKEY RW 0x0 2:1 ALPHA_CNTL RW 0x0 Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Embedded = 0x0 Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override = 0x1 Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply = 0x2 Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs = 0x3 Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0 ENABLE RW 0x0 Indicates that the overlay is active for this operation. i.MX23 Applications Processor Reference Manual, Rev. 1 17-64 Preliminary--Subject to Change Without Notice Freescale Semiconductor ENABLE ALPHA RSVD1 ROP Pixel Pipeline (PXP) DESCRIPTION: The S1 Overlay 3 Parameter register provides additional controls for Overlay 3. EXAMPLE: u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(3,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay 17.4.40 PXP Overlay 3 Parameters 2 Description This register contains buffer parameters for the Overlay 3 input buffer. HW_PXP_OL3PARAM2 Table 17-88. HW_PXP_OL3PARAM2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x2f0 RSVD Table 17-89. HW_PXP_OL3PARAM2 Bit Field Descriptions BITS 31:0 RSVD LABEL RW RESET RO 0x00000000 DEFINITION Reserved, always set to zero. DESCRIPTION: The Overlay 3 Parameter 2 register is reserved for future use. EXAMPLE: Empty Example. 17.4.41 PXP Overlay 4 Buffer Pointer Description Overlay 4 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 4 input buffer. HW_PXP_OL4 Table 17-90. HW_PXP_OL4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x300 ADDR Table 17-91. HW_PXP_OL4 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Address pointer for the overlay 4 buffer. The address MUST be word-aligned for proper PXP operation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-65 Pixel Pipeline (PXP) DESCRIPTION: This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE: u32* overlay_ptr; HW_PXP_OLn_WR(4,overlay_ptr); 17.4.42 PXP Overlay 4 Size Description This register contains buffer size/location information for the Overlay 4 input buffer. HW_PXP_OL4SIZE Table 17-92. HW_PXP_OL4SIZE 3 1 3 0 2 9 2 8 XBASE 0x310 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 YBASE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 WIDTH 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 HEIGHT 0 3 0 2 0 1 0 0 Table 17-93. HW_PXP_OL4SIZE Bit Field Descriptions BITS 31:24 XBASE LABEL RW RESET RW 0x00 DEFINITION This field indicates the X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. This field indicates the Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. Indicates number of horizontal 8x8 blocks in the image (non-rotated). Indicates the number of vertical 8x8 blocks in the image (non-rotated). 23:16 YBASE RW 0x00 15:8 7:0 WIDTH HEIGHT RW 0x0 RW 0x0 DESCRIPTION: This register contains information about Overlay 4 indicating the size of the overlay (in 8x8 blocks) and the overlay's location within the output frame buffer (in 8x8 blocks). EXAMPLE: HW_PXP_OLnSIZE_WR(4,0x10000401); // 32x8 overlay at offset +128+0 17.4.43 PXP Overlay 4 Parameters Description This register contains buffer parameters for the Overlay 4 input buffer. HW_PXP_OL4PARAM 0x320 i.MX23 Applications Processor Reference Manual, Rev. 1 17-66 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Table 17-94. HW_PXP_OL4PARAM 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ENABLE_COLORKEY 0 2 0 1 0 0 ALPHA_CNTL FORMAT Table 17-95. HW_PXP_OL4PARAM Bit Field Descriptions BITS 31:20 RSVD1 19:16 ROP LABEL RW RESET RO 0x0000 RW 0x0 DEFINITION Reserved, always set to zero. Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. MASKOL = 0x0 OL AND S0 MASKNOTOL = 0x1 nOL AND S0 MASKOLNOT = 0x2 OL AND nS0 MERGEOL = 0x3 OL OR S0 MERGENOTOL = 0x4 nOL OR S0 MERGEOLNOT = 0x5 OL OR nS0 NOTCOPYOL = 0x6 nOL NOT = 0x7 nS0 NOTMASKOL = 0x8 OL NAND S0 NOTMERGEOL = 0x9 OL NOR S0 XOROL = 0xA OL XOR S0 NOTXOROL = 0xB OL XNOR S0 15:8 ALPHA RW 0x0 7:4 FORMAT RW 0x0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. ARGB8888 = 0x0 32-bit pixels with alpha RGB888 = 0x1 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 = 0x3 16-bit pixels with alpha RGB565 = 0x4 16-bit pixels without alpha RGB555 = 0x5 16-bit pixels without alpha 3 ENABLE_COLORKEY RW 0x0 2:1 ALPHA_CNTL RW 0x0 Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Embedded = 0x0 Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override = 0x1 Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply = 0x2 Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs = 0x3 Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0 ENABLE RW 0x0 Indicates that the overlay is active for this operation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice ENABLE ALPHA RSVD1 ROP 17-67 Pixel Pipeline (PXP) DESCRIPTION: The S1 Overlay 4 Parameter register provides additional controls for Overlay 4. EXAMPLE: u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(4,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay 17.4.44 PXP Overlay 4 Parameters 2 Description This register contains buffer parameters for the Overlay 4 input buffer. HW_PXP_OL4PARAM2 Table 17-96. HW_PXP_OL4PARAM2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x330 RSVD Table 17-97. HW_PXP_OL4PARAM2 Bit Field Descriptions BITS 31:0 RSVD LABEL RW RESET RO 0x00000000 DEFINITION Reserved, always set to zero. DESCRIPTION: The Overlay 4 Parameter 2 register is reserved for future use. EXAMPLE: Empty Example. 17.4.45 PXP Overlay 5 Buffer Pointer Description Overlay 5 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 5 input buffer. HW_PXP_OL5 Table 17-98. HW_PXP_OL5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x340 ADDR Table 17-99. HW_PXP_OL5 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Address pointer for the overlay 5 buffer. The address MUST be word-aligned for proper PXP operation. i.MX23 Applications Processor Reference Manual, Rev. 1 17-68 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) DESCRIPTION: This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE: u32* overlay_ptr; HW_PXP_OLn_WR(5,overlay_ptr); 17.4.46 PXP Overlay 5 Size Description This register contains buffer size/location information for the Overlay 5 input buffer. HW_PXP_OL5SIZE Table 17-100. HW_PXP_OL5SIZE 3 1 3 0 2 9 2 8 XBASE 0x350 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 YBASE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 WIDTH 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 HEIGHT 0 3 0 2 0 1 0 0 Table 17-101. HW_PXP_OL5SIZE Bit Field Descriptions BITS 31:24 XBASE LABEL RW RESET RW 0x00 DEFINITION This field indicates the X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. This field indicates the Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. Indicates number of horizontal 8x8 blocks in the image (non-rotated). Indicates the number of vertical 8x8 blocks in the image (non-rotated). 23:16 YBASE RW 0x00 15:8 7:0 WIDTH HEIGHT RW 0x0 RW 0x0 DESCRIPTION: This register contains information about Overlay 5 indicating the size of the overlay (in 8x8 blocks) and the overlay's location within the output frame buffer (in 8x8 blocks). EXAMPLE: HW_PXP_OLnSIZE_WR(5,0x10000401); // 32x8 overlay at offset +128+0 17.4.47 PXP Overlay 5 Parameters Description This register contains buffer parameters for the Overlay 5 input buffer. HW_PXP_OL5PARAM 0x360 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-69 Pixel Pipeline (PXP) Table 17-102. HW_PXP_OL5PARAM 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ENABLE_COLORKEY 0 2 0 1 0 0 ALPHA_CNTL FORMAT Table 17-103. HW_PXP_OL5PARAM Bit Field Descriptions BITS 31:20 RSVD1 19:16 ROP LABEL RW RESET RO 0x0000 RW 0x0 DEFINITION Reserved, always set to zero. Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. MASKOL = 0x0 OL AND S0 MASKNOTOL = 0x1 nOL AND S0 MASKOLNOT = 0x2 OL AND nS0 MERGEOL = 0x3 OL OR S0 MERGENOTOL = 0x4 nOL OR S0 MERGEOLNOT = 0x5 OL OR nS0 NOTCOPYOL = 0x6 nOL NOT = 0x7 nS0 NOTMASKOL = 0x8 OL NAND S0 NOTMERGEOL = 0x9 OL NOR S0 XOROL = 0xA OL XOR S0 NOTXOROL = 0xB OL XNOR S0 15:8 ALPHA RW 0x0 7:4 FORMAT RW 0x0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. ARGB8888 = 0x0 32-bit pixels with alpha RGB888 = 0x1 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 = 0x3 16-bit pixels with alpha RGB565 = 0x4 16-bit pixels without alpha RGB555 = 0x5 16-bit pixels without alpha 3 ENABLE_COLORKEY RW 0x0 2:1 ALPHA_CNTL RW 0x0 Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Embedded = 0x0 Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override = 0x1 Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply = 0x2 Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs = 0x3 Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0 ENABLE RW 0x0 Indicates that the overlay is active for this operation. i.MX23 Applications Processor Reference Manual, Rev. 1 17-70 Preliminary--Subject to Change Without Notice Freescale Semiconductor ENABLE ALPHA RSVD1 ROP Pixel Pipeline (PXP) DESCRIPTION: The S1 Overlay 5 Parameter register provides additional controls for Overlay 5. EXAMPLE: u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(5,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay 17.4.48 PXP Overlay 5 Parameters 2 Description This register contains buffer parameters for the Overlay 5 input buffer. HW_PXP_OL5PARAM2 Table 17-104. HW_PXP_OL5PARAM2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x370 RSVD Table 17-105. HW_PXP_OL5PARAM2 Bit Field Descriptions BITS 31:0 RSVD LABEL RW RESET RO 0x00000000 DEFINITION Reserved, always set to zero. DESCRIPTION: The Overlay 5 Parameter 2 register is reserved for future use. EXAMPLE: Empty Example. 17.4.49 PXP Overlay 6 Buffer Pointer Description Overlay 6 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 6 input buffer. HW_PXP_OL6 Table 17-106. HW_PXP_OL6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x380 ADDR Table 17-107. HW_PXP_OL6 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Address pointer for the overlay 6 buffer. The address MUST be word-aligned for proper PXP operation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-71 Pixel Pipeline (PXP) DESCRIPTION: This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE: u32* overlay_ptr; HW_PXP_OLn_WR(6,overlay_ptr); 17.4.50 PXP Overlay 6 Size Description This register contains buffer size/location information for the Overlay 6 input buffer. HW_PXP_OL6SIZE Table 17-108. HW_PXP_OL6SIZE 3 1 3 0 2 9 2 8 XBASE 0x390 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 YBASE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 WIDTH 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 HEIGHT 0 3 0 2 0 1 0 0 Table 17-109. HW_PXP_OL6SIZE Bit Field Descriptions BITS 31:24 XBASE LABEL RW RESET RW 0x00 DEFINITION This field indicates the X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. This field indicates the Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. Indicates number of horizontal 8x8 blocks in the image (non-rotated). Indicates the number of vertical 8x8 blocks in the image (non-rotated). 23:16 YBASE RW 0x00 15:8 7:0 WIDTH HEIGHT RW 0x0 RW 0x0 DESCRIPTION: This register contains information about Overlay 6 indicating the size of the overlay (in 8x8 blocks) and the overlay's location within the output frame buffer (in 8x8 blocks). EXAMPLE: HW_PXP_OLnSIZE_WR(6,0x10000401); // 32x8 overlay at offset +128+0 17.4.51 PXP Overlay 6 Parameters Description This register contains buffer parameters for the Overlay 6 input buffer. HW_PXP_OL6PARAM 0x3a0 i.MX23 Applications Processor Reference Manual, Rev. 1 17-72 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) Table 17-110. HW_PXP_OL6PARAM 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ENABLE_COLORKEY 0 2 0 1 0 0 ALPHA_CNTL FORMAT Table 17-111. HW_PXP_OL6PARAM Bit Field Descriptions BITS 31:20 RSVD1 19:16 ROP LABEL RW RESET RO 0x0000 RW 0x0 DEFINITION Reserved, always set to zero. Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. MASKOL = 0x0 OL AND S0 MASKNOTOL = 0x1 nOL AND S0 MASKOLNOT = 0x2 OL AND nS0 MERGEOL = 0x3 OL OR S0 MERGENOTOL = 0x4 nOL OR S0 MERGEOLNOT = 0x5 OL OR nS0 NOTCOPYOL = 0x6 nOL NOT = 0x7 nS0 NOTMASKOL = 0x8 OL NAND S0 NOTMERGEOL = 0x9 OL NOR S0 XOROL = 0xA OL XOR S0 NOTXOROL = 0xB OL XNOR S0 15:8 ALPHA RW 0x0 7:4 FORMAT RW 0x0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. ARGB8888 = 0x0 32-bit pixels with alpha RGB888 = 0x1 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 = 0x3 16-bit pixels with alpha RGB565 = 0x4 16-bit pixels without alpha RGB555 = 0x5 16-bit pixels without alpha 3 ENABLE_COLORKEY RW 0x0 2:1 ALPHA_CNTL RW 0x0 Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Embedded = 0x0 Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override = 0x1 Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply = 0x2 Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs = 0x3 Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0 ENABLE RW 0x0 Indicates that the overlay is active for this operation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice ENABLE ALPHA RSVD1 ROP 17-73 Pixel Pipeline (PXP) DESCRIPTION: The S1 Overlay 6 Parameter register provides additional controls for Overlay 6. EXAMPLE: u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(6,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay 17.4.52 PXP Overlay 6 Parameters 2 Description This register contains buffer parameters for the Overlay 6 input buffer. HW_PXP_OL6PARAM2 Table 17-112. HW_PXP_OL6PARAM2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x3b0 RSVD Table 17-113. HW_PXP_OL6PARAM2 Bit Field Descriptions BITS 31:0 RSVD LABEL RW RESET RO 0x00000000 DEFINITION Reserved, always set to zero. DESCRIPTION: The Overlay 6 Parameter 2 register is reserved for future use. EXAMPLE: Empty Example. 17.4.53 PXP Overlay 7 Buffer Pointer Description Overlay 7 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 7 input buffer. HW_PXP_OL7 Table 17-114. HW_PXP_OL7 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x3c0 ADDR Table 17-115. HW_PXP_OL7 Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x0 DEFINITION Address pointer for the overlay 7 buffer. The address MUST be word-aligned for proper PXP operation. i.MX23 Applications Processor Reference Manual, Rev. 1 17-74 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pixel Pipeline (PXP) DESCRIPTION: This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE: u32* overlay_ptr; HW_PXP_OLn_WR(7,overlay_ptr); 17.4.54 PXP Overlay 7 Size Description This register contains buffer size/location information for the Overlay 7 input buffer. HW_PXP_OL7SIZE Table 17-116. HW_PXP_OL7SIZE 3 1 3 0 2 9 2 8 XBASE 0x3d0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 YBASE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 WIDTH 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 HEIGHT 0 3 0 2 0 1 0 0 Table 17-117. HW_PXP_OL7SIZE Bit Field Descriptions BITS 31:24 XBASE LABEL RW RESET RW 0x00 DEFINITION This field indicates the X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. This field indicates the Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer. Indicates number of horizontal 8x8 blocks in the image (non-rotated). Indicates the number of vertical 8x8 blocks in the image (non-rotated). 23:16 YBASE RW 0x00 15:8 7:0 WIDTH HEIGHT RW 0x0 RW 0x0 DESCRIPTION: This register contains information about Overlay 7 indicating the size of the overlay (in 8x8 blocks) and the overlay's location within the output frame buffer (in 8x8 blocks). EXAMPLE: HW_PXP_OLnSIZE_WR(7,0x10000401); // 32x8 overlay at offset +128+0 17.4.55 PXP Overlay 7 Parameters Description This register contains buffer parameters for the Overlay 7 input buffer. HW_PXP_OL7PARAM 0x3e0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-75 Pixel Pipeline (PXP) Table 17-118. HW_PXP_OL7PARAM 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ENABLE_COLORKEY 0 2 0 1 0 0 ALPHA_CNTL FORMAT Table 17-119. HW_PXP_OL7PARAM Bit Field Descriptions BITS 31:20 RSVD1 19:16 ROP LABEL RW RESET RO 0x0000 RW 0x0 DEFINITION Reserved, always set to zero. Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. MASKOL = 0x0 OL AND S0 MASKNOTOL = 0x1 nOL AND S0 MASKOLNOT = 0x2 OL AND nS0 MERGEOL = 0x3 OL OR S0 MERGENOTOL = 0x4 nOL OR S0 MERGEOLNOT = 0x5 OL OR nS0 NOTCOPYOL = 0x6 nOL NOT = 0x7 nS0 NOTMASKOL = 0x8 OL NAND S0 NOTMERGEOL = 0x9 OL NOR S0 XOROL = 0xA OL XOR S0 NOTXOROL = 0xB OL XNOR S0 15:8 ALPHA RW 0x0 7:4 FORMAT RW 0x0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. ARGB8888 = 0x0 32-bit pixels with alpha RGB888 = 0x1 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 = 0x3 16-bit pixels with alpha RGB565 = 0x4 16-bit pixels without alpha RGB555 = 0x5 16-bit pixels without alpha 3 ENABLE_COLORKEY RW 0x0 2:1 ALPHA_CNTL RW 0x0 Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Embedded = 0x0 Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override = 0x1 Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply = 0x2 Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs = 0x3 Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0 ENABLE RW 0x0 Indicates that the overlay is active for this operation. i.MX23 Applications Processor Reference Manual, Rev. 1 17-76 Preliminary--Subject to Change Without Notice Freescale Semiconductor ENABLE ALPHA RSVD1 ROP Pixel Pipeline (PXP) DESCRIPTION: The S1 Overlay 7 Parameter register provides additional controls for Overlay 7. EXAMPLE: u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(7,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay 17.4.56 PXP Overlay 7 Parameters 2 Description This register contains buffer parameters for the Overlay 7 input buffer. HW_PXP_OL7PARAM2 Table 17-120. HW_PXP_OL7PARAM2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x3f0 RSVD Table 17-121. HW_PXP_OL7PARAM2 Bit Field Descriptions BITS 31:0 RSVD LABEL RW RESET RO 0x00000000 DEFINITION Reserved, always set to zero. DESCRIPTION: The Overlay 7 Parameter 2 register is reserved for future use. EXAMPLE: Empty Example. PXP Block v2.0, Revision 1.57 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17-77 Pixel Pipeline (PXP) i.MX23 Applications Processor Reference Manual, Rev. 1 17-78 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 18 LCD Interface (LCDIF) This chapter describes the LCD interface included on the i.MX23 and includes operation examples. Programmable registers are described in Section 18.4, "Programmable Registers." 18.1 Overview Many products based on the i.MX23 include an LCD panel with an integrated controller/driver. These smart LCDs are available in a range of sizes and capabilities, from simple text-only displays to QVGA, 16/18/24 bpp color TFT panels. Traditionally, many of these display controllers have had an asynchronous parallel System (or MCU) interface for command and data transfer to the frame buffer. There are other popular displays that support moving pictures and require the RGB interface mode (called DOTCLK interface in this document) or the VSYNC mode for high-speed data transfers. In addition to these displays, it is also common to provide support for digital video encoders that accept ITU-R BT.656 format 4:2:2 YCbCr digital component video and convert it to analog TV signals. The LCDIF block on i.MX23 supports all of these different interfaces by providing fully programmable functionality and sharing register space, FIFOs, and ALU resources at the same time. The high-level block diagram of the LCD interface provided on the i.MX23 is shown in Figure 18-1. The block has several major features: * * * * Bus master and PIO operating modes for LCD writes requiring minimal CPU overhead. 8/16/18/24 bit LCD data bus support available depending on the package size. Programmable timing and parameters for system, VSYNC and DOTCLK LCD interfaces to support a wide variety of displays. ITU-R BT.656 mode (called Digital Video Interface or DVI mode here) including progressive-to-interlace feature and RGB to YCbCr 4:2:2 color space conversion to support 525/60 (NTSC) and 625/50 (PAL) operation. Hardware-based pin sharing with NAND data pins in system and VSYNC modes. * 18.2 Operation The general description provided in Section 18.2.1, "Bus Interface Mechanisms," through Section 18.2.4, "Initializing the LCDIF," is applicable to all the interface modes, because they all share the same pipeline until the TXFIFO. The differences for each mode are then described in separate sections, as follows: * * Section 18.2.5, "System Interface," "System Interface" Section 18.2.6, "VSYNC Interface," "VSYNC Interface" i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-1 LCD Interface (LCDIF) * * Section 18.2.7, "DOTCLK Interface,""DOTCLK Interface" Section 18.2.8, "ITU-R BT.656 Digital Video Interface (DVI)," "ITU-R BT.656 Digital Video Interface (DVI)" LCDIF pin usage by interface mode is described in Section 18.2.9, "LCDIF Pin Usage by Interface Mode." EMI ARM Core SRAM 24-MHz XTAL Osc. or PLL AHB AHB Slave AHB Master DIV HCLK DIV PIXCLK Shared DMA AXI APBH Master APBH AHB-to-APBH Bridge APBH LCDIF APB AXI Master HCLK Domain HW_LCDIF_CTRL and _DATA Registers and APB Slave APBH Ctrl Write Data 38x128 LFIFO System / VSYNC/ DOTCLK LCD Interface 38x2 INTFIFO 38x8 TXFIFO Digital Video Interface PIXCLK Domain To LCD Pins Figure 18-1. LCDIF Top Level Diagram i.MX23 Applications Processor Reference Manual, Rev. 1 18-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) 18.2.1 Bus Interface Mechanisms The LCDIF block has memory-mapped control, data and status registers. It provides two efficient methods of transferring data, namely APB PIO and AXI bus master, to an external LCD controller or a digital video encoder. In either mode of operation, the bus interface portion of the block works off the HCLK domain, while the actual interface to external display/encoder works off the PIXCLK domain. There are two main FIFOs in the block datapath. The latency FIFO (LFIFO) is a 128 words deep synchronous FIFO that offers buffering against system bandwidth and latency. The other FIFO, called TXFIFO, is an 8 words deep asynchronous FIFO that assists data crossing between the two clock domains. In between these two FIFOs is a small 2-word deep INTFIFO that is used for unpacking the data and color space conversion. The following sub-sections describe the two system bus interface mechanisms. 18.2.1.1 PIO Operation The CPU can directly send commands or data to the LCD panel by setting up the block in non-bus-master mode (HW_LCDIF_CTRL_LCDIF_MASTER = 0) and writing directly to the HW_LCDIF_DATA register. The FIFO status bits in the HW_LCDIF_STAT register indicate the full and empty states of both the LFIFO and the TXFIFO. When the LFIFO is not full, the data register can be safely written with a word, halfword, or byte as required; doing otherwise will result in incorrect operation. Software can also wait for the DMA_REQ bit in HW_LCDIF_STAT register to toggle before writing new data into the HW_LCDIF_DATA register. Since PIO mode is a very low speed mode of operation, it should be used only for system mode, not in DOTCLK and DVI modes. 18.2.1.2 Bus Master Operation In this mode, the LCDIF block acts as a master on the AXI bus shared by other blocks like DCP, PXP and BCH. This is a high performance mode that can be used for sending large frames of data quickly and efficiently. In this mode, LCDIF issues bursts of 16-word fetches (or 15-word in packed 24-bit mode) from the memory. In Bus Master operation, the HW_LCDIF_CTRL_LCDIF_MASTER bit should be set to 1. The HW_LCDIF_CUR_BUF_ADDR and HW_LCDIF_NEXT_BUF_ADDR registers should be programmed to point to the base address of the frame buffers that needs to be transferred out. In system and VSYNC modes, once the data in the frame buffer pointed to by the HW_LCDIF_CUR_BUF_ADDR is transferred out, the LCDIF stops transmitting and turns off the RUN bit in HW_LCDIF_CTRL. Hence, HW_LCDIF_CUR_BUF_ADDR has to be setup and kicked off again for transmitting the next frame; In this mode, the HW_LCDIF_NEXT_BUF_ADDR register is not used at all. In the DOTCLK and DVI modes, before the RUN bit is set, software should start off with programming both the HW_LCDIF_CUR_BUF_ADDR and HW_LCDIF_NEXT_BUF_ADDR registers, and then, it should update only the HW_LCDIF_NEXT_BUF_ADDR register at the end of every frame. The LCDIF will automatically copy the value in the HW_LCDIF_NEXT_BUF register to the i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-3 LCD Interface (LCDIF) HW_LCDIF_CUR_BUF register before issuing the cur_frame_done interrupt and it will start fetching the next frame from the new address. In other words, when the ISR for the cur_frame_done interrupt is entered, HW_LCDIF_CUR_BUF and HW_LCDIF_NEXT_BUF registers will have the same value until a new value is programmed in the HW_LCDIF_NEXT_BUF register. Thus, software has about one frame worth of time to update HW_LCDIF_NEXT_BUF_ADDR before it actually gets used. If for some reason, the HW_LCDIF_NEXT_BUF_ADDR register was not updated within a frame, the LCDIF will continue transmitting the last frame until a new value is programmed into that register. The LCDIF also provides the capability of interlacing a progressive frame by fetching odd lines in the first field and then fetching even lines in the second field. This feature is likely to be used in the DVI mode for transmitting to an internal/external TV encoder and can be turned on by setting the INTERLACE_FIELDS bit in the HW_LCDIF_CTRL1 register. 18.2.2 Write Datapath All frame buffers must be arranged in the raster format since external displays and digital video encoders require data in the raster format. The LCDIF receives little-endian data from the CPU or directly fetches it from memory. This raw input data can be swizzled according to the INPUT_DATA_SWIZZLE field in the HW_LCDIF_CTRL1 register before any other operation is performed on the incoming data. The following four combinations are supported: * * * * 00 (0): No swizzle (little-endian) 01 (1): Swap bytes 0 and 3, swap bytes 1 and 2 (big-endian) 10 (2): Swap half-words 11 (3): Swap bytes within each half-word The WORD_LENGTH field of the HW_LCDIF_CTRL register indicates the input data/pixel format. HW_LCDIF_TRANSFER_COUNT register denotes how much data is contained in each frame. The H_COUNT field of this register indicates the number of active pixels per line and V_COUNT indicates the total active number of lines per frame. A special bit field in the CTRL1 register, called the BYTE_PACKING_FORMAT, can be used to specify which bytes within the 32-bit word are going to be valid. For example, if the entire 32-bit word is valid, BYTE_PACKING_FORMAT should be set to 0xF, if only lower 3 bytes of each word in the frame buffer are valid, then BYTE_PACKING_FORMAT should be set to 0x7. The LCD_DATABUS_WIDTH field in HW_LCDIF_CTRL register indicates the width of the bus going to the external display controller. If the LCD_DATABUS_WIDTH is not the same as WORD_LENGTH, LCDIF will do minor RGB-to-RGB color space conversion (CSC). For example, if the input frame has more bits per pixel than the display, e.g. 16 bpp input frame going to 24 bpp LCD, the LCDIF will pad the MSBs of each color component to the LSBs of the same color component for each pixel. If the input frame has fewer bits per pixel than the display, e.g. a 24 bpp input frame going to a 16 bpp LCD, the LCDIF will drop the LSBs of each color component to go to the lower resolution. If software wants to i.MX23 Applications Processor Reference Manual, Rev. 1 18-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) make sure that CSC does not take place, it must ensure that WORD_LENGTH and LCD_DATABUS_WIDTH have the same value. The LCDIF also supports RGB to YCbCr 4:2:2 color space conversion. This is useful in the DVI mode since the TV encoder requires input in YCbCr 4:2:2 format. The HW_LCDIF_CSC registers have complete programmability over the CSC coefficients and offsets. The values must be written into these registers in the signed two's complement format. The following list shows how the different input/output combinations can be obtained: * WORD_LENGTH=1 indicates that the input is 8-bit data. This is most likely going to be used for sending commands in System interface, or maybe a grayscale image. Any combination of BYTE_PACKING_FORMAT [3:0] is permissible (except 0). Limitations: -- H_COUNT must be a multiple of the sum of BYTE_PACKING_FORMAT [3], BYTE_PACKING_FORMAT [2], BYTE_PACKING_FORMAT [1] and BYTE_PACKING_FORMAT [0]. -- LCD_DATABUS_WIDTH must be 1, indicating an 8-bit data bus. WORD_LENGTH=0 implies the input frame buffer is RGB 16 bits per pixel. DATA_FORMAT_16_BIT field indicates if the pixels are in RGB 555 or RGB 565 format. Limitations: -- BYTE_PACKING_FORMAT [3:0] should be 0x3 or 0xC if there is only one pixel per word. -- If there are two pixels per word, BYTE_PACKING_FORMAT [3:0] should be 0xF and H_COUNT will be restricted to be a multiple of 2 pixels. WORD_LENGTH=2 indicates that input frame buffer is RGB 18 bits per pixel, i.e. RGB 666. The valid RGB values can be left-aligned or right-aligned within a 32-bit word. The alignment of the valid 18 bits within a word is indicated by the DATA_FORMAT_18_BIT bit. There is no limitation on H_COUNT. Limitations: -- BYTE_PACKING_FORMAT must be 0xF. -- Packed pixels are not supported in this case. WORD_LENGTH=3 indicates that the input frame-buffer is RGB 24 bits per pixel (RGB 888). If BYTE_PACKING_FORMAT [3:0] is 0x7, it indicates that there is only one pixel per 32-bit word and there is no restriction on H_COUNT. Limitations: -- If BYTE_PACKING_FORMAT [3:0] is 0xF, it indicates that the pixels are packed, i.e. there are 4 pixels in 3 words or 12 bytes. In that case, H_COUNT must be a multiple of 4 pixels. YCBCR422_INPUT=1 implies that the input frame is in YCbCr 4:2:2 format. BYTE_PACKING_FORMAT must be 0xF. Limitations: -- LCD_DATABUS_WIDTH must be 8-bit -- H_COUNT must be a multiple of 2 pixels. i.MX23 Applications Processor Reference Manual, Rev. 1 * * * * Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-5 LCD Interface (LCDIF) After the RGB-to-RGB or RGB-to-YCbCr 4:2:2 color space conversions, there is one more opportunity to swizzle the data before sending it out to the display or the encoder. This can be done with the CSC_DATA_SWIZZLE field in the HW_LCDIF_CTRL1 register, and it provides the same options as the INPUT_DATA_SWIZZLE register. Finally, there is an option to shift the output data before sending it out to the display. This is done based on the SHIFT_DIR and SHIFT_NUM_BITS fields in HW_LCDIF_CTRL1 register. Figure 18-2 shows the general operations that occur in the write data path. HC LK D o m a in VSYNC and DO TCLK M ode C o n tro l P IX C L K D o m a in W r ite C o n tr o l 2 X m it D a ta P IO / AXI MST CTRL 32 32 R G B to YCbCr 4 :2 :2 38 R ead C o n tro l 32 38 38 S h ift LC D D a ta Swzl 4 38x 128 L f if o 4 4 38 B y te En C n t C a lc U npack & RGB to R G B 888 CSC 38x 8 Tx fifo X fe r C tr l 4 32 S ig G en LC D C tr l F IF O S ta tu s F IF O S ta tu s Figure 18-2. LCDIF Write DataPath The examples in Figure 18-3-Figure 18-6 illustrate some different combinations of register programming for write mode. Assume that the data written into the HW_LCDIF_DATA register is of the format {A7-A0, B7-B0, C7-C0, D7-D0} in 8-bit mode and {A15-A0, B15-B0} in 16-bit mode. i.MX23 Applications Processor Reference Manual, Rev. 1 18-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) WORD_LENGTH = 1 HW_LCDIF_DATA A7-A0 B7-B0 C7-C0 D7-D0 BYTE_PACKING_FORMAT[3:0] = 1111 A7-A0 B7-B0 C7-C0 D7-D0 DATA_SWIZZLE[1:0] = 00 A7-A0 B7-B0 C7-C0 D7-D0 SHIFT_DIR = 1, SHIFT_NUM_BITS[1:0] = 10 {0,0,A7-A2} {0,0,B7-B2} {0,0,C7-C2} {0,0,D7-D2} LCD_DATABUS_WIDTH = 1 LCD_D[7:0] Pins {0,0,D7-D2} {0,0,C7-C2} {0,0,B7-B2} {0,0,A7-A2} Figure 18-3. 8-Bit LCDIF Register Programming--Example A i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-7 LCD Interface (LCDIF) WORD_LENGTH = 1 HW_LCDIF_DATA A7-A0 B7-B0 C7-C0 D7-D0 BYTE_PACKING_FORMAT[3:0] = 0111 X B7-B0 C7-C0 D7-D0 DATA_SWIZZLE[1:0] = 01 D7-D0 C7-C0 B7-B0 X SHIFT_DIR = 0, SHIFT_NUM_BITS[1:0] = 00 D7-D0 C7-C0 B7-B0 X LCD_DATABUS_WIDTH = 1 LCD_D[7:0] Pins B7-B0 C7-C0 D7-D0 Figure 18-4. 8-Bit LCDIF Register Programming--Example B i.MX23 Applications Processor Reference Manual, Rev. 1 18-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) WORD_LENGTH = 0 HW_LCDIF_DATA A15-A0 B15-B0 BYTE_PACKING_FORMAT[3:0] = 1111 A15-A0 B15-B0 DATA_SWIZZLE[1:0] = 00 A15-A0 B15-B0 SHIFT_DIR = 1, SHIFT_NUM_BITS[1:0] = 10 {0,0,A15-A2} {0,0,B15-B2} LCD_DATABUS_WIDTH = 0 LCD_D[15:0] Pins {0,0,A15-A2} {0,0,B15-B2} Figure 18-5. 16-Bit LCDIF Register Programming--Example A i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-9 LCD Interface (LCDIF) WORD_LENGTH = 0 HW_LCDIF_DATA A15-A0 B15-B0 BYTE_PACKING_FORMAT[3:0] = 1100 A15-A0 X DATA_SWIZZLE[1:0] = 01 X A15-A0 RGB-TO-RGB CSC NEW_A X {A15 - A11, A15 - A13} {A10 - A5, A10 - A9} {A4 - A0, A4 - A2} SHIFT_DIR = 1, SHIFT_NUM_BITS[1:0] = 00 X NEW_A23 - NEW_A0 LCD_DATABUS_WIDTH = 3 LCD_D[23:0] Pins NEW_A23 - NEW_A0 Figure 18-6. 16-Bit LCDIF Register Programming--Example B 18.2.3 LCDIF Interrupts The LCDIF supports a number of interrupts to aid controlling and status reporting of the block. All the interrupts have individual mask bits for enabling or disabling each of them. They all get funneled through a single interrupt line connected to the interrupt collector (ICOLL). The following list describes the different interrupts supported by the LCDIF: * Underflow interrupt is asserted when the clock domain crossing FIFO (TXFIFO) becomes empty but the block is in active display portion at that time. Software should take corrective action to make sure that this does not happen. This interrupt is of value only in DOTCLK and DVI modes. Overflow interrupt will be asserted in PIO mode if software writes to LFIFO while it is full. * i.MX23 Applications Processor Reference Manual, Rev. 1 18-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) * * * VSYNC edge interrupt will be asserted every time a leading VSYNC edge occurs. Cur_frame_done interrupt occurs at the end of every frame in all modes except DVI. In DVI mode, if IRQ_ON_ALTERNATE_FIELDS bit is set, it will occur at the end of every frame, otherwise it will occur at the end of every field. In the DOTCLK and DVI modes, the LCDIF will automatically copy the value in the HW_LCDIF_NEXT_BUF register to the HW_LCDIF_CUR_BUF register before issuing the cur_frame_done interrupt. Bus master error interrupt occurs when the LCDIF receives an AXI bus error from the slave memory it is trying to access. Software should debug the source of this error before proceeding further. The address corresponding to the error response is reflected in the BM_ERROR_STAT register. 18.2.4 Initializing the LCDIF The following initialization steps are common to all LCDIF modes of operation before entering any particular mode. Initialization Steps: 1. To select the pins and their directions for interfacing to the LCD panel, set the appropriate bits in the HW_PINCTRL_MUXSELx registers in the PINCTRL block. 2. Start the PIXCLK and set the appropriate frequency by programming the registers in CLKCTRL. 3. Bring the LCDIF out of soft reset and clock gate. 4. Reset the LCD controller by setting LCDIF_CTRL1_RESET bit appropriately, being careful to observe the reset requirements of the controller. Select the bus interface mechanism with the LCDIF_MASTER bit in HW_LCDIF_CTRL register. If bus master mode is enabled (LCDIF_MASTER=1), set the HW_LCDIF_CUR_BUF and HW_LCDIF_NEXT_BUF registers by following the description in Section 18.2.1, "Bus Interface Mechanisms. 5. Set the INPUT_DATA_SWIZZLE according to the endianness of the LCD controller. Also set the DATA_SHIFT_DIR and SHIFT_NUM_BITS if it is required to shift the data left or right before it is output. 6. Set the WORD_LENGTH field appropriately, indicating the resolution of the pixels in the frame buffer: 0 = 16-bit pixel, 1 = 8-bit pixel, 2 = 18-bit pixel, 3 = 24-bit pixel. Also select the correct 16/18/24 bit data format with the corresponding fields in HW_LCDIF_CTRL register. 7. Set the BYTE_PACKING_FORMAT field in HW_LCDIF_CTRL1 according to the input frame. 8. Set the LCD_DATABUS_WIDTH appropriately: 0 = 16-bit output, 1 = 8-bit output, 2 = 18-bit output, 3 = 24-bit output. 9. Enable the necessary IRQs. The following sections are dedicated to detailing the different external interfaces supported by LCDIF. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-11 LCD Interface (LCDIF) 18.2.5 System Interface The System interface is used to transfer data and commands between the internal buffer of an LCD controller/display and the ARM processor at relatively lower speeds. The LCDIF supports both the 6800 and the 8080 MCU protocols. If DOTCLK_MODE, DVI_MODE and VSYNC_MODE bits in HW_LCDIF_CTRL registers are 0, it implies that the block is in system interface mode. The LCDIF system mode has four basic timing parameters: Setup and Hold for the Command/Data register selection (TCS, TCH) and Setup and Hold for the Data bus (TDS, TDH). These parameters are expressed in PIXCLK cycles. The LCD_WR signal is used as the write strobe while LCD_RS (Register Select) signal is typically used to switch between command and data modes. Figure 18-7 shows the timing-related information in the write mode of both 6800 and 8080 protocols. IDLE START W1+ W3 WR/RD LATCH W2 WR/RD LATCH STOP IDLE VSYNC_PULSE_WIDTH LCD_VSYNC LCD_RS TCS TCH LCD_CS LCD_WR (8080) LCD_WR (6800) TDSW TDHW Data0 TDSW TDHW Data1 LCD_DATA[23:0] Figure 18-7. LCD Interface Signals in System Write Mode In the 6800 mode, the LCD_WR pin acts as an active high data strobe (ENABLE) and in the 8080 mode, it acts as an active low data strobe (WRn). The LCDIF has flexible pin and strobe timings which enable it to optimally support a wide range of LCDs. The minimum cycle time is two PIXCLK cycles (TDS=TDH=1). For example, this results in a maximum LCD data rate of 12MB/s when PIXCLK is 24 MHz. TDS and TDH are 8-bit values, so the minimum LCDIF period is 510 PIXCLK cycles (47 kHz with a 24-MHz PIXCLK). The timings are not automatically adjusted if the PIXCLK frequency changes, so it may be necessary to adjust the timings if PIXCLK changes. In the system interface mode, the HW_LCDIF_CTRL_ BYPASS_COUNT bit must be 0. The RUN bit is cleared automatically once the LCDIF has transmitted all the data as per the HW_LCDIF_TRANSFER_COUNT register and has completed the transfer to the panel. The current transfer can be cancelled/aborted if the RUN bit is manually set to 0. i.MX23 Applications Processor Reference Manual, Rev. 1 18-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) 18.2.5.1 Code Example to initialize LCDIF in System mode // Note: Common initialization steps in Section 18.2.4, "Initializing the LCDIF," must also be // executed along with the following code BF_CS1(LCDIF_CTRL, DATA_SELECT, 1); // 0 if sending command, 1 if sending data. Note that the idle state for LCD_RS signal is high, regardless of the programming of the DATA_SELECT register. BF_CS1 (LCDIF_CTRL, MODE86, 8080_MODE); BF_CS1 (LCDIF_CTRL, BYPASS_COUNT, 0); //Must be 0 in system mode BF_CS1 (LCDIF_CTRL1, BUSY_ENABLE, 1);//Only if LCD controller implements a busy line BF_CS4 (LCDIF_TIMING, CMD_HOLD, 2, CMD_SETUP, 2, DATA_HOLD, 2, DATA_SETUP, 2); //Values based on PIXCLK frequency and timing requirements of controller. Note that these register must be non-zero for correct operation. BF_CS2 (LCDIF_TRANSFER_COUNT, H_COUNT, 320, V_COUNT, 240); //For a 320 RGB x 240 display BF_CS1 (LCDIF_CTRL, RUN, 1); The LCDIF is now ready to receive data through PIO writes to the HW_LCDIF_DATA register or fetch data directly from memory as a bus master. Also, note that, while in PIO mode, the software will need to poll the FIFO STATUS bits to ensure that it does not overflow the LCDIF data buffers. When LCDIF is done transmitting H_COUNT x V_COUNT pixels, it will stop, turn off the RUN bit and assert the cur_frame_done interrupt. 18.2.6 VSYNC Interface The VSYNC interface uses the same protocol as the System interface, with an additional signal VSYNC at the frame rate of the display, as shown in Figure 18-7. It is used in the moving picture display mode where data has to be written to the internal LCD buffer at a speed higher than the display rate and displayed in synchronization with the VSYNC signal. This mode is selected by setting the VSYNC_MODE bit in HW_LCDIF_CTRL register. The VSYNC signal is programmable for period, polarity and direction. Many other programmable parameters are shared with the System interface. The VSYNC_OEB bit in HW_LCDIF_VDCTRL0 register indicates whether the display controller will send the VSYNC signal, or whether it should be generated by the LCDIF. The timing of the VSYNC signal is based on the PIXCLK (make sure VSYNC_PULSE_WIDTH_UNIT = VSYNC_PERIOD_UNIT = 0 and VSYNC_ONLY = 1) and it is determined by the VSYNC_PERIOD, VSYNC_PULSE_WIDTH and VSYNC_POL fields in HW_LCDIF_VDCTRL0-4 registers. The SYNC_SIGNALS_ON bit in HW_LCDIF_VDCTRL4 register must be set if the target requires the VSYNC signal to be generated by the LCDIF. If the WAIT_FOR_VSYNC_EDGE bit in HW_LCDIF_CTRL register is set, it indicates that the hardware should wait until it sees the leading VSYNC edge before starting the data transfer. The VERTICAL_WAIT_CNT indicates the number of PIXCLKs from the leading VSYNC edge after which data transfer will be started on the interface. In the VSYNC interface mode, the HW_LCDIF_CTRL_ BYPASS_COUNT bit must be 0. The RUN bit is cleared automatically once the LCDIF has received/transmitted all the data as per the HW_LCDIF_TRANSFER_COUNT register and has completed the transfer to the panel. The current transfer can be cancelled/aborted if the RUN bit is manually set to 0. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-13 LCD Interface (LCDIF) 18.2.6.1 Code Example to initialize LCDIF in VSYNC mode // Note: Common initialization steps in Section 18.2.4, "Initializing the LCDIF," must also be // executed along with the following code BF_CS1 (LCDIF_CTRL, DATA_SELECT, 1); // 0 if sending command, 1 if sending data. Note that //the idle state for LCD_RS signal is high, regardless of the programming of the DATA_SELECT //register. BF_CS1 (LCDIF_CTRL, MODE86, 8080_MODE); BF_CS1 (LCDIF_CTRL, BYPASS_COUNT, 0); //Must be 0 in system mode BF_CS1 (LCDIF_CTRL1, BUSY_ENABLE, 0); BF_CS4 (LCDIF_TIMING, CMD_HOLD, 2, CMD_SETUP, 2, DATA_HOLD, 2, DATA_SETUP, 2); //Values //based on PIXCLK frequency and timing requirements of controller. Note that these register //must be non-zero for the system and VSYNC modes. BF_CS2 (LCDIF_TRANSFER_COUNT, H_COUNT, 320, V_COUNT, 240);//For a 320 RGB x 240 display //The following section indicates setting up the VSYNC signal timing when VSYNC is an output BF_CS1 (LCDIF_VDCTRL0, VSYNC_OEB, 0); //Making VSYNC signal an output BF_CS1 (LCDIF_VDCTRL4, VSYNC_ONLY, 1); //Only need to generate VSYNC signal, not HSYNC/DOTCLK/ENABLE BF_CS1 (VDCTRL0, VSYNC_POL, 0); //Setting the polarity of VSYNC signal to be low during //VSYNC_PULSE_WIDTH time BF_CS2 (LCDIF_VDCTRL0, VSYNC_PERIOD_UNIT, 0, VSYNC_PULSE_WIDTH_UNIT, 0); BF_CS2 (LCDIF_VDCTRL1, VSYNC_PERIOD, 400000, VSYNC_PULSE_WIDTH, 100);//Frame display rate in //terms of number of PIXCLKs. BF_CS2 (LCDIF_VDCTRL2, HSYNC_PULSE_WIDTH, 0, HSYNC_PERIOD, 0); BF_CS1 (LCDIF_VDCTRL3, VERTICAL_WAIT_CNT, 50); BF_CS1 (LCDIF_VDCTRL4, SYNC_SIGNALS_ON, 1); BF_CS2 (LCDIF_CTRL, VSYNC_MODE, 1, WAIT_FOR_VSYNC_EDGE, 1); //set WAIT_FOR_VSYNC_EDGE if //software wishes to transfer the next frame after the VSYNC edge occurs. BF_CS1 (LCDIF_CTRL, RUN, 1); The LCDIF is now ready to receive data through PIO writes to the HW_LCDIF_DATA register or fetch data directly from memory as a bus master. When LCDIF is done transmitting H_COUNT x V_COUNT pixels, it will stop, turn off the RUN bit and assert the cur_frame_done interrupt. 18.2.7 DOTCLK Interface The DOTCLK interface is another mode used in moving picture displays that constantly require display refreshes. It includes the VSYNC, HSYNC, DOTCLK and (optional) ENABLE signals. The interface is popularly called the RGB interface if the ENABLE signal is present. i.MX23 Applications Processor Reference Manual, Rev. 1 18-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) Figure 18-8 shows the DOTCLK protocol with its programmable parameters. One Frame (VSYNC) Period Vertical Back Porch Vertical Front Porch VSYNC VSYNC Pulse Width HSYNC DOTCLK Vertical Valid Data Count ENABLE VSYNC Wait Count D7-D0 VSYNC_POL = 0 One Line (HSYNC) Period HSYNC Pulse Width HSYNC_POL = 0 DOTCLK_POL = 0 ENABLE_POL = 0 HSYNC DOTCLK ENABLE HSYNC Wait Count D7-D0 Horizontal Valid Data Count Figure 18-8. LCD Interface Signals in DOTCLK Mode The DOTCLK mode writes data at high speed to the LCD, and the display operation is synchronized with the VSYNC, HSYNC, ENABLE and DOTCLK signals. The polarities, periods and pulse-widths of the sync signals are programmable using the HW_LCDIF_VDCTRL0-4 registers. The units for the VSYNC signal must be number of horizontal lines and can be set using the VSYNC_PULSE_WIDTH_UNIT and VSYNC_PERIOD_UNIT bit fields. The VERTICAL_WAIT_CNT is by default given the same unit as the VSYNC_PERIOD. The PIXCLK is controlled using the HW_CLKCTRL_PIX, HW_CLKCTRL_FRAC, and HW_CLKCTRL_CLKSEQ registers in the CLCKTRL block. In DOTCLK mode, HW_LCDIF_CTRL_BYPASS_COUNT bit must be set to 1. To end the current transfer, the software should make the DOTCLK_MODE bit 0, so that all data that is currently in the LCDIF FIFOs is transmitted. Once that transfer is complete, the block will automatically clear the RUN bit and issue the cur_frame_done interrupt. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-15 LCD Interface (LCDIF) 18.2.7.1 Code Example The following code shows an example for programming a 320x240 display. Note that setting up the display must be done through the System mode or via SPI. // Note: Common initialization steps in Section 18.2.4, "Initializing the LCDIF," must also be // executed along with the following code BF_CS1 (LCDIF_CTRL, DOTCLK_MODE, 1); BF_CS1 (LCDIF_CTRL, BYPASS_COUNT, 1); //Always for DOTCLK mode BF_CS1 (LCDIF_VDCTRL0, VSYNC_OEB, 0); //Vsync is always an output in the DOTCLK mode BF_CS4 (LCDIF_VDCTRL0, VSYNC_POL, 0, HSYNC_POL, 0, DOTCLK_POL, 0, ENABLE_POL, 0); BF_CS1 (LCDIF_VDCTRL0, ENABLE_PRESENT, 1); BF_CS2 (LCDIF_VDCTRL0, VSYNC_PERIOD_UNIT, 1, VSYNC_PULSE_WIDTH_UNIT, 1); BF_CS1 (LCDIF_VDCTRL0, VSYNC_PULSE_WIDTH, 2); BF_CS1 (LCDIF_VDCTRL1, VSYNC_PERIOD, 280); BF_CS2 (LCDIF_VDCTRL2, HSYNC_PULSE_WIDTH, 10, HSYNC_PERIOD, 360); //Assuming LCD_DATABUS_WIDTH //is 24bit BF_CS2 (LCDIF_VDCTRL3, VSYNC_ONLY, 0); BF_CS2 (LCDIF_VDCTRL3, HORIZONTAL_WAIT_CNT, 20, VERTICAL_WAIT_CNT, 20); BF_CS1 (LCDIF_VDCTRL4, DOTCLK_H_VALID_DATA_CNT, 320);//Note that DOTCLK_V_VALID_DATA_CNT is //implicitly assumed to be HW_LCDIF_TRANSFER_COUNT_V_COUNT BF_CS1 (LCDIF_VDCTRL4, SYNC_SIGNALS_ON, 1); BF_CS1 (LCDIF_CTRL, RUN, 1); 18.2.8 ITU-R BT.656 Digital Video Interface (DVI) ITU-R BT.656 Digital Video Interface shown in Figure 18-9 transmits 4:2:2 YCbCr digital component video to the digital video encoder block (TVENC) that can translate it into 525/60 or 625/50 analog TV signal. Unique timing codes (timing reference signals) are embedded within the video stream to indicate the different timing events that would have been otherwise indicated by VSYNC, HSYNC and BLANK signals. The hardware supports 8-bit data transfers; the pins are shared with the lower 8 bits of LCD data bus. The LCD_RS pin is shared with the clock signal of the interface (called CCIRCLK here for uniqueness). CCIRCLK also can be obtained on the LCD_DOTCK pin. The DVI mode shares the write FIFO with the LCD interface and the associated pipeline. The programmable parameters in registers HW_LCDIF_DVICTRL0-3 allow setting the total number of horizontal lines per frame, vertical and horizontal blanking interval, odd and even field start and end positions, etc. In short, these parameters are provided to ensure that the hardware has enough flexibility to generate the right 525/60 or 625/50 data streams. Most of the initialization steps in Section 18.2.4, "Initializing the LCDIF," such as data shifting, swizzle, etc., are applicable to DVI mode also. The register descriptions in Section 18.4, "Programmable Registers," include example code for programming the DVICTRL0-4 registers. In DVI mode, HW_LCDIF_CTRL_BYPASS_COUNT bit must be set to 1. To end the current transfer, the software should make the DVI_MODE bit the value 0, so that all data that is currently in the LCDIF LFIFO and TXFIFO is transmitted. Once that transfer is complete, the block will automatically clear the RUN bit and assert the cur_frame_done interrupt. i.MX23 Applications Processor Reference Manual, Rev. 1 18-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) H Control Signal Start of Digital Line EAV Code F F 0 0 0 0 X Y 8 0 1 0 8 0 Blanking 1 0 8 0 1 0 F F SAV Code 0 0 0 0 X Y Start of Digital Active Line Co-Sited C B Y C R Y Co-Sited C B Y C R Y C B Y F F Next Line Digital Video Stream 4 268 (280) 1716 (1728) 4 1440 Figure 18-9. LCDIF Interface Signals in ITU-R BT.656 Digital Video Interface Mode 18.2.9 LCDIF Pin Usage by Interface Mode The following table shows the pin usage for all of the supported modes when the HW_PINCTRL_MUXSEL2 and HW_PINCTRL_MUXSEL3 registers are programmed for LCD functionality. See Chapter 37, "Pin Control and GPIO," for a more complete description of pin multiplexing options and how to program each pin individually. Notes: 1. When LCD_DATABUS_WIDTH is more than 8 bits, the R component is on the MSB bits of the LCD data pins, the G component is in the middle and the B component is on the LSB bits. For example, if LCD_DATABUS_WIDTH = 16 bits, LCD_D15 - LCD_D11 = R[4:0], LCD_D10 -LCD_D05 = G[5:0], LCD_D04 - LCD_D00 = B[4:0]. 2. The VSYNC signal has been mapped onto two pins, LCD_BUSY and LCD_VSYNC. The PINCTRL block can be programmed to select either of those pins to function as VSYNC. 3. There is an option to internally mux the HSYNC, DOTCLK and ENABLE signals in the DOTCLK mode onto the LCD_D14-LCD_12 pins by setting the MUX_SYNC_SIGNALS bit in the VDCTRL0 register for backward compatibility with previous generation SoCs. Table 18-1. Pin Usage in System Mode and VSYNC Mode PIN LCD_RS LCD_CS LCD_WR LCD_VSYNC* LCD_HSYNC SYS - 8 LCD_ RS LCD_CS LCD_WR X X SYS - 16 LCD_ RS LCD_CS LCD_ WR X X SYS -18 LCD_ RS LCD_ CS LCD_WR X X SYS - 24 LCD_RS LCD_CS LCD_WR X X VSYNC - 8 LCD_RS LCD_CS LCD_WR LCD_VSYNC X VSYNC - 16 LCD_ RS LCD_CS LCD_ WR LCD_VSYNC X VSYNC - 18 LCD_RS LCD_ CS LCD_WR LCD_ VSYNC X VSYNC - 24 LCD_RS LCD_CS LCD_WR LCD_VSYNC X i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-17 LCD Interface (LCDIF) Table 18-1. Pin Usage in System Mode and VSYNC Mode (continued) LCD_DOTCLK LCD_ENABLE LCD_D23 LCD_D22 LCD_D21 LCD_D20 LCD_D19 LCD_D18 LCD_D17 LCD_D16 LCD_D15* LCD_D14 * LCD_D13* LCD_D12* LCD_D11 LCD_D10 LCD_D09 LCD_D08 LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 LCD_RESET LCD_BUSY/ LCD_VSYNC X X X X X X X X X X X X X X X X X X LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 X X X X X X X X X X LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D09 LCD_D08 LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 X X X X X X X X LCD_D17 LCD_D16 LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D09 LCD_D08 LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 X X LCD_D23 LCD_D22 LCD_D21 LCD_D20 LCD_D19 LCD_D18 LCD_D17 LCD_D16 LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D09 LCD_D08 LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 X X X X X X X X X X VSYNC (optional) X X X X X X X LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 LCD_RESET X X X X X X X X X X LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D09 LCD_D08 LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 LCD_RESET X X X X X X X X LCD_D17 LCD_D16 LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D09 LCD_D07 LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 LCD_RESET X X LCD_D23 LCD_D22 LCD_D21 LCD_D20 LCD_D19 LCD_D18 LCD_D17 LCD_D16 LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D09 LCD_D08 LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 LCD_RESET LCD_RESET LCD_RESET LCD_RESET LCD_RESET LCD_BUSY LCD_BUSY LCD_BUSY LCD_BUSY LCD_BUSY LCD_BUSY LCD_BUSY LCD_BUSY (OR optional (OR optional (OR optional (OR optional LCD_VSYNC) LCD_VSYNC) LCD_VSYNC) LCD_VSYNC) Table 18-2. Pin Usage in DOTCLK Mode and DVI Mode PIN LCD_RS LCD_CS LCD_WR DOTCLK - 8 X X X DOTCLK - 16 X X X DOTCLK - 18 X X X DOTCLK - 24 X X X DVI - 8 CCIR_CLK X X i.MX23 Applications Processor Reference Manual, Rev. 1 18-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) Table 18-2. Pin Usage in DOTCLK Mode and DVI Mode (continued) LCD_VSYNC (Two options) LCD_HSYNC LCD_DOTCLK LCD_ENABLE LCD_D23 LCD_D22 LCD_D21 LCD_D20 LCD_D19 LCD_D18 LCD_D17 LCD_D16 LCD_D15* LCD_D14* LCD_D13* LCD_D12* LCD_D11 LCD_D10 LCD_D09 LCD_D08 LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 LCD_RESET LCD_BUSY / LCD_VSYNC LCD_VSYNC LCD_HSYNC LCD_DOTCLK LCD_ENABLE X X X X X X X X X X X X X X X X LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 LCD_RESET LCD_BUSY (OR optional LCD_VSYNC) LCD_VSYNC LCD_HSYNC LCD_DOTCLK LCD_ENABLE X X X X X X X X LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D09 LCD_D08 LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 LCD_RESET LCD_BUSY (OR optional LCD_VSYNC) LCD_VSYNC LCD_HSYNC LCD_DOTCLK LCD_ENABLE X X X X X X LCD_D17 LCD_D16 LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D09 LCD_D08 LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 LCD_RESET LCD_BUSY (OR optional LCD_VSYNC) LCD_VSYNC LCD_HSYNC LCD_DOTCLK LCD_ENABLE LCD_D23 LCD_D22 LCD_D21 LCD_D20 LCD_D19 LCD_D18 LCD_D17 LCD_D16 LCD_D15 LCD_D14 LCD_D13 LCD_D12 LCD_D11 LCD_D10 LCD_D09 LCD_D08 LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 LCD_RESET LCD_BUSY (OR optional LCD_VSYNC) X X X X X X X X X X X X X X X X X X X X LCD_D07 LCD_D06 LCD_D05 LCD_D04 LCD_D03 LCD_D02 LCD_D01 LCD_D00 X X 18.3 Behavior During Reset Note that HCLK and PIXCLK must be running before making any changes to SFTRST or CLKGATE bits. A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-19 LCD Interface (LCDIF) setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. 18.4 Programmable Registers The LCD interface block contains the following directly programmable registers. The starting address in LCDIF's memory map is 0x80030000 and all the register addresses mentioned below are offset from this address. For example, address of HW_LCDIF_CTRL is 0x80030000 and HW_LCDIF_CTRL1 is 0x80030010. 18.4.1 LCDIF General Control Register Description HW_LCDIF_CTRL HW_LCDIF_CTRL_SET HW_LCDIF_CTRL_CLR HW_LCDIF_CTRL_TOG Table 18-3. HW_LCDIF_CTRL The LCD Interface Control Register provides overall control of the LCDIF block. 0x000 0x004 0x008 0x00C 3 1 3 0 2 9 2 8 2 7 WAIT_FOR_VSYNC_EDGE 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 INPUT_DATA_SWIZZLE 1 4 1 3 CSC_DATA_SWIZZLE 1 2 1 1 LCD_DATABUS_WIDTH 1 0 0 9 0 8 0 7 RGB_TO_YCBCR422_CSC 0 6 0 5 0 4 0 3 DATA_FORMAT_16_BIT 0 2 DATA_FORMAT_18_BIT 0 1 DATA_FORMAT_24_BIT 0 0 YCBCR422_INPUT SHIFT_NUM_BITS DATA_SHIFT_DIR BYPASS_COUNT WORD_LENGTH DOTCLK_MODE LCDIF_MASTER DATA_SELECT VSYNC_MODE DVI_MODE CLKGATE SFTRST RSVD2 RSVD3 RSVD1 Table 18-4. HW_LCDIF_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION This bit must be set to zero to enable normal operation of the LCDIF. When set to one, it forces a block level reset. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. 30 CLKGATE RW 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 18-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor RUN LCD Interface (LCDIF) Table 18-4. HW_LCDIF_CTRL Bit Field Descriptions BITS LABEL 29 YCBCR422_INPUT RW RESET RW 0x0 DEFINITION Zero implies input data is in RGB color space. One implies input data is in YCbCr 4:2:2 format, such that YCbYCr are packed in a 32-bit word. It also means that there are 2 pixels in 4 bytes. If this bit is set, software should program the H_COUNT field in the TRANSFER_COUNT register to the total number of pixels that will have to be fetched by the LCDIF block per line and the BYTE_PACKING_FORMAT should be 0xF. The WORD_LENGTH does not matter in this case. Reserved bits. Write as 0. Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD. Used only in the VSYNC mode of operation. Use this bit to determine the direction of shift of transmit data. In the DVI mode, it works only on the active data, not on the timing codes and ancillary data. TXDATA_SHIFT_LEFT = 0x0 Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. TXDATA_SHIFT_RIGHT = 0x1 Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. 28 27 RSVD3 WAIT_FOR_VSYNC_EDGE RO 0x0 RW 0x0 26 DATA_SHIFT_DIR RW 0x0 25:21 SHIFT_NUM_BITS 20 DVI_MODE RW 0x0 RW 0x0 19 BYPASS_COUNT RW 0x0 18 VSYNC_MODE RW 0x0 17 DOTCLK_MODE RW 0x0 16 DATA_SELECT RW 0x0 The data to be transmitted is shifted left or right by this number of bits. Set this bit to 1 to get into theITU-R BT.656 digital video interface mode. Toggle this bit from 1 to 0 to make the hardware go out of DVI mode after completing all data transfer and deassert the RUN bit. When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the HW_LCDIF_TRANSFER_COUNT register has been transferred out. When this bit is set to 1, the block will continue normal operation indefinitely until it is told to stop. This bit must be 0 in system and VSYNC modes, and must be 1 in DOTCLK and DVI modes of operation. Setting this bit to 1 will make the LCDIF hardware go into VSYNC mode. WAIT_FOR_VSYNC_EDGE can be used only if this bit is set. If VSYNC signal is required to be an output from the block, SYNC_SIGNALS_ON bit in HW_LCDIF_VDCTRL4 register must be set. Set this bit to 1 to make the hardware go into the DOTCLK mode, i.e. VSYNC/HSYNC/DOTCLK/ENABLE interface mode. ENABLE is optional, selected by the ENABLE_PRESENT bit. Toggle this bit from 1 to 0 to make the hardware go out of DOTCLK mode after completing all data transfer and deasserting the RUN bit. Command Mode polarity bit. This bit should only be changed when RUN is 0. CMD_MODE = 0x0 Command Mode. DCn signal is Low. DATA_MODE = 0x1 Data Mode. DCn signal is High. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-21 LCD Interface (LCDIF) Table 18-4. HW_LCDIF_CTRL Bit Field Descriptions BITS LABEL 15:14 INPUT_DATA_SWIZZLE RW RESET RW 0x0 DEFINITION This field specifies how to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF.The swizzle function is independent of the WORD_LENGTH bit. See the explanation of the HW_LCDIF_DATA below for names and definitions of data register fields. The supported swizzle configurations are: NO_SWAP = 0x0 No byte swapping.(Little endian) LITTLE_ENDIAN = 0x0 Little Endian byte ordering (same as NO_SWAP). BIG_ENDIAN_SWAP = 0x1 Big Endian swap (swap bytes 0,3 and 1,2). SWAP_ALL_BYTES = 0x1 Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). HWD_SWAP = 0x2 Swap half-words. HWD_BYTE_SWAP = 0x3 Swap bytes within each half-word. 13:12 CSC_DATA_SWIZZLE RW 0x0 This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus. The data is always transmitted with the least significant byte/hword (half word) first after the swizzle takes place. So, INPUT_DATA_SWIZZLE takes place first on the incoming data, and then CSC_DATA_SWIZZLE is applied. The swizzle function is independent of the WORD_LENGTH or the LCD_DATABUS_WIDTH fields. If RGB_TO_YCRCB422_CSC bit is set, the swizzle occurs on the Y, Cb, Cr values. The supported swizzle configurations are: NO_SWAP = 0x0 No byte swapping.(Little endian) LITTLE_ENDIAN = 0x0 Little Endian byte ordering (same as NO_SWAP). BIG_ENDIAN_SWAP = 0x1 Big Endian swap (swap bytes 0,3 and 1,2). SWAP_ALL_BYTES = 0x1 Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). HWD_SWAP = 0x2 Swap half-words. HWD_BYTE_SWAP = 0x3 Swap bytes within each half-word. 11:10 LCD_DATABUS_WIDTH RW 0x0 LCD Data bus transfer width. 16_BIT = 0x0 16-bit data bus mode. 8_BIT = 0x1 8-bit data bus mode. 18_BIT = 0x2 18-bit data bus mode. 24_BIT = 0x3 24-bit data bus mode. 9:8 WORD_LENGTH RW 0x0 Input data format. 16_BIT = 0x0 Input data is 16 bits per pixel. Valid BYTE_PACKING_FORMAT settings are 0x3, 0xC and 0xF. H_COUNT must be a multiple of 2 pixels if BYTE_PACKING_FORMAT = 0xF. 8_BIT = 0x1 Input data is 8 bits wide. Any setting in BYTE_PACKING_FORMAT is valid as long as it is non-zero. H_COUNT must be a multiple of sum of the bits of BYTE_PACKING_FORMAT[3:0]. 18_BIT = 0x2 Input data is 18 bits per pixel. Valid BYTE_PACKING_FORMAT setting is 0xF. There are no restrictions on H_COUNT. 24_BIT = 0x3 Input data is 24 bits per pixel. Valid BYTE_PACKING_FORMAT settings are 0x7, 0xE and 0xF. If BYTE_PACKING_FORMAT = 0xF, H_COUNT must be a multiple of 4 pixels, otherwise there are no restrictions. 7 RGB_TO_YCBCR422_CSC RW 0x0 6 RSVD2 RW 0x0 Set this bit to 1 to enable conversion from RGB to YCbCr colorspace. See the HW_LCDIF_CSC_ registers for further details. Program this field to 0x0. i.MX23 Applications Processor Reference Manual, Rev. 1 18-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) Table 18-4. HW_LCDIF_CTRL Bit Field Descriptions BITS LABEL 5 LCDIF_MASTER RW RESET RW 0x0 DEFINITION Set this bit to make the LCDIF act as a bus master. If this bit is reset, the LCDIF will act in PIO mode. Program this field to 0x0. When this bit is 1 and WORD_LENGTH = 0, it implies that the the 16-bit pixel is in ARGB555 format. In other words, the pixel is right-aligned within 16 bits. When DATA_FORMAT_16_BIT = 0 and WORD_LENGTH = 0, it implies that the 16-bit pixel is in RGB565 format, and the pixel completely fits in 16 bits. When WORD_LENGTH != 0, this bit is a dont care. Used only when WORD_LENGTH = 2, i.e. 18-bit. Valid BYTE_PACKING_FORMAT setting is 0xF. LOWER_18_BITS_VALID = 0x0 Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. In other words, each pixel is right-aligned within 32 bits. UPPER_18_BITS_VALID = 0x1 Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. In other words, each pixel is left-aligned within 32 bits. 4 3 RSVD1 DATA_FORMAT_16_BIT RW 0x0 RW 0x0 2 DATA_FORMAT_18_BIT RW 0x0 1 DATA_FORMAT_24_BIT RW 0x0 Used only when WORD_LENGTH = 3, i.e. 24-bit. Note that this applies to both packed and unpacked 24-bit data. Valid BYTE_PACKING_FORMAT settings are 0x7, 0xE and 0xF. ALL_24_BITS_VALID = 0x0 Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. The alignment within 32 bits is determined by BYTE_PACKING_FORMAT field. DROP_UPPER_2_BITS_PER_BYTE = 0x1 Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. Thus, each color component is right aligned, but alignment of each pixel within 32 bits is determined by the BYTE_PACKING_FORMAT field. 0 RUN RW 0x0 When this bit is set by software, the LCDIF will start fetching data in either the PIO mode or the bus master mode and sending it across the interface. This bit must remain set for all the time the block is in operation. DESCRIPTION: The LCDIF Control Register provides a variety of control functions to the programmer. These functions allow the interface to be very flexible to work with a variety of LCD controllers, and to minimize overhead and increase performance of LCD programming. The register has been organized such that switching between the different LCD modes can be done with minimum PIO writes. EXAMPLE: Empty Example. 18.4.2 LCDIF General Control1 Register Description HW_LCDIF_CTRL1 HW_LCDIF_CTRL1_SET HW_LCDIF_CTRL1_CLR HW_LCDIF_CTRL1_TOG 0x010 0x014 0x018 0x01C The LCDIF Control Register provides overall control of the LCDIF block. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-23 LCD Interface (LCDIF) Table 18-5. HW_LCDIF_CTRL1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 START_INTERLACE_FROM_SECOND_FIELD 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 IRQ_ON_ALTERNATE_FIELDS RECOVER_ON_UNDERFLOW CUR_FRAME_DONE_IRQ_EN BYTE_PACKING_FORMAT CUR_FRAME_DONE_IRQ VSYNC_EDGE_IRQ_EN UNDERFLOW_IRQ_EN OVERFLOW_IRQ_EN BM_ERROR_IRQ_EN INTERLACE_FIELDS VSYNC_EDGE_IRQ UNDERFLOW_IRQ OVERFLOW_IRQ BM_ERROR_IRQ BUSY_ENABLE LCD_CS_CTRL FIFO_CLEAR MODE86 RSVD5 Table 18-6. HW_LCDIF_CTRL1 Bit Field Descriptions BITS LABEL 31:27 RSVD5 BM_ERROR_IRQ_EN 26 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved bits. Write as 0. This bit is set to enable bus master error interrupt in the LCDIF master mode. This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software by writing a one to its SCT clear address. This bit will be set when the LCDIF is in master mode and an error response was returned by the slave. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 25 BM_ERROR_IRQ RW 0x0 24 RECOVER_ON_UNDERFLOW RW 0x0 23 INTERLACE_FIELDS RW 0x0 22 START_INTERLACE_FROM_ SECOND_FIELD RW 0x0 21 20 FIFO_CLEAR RW 0x0 IRQ_ON_ALTERNATE_FIELD RW 0x0 S Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame. Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field. It will work only in LCDIF_MASTER is set to 1. The default is to grab the odd lines first and then the even lines. Set this bit if it is required to grab the even lines first and then the odd lines. (Line numbers start from 1, so odd lines are 1,3,5,etc. and even lines are 2,4,6, etc.) Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field. This bit is mostly relevant if INTERLACE_FIELDS is set. This feature is only available in DOTCLK and DVI modes. i.MX23 Applications Processor Reference Manual, Rev. 1 18-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor RESET RSVD4 RSVD3 RSVD2 RSVD1 LCD Interface (LCDIF) Table 18-6. HW_LCDIF_CTRL1 Bit Field Descriptions BITS LABEL 19:16 BYTE_PACKING_FORMAT RW RESET RW 0xf DEFINITION This bitfield is used to show which data bytes in the 32-bit word written in the HW_LCDIF_DATA register or fetched from memory are valid and should be transmitted. Default value 0xf indicates that all bytes are valid. For 8-bit transfers, any combination in this bitfield will mean valid data is present in the corresponding bytes. In the 16-bit mode, a 16-bit half-word is valid only if the value in this field is 0x3, 0xC or 0xF. In the 18-bit mode, BYTE_PACKING_FORMAT must be 0xF. If the frame buffer data is unpacked 24-bit, set the bit field value to 0x7 (X-R-G-B where X value is invalid and should not be transmitted). If it is packed 24-bit (i.e. 4 pixels in 3 words), set BYTE_PACKING_FORMAT to 0xF. When input data is is in YCbCr 4:2:2 format (YCBCR422_INPUT = 1), the BYTE_PACKING_FORMAT should be 0xF.(Note YCBCR422_INPUT = 1 implies 2 pixels per 32 bits). BYTE_PACKING_FORMAT = 0 means that none of the bytes are valid and should not be used in any mode. This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state. This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode. This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software by writing a one to its SCT clear address. A latency FIFO (LFIFO) overflow in the write mode (system/VSYNC/DOTCLK/DVI mode) was detected, data samples have been lost. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 15 14 13 12 OVERFLOW_IRQ_EN UNDERFLOW_IRQ_EN RW 0x0 RW 0x0 CUR_FRAME_DONE_IRQ_EN RW 0x0 VSYNC_EDGE_IRQ_EN RW 0x0 11 OVERFLOW_IRQ RW 0x0 10 UNDERFLOW_IRQ RW 0x0 This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software by writing a one to its SCT clear address. A TXFIFO underflow in the write mode (system/VSYNC/DOTCLK/DVI mode) was detected. Could produce an error in the DOTCLK / DVI modes. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-25 LCD Interface (LCDIF) Table 18-6. HW_LCDIF_CTRL1 Bit Field Descriptions BITS LABEL 9 CUR_FRAME_DONE_IRQ RW RESET RW 0x0 DEFINITION This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software by writing a one to its SCT clear address. It indicates that the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes. In the VSYNC and system modes, this IRQ is asserted at the end of the data transfer indicated by HW_LCDIF_TRANSFER_COUNT register. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 8 VSYNC_EDGE_IRQ RW 0x0 This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software by writing a one to its SCT clear address. It is set whenever the leading VSYNC edge is detected in the VSYNC and DOTCLK modes. In the DVI mode, it is asserted every time the block enters a new field. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 7 6 5 4 3 RSVD4 RSVD3 RSVD2 RSVD1 LCD_CS_CTRL RO RW RW RW 0x0 0x0 0x0 0x0 Reserved bits. Write as 0. Program this field to 0x0. Program this field to 0x0. Program this field to 0x0. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. RW 0x0 2 BUSY_ENABLE RW 0x0 If this bit is set to 0 in the VSYNC mode, the LCD_CS pin will toggle according to the system interface protocol. If it set to 0 in the DOTCLK mode, the LCD_CS pin will be driven high throughout the operation. In both the VSYNC and DOTCLK modes, if this bit is set to 1, the LCD_CS pin will be driven low throughout the operation. In the system interface mode, this bit must be set to the default value of 0. This bit enables the use of the interface's busy signal input. This should be enabled for LCD controllers that implement a busy line (to stall the LCDIF from sending more data until ready). Otherwise this bit should be cleared. BUSY_DISABLED = 0x0 The busy signal from the LCD controller will be ignored. BUSY_ENABLED = 0x1 Enable the use of the busy signal from the LCD controller. 1 MODE86 RW 0x0 This bit is used to select between the 8080 and 6800 series of microprocessor modes. This bit should only be changed when RUN is 0. 8080_MODE = 0x0 Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. 6800_MODE = 0x1 Pins LCD_WR_RWn and LCD_RD_E function as Read/Writeb and active high Enable signals respectively. 0 RESET RW 0x0 Reset bit for the external LCD controller. This bit can be changed at any time. It CANNOT be reset by SFTRST. LCDRESET_LOW = 0x0 LCD_RESET output signal is low. LCDRESET_HIGH = 0x1 LCD_RESET output signal is high. i.MX23 Applications Processor Reference Manual, Rev. 1 18-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) DESCRIPTION: The LCDIF Control1 Register provides additional programming to the LCDIF. It implements some bits which are unlikely to change often in a particular application. It also carries interrupt-related bits which are common across more than one mode of operation. EXAMPLE: Empty Example. 18.4.3 LCDIF Horizontal and Vertical Valid Data Count Register Description This register tells the LCDIF how much data will be sent for this frame, or transaction. The total number of words is a product of the V_COUNT and H_COUNT fields. The word size is specified by the WORD_LENGTH field. HW_LCDIF_TRANSFER_COUNT 0x020 Table 18-7. HW_LCDIF_TRANSFER_COUNT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 V_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 H_COUNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 18-8. HW_LCDIF_TRANSFER_COUNT Bit Field Descriptions BITS LABEL 31:16 V_COUNT RW RESET RW 0x0001 DEFINITION Number of horizontal lines per frame which contain valid data. In DOTCLK mode, V_COUNT should be the same as the number of active horizontal lines in a progressive frame. In DVI mode, V_COUNT should be the number of active horizontal lines per frame, and not per field. Total valid data (pixels) in each horizontal line. The data size is given by the WORD_LENGTH. When input data is is in YCbCr 4:2:2 format (YCBCR422_INPUT is 1), H_COUNT should be the number of 32-bit words that should be fetched by the block and the BYTE_PACKING_FORMAT should be 0xF. In 24-bit packed format (WORD_LENGTH=0x3, BYTE_PACKING_FORMAT=0xF), the H_COUNT must be a multiple of 4 pixels. In 16-bit packed format (WORD_LENGTH=0x0, BYTE_PACKING_FORMAT=0xF), the H_COUNT must be a multiple of 2 pixels. 15:0 H_COUNT RW 0x0000 DESCRIPTION: This register gives the dimensions of the input frame. For normal operation, but V_COUNT and H_COUNT should be non-zero. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-27 LCD Interface (LCDIF) EXAMPLE: Empty Example. 18.4.4 LCD Interface Current Buffer Address Register Description HW_LCDIF_CUR_BUF Table 18-9. HW_LCDIF_CUR_BUF This register indicates the address of the current frame that is being transmitted by LCDIF. 0x030 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ADDR Table 18-10. HW_LCDIF_CUR_BUF Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x00 DEFINITION DESCRIPTION: When the LCDIF is behaving as a master, this address points to the address of the current frame of data being sent out via the LCDIF. When the current frame is done, the LCDIF block will assert the cur_frame_done interrupt for software to take action. The block will also copy the HW_LCDIF_NEXT_BUF_ADDR into this bitfield so that the software can program the next frame address into the HW_LCDIF_NEXT_BUF_ADDR bitfield. EXAMPLE: Empty Example. 18.4.5 LCD Interface Next Buffer Address Register Description HW_LCDIF_NEXT_BUF Table 18-11. HW_LCDIF_NEXT_BUF This register indicates the address of next frame that will be transmitted by LCDIF. 0x040 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ADDR Table 18-12. HW_LCDIF_NEXT_BUF Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x00 DEFINITION i.MX23 Applications Processor Reference Manual, Rev. 1 18-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) DESCRIPTION: When the LCDIF is behaving as a master, this address points to the address of the next frame of data that will be sent out via the LCDIF. It is upto the software to make sure that this register is programmed before the end of the current frame, otherwise it might result in old data going out the LCDIF. EXAMPLE: Empty Example. 18.4.6 LCD Interface Timing Register Description The LCD interface timing register controls the various setup and hold times enforced by the LCD interface in the 6800/8080 system and VSYNC modes of operation. HW_LCDIF_TIMING Table 18-13. HW_LCDIF_TIMING 3 1 3 0 2 9 2 8 CMD_HOLD 0x060 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 CMD_SETUP 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 DATA_HOLD 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 DATA_SETUP 0 3 0 2 0 1 0 0 Table 18-14. HW_LCDIF_TIMING Bit Field Descriptions BITS LABEL 31:24 CMD_HOLD RW RESET RW 0x00 DEFINITION Number of PIXCLK cycles that the DCn signal is active after CEn is deasserted. Number of PIXCLK cycles that the the DCn signal is active before CEn is asserted. Data bus hold time in PIXCLK cycles. Also the time that the data strobe is de-asserted in a cycle Data bus setup time in PIXCLK cycles. Also the time that the data strobe is asserted in a cycle. 23:16 CMD_SETUP 15:8 7:0 DATA_HOLD DATA_SETUP RW 0x00 RW 0x00 RW 0x00 DESCRIPTION: The values used in this register are dependent on the particular LCD controller used, consult the users manual for the particular controller for required timings. Each field of the register must be non-zero, therefore the minimum value is: 0x01010101. NOTE: the timings are not automatically adjusted if the PIXCLK frequency changes--it may be necessary to adjust the timings if PIXCLK changes. NOTE: Each field in this register must be non-zero for the system and VSYNC modes to function. The settings in this register do not affect the DOTCLK and DVI modes. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-29 LCD Interface (LCDIF) 18.4.7 LCDIF VSYNC Mode and Dotclk Mode Control Register0 Description This register is used to control the VSYNC and DOTCLK modes of the LCDIF so as to work with different types of LCDs like moving picture displays and delta pixel displays. HW_LCDIF_VDCTRL0 HW_LCDIF_VDCTRL0_SET HW_LCDIF_VDCTRL0_CLR HW_LCDIF_VDCTRL0_TOG Table 18-15. HW_LCDIF_VDCTRL0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 VSYNC_PERIOD_UNIT 0x070 0x074 0x078 0x07C 2 0 VSYNC_PULSE_WIDTH_UNIT 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 VSYNC_PULSE_WIDTH 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ENABLE_PRESENT Table 18-16. HW_LCDIF_VDCTRL0 Bit Field Descriptions BITS LABEL 31:30 RSRVD2 VSYNC_OEB 29 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved bits. Write as 0. 0 means the VSYNC signal is an output, 1 means it is an input. Should be set to 0 in the DOTCLK mode. VSYNC_OUTPUT = 0x0 The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. VSYNC_INPUT = 0x1 The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. 28 ENABLE_PRESENT RW 0x0 HALF_LINE_MODE DOTCLK_POL ENABLE_POL VSYNC_OEB HSYNC_POL VSYNC_POL HALF_LINE RSRVD2 RSRVD1 27 VSYNC_POL RW 0x0 26 HSYNC_POL RW 0x0 25 DOTCLK_POL RW 0x0 24 ENABLE_POL RW 0x0 RO 0x0 23:22 RSRVD1 Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK. Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period. Set it to 1 to invert the polarity. Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period. Set it to 1 to invert the polarity. Default is data launched at negative edge of DOTCLK and captured at positive edge. Set it to 1 to invert the polarity. Set it to 0 in DVI mode. Default 0 active low during valid data transfer on each horizontal line. Reserved bits. Write as 0. i.MX23 Applications Processor Reference Manual, Rev. 1 18-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) Table 18-16. HW_LCDIF_VDCTRL0 Bit Field Descriptions BITS LABEL 21 VSYNC_PERIOD_UNIT RW RESET RW 0x0 DEFINITION Default 0 for counting VSYNC_PERIOD in terms of PIXCLKs. Set it to 1 to count in terms of complete horizontal lines. PIXCLKs should be used in the VSYNC mode, while horizontal line should be used in the DOTCLK mode. Default 0 for counting VSYNC_PULSE_WIDTH in terms of PIXCLKs. Set it to 1 to count in terms of complete horizontal lines. Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i.e. VSYNC_PERIOD field plus half horizontal line), otherwise it is just VSYNC_PERIOD. Should be only used in the DOTCLK mode, not in the VSYNC interface mode. When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line. When this bit is 1, all fields will end with half a horizontal line, and none will begin with half a horizontal line. Number of units for which VSYNC signal is active. For the DOTCLK mode, the unit is determined by the VSYNC_PULSE_WIDTH_UNIT. If the VSYNC_PULSE_WIDTH_UNIT is 0 for DOTCLK mode, VSYNC_PULSE_WIDTH must be less than HSYNC_PERIOD. For the VSYNC interface mode, it should be in terms of number of PIXCLKs only. 20 VSYNC_PULSE_WIDTH_UNIT RW 0x0 19 HALF_LINE RW 0x0 18 HALF_LINE_MODE RW 0x0 17:0 VSYNC_PULSE_WIDTH RW 0x00000 DESCRIPTION: This register gives general programmability to the VSYNC signal including polarity, direction, pulse width, etc. EXAMPLE: Empty Example. 18.4.8 LCDIF VSYNC Mode and Dotclk Mode Control Register1 Description HW_LCDIF_VDCTRL1 Table 18-17. HW_LCDIF_VDCTRL1 This register is used to control the VSYNC signal in the VSYNC and DOTCLK modes of the block. 0x080 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VSYNC_PERIOD i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-31 LCD Interface (LCDIF) Table 18-18. HW_LCDIF_VDCTRL1 Bit Field Descriptions BITS LABEL 31:0 VSYNC_PERIOD RW RESET RW 0x000000 DEFINITION Total number of units between two positive or two negative edges of the VSYNC signal. If HALF_LINE is set, it is implicitly calculated to be VSYNC_PERIOD plus half HSYNC_PERIOD. DESCRIPTION: This register determines the period and duty cycle of the VSYNC signal when it is generated in the block. EXAMPLE: Empty Example. 18.4.9 LCDIF VSYNC Mode and Dotclk Mode Control Register2 Description HW_LCDIF_VDCTRL2 Table 18-19. HW_LCDIF_VDCTRL2 This register is used to control the HSYNC signal in the DOTCLK mode of the block. 0x090 3 1 3 0 2 9 2 8 HSYNC_PULSE_WIDTH 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 HSYNC_PERIOD 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 18-20. HW_LCDIF_VDCTRL2 Bit Field Descriptions BITS LABEL 31:24 HSYNC_PULSE_WIDTH 23:18 RSRVD0 17:0 HSYNC_PERIOD RW RESET RW 0x00 RO 0x0 RW 0x0000 DEFINITION Number of PIXCLKs for which HSYNC signal is active. Reserved bits, write as 0. Total number of PIXCLKs between two positive or two negative edges of the HSYNC signal. DESCRIPTION: This register determines the period and duty cycle of the HSYNC signal when it is generated in the block. EXAMPLE: Empty Example. 18.4.10 LCDIF VSYNC Mode and Dotclk Mode Control Register3 Description This register is used to determine the vertical and horizontal wait counts. i.MX23 Applications Processor Reference Manual, Rev. 1 18-32 Preliminary--Subject to Change Without Notice RSRVD0 Freescale Semiconductor LCD Interface (LCDIF) HW_LCDIF_VDCTRL3 Table 18-21. HW_LCDIF_VDCTRL3 3 1 3 0 2 9 MUX_SYNC_SIGNALS 0x0a0 2 8 2 7 2 6 2 5 2 4 2 3 2 2 HORIZONTAL_WAIT_CNT 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 VERTICAL_WAIT_CNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VSYNC_ONLY RSRVD0 Table 18-22. HW_LCDIF_VDCTRL3 Bit Field Descriptions BITS LABEL 31:30 RSRVD0 MUX_SYNC_SIGNALS 29 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved bits, write as 0. When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins. This feature can be used to maintain backward compatability with older generation SoCs. This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation. In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins. In the VSYNC interface mode, wait for this number of PIXCLKs from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set. Minimum is CMD_SETUP+5. In the DOTCLK mode, it accounts for the veritcal back porch lines plus the number of horizontal lines before the moving picture begins. The unit for this parameter is inherently the same as the VSYNC_PERIOD_UNIT. 28 VSYNC_ONLY RW 0x0 RW 0x000 27:16 HORIZONTAL_WAIT_CNT 15:0 VERTICAL_WAIT_CNT RW 0x000 DESCRIPTION: This register determines the back porches of HSYNC and VSYNC signals when they are generated by the block. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-33 LCD Interface (LCDIF) 18.4.11 LCDIF VSYNC Mode and Dotclk Mode Control Register4 Description This register is used to control the DOTCLK mode of the block. HW_LCDIF_VDCTRL4 Table 18-23. HW_LCDIF_VDCTRL4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 DOTCLK_H_VALID_DATA_CNT 0x0b0 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 18-24. HW_LCDIF_VDCTRL4 Bit Field Descriptions BITS LABEL 31:19 RSRVD0 SYNC_SIGNALS_ON 18 RW RESET RO 0x0000 RW 0x0 DEFINITION Reserved bits, write as 0. Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active atleast one frame before the data transfers actually start and remain active atleast one frame after the data transfers end. The hardware does not count the number of frames automatically. Rather, the VSYNC edge interrupt can be monitored by software to count the number of frames that have occured after this bit is set and then the RUN bit can be set to start the data transactions. This bit must always be set in the DOTCLK mode of operation, and it must be set in the VSYNC mode of operation when VSYNC signal is an output. Total number of PIXCLKs on each horizontal line that carry valid data in DOTCLK mode. 17:0 DOTCLK_H_VALID_DATA_C NT RW 0x00000 DESCRIPTION: This register determines the active data in each horizontal line in the DOTCLK mode. Note that the total number of active horizontal lines in the DOTCLK mode is the same as the V_COUNT bitfield in the HW_LCDIF_TRANSFER_COUNT register. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 18-34 Preliminary--Subject to Change Without Notice SYNC_SIGNALS_ON RSRVD0 Freescale Semiconductor LCD Interface (LCDIF) 18.4.12 Digital Video Interface Control0 Register Description The Digital Video interface Control0 register provides the overall control of the Digital Video interface. HW_LCDIF_DVICTRL0 Table 18-25. HW_LCDIF_DVICTRL0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 H_ACTIVE_CNT 0x0c0 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 H_BLANKING_CNT 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 V_LINES_CNT 0 4 0 3 0 2 0 1 0 0 RSVD1 Table 18-26. HW_LCDIF_DVICTRL0 Bit Field Descriptions BITS LABEL 31 RSVD1 30:20 H_ACTIVE_CNT RW RESET RW 0x0 RW 0x000 DEFINITION Program this field to 0x0. Number of active video samples to be transmitted. (Mostly will be 1440 for both PAL and NTSC). Must always be a multiple of 4. Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval. Total number of vertical lines per frame (generally 525 or 625) 19:10 H_BLANKING_CNT 9:0 V_LINES_CNT RW 0x000 RW 0x000 DESCRIPTION: This register gives information about the horizontal active, horizontal blanking and total number of lines in the ITU-R BT.656 interface. EXAMPLE: //525/60 video system HW_LCDIF_DVICTRL0_H_ACTIVE_CNT_WR(0x5A0);//1440 HW_LCDIF_DVICTRL0_H_BLANKING_CNT_WR(0x106);//262 HW_LCDIF_DVICTRL0_V_LINES_CNT_WR(0x20D);//525 //625/50 video system HW_LCDIF_DVICTRL0_H_ACTIVE_CNT_WR(0x5A0);//1440 HW_LCDIF_DVICTRL0_H_BLANKING_CNT_WR(0x112);//274 HW_LCDIF_DVICTRL0_V_LINES_CNT_WR(0x271);//625 18.4.13 Digital Video Interface Control1 Register Description The Digital Video interface Control1 register provides the overall control of the Digital Video interface. HW_LCDIF_DVICTRL1 0x0d0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-35 LCD Interface (LCDIF) Table 18-27. HW_LCDIF_DVICTRL1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 F1_START_LINE 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 F1_END_LINE 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 F2_START_LINE 0 4 0 3 0 2 0 1 0 0 RSRVD0 Table 18-28. HW_LCDIF_DVICTRL1 Bit Field Descriptions BITS 31:30 29:20 19:10 9:0 LABEL RSRVD0 F1_START_LINE F1_END_LINE F2_START_LINE RW RO RW RW RW RESET 0x0 0x000 0x000 0x000 DEFINITION Reserved bits, write as 0. Vertical line number from which Field 1 begins. Vertical line number at which Field1 ends. Vertical line number from which Field 2 begins. DESCRIPTION: This register contains information about the Field1 start and end, and the Field2 start in the ITU-R BT.656 interface. EXAMPLE: //525/60 video system HW_LCDIF_DVICTRL1_F1_START_LINE_WR(0x4);//4 HW_LCDIF_DVICTRL1_F1_END_LINE_WR(0x109);//265 HW_LCDIF_DVICTRL1_F2_START_LINE_WR(0x10A);//266 //625/50 video system HW_LCDIF_DVICTRL1_F1_START_LINE_WR(0x1);//1 HW_LCDIF_DVICTRL1_F1_END_LINE_WR(0x138);//312 HW_LCDIF_DVICTRL1_F2_START_LINE_WR(0x139);//313 18.4.14 Digital Video Interface Control2 Register Description The Digital Video interface Control2 register provides the overall control of the Digital Video interface. HW_LCDIF_DVICTRL2 Table 18-29. HW_LCDIF_DVICTRL2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 V1_BLANK_START_LINE 0x0e0 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 V1_BLANK_END_LINE 0 4 0 3 0 2 0 1 0 0 F2_END_LINE RSRVD0 i.MX23 Applications Processor Reference Manual, Rev. 1 18-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) Table 18-30. HW_LCDIF_DVICTRL2 Bit Field Descriptions BITS LABEL 31:30 RSRVD0 29:20 F2_END_LINE 19:10 V1_BLANK_START_LINE RW RESET RO 0x0 RW 0x000 RW 0x000 DEFINITION Reserved bits, write as 0. Vertical line number at which Field 2 ends. Vertical line number towards the end of Field1 where first Vertical Blanking interval starts. Vertical line number in the beginning part of Field2 where first Vertical Blanking interval ends. 9:0 V1_BLANK_END_LINE RW 0x000 DESCRIPTION: This register contains information about the Field2 end, and the Vertical Blanking1 interval in the ITU-R BT.656 interface. EXAMPLE: //525/60 video system HW_LCDIF_DVICTRL2_F2_END_LINE_WR(0x3);//3 HW_LCDIF_DVICTRL2_V1_BLANK_START_LINE_WR(0x108);//264 HW_LCDIF_DVICTRL2_V1_BLANK_END_LINE_WR(0x11A);//282 //625/50 video system HW_LCDIF_DVICTRL2_F2_END_LINE_WR(0x271);//625 HW_LCDIF_DVICTRL2_V1_BLANK_START_LINE_WR(0x137);//311 HW_LCDIF_DVICTRL2_V1_BLANK_END_LINE_WR(0x14F);//335 18.4.15 Digital Video Interface Control3 Register Description The Digital Video interface Control3 register provides the overall control of the Digital Video interface. HW_LCDIF_DVICTRL3 Table 18-31. HW_LCDIF_DVICTRL3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 V2_BLANK_START_LINE 0x0f0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 V2_BLANK_END_LINE 0 4 0 3 0 2 0 1 0 0 RSRVD1 Table 18-32. HW_LCDIF_DVICTRL3 Bit Field Descriptions BITS LABEL 31:26 RSRVD1 25:16 V2_BLANK_START_LINE RW RESET RO 0x0 RW 0x000 DEFINITION Reserved bits, write as 0. Vertical line number towards the end of Field2 where second Vertical Blanking interval starts. Reserved bits, write as 0. Vertical line number in the beginning part of Field1 where second Vertical Blanking interval ends. 15:10 RSRVD0 V2_BLANK_END_LINE 9:0 RO 0x00 RW 0x000 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD0 18-37 LCD Interface (LCDIF) DESCRIPTION: This register contains information about the Vertical Blanking2 interval in the ITU-R BT.656 interface. EXAMPLE: //525/60 video system HW_LCDIF_DVICTRL3_V2_BLANK_START_LINE_WR(0x1);//1 HW_LCDIF_DVICTRL3_V2_BLANK_END_LINE_WR(0x13);//19 //625/50 video system HW_LCDIF_DVICTRL3_V2_BLANK_START_LINE_WR(0x270);//624 HW_LCDIF_DVICTRL3_V2_BLANK_END_LINE_WR(0x16);//22 18.4.16 Digital Video Interface Control4 Register Description The Digital Video interface Control4 register provides the overall control of the Digital Video interface. HW_LCDIF_DVICTRL4 Table 18-33. HW_LCDIF_DVICTRL4 3 1 3 0 2 9 2 8 Y_FILL_VALUE 0x100 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 CB_FILL_VALUE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 CR_FILL_VALUE 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 H_FILL_CNT 0 3 0 2 0 1 0 0 Table 18-34. HW_LCDIF_DVICTRL4 Bit Field Descriptions BITS 31:24 23:16 15:8 7:0 LABEL Y_FILL_VALUE CB_FILL_VALUE CR_FILL_VALUE H_FILL_CNT RW RW RW RW RW RESET 0x00 0x00 0x00 0x00 DEFINITION Value of Y component of filler data Value of CB component of filler data Value of CR component of filler data. Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval. Must be a multiple of 4. This field will have to be programmed if the input frame has less than 720 pixels per line. DESCRIPTION: This register is used to add side borders to the output if the input frame width is less than 720 pixels. EXAMPLE: //If input frame has only 640 pixels per line, but output is supposed to have 720 pixels per line. HW_LCDIF_DVICTRL4_H_FILL_CNT_WR(0x50);//80 HW_LCDIF_DVICTRL4_Y_FILL_VALUE_WR(0x10);//16 HW_LCDIF_DVICTRL4_CB_FILL_VALUE_WR(0x80);//128 HW_LCDIF_DVICTRL4_CR_FILL_VALUE_WR(0x80);//128 i.MX23 Applications Processor Reference Manual, Rev. 1 18-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) 18.4.17 RGB to YCbCr 4:2:2 CSC Coefficient0 Register Description HW_LCDIF_CSC_COEFF0 register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset HW_LCDIF_CSC_COEFF0 0x110 Table 18-35. HW_LCDIF_CSC_COEFF0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 CSC_SUBSAMPLE_FILTER 0 0 RSRVD1 Table 18-36. HW_LCDIF_CSC_COEFF0 Bit Field Descriptions BITS 31:26 25:16 15:2 1:0 LABEL RSRVD1 C0 RSRVD0 CSC_SUBSAMPLE_FILTER RW RO RW RO RW RESET 0x00 0x000 0x000 0x0 DEFINITION Reserved bits, write as 0. Two's complement red multiplier coefficient for Y Reserved bits, write as 0. This register describes the filtering and subsampling scheme to be performed on the chroma components in order to convert from YCbCr 4:4:4 to YCbCr 4:2:2 space. Note that the following descriptions apply individually to Cb and Cr. SAMPLE_AND_HOLD = 0x0 No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with all samples numbered 2n+1. RSRVD = 0x1 Reserved INTERSTITIAL = 0x2 Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2) and that chroma value replaces the two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway between the two luma samples. COSITED = 0x3 Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4,1/2,1/4) and that chroma value exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are discarded. DESCRIPTION: This register carries programming information about RGB to YCbCr 4:2:2 CSC. EXAMPLE: HW_LCDIF_CSC_COEFF0_C0_WR(0x41);//0.257x256=65 HW_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_WR(0x3); i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD0 C0 18-39 LCD Interface (LCDIF) 18.4.18 RGB to YCbCr 4:2:2 CSC Coefficient1 Register Description HW_LCDIF_CSC_COEFF1 register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset HW_LCDIF_CSC_COEFF1 0x120 Table 18-37. HW_LCDIF_CSC_COEFF1 3 1 3 0 2 9 RSRVD1 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 C2 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSRVD0 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 C1 0 4 0 3 0 2 0 1 0 0 Table 18-38. HW_LCDIF_CSC_COEFF1 Bit Field Descriptions BITS 31:26 25:16 15:10 9:0 LABEL RSRVD1 C2 RSRVD0 C1 RW RO RW RO RW RESET 0x00 0x000 0x00 0x000 DEFINITION Reserved bits, write as 0. Two's complement blue multiplier coefficient for Y Reserved bits, write as 0. Two's complement green multiplier coefficient for Y DESCRIPTION: This register carries programming information about RGB to YCbCr 4:2:2 CSC. EXAMPLE: HW_LCDIF_CSC_COEFF1_C1_WR(0x81);//0.504x256=129 HW_LCDIF_CSC_COEFF1_C2_WR(0x19);//0.098x256=25 18.4.19 RGB to YCbCr 4:2:2 CSC Coefficent2 Register Description HW_LCDIF_CSC_COEFF2 register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset HW_LCDIF_CSC_COEFF2 0x130 Table 18-39. HW_LCDIF_CSC_COEFF2 3 1 3 0 2 9 RSRVD1 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 C4 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSRVD0 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 C3 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 18-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) Table 18-40. HW_LCDIF_CSC_COEFF2 Bit Field Descriptions BITS 31:26 25:16 15:10 9:0 LABEL RSRVD1 C4 RSRVD0 C3 RW RO RW RO RW RESET 0x00 0x000 0x00 0x000 DEFINITION Reserved bits, write as 0. Two's complement green multiplier coefficient for Cb Reserved bits, write as 0. Two's complement red multiplier coefficient for Cb DESCRIPTION: This register carries programming information about RGB to YCbCr 4:2:2 CSC. EXAMPLE: HW_LCDIF_CSC_COEFF2_C3_WR(0x3DB);//-0.148x256=-37 HW_LCDIF_CSC_COEFF2_C4_WR(0x3B6);//-0.291x256=-74 18.4.20 RGB to YCbCr 4:2:2 CSC Coefficient3 Register Description HW_LCDIF_CSC_COEFF3 register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset HW_LCDIF_CSC_COEFF3 0x140 Table 18-41. HW_LCDIF_CSC_COEFF3 3 1 3 0 2 9 RSRVD1 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 C6 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSRVD0 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 C5 0 4 0 3 0 2 0 1 0 0 Table 18-42. HW_LCDIF_CSC_COEFF3 Bit Field Descriptions BITS 31:26 25:16 15:10 9:0 LABEL RSRVD1 C6 RSRVD0 C5 RW RO RW RO RW RESET 0x00 0x000 0x00 0x000 DEFINITION Reserved bits, write as 0. Two's complement red multiplier coefficient for Cr Reserved bits, write as 0. Two's complement blue multiplier coefficient for Cb DESCRIPTION: This register carries programming information about RGB to YCbCr 4:2:2 CSC. EXAMPLE: HW_LCDIF_CSC_COEFF3_C5_WR(0x70);//0.439x256=112 HW_LCDIF_CSC_COEFF3_C6_WR(0x70);//0.439x256=112 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-41 LCD Interface (LCDIF) 18.4.21 RGB to YCbCr 4:2:2 CSC Coefficient4 Register Description HW_LCDIF_CSC_COEFF4 register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset HW_LCDIF_CSC_COEFF4 0x150 Table 18-43. HW_LCDIF_CSC_COEFF4 3 1 3 0 2 9 RSRVD1 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 C8 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSRVD0 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 C7 0 4 0 3 0 2 0 1 0 0 Table 18-44. HW_LCDIF_CSC_COEFF4 Bit Field Descriptions BITS 31:26 25:16 15:10 9:0 LABEL RSRVD1 C8 RSRVD0 C7 RW RO RW RO RW RESET 0x00 0x000 0x00 0x000 DEFINITION Reserved bits, write as 0. Two's complement blue multiplier coefficient for Cr Reserved bits, write as 0. Two's complement green multiplier coefficient for Cr DESCRIPTION: This register carries programming information about RGB to YCbCr 4:2:2 CSC. EXAMPLE: HW_LCDIF_CSC_COEFF4_C7_WR(0x3A2);//-0.368x256=-94 HW_LCDIF_CSC_COEFF4_C8_WR(0x3EE);//-0.071x256=-18 18.4.22 RGB to YCbCr 4:2:2 CSC Offset Register Description HW_LCDIF_CSC_ register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset HW_LCDIF_CSC_OFFSET Table 18-45. HW_LCDIF_CSC_OFFSET 3 1 3 0 2 9 2 8 RSRVD1 0x160 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 CBCR_OFFSET 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RSRVD0 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 Y_OFFSET 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 18-42 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) Table 18-46. HW_LCDIF_CSC_OFFSET Bit Field Descriptions BITS LABEL 31:25 RSRVD1 24:16 CBCR_OFFSET RW RESET RO 0x00 RW 0x080 DEFINITION Reserved bits, write as 0. Two's complement offset for the Cb and Cr components Reserved bits, write as 0. Two's complement offset for the Y component 15:9 8:0 RSRVD0 Y_OFFSET RO 0x00 RW 0x010 DESCRIPTION: This register carries programming information about RGB to YCbCr 4:2:2 CSC. EXAMPLE: Empty Example. 18.4.23 RGB to YCbCr 4:2:2 CSC Limit Register Description HW_LCDIF_CSC_CTRL0 register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset HW_LCDIF_CSC_LIMIT Table 18-47. HW_LCDIF_CSC_LIMIT 3 1 3 0 2 9 2 8 CBCR_MIN 0x170 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 CBCR_MAX 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 Y_MIN 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 Y_MAX 0 3 0 2 0 1 0 0 Table 18-48. HW_LCDIF_CSC_LIMIT Bit Field Descriptions BITS LABEL 31:24 CBCR_MIN RW RESET RW 0x00 DEFINITION Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion Lower limit of Y after RGB to 4:2:2 YCbCr conversion Upper limit of Y after RGB to 4:2:2 YCbCr conversion 23:16 CBCR_MAX 15:8 7:0 Y_MIN Y_MAX RW 0xff RW 0x00 RW 0xff DESCRIPTION: This register carries programming information about RGB to YCbCr 4:2:2 CSC. Note that the values in this register are unsigned. EXAMPLE: HW_LCDIF_CSC_LIMIT_CBCR_MIN_WR(0x10);//16 HW_LCDIF_CSC_LIMIT_CBCR_MAX_WR(0xF0);//240 HW_LCDIF_CSC_LIMIT_Y_MIN_WR(0x10);//16 HW_LCDIF_CSC_LIMIT_Y_MAX_WR(0xEB);//235 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 18-43 LCD Interface (LCDIF) 18.4.24 LCD Interface Data Register Description The data sent to an external LCD controller is written to this register. Data can be written to this register (from the processor's perspective) as bytes half-words (16 bits) or words (32 bits) as appropriate. HW_LCDIF_DATA Table 18-49. HW_LCDIF_DATA 3 1 3 0 2 9 2 8 DATA_THREE 0x1b0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 DATA_TWO 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 DATA_ONE 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 DATA_ZERO 0 3 0 2 0 1 0 0 Table 18-50. HW_LCDIF_DATA Bit Field Descriptions BITS LABEL 31:24 DATA_THREE RW RESET RW 0x00 DEFINITION Byte 3 (most significant byte) of data written to LCDIF by the CPU. Byte 2 of data written to LCDIF by the CPU. Byte 1 of data written to LCDIF by the CPU. Byte 0 (least significant byte) of data written to LCDIF by the CPU. 23:16 DATA_TWO 15:8 DATA_ONE DATA_ZERO 7:0 RW 0x00 RW 0x00 RW 0x00 DESCRIPTION: This register holds the 32-bit word written by the CPU into LCDIF. This data then gets sent out by the block across the interface. This register plays no role in the bus master mode of operation. EXAMPLE: Empty Example. 18.4.25 Bus Master Error Status Register Description This register reflects the virtual address at which the AXI master received an error response from the slave. HW_LCDIF_BM_ERROR_STAT 0x1c0 Table 18-51. HW_LCDIF_BM_ERROR_STAT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ADDR Table 18-52. HW_LCDIF_BM_ERROR_STAT Bit Field Descriptions BITS 31:0 ADDR LABEL RW RESET RW 0x00000000 DEFINITION Virtual address at which bus master error occurred. i.MX23 Applications Processor Reference Manual, Rev. 1 18-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) DESCRIPTION: When the BM_ERROR_IRQ is asserted, the address of the bus error is updated in the register. EXAMPLE: Empty Example. 18.4.26 LCD Interface Status Register Description The LCD interface status register can be used to check the current status of the LCDIF block. HW_LCDIF_STAT Table 18-53. HW_LCDIF_STAT 3 1 3 0 2 9 2 8 2 7 2 6 TXFIFO_EMPTY 0x1d0 2 5 2 4 DVI_CURRENT_FIELD 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 LFIFO_EMPTY TXFIFO_FULL LFIFO_FULL DMA_REQ PRESENT Table 18-54. HW_LCDIF_STAT Bit Field Descriptions BITS LABEL 31 PRESENT RW RESET RO 0x1 DEFINITION 0: LCDIF not present on this product 1: LCDIF is present. Reflects the current state of the DMA Request line for the LCDIF. The DMA Request line toggles for each new request. Read only view of the signal that indicates that LCD read datapath FIFO is full, will be generally used in the write mode of the LCD interface. Read only view of the signal that indicates that LCD read dapatath FIFO is empty, will be generally used in the read mode of the LCD interface. Read only view of the signal that indicates that LCD write datapath FIFO is full, will be generally used in the write mode of the LCD interface. Read only view of the signal that indicates that LCD write dapatath FIFO is empty, will be generally used in the read mode of the LCD interface. Read only view of the input busy signal from the external LCD controller. Read only view of the current field being transmitted. DVI_CURRENT_FIELD = 0 means field 1. DVI_CURRENT_FIELD = 1 means field 2. Reserved bits. Write as 0. 30 DMA_REQ RO 0x0 29 LFIFO_FULL RO 0x0 28 LFIFO_EMPTY RO 0x1 27 TXFIFO_FULL RO 0x0 26 TXFIFO_EMPTY RO 0x0 25 24 BUSY DVI_CURRENT_FIELD RO 0x0 RO 0x0 23:0 RSRVD0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD0 BUSY 18-45 LCD Interface (LCDIF) DESCRIPTION: The LCD interface status register that contains read only views of some parameters or current state of the block. EXAMPLE: Empty Example. 18.4.27 LCD Interface Version Register Description The LCD interface version register can be used to read the version of the LCDIF IP being used in this SoC. HW_LCDIF_VERSION Table 18-55. HW_LCDIF_VERSION 3 1 3 0 2 9 2 8 MAJOR 0x1e0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 18-56. HW_LCDIF_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x3 DEFINITION Fixed read-only value reflecting the MAJOR field of RTL version. Fixed read-only value reflecting the MINOR field of RTL version. Fixed read-only value reflecting the stepping of RTL version. 23:16 MINOR 15:0 STEP RO 0x0 RO 0x0 DESCRIPTION: The LCD interface debug register is for diagnostic use only. EXAMPLE: Empty Example. 18.4.28 LCD Interface Debug0 Register Description The LCD interface debug0 register provides a diagnostic view of the state machine and other useful internal signals. HW_LCDIF_DEBUG0 0x1f0 i.MX23 Applications Processor Reference Manual, Rev. 1 18-46 Preliminary--Subject to Change Without Notice Freescale Semiconductor LCD Interface (LCDIF) Table 18-57. HW_LCDIF_DEBUG0 3 1 STREAMING_END_DETECTED 3 0 WAIT_FOR_VSYNC_EDGE_OUT 2 9 SYNC_SIGNALS_ON_REG 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CUR_FRAME_TX EMPTY_WORD CUR_STATE ENABLE HSYNC VSYNC RSVD8 RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 Table 18-58. HW_LCDIF_DEBUG0 Bit Field Descriptions BITS LABEL 31 STREAMING_END_DETECTE D WAIT_FOR_VSYNC_EDGE_O 30 UT SYNC_SIGNALS_ON_REG 29 RSVD8 28 ENABLE 27 HSYNC 26 VSYNC 25 24 CUR_FRAME_TX RW RESET RO 0x0 DEFINITION Read only view of the DOTCLK_MODE or DVI_MODE bit going from 1 to 0. Read only view of WAIT_FOR_VSYNC_EDGE bit in the VSYNC mode after it comes out of the TXFIFO. Read only view of internal sync_signals_on_reg signal. Program this field to 0x0. Read only view of ENABLE signal. Read only view of HSYNC signal. Read only view of VSYNC signal. This bit is 1 for the time the current frame is being transmitted in the VSYNC mode. Useful for VSYNC mode debug. Indicates that the current word is empty. Read only view of the current state machine state in the current mode of operation. Program this field to 0x0. Program this field to 0x0. Program this field to 0x0. Program this field to 0x0. Program this field to 0x0. Program this field to 0x1. Reserved bits. Write as 0. RO 0x0 RO RO RO RO RO RO 0x0 0x0 0x1 0x1 0x1 0x0 EMPTY_WORD 23 22:16 CUR_STATE RO 0x1 RO 0x01 RO RO RO RO RO RO RO 0x0 0x0 0x0 0x0 0x0 0x1 0x0 15 14 13 12 11 10 9:0 RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 DESCRIPTION: The LCD interface debug register is for diagnostic use only. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 18-47 LCD Interface (LCDIF) 18.4.29 LCD Interface Debug1 Register Description The LCD interface debug1 register provides a diagnostic view of the state machine and other useful internal signals. HW_LCDIF_DEBUG1 Table 18-59. HW_LCDIF_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 H_DATA_COUNT 0x200 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 V_DATA_COUNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 18-60. HW_LCDIF_DEBUG1 Bit Field Descriptions BITS LABEL 31:16 H_DATA_COUNT RW RESET RO 0x0000 DEFINITION Read only view of the current state of the horizontal data counter. Read only view of the current state of the vertical data counter. 15:0 V_DATA_COUNT RO 0x0000 DESCRIPTION: The LCD interface debug register is for diagnostic use only. EXAMPLE: Empty Example. LCDIF Block v3.0, Revision 1.32 i.MX23 Applications Processor Reference Manual, Rev. 1 18-48 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 19 TV-Out NTSC/PAL Encoder 19.1 Implementation The TV encoder (TVENC) is a digital video encoder that takes its input from LCDIF in the ITU-R BT.656 format and sends its output to the Video DAC (VDAC). The VDAC in turn gets connected to the video jack of the device and the output can be displayed on standard definition television. The DVE block from Sarnoff is the main functional block of the TV encoder. The DVE block generates the output data that is sent to an asynchronous FIFO and then sent to the pix_int block. Finally, pix_int sends the video data to the VDAC. Figure 19-1 contains a brief diagram showing this data flow. LCDIF Synchronizing FLIP-FLOPS DVE Asynchronous FIFO VDAC pix_int Figure 19-1. TV Encoder Block Diagram The data that comes from LCDIF runs on pix_clk, which is asynchronous to the tv27m_clk that runs the TV encoder. The pix_int receives input from the asynchronous FIFO using vdac_clk, which is the clock that runs Video DAC. Tha major component of the TVENC block is the Digital Video Encoder (DVE), which is used under license from the Sarnoff Corporation. The DVE design specification from Sarnoff is the main documentation about how the encoder works and it has all the information available about the IP from the vendor. (Please refer to Appendix A at the end of this document for DVE specification.) One thing to note about this documentation is that the register map of TVENC used on i.MX23 has been considerably changed from the original Sarnoff register map. The register settings have been re-arranged and more control bits have been added to the wrapper. The user should refer to the register definitions in Section 19.4, "Programmable Registers" of this chapter for the correct address and bit positions of the programmable registers. The PIX_INT block interpolates the Composite video samples to a higher rate to reduce the requirements of off-chip video filtering. The Sarnoff IP block outputs the composite video pixel stream at 27M samples/sec. The PIX_INT interpolates this to 108 MS/sec. There are no official specifications for the spectral characteristics of the composite video signal. The PIX_INT block and the interpolation done in the i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19-1 TV-Out NTSC/PAL Encoder Sarnoff block combined have passband droop better than 0.4 dB from 0 to 5 MHz and stopband attenuation better than 40 dB. The off-chip filter required is an RC filter with a cut-off frequency of 10 MHz. 19.2 Unsupported DVE features The DVE from Sarnoff supports component, S-video, and composite video outputs. However, only the composite video mode is supported on i.MX23. Accordingly, logic functions and registers that are only intended for S-video and component video functionalities have been removed. This is a brief summary of features that have been changed in the original DVE engine: * * * * * Component and S-video support removed. rgbmatrix module and its corresponding control registers removed. Only one DAC support is available, instead of four. Only supported input data format is single 8-bit port clocked at 27 MHz in CbYCrY order. Register map has been significantly modified, so please refer to the register map at the end of this chapter. 19.3 Programming Example The following are example register settings that can be used to set up the LCDIF, CLKCTRL, TVENC and VDAC blocks for NTSC and PAL systems. Please note that these are just for reference, and some parameters might have to be tweaked by the programmer if needed. //LCDIF PIXCLK setup HW_CLKCTRL_FRAC.B.PIXFRAC = 32;//270 MHz ref pix HW_CLKCTRL_FRAC_CLR(BM_CLKCTRL_FRAC_CLKGATEPIX); // now set PIX clk to use ref_pix HW_CLKCTRL_CLKSEQ_CLR(BM_CLKCTRL_CLKSEQ_BYPASS_PIX); HW_CLKCTRL_PIX.B.DIV_FRAC_EN = 0; HW_CLKCTRL_PIX.B.DIV = 10; //27 MHz HW_CLKCTRL_PIX_CLR(BM_CLKCTRL_PIX_CLKGATE); //Setup LCDIF registers (HW_LCDIF_*) according to NTSC or PAL settings. #if NTSC_FORMAT // NTSC is 525/60 HW_LCDIF_DVICTRL0.B.H_ACTIVE_CNT = 1440; HW_LCDIF_DVICTRL0.B.H_BLANKING_CNT = 262; HW_LCDIF_DVICTRL0.B.V_LINES_CNT = 525; HW_LCDIF_DVICTRL1.B.F1_START_LINE = 4; HW_LCDIF_DVICTRL1.B.F1_END_LINE = 265; HW_LCDIF_DVICTRL1.B.F2_START_LINE = 266; HW_LCDIF_DVICTRL2.B.F2_END_LINE = 3; HW_LCDIF_DVICTRL2.B.V1_BLANK_START_LINE = 263; HW_LCDIF_DVICTRL2.B.V1_BLANK_END_LINE = 285; HW_LCDIF_DVICTRL3.B.V2_BLANK_START_LINE = 1; HW_LCDIF_DVICTRL3.B.V2_BLANK_END_LINE = 22; #else // PAL is 625/50 i.MX23 Applications Processor Reference Manual, Rev. 1 19-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor TV-Out NTSC/PAL Encoder HW_LCDIF_DVICTRL0.B.H_ACTIVE_CNT = 1440; HW_LCDIF_DVICTRL0.B.H_BLANKING_CNT = 274; HW_LCDIF_DVICTRL0.B.V_LINES_CNT = 625; HW_LCDIF_DVICTRL1.B.F1_START_LINE = 1; HW_LCDIF_DVICTRL1.B.F1_END_LINE = 312; HW_LCDIF_DVICTRL1.B.F2_START_LINE = 313; HW_LCDIF_DVICTRL2.B.F2_END_LINE = 625; HW_LCDIF_DVICTRL2.B.V1_BLANK_START_LINE HW_LCDIF_DVICTRL2.B.V1_BLANK_END_LINE = HW_LCDIF_DVICTRL3.B.V2_BLANK_START_LINE HW_LCDIF_DVICTRL3.B.V2_BLANK_END_LINE = #endif BW_LCDIF_CSC_COEFF0_C0(0x41);//0.257X256 = 65 BW_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(2);//co-sited BW_LCDIF_CSC_COEFF1_C1(0x81);//0.504x256 = 129 BW_LCDIF_CSC_COEFF1_C2(0x19);//0.098x256 = 25 BW_LCDIF_CSC_COEFF2_C3(0x3DB);//-0.148x256 = -37 BW_LCDIF_CSC_COEFF2_C4(0x3B6);//-0.291x256 = -74 BW_LCDIF_CSC_COEFF3_C5(0x70);//0.439x256 = 112 BW_LCDIF_CSC_COEFF3_C6(0x70);//0.439x256 = 112 BW_LCDIF_CSC_COEFF4_C7(0x3A2);//-0.368x256 = -94 BW_LCDIF_CSC_COEFF4_C8(0x3EE);//-0.071x256 = -18 BW_LCDIF_CSC_OFFSET_CBCR_OFFSET(128); BW_LCDIF_CSC_OFFSET_Y_OFFSET(16); //limiting values to be applied in both YCBCR input and CSC BW_LCDIF_CSC_LIMIT_CBCR_MIN (16); BW_LCDIF_CSC_LIMIT_CBCR_MAX (240); BW_LCDIF_CSC_LIMIT_Y_MIN (16); BW_LCDIF_CSC_LIMIT_Y_MAX (235); //Setup TVENC block for NTSC/PAL mode of operation. The registers which are not mentioned here maintain their reset values. #if NTSC_FORMAT//NTSC system HW_CLKCTRL_PLLCTRL0_WR (0x00050000); HW_CLKCTRL_FRAC1_WR (0x00000000); HW_CLKCTRL_TV_WR (0x00000000); HW_TVENC_CTRL_WR (0x00000000); HW_TVENC_CONFIG_WR (0x0C000240); HW_TVENC_FILTCTRL_WR (0x00080000); HW_TVENC_SYNCOFFSET_WR (0x00000359); HW_TVENC_VDACTEST_WR (0x00001000); HW_TVENC_MACROVISION0_WR( 0x00000000); HW_TVENC_MACROVISION1_WR ( 0x00000000); HW_TVENC_MACROVISION2_WR( 0x00000000); HW_TVENC_MACROVISION3_WR( 0x00000000); HW_TVENC_MACROVISION4_WR( 0x00000000); = 311; 335; = 624; 22; i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19-3 TV-Out NTSC/PAL Encoder #else//PAL system HW_CLKCTRL_PLLCTRL0_WR (0x00050000); HW_CLKCTRL_FRAC1_WR (0x00000000); HW_CLKCTRL_TV_WR (0x00000000); HW_TVENC_CTRL_WR (0x00000000); HW_TVENC_CONFIG_WR (0x0C000241); HW_TVENC_FILTCTRL_WR (0x00080000); HW_TVENC_SYNCOFFSET_WR (0x00000359); HW_TVENC_VDACTEST_WR (0x00001000); HW_TVENC_MACROVISION0_WR( 0x00000000); HW_TVENC_MACROVISION1_WR ( 0x00000000); HW_TVENC_MACROVISION2_WR( 0x00000000); HW_TVENC_MACROVISION3_WR( 0x00000000); HW_TVENC_MACROVISION4_WR( 0x00000000); HW_TVENC_COLORSUB0_WR (0x2A098ACB); HW_TVENC_COLORBURST_WR (0xD62A0000); #endif //VDAC setup HW_TVENC_DACCTRL_WR(0x000c113b); //TVENC clock settings HW_CLKCTRL_TV.B.CLK_TV108M_GATE = 0; HW_CLKCTRL_TV.B.CLK_TV_GATE = 0; //Start the LCDIF HW_LCDIF_CTRL.B.RUN = 1; 19.4 Programmable Registers The following registers are available for programmer access and control of the TV encoder. 19.4.1 TV Encoder Control Register Description HW_TVENC_CTRL HW_TVENC_CTRL_SET HW_TVENC_CTRL_CLR HW_TVENC_CTRL_TOG 0x000 0x004 0x008 0x00C This is the control register of the TV Encoder Block i.MX23 Applications Processor Reference Manual, Rev. 1 19-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor TV-Out NTSC/PAL Encoder Table 19-1. HW_TVENC_CTRL 3 1 3 0 2 9 TVENC_MACROVISION_PRESENT 2 8 TVENC_COMPOSITE_PRESENT 2 7 2 6 TVENC_COMPONENT_PRESENT 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TVENC_SVIDEO_PRESENT DAC_FIFO_NO_WRITE DAC_DATA_FIFO_RST DAC_FIFO_NO_READ Table 19-2. HW_TVENC_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION This bit must be set to zero for normal operation. When set to one, it forces a block wide reset. This bit must be set to zero for normal operation. When set to one, it gates off the clocks to the block. 0= TV Encoder is not present in this product. 30 29 28 27 26 25:6 5 CLKGATE TVENC_MACROVISION_PRE SENT TVENC_COMPOSITE_PRESE NT TVENC_SVIDEO_PRESENT TVENC_COMPONENT_PRES ENT RSRVD1 DAC_FIFO_NO_WRITE RW 0x1 RO 0x1 RO 0x1 RO 0x0 RO 0x0 RO 0x0 RW 0x0 0= TV Encoder is not present in this product. 0= TV Encoder is not present in this product. 0= TV Encoder is not present in this product. Always write zeroes to this bit field. Setting this bit prohibits writes the DAC data fifo. This may be useful for draining the FIFO for diagnostic testing. Setting this bit prohibits reads from the DAC data fifo. This may be useful for filling the FIFO at the beginning of an experiment in test mode. Set this bit to one to clear the DAC data FIFO and reset the FIFO pointers. Software should then set this bit back to zero before data can be written to the FIFO. Always write zero to this bit field. Specifies the meaning of the output stream to each DAC. 0: Default. Composite mode where the composite signal is on DAC-A. 1: DAC test mode. This outputs the data written to the HW_TVENC_VDACTEST register directly to DAC-A. Set to 1 to enable DAC Test Mode. 4 DAC_FIFO_NO_READ RW 0x0 3 DAC_DATA_FIFO_RST RW 0x0 2:1 0 RSRVD2 DAC_MUX_MODE RO 0x0 RW 0x0 DESCRIPTION: Control register of TV Encoder i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice DAC_MUX_MODE CLKGATE RSRVD1 RSRVD2 SFTRST 19-5 TV-Out NTSC/PAL Encoder EXAMPLE: Empty example. 19.4.2 TV Encoder Configuration Register Description HW_TVENC_CONFIG HW_TVENC_CONFIG_SET HW_TVENC_CONFIG_CLR HW_TVENC_CONFIG_TOG Table 19-3. HW_TVENC_CONFIG This is configuration register of the TV Encoder Block 0x010 0x014 0x018 0x01C 3 1 3 0 2 9 2 8 2 7 DEFAULT_PICFORM 2 6 2 5 2 4 2 3 2 2 2 1 ADD_YPBPR_PED 2 0 1 9 1 8 COLOR_BAR_EN 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 FSYNC_ENBL 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 ENCD_MODE 0 0 SYNC_MODE HSYNC_PHS VSYNC_PHS FSYNC_PHS PAL_SHAPE YGAIN_SEL YDEL_ADJ CLK_PHS NO_PED RSRVD5 RSRVD4 RSRVD3 RSRVD2 Table 19-4. HW_TVENC_CONFIG Bit Field Descriptions BITS LABEL 31:28 RSRVD5 DEFAULT_PICFORM 27 RW RESET RO 0x0 RW 0x1 DEFINITION Always write zeroes to this bit field. Permits use of a set of default parameters, tailored to the mode defined by T_ENCD_MODE, to be used in place of the values in the LINEx registers. Delays luma versus chroma for composite output. Luma lags chroma by YDEL_ADJ-4 cycles of 27MHz clock. For example, if YDEL_ADJ=0, the luma leads by 4 cycles. And if YDEL_ADJ=7, the luma lags by 3 cycles. Always write zeroes to this bit field. Enables Svideo output on DAC-B and DAC-D, not available on HuaShan. Permits the insertion of a black pedestal when sync is inserted on one or more component signals. Set to impose a 250nS edge shape as required by PAL, otherwise the steeper edges as specified by NTSC are used. Can be set to prevent insertion of a black pedestal as required by NTSC-J. Enable insertion of internally generated color bars. Controls the luma gain: 00 : NTSC 01 : PAL 1x : no gain 26:24 YDEL_ADJ RW 0x4 23 22 21 20 RSRVD4 RSRVD3 ADD_YPBPR_PED PAL_SHAPE RO 0x0 RO 0x0 RW 0x0 RW 0x0 19 NO_PED RW 0x0 RW 0x0 RW 0x0 COLOR_BAR_EN 18 17:16 YGAIN_SEL i.MX23 Applications Processor Reference Manual, Rev. 1 19-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD1 CGAIN TV-Out NTSC/PAL Encoder Table 19-4. HW_TVENC_CONFIG Bit Field Descriptions BITS 15:14 CGAIN LABEL RW RESET RW 0x0 DEFINITION Controls chroma gain for composite: 00 : NTSC Gain 01 : PAL Gain 1x : no gain Sync gen sub-block control. Phase adjustment of pixel clock at line-end. In 8-bit input mode, these distinguish Cb, Y1, Cr, Y2. Use to adjust the phase at the beginning of the line. The value of 00 has been used in all cases simulated to date. Always write zeroes to this bit field. External Sync sub-block control. Relates the internal field polarity to those of the input and/or output signals in interlaced modes. Set to 0. External Sync sub-block control. Relates the internal field polarity to those of the input and/or output signals in interlaced modes. 0 for PAL, 1 for NTSC External Sync sub-block control. If this bit is 0, in external-sync ("slave") mode, the rising edge of an external hsync input is used to derive the horiztonal sync for the TVENC block. Otherwise, the falling edge is used. External Sync sub-block control. If this bit is 0, in external-sync ("slave") mode, the rising edge of an external vsync input is used to derive the vertical sync for the TVENC block. Otherwise, the falling edge is used. External Sync sub-block control. Defines the manner in which the input is synchronized to the display: 000: Ext slave: 8-bit Y/C in, SYNC in 001: Ext slave: 16-bit Y/C in, SYNC in 010: Master: 8-bit Y/C in, SYNC in 011: Master: 16-bit Y/C in, SYNC in 1xx: D1 mode: 8-bit Y/C in, SYNC out Always write zeroes to this bit field. External Sync sub-block control. Defines the video mode: 000: NTSC-M Mode 001: PAL-B Mode 010: PAL-M Mode 011: PAL-N Mode 100: PAL-CN Mode 101: NTSC with 700:300 scaling on "G" 110: PAL-60 Mode 111: NTSC Progressive 13:12 CLK_PHS RW 0x0 11 10 RSRVD2 FSYNC_ENBL RO 0x0 RW 0x0 9 FSYNC_PHS RW 0x0 8 HSYNC_PHS RW 0x0 7 VSYNC_PHS RW 0x0 6:4 SYNC_MODE RW 0x0 3 2:0 RSRVD1 ENCD_MODE RO 0x0 RW 0x0 DESCRIPTION: Configuration register of TV Encoder. Configures the output mode and related parameters. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19-7 TV-Out NTSC/PAL Encoder 19.4.3 TV Encoder Filter Control Register Description HW_TVENC_FILTCTRL HW_TVENC_FILTCTRL_SET HW_TVENC_FILTCTRL_CLR HW_TVENC_FILTCTRL_TOG Table 19-5. HW_TVENC_FILTCTRL This is filter control register of the TV Encoder Block 0x020 0x024 0x028 0x02C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 YSHARP_BW 1 8 YD_OFFSETSEL 1 7 SEL_YLPF 1 6 SEL_CLPF 1 5 SEL_YSHARP 1 4 YLPF_COEFSEL 1 3 COEFSEL_CLPF 1 2 YS_GAINSGN 1 1 YS_GAINSEL 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD2 RSRVD3 RSRVD1 Table 19-6. HW_TVENC_FILTCTRL Bit Field Descriptions BITS LABEL 31:20 RSRVD1 YSHARP_BW 19 RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bit field. Controls the luma sharpness filter bandwidth inside the luma filter sub-block. LU sub-block vector controls. Control the luma offset: 0 : do not substract 1 : subtract 16 from luma. LU sub-block vector controls. Enables the luma low pass filter. LU sub-block vector controls. Enables the chroma low pass filter. LU sub-block vector controls. Enables the luma sharpness filter. LU sub-block vector controls. Controls the luma low pass filter bandwidth: 0 : 5.5 MHz 1 : 4.2 MHz LU sub-block vector controls. Controls the chroma low pass filter bandwidth: 0 : 1.3 MHz 1 : 0.6 MHz LU sub-block vector controls. Controls the sign of the sharpness modification: 0 : positive 1 : negative LU sub-block vector controls. Controls the degree of luma sharpness enhancement by luma sharpness filter: 00 : 3dB 01 : 6dB 10 : 9dB 11 : 12dB 18 YD_OFFSETSEL RW 0x0 17 16 15 14 SEL_YLPF SEL_CLPF SEL_YSHARP YLPF_COEFSEL RW 0x0 RW 0x0 RW 0x0 RW 0x0 13 COEFSEL_CLPF RW 0x0 12 YS_GAINSGN RW 0x0 11:10 YS_GAINSEL RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 19-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD4 TV-Out NTSC/PAL Encoder Table 19-6. HW_TVENC_FILTCTRL Bit Field Descriptions BITS 9 RSRVD2 RSRVD3 8 RSRVD4 7:0 LABEL RW RESET RO 0x0 RO 0x0 RO 0x0 DEFINITION Always write zeroes to this bit field. Always write zeroes to this bit field. Always write zeroes to this bit field. DESCRIPTION: Filter register of TV Encoder. Settings for input filter and RGB conversion blocks. EXAMPLE: Empty example. 19.4.4 TV Sync Offset Register Description HW_TVENC_SYNCOFFSET HW_TVENC_SYNCOFFSET_SET HW_TVENC_SYNCOFFSET_CLR HW_TVENC_SYNCOFFSET_TOG Table 19-7. HW_TVENC_SYNCOFFSET This is the Sync Offset register of the TV Encoder Block 0x030 0x034 0x038 0x03C 3 1 RSRVD1 3 0 2 9 2 8 2 7 2 6 2 5 HSO 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 VSO 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 HLC 0 4 0 3 0 2 0 1 0 0 Table 19-8. HW_TVENC_SYNCOFFSET Bit Field Descriptions BITS 31 RSRVD1 30:20 HSO LABEL RW RESET RO 0x0 RW 0x3ff DEFINITION Always write zeroes to this bit field. Defines the horizontal linestart in counts of CLK27 following the external sync edge (or EAV code in the case of D1). Works in conjuction with the CTRL0_HSYNC_PHS bit. Similar to HSO bit above in that it defines the vertical fieldstart in units of lines following the designated edge of the external vertical sync (or SFB rising edge in D1). Pixel count (pixels per line minus 1). It should be set to 857 for NTSC (interlaced and progressive) and to 863 for PAL. 19:10 VSO RW 0x3ff 9:0 HLC RW 0x359 DESCRIPTION: Sync Offset register of TV Encoder. This register sets vertical and horizontal sync offset values and the pixels/line count. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19-9 TV-Out NTSC/PAL Encoder EXAMPLE: Empty example. 19.4.5 TV Encoder Horizontal Timing Sync Register 0 Description HW_TVENC_HTIMINGSYNC0 HW_TVENC_HTIMINGSYNC0_SET HW_TVENC_HTIMINGSYNC0_CLR HW_TVENC_HTIMINGSYNC0_TOG 0x040 0x044 0x048 0x04C This is the Horizontal Timing Sync Register 0 of the TV Encoder Block Table 19-9. HW_TVENC_HTIMINGSYNC0 3 1 3 0 2 9 RSRVD2 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 SYNC_END 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSRVD1 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 SYNC_STRT 0 4 0 3 0 2 0 1 0 0 Table 19-10. HW_TVENC_HTIMINGSYNC0 Bit Field Descriptions BITS LABEL 31:26 RSRVD2 25:16 SYNC_END RW RESET RO 0x0 RW 0x04d DEFINITION Always write zeroes to this bit field. Normal end of sync pulse in first half line of video line (pixel count - 1). Always write zeroes to this bit field. Start of sync pulse in line or half-line(pixel count - 1). 15:10 RSRVD1 SYNC_STRT 9:0 RO 0x0 RW 0x00e DESCRIPTION: Horizontal Timing Sync Register 0 of TV Encoder. The line registers only needs to be programmed if the DEFAULT_PICFORM bit is cleared. EXAMPLE: Empty example. 19.4.6 TV Encoder Horizontal Timing Sync Register 1 Description HW_TVENC_HTIMINGSYNC1 HW_TVENC_HTIMINGSYNC1_SET HW_TVENC_HTIMINGSYNC1_CLR HW_TVENC_HTIMINGSYNC1_TOG 0x050 0x054 0x058 0x05C This is the Horizontal Timing Sync Register 1 of the TV Encoder Block i.MX23 Applications Processor Reference Manual, Rev. 1 19-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor TV-Out NTSC/PAL Encoder Table 19-11. HW_TVENC_HTIMINGSYNC1 3 1 3 0 2 9 RSRVD2 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 SYNC_EQEND 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSRVD1 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 SYNC_SREND 0 4 0 3 0 2 0 1 0 0 Table 19-12. HW_TVENC_HTIMINGSYNC1 Bit Field Descriptions BITS LABEL 31:26 RSRVD2 25:16 SYNC_EQEND RW RESET RO 0x0 RW 0x02d DEFINITION Always write zeroes to this bit field. End of sync pulse in each half line in equalization regions of vertical blanking (pixel count - 1). Always write zeroes to this bit field. End of sync pulse in each half line in serration region of vertical blanking (pixel count - 1). 15:10 RSRVD1 SYNC_SREND 9:0 RO 0x0 RW 0x17b DESCRIPTION: Horizontal Timing Sync Register 1 of TV Encoder. This register only needs to be programmed if the DEFAULT_PICFORM bit is cleared. EXAMPLE: Empty example. 19.4.7 TV Encoder Horizontal Timing Active Register Description HW_TVENC_HTIMINGACTIVE HW_TVENC_HTIMINGACTIVE_SET HW_TVENC_HTIMINGACTIVE_CLR HW_TVENC_HTIMINGACTIVE_TOG 0x060 0x064 0x068 0x06C This is the Horizontal Timing Active Register of the TV Encoder Block Table 19-13. HW_TVENC_HTIMINGACTIVE 3 1 3 0 2 9 RSRVD2 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 ACTV_END 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSRVD1 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 ACTV_STRT 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19-11 TV-Out NTSC/PAL Encoder Table 19-14. HW_TVENC_HTIMINGACTIVE Bit Field Descriptions BITS 31:26 25:16 15:10 9:0 LABEL RSRVD2 ACTV_END RSRVD1 ACTV_STRT RW RO RW RO RW RESET 0x0 0x3a4 0x0 0x089 DEFINITION Always write zeroes to this bit field. Horizontal end of active video (pixel count - 1). Always write zeroes to this bit field. Horizontal start of active video (pixel count - 1). DESCRIPTION: Horizontal Timing Active Register of TV Encoder. Specifies active line timing. This register only needs to be programmed if the DEFAULT_PICFORM bit is cleared. EXAMPLE: Empty example. 19.4.8 TV Encoder Horizontal Timing Color Burst Register 0 Description HW_TVENC_HTIMINGBURST0 HW_TVENC_HTIMINGBURST0_SET HW_TVENC_HTIMINGBURST0_CLR HW_TVENC_HTIMINGBURST0_TOG 0x070 0x074 0x078 0x07C This is the Horizontal Timing Color Burst Register 0 of the TV Encoder Block Table 19-15. HW_TVENC_HTIMINGBURST0 3 1 3 0 2 9 RSRVD2 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 WBRST_STRT 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSRVD1 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 NBRST_STRT 0 4 0 3 0 2 0 1 0 0 Table 19-16. HW_TVENC_HTIMINGBURST0 Bit Field Descriptions BITS LABEL 31:26 RSRVD2 25:16 WBRST_STRT RW RESET RO 0x0 RW 0x051 DEFINITION Always write zeroes to this bit field. Start of wide color burst for Macrovision (pixel count 1). Always write zeroes to this bit field. Start of normal color burst (pixel count - 1). 15:10 RSRVD1 NBRST_STRT 9:0 RO 0x0 RW 0x059 DESCRIPTION: Horizontal Timing Color Burst Register 0 of TV Encoder. This register only needs to be programmed if the DEFAULT_PICFORM bit is cleared. EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 19-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor TV-Out NTSC/PAL Encoder 19.4.9 TV Encoder Horizontal Timing Color Burst Register 1 Description HW_TVENC_HTIMINGBURST1 HW_TVENC_HTIMINGBURST1_SET HW_TVENC_HTIMINGBURST1_CLR HW_TVENC_HTIMINGBURST1_TOG 0x080 0x084 0x088 0x08C This is the Horizontal Timing Color Burst Register 1 of the TV Encoder Block Table 19-17. HW_TVENC_HTIMINGBURST1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 RSRVD1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 BRST_END 0 4 0 3 0 2 0 1 0 0 Table 19-18. HW_TVENC_HTIMINGBURST1 Bit Field Descriptions BITS LABEL 31:10 RSRVD1 BRST_END 9:0 RW RESET RO 0x0 RW 0x07b DEFINITION Always write zeroes to this bit field. End of normal or wide color burst (pixel count - 1). DESCRIPTION: Horizontal Timing Color Burst Register 1 of TV Encoder. This register only needs to be programmed if the DEFAULT_PICFORM bit is cleared. EXAMPLE: Empty example. 19.4.10 TV Encoder Vertical Timing Register 0 Description This is the Vertical Timing Register 0 of the TV Encoder Block HW_TVENC_VTIMING0 HW_TVENC_VTIMING0_SET HW_TVENC_VTIMING0_CLR HW_TVENC_VTIMING0_TOG Table 19-19. HW_TVENC_VTIMING0 3 1 3 0 2 9 RSRVD3 0x090 0x094 0x098 0x09C 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 VSTRT_PREEQ 2 0 1 9 1 8 1 7 1 6 1 5 RSRVD2 1 4 1 3 1 2 1 1 VSTRT_ACTV 1 0 0 9 0 8 0 7 RSRVD1 0 6 0 5 0 4 0 3 VSTRT_SUBPH 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19-13 TV-Out NTSC/PAL Encoder Table 19-20. HW_TVENC_VTIMING0 Bit Field Descriptions BITS LABEL 31:26 RSRVD3 25:16 VSTRT_PREEQ RW RESET RO 0x0 RW 0x20c DEFINITION Always write zeroes to this bit field. Last half line of active video followed by pre-equalization. Always write zeroes to this bit field. Last half line of sub-phase followed by active video. Always write zeroes to this bit field. Last half line of post equalization followed by sub-phase -- vertical blanking lines after post equalization. 15:14 13:8 7:6 5:0 RSRVD2 VSTRT_ACTV RSRVD1 VSTRT_SUBPH RO RW RO RW 0x0 0x29 0x0 0x11 DESCRIPTION: Vertical Timing Register 0 of TV Encoder. Specifies frame vertical timing parameters. This register only needs to be programmed if the DEFAULT_PICFORM bit is cleared. EXAMPLE: Empty example. 19.4.11 TV Encoder Vertical Timing Register 1 Description This is the Vertical Timing Register 1 of the TV Encoder Block HW_TVENC_VTIMING1 HW_TVENC_VTIMING1_SET HW_TVENC_VTIMING1_CLR HW_TVENC_VTIMING1_TOG Table 19-21. HW_TVENC_VTIMING1 3 1 3 0 2 9 2 8 2 7 VSTRT_POSTEQ 0x0a0 0x0a4 0x0a8 0x0aC 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 VSTRT_SERRA 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 LAST_FLD_LN 0 4 0 3 0 2 0 1 0 0 RSRVD3 RSRVD2 Table 19-22. HW_TVENC_VTIMING1 Bit Field Descriptions BITS 31:30 29:24 23:22 21:16 15:10 9:0 LABEL RSRVD3 VSTRT_POSTEQ RSRVD2 VSTRT_SERRA RSRVD1 LAST_FLD_LN RW RO RW RO RW RO RW RESET 0x0 0x0b 0x0 0x05 0x0 0x20c DEFINITION Always write zeroes to this bit field. Last half line of serration followed by post-equalization. Always write zeroes to this bit field. Last half line of pre-equalization followed by serration. Always write zeroes to this bit field. Last half line of field. Usually the same as VSTRT_PREEQ. i.MX23 Applications Processor Reference Manual, Rev. 1 19-14 Preliminary--Subject to Change Without Notice RSRVD1 Freescale Semiconductor TV-Out NTSC/PAL Encoder DESCRIPTION: Vertical Timing Register 1 of TV Encoder. Specifies frame vertical timing parameters. This register only needs to be programmed if the DEFAULT_PICFORM bit is cleared. EXAMPLE: Empty example. 19.4.12 TV Encoder Miscellaneous Line Control Register Description This is the Miscellaneous Register of the TV Encoder Block HW_TVENC_MISC HW_TVENC_MISC_SET HW_TVENC_MISC_CLR HW_TVENC_MISC_TOG Table 19-23. HW_TVENC_MISC 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 PAL_FSC_PHASE_ALT 0x0b0 0x0b4 0x0b8 0x0bC 0 9 FSC_PHASE_RST 0 8 0 7 0 6 0 5 AGC_LVL_CTRL 0 4 0 3 0 2 CS_INVERT_CTRL 0 1 Y_BLANK_CTRL 0 0 NTSC_LN_CNT LPF_RST_OFF BRUCHB RSRVD3 RSRVD2 Table 19-24. HW_TVENC_MISC Bit Field Descriptions BITS LABEL 31:25 RSRVD3 24:16 LPF_RST_OFF RW RESET RO 0x0 RW 0x110 DEFINITION Always write zeroes to this bit field. Programs the time to generate a pulse (in External Sync unit) so as to preload a pipeline in the Y delay module in the Filter unit. The value was emperically found to be 272 for NTSC and D1 mode, 284 for PAL in D1 mode and 136 for progressive in external sync mode. Always write zeroes to this bit field. Aligns even/odd field identification with internal field count in Sync Gen unit. 0 : for PAL-B. 1 : for NTSC. Enables PAL manner of phase alternation by field of color subcarrier in Sync Gen unit. Controls timing of color subcarrier phase reset in Sync Gen unit. 00 : for progressive. 01 : for NTSC. 10 : for PAL-M, PAL-N and PAL-60. 11 : for other PAL cases. 15:12 RSRVD2 NTSC_LN_CNT 11 RO 0x0 RW 0x1 10 9:8 PAL_FSC_PHASE_ALT FSC_PHASE_RST RW 0x0 RW 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD1 19-15 TV-Out NTSC/PAL Encoder Table 19-24. HW_TVENC_MISC Bit Field Descriptions BITS 7:6 BRUCHB LABEL RW RESET RW 0x1 DEFINITION Controls Bruch blanking in Sync Gen unit. 00 : for progressive. 01 : for 525 line cases with NTSC color. 10 : for PAL-M and PAL-60. 11 : for other PAL cases. Controls AGC levels in Macrovision sub-block. 00 : for "mixed NTSC". i.e., 714:286 on composite and 700:300 on component. 01 : for NTSC. 10 : for PAL. 11 : for progressive. Always write zeroes to this bit field. Disables illegal color stripe inversion modes in Macrovision sub-block. Controls the blanking level in the luma processing sub-block. 00 : 700:300 blanking for progressive. 01 : 714:286 blanking on both composite and component. 10 : 714:286 blanking for somposite and 700:300 blanking for component. 11 : 700:300 blanking for PAL systems. 5:4 AGC_LVL_CTRL RW 0x1 3 2 1:0 RSRVD1 CS_INVERT_CTRL Y_BLANK_CTRL RO 0x0 RW 0x0 RW 0x1 DESCRIPTION: Miscellaneous Control Register of TV Encoder. This register contains miscellaneous line control parameters. This register only needs to be programmed if the DEFAULT_PICFORM bit is cleared. EXAMPLE: Empty example. 19.4.13 TV Encoder Color Subcarrier Register 0 Description This is Color Subcarrier register 0 of the TV Encoder Block HW_TVENC_COLORSUB0 HW_TVENC_COLORSUB0_SET HW_TVENC_COLORSUB0_CLR HW_TVENC_COLORSUB0_TOG 0x0c0 0x0c4 0x0c8 0x0cC Table 19-25. HW_TVENC_COLORSUB0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PHASE_INC i.MX23 Applications Processor Reference Manual, Rev. 1 19-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor TV-Out NTSC/PAL Encoder Table 19-26. HW_TVENC_COLORSUB0 Bit Field Descriptions BITS LABEL 31:0 PHASE_INC RW RESET RW 0x21F07C1F DEFINITION Defines the frequency for the color subcarrier. The value should be set to 0x21f07c1f for NTSC or 0x2a098acb for PAL-B. This relevant to composite output only. The units are such that a phase increment of 360 degrees is entered as 0xffffffff. DESCRIPTION: Color Subcarrier register 0 of TV Encoder EXAMPLE: Empty example. 19.4.14 TV Encoder Color Subcarrier Register 1 Description This is Color Subcarrier register 1 of the TV Encoder Block HW_TVENC_COLORSUB1 HW_TVENC_COLORSUB1_SET HW_TVENC_COLORSUB1_CLR HW_TVENC_COLORSUB1_TOG 0x0d0 0x0d4 0x0d8 0x0dC Table 19-27. HW_TVENC_COLORSUB1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PHASE_OFFSET Table 19-28. HW_TVENC_COLORSUB1 Bit Field Descriptions BITS LABEL 31:0 PHASE_OFFSET RW RESET RW 0x0 DEFINITION Phase offset for color subcarrier. This is added to the phase as otherwise generated. This should typically be set to zero (default). DESCRIPTION: Color Subcarrier register 1 of TV Encoder EXAMPLE: Empty example. 19.4.15 TV Encoder Copy Protect Register Description This is the Copy Protect register of the TV Encoder Block HW_TVENC_COPYPROTECT HW_TVENC_COPYPROTECT_SET HW_TVENC_COPYPROTECT_CLR HW_TVENC_COPYPROTECT_TOG 0x0e0 0x0e4 0x0e8 0x0eC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19-17 TV-Out NTSC/PAL Encoder Table 19-29. HW_TVENC_COPYPROTECT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 CGMS_ENBL 1 3 1 2 1 1 1 0 0 9 0 8 0 7 WSS_CGMS_DATA 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 19-30. HW_TVENC_COPYPROTECT Bit Field Descriptions BITS LABEL 31:16 RSRVD1 WSS_ENBL 15 CGMS_ENBL 14 RW RESET RO 0x0 RW 0x0 RW 0x0 DEFINITION Always write zeroes to this bit field. Enable WSS insertion for 625 line modes. Enable CGMS insertion for 525 line modes (both interlaced and progressive). Payload data for insertion in either WSS or CGMS mode. 13:0 WSS_CGMS_DATA RW 0x0 DESCRIPTION: Copy Protect register of TV Encoder EXAMPLE: Empty example. 19.4.16 TV Encoder Closed Caption Register Description This is the Closed Caption register of the TV Encoder Block HW_TVENC_CLOSEDCAPTION HW_TVENC_CLOSEDCAPTION_SET HW_TVENC_CLOSEDCAPTION_CLR HW_TVENC_CLOSEDCAPTION_TOG 0x0f0 0x0f4 0x0f8 0x0fC Table 19-31. HW_TVENC_CLOSEDCAPTION 3 1 3 0 2 9 2 8 2 7 2 6 RSRVD1 2 5 2 4 2 3 2 2 2 1 2 0 1 9 CC_ENBL 1 8 1 7 CC_FILL 1 6 WSS_ENBL RSRVD1 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 CC_DATA 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 19-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor TV-Out NTSC/PAL Encoder Table 19-32. HW_TVENC_CLOSEDCAPTION Bit Field Descriptions BITS LABEL 31:20 RSRVD1 19:18 CC_ENBL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bit field. Closed Caption Enable. Set mutually exclusive????? bit 1: enable insertion in even (bottom) field bit 0: enable insertion in odd (top) field } Holds bits used to determine whether the two bytes in CC_DATA are to be inserted in the odd (upper) field or the even (lower) field. Data to be inserted. 17:16 CC_FILL RW 0x0 15:0 CC_DATA RW 0x0 DESCRIPTION: Closed Caption register of TV Encoder EXAMPLE: Empty example. 19.4.17 TV Encoder Color Burst Register Description This is Color Burst Register of the TV Encoder Block HW_TVENC_COLORBURST HW_TVENC_COLORBURST_SET HW_TVENC_COLORBURST_CLR HW_TVENC_COLORBURST_TOG 0x140 0x144 0x148 0x14C Table 19-33. HW_TVENC_COLORBURST 3 1 3 0 2 9 2 8 NBA 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 PBA 1 9 1 8 1 7 1 6 1 5 1 4 RSRVD1 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 RSRVD2 0 5 0 4 0 3 0 2 0 1 0 0 Table 19-34. HW_TVENC_COLORBURST Bit Field Descriptions BITS 31:24 NBA LABEL RW RESET RW 0xc8 DEFINITION Parameter to define color burst. Should be set to 0xc8 for NTSC and 0xd6 for PAL-B Parameter to define color burst. Should be set to 0x00 for NTSC and 0x2a for PAL-B Always write zeroes to this bit field. Always write zeros to this bit field. 23:16 PBA 15:12 RSRVD1 11:0 RSRVD2 RW 0x0 RO 0x0 RO 0x0 DESCRIPTION: Color Burst Register of TV Encoder EXAMPLE: Empty example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19-19 TV-Out NTSC/PAL Encoder 19.4.18 TV Encoder DAC Control Register Description This register controls the Video DACs associated with the TVENC. HW_TVENC_DACCTRL HW_TVENC_DACCTRL_SET HW_TVENC_DACCTRL_CLR HW_TVENC_DACCTRL_TOG Table 19-35. HW_TVENC_DACCTRL 3 1 3 0 2 9 2 8 JACK1_DIS_DET_EN 0x1a0 0x1a4 0x1a8 0x1aC 2 7 2 6 2 5 2 4 2 3 2 2 DISABLE_GND_DETECT 2 1 2 0 1 9 1 8 1 7 1 6 1 5 BYPASS_ACT_CASCODE 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 NO_INTERNAL_TERM 0 2 0 1 0 0 HALF_CURRENT LOWER_SIGNAL JACK1_DET_EN DUMP_TOVDD1 JACK_DIS_ADJ WELL_TOVDD SELECT_CLK INVERT_CLK Table 19-36. HW_TVENC_DACCTRL Bit Field Descriptions BITS 31 30 29 28 LABEL TEST3 RSRVD1 RSRVD2 JACK1_DIS_DET_EN RW RW RO RO RW RESET 0x0 0x0 0x0 0x0 DEFINITION Test bit. Always write zero to this bit. Always write zero to this bit. Enables the jack1 disconnect detector. This should only be activated when pwrup1 is high (the video dac is active). Test bit. Always write zero to this bit. Always write zero to this bit. Enables the jack1 connect detector. This places a weak pullup to VDDA on the video1 output pad. When a 75ohm termination load is applied the pad is pulled to ground enabling the detect circuitry. This signal should only be active when PWRUP1 is low (the video dac is turned off). Test bit. If the video jack detects a grounded output (headphone plugged into video/audio jack) then the IRQ handler should set this bit to turn off the power of the ground detector until the jack is unplugged and replugged (to check the impedance again). These bits adjust the trip voltage for the disconnect detector. 00=1.35 (default), 01=1.50, 10=1.65, 11=1.80. 27 26 25 24 TEST2 RSRVD3 RSRVD4 JACK1_DET_EN RW RO RO RW 0x0 0x0 0x0 0x0 23 22 TEST1 DISABLE_GND_DETECT RW 0x0 RW 0x0 21:20 JACK_DIS_ADJ RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 19-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor CASC_ADJ PWRUP1 RSRVD1 RSRVD2 RSRVD3 RSRVD4 RSRVD5 RSRVD6 RSRVD7 RSRVD8 GAINDN GAINUP TEST3 TEST1 TEST2 RVAL TV-Out NTSC/PAL Encoder Table 19-36. HW_TVENC_DACCTRL Bit Field Descriptions BITS 19 GAINDN LABEL RW RESET RW 0x0 DEFINITION Set to gain the digital code down. This mode will usually be used with the gainup bit to turn the DAC conversion gain down 20%. When both gaindn and gainup are set the max digital code (in non-Macrovision mode) will be 1003 and will give a DAC output voltage of 1.02V. Set to gain the digital code up by 25%. This mode (along with GAINDN) can be used in non-macrovision mode to reduce power consumption by 20% and use more dynamic range in the DAC. In non-Macrovision mode the max digital code (pregain) is 802 and is 1003 after the gain. Set to invert the dac clk (change the clock edge that the DAC updates on). Default value of 0 selects a 27MHz sample rate for the video DACs. Set to one to use an internal 4X upsampler to run the video DAC at 108MHz. This should reduce out of band energy and reduce needed external filtering. This bit bypasses/disables the active cascode amp that is used to improve the low frequency PSRR of the video DACs. It defaults low where the active cascode is enabled. Always write zero to this bit. Always write zero to this bit. Power up video dac channel 1. Set to change the nwell connection for the current steering PFET switched from VDDA to VDDD for all 3 video DACs. It trades off slightly better glitch energy for reduced VDDD PSRR. Always write zero to this bit. Always write zero to this bit. Enables low power feature for video DAC1 to dump the unused DAC current to the VDDD rail instead of ground. Each channel has a separate control because VDDD may not be able to handle the power from all three DACs. Decreases video DAC output swings by 33% to save corresponding power. Default is low- disabled. Used to adjust the on-chip resistances that set the termination resistor and the peak output current. 000 = +20%, 001 = +12.4%, 010=+5.8%, 011=nom, 100=-4.4%, 101=-10%, 110=-14.2%, 111=-17.3%. This effects all video DAC channels. This bit disables the internal termination mode for all three video DACs. With this bit cleared each video dac (that is powered up) has an internal 75ohm termation. When the bit is set the 75ohm termination is removed. 18 GAINUP RW 0x0 17 16 INVERT_CLK SELECT_CLK RW 0x0 RW 0x0 15 BYPASS_ACT_CASCODE RW 0x0 14 13 12 11 RSRVD5 RSRVD6 PWRUP1 WELL_TOVDD RO RO RW RW 0x0 0x0 0x0 0x0 10 9 8 RSRVD7 RSRVD8 DUMP_TOVDD1 RO 0x0 RO 0x0 RW 0x0 7 6:4 LOWER_SIGNAL RVAL RW 0x0 RW 0x0 3 NO_INTERNAL_TERM RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19-21 TV-Out NTSC/PAL Encoder Table 19-36. HW_TVENC_DACCTRL Bit Field Descriptions BITS LABEL 2 HALF_CURRENT RW RESET RW 0x0 DEFINITION When cleared the nominal peak output current for each DAC is 34.67mA. When set the nominal peak output current is 17.3mA. The half current bit should be set whenever NO_INTERNAL_TERM is set AND there is only a signal 75ohm external load. This field adjusts the cascode voltage for the current sources (all three video DACs). 00=nom, 01=-50mV, 10=+50mV, 11=+100mV. The higher settings might be useful when headroom is low. 1:0 CASC_ADJ RW 0x0 DESCRIPTION: This register contains control bits for programming the DAC. EXAMPLE: Empty example. 19.4.19 TV Encoder DAC Status Register Description This register contains status bits for DAC connect/disconnect interrupts. HW_TVENC_DACSTATUS HW_TVENC_DACSTATUS_SET HW_TVENC_DACSTATUS_CLR HW_TVENC_DACSTATUS_TOG Table 19-37. HW_TVENC_DACSTATUS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 JACK1_DET_STATUS 0x1b0 0x1b4 0x1b8 0x1bC 0 9 0 8 0 7 JACK1_GROUNDED 0 6 0 5 0 4 JACK1_DIS_DET_IRQ 0 3 0 2 0 1 JACK1_DET_IRQ 0 0 Table 19-38. HW_TVENC_DACSTATUS Bit Field Descriptions BITS 31:13 12 11 10 LABEL RSRVD1 RSRVD2 RSRVD3 JACK1_DET_STATUS RSRVD4 RSRVD5 JACK1_GROUNDED RW RO RO RO RO RESET 0x0 0x0 0x0 0x0 DEFINITION Always write zeroes to this bit field. Always write zero to this bit. Always write zero to this bit. This status bit is high if the output is pulled to ground with an impedance less than 20ohm (not a video load). Always write zero to this bit. Always write zero to this bit. This status bit is high if the output is pulled to ground with an impedance less than 20ohm (not a video load). 9 8 7 RO 0x0 RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 19-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor ENIRQ_JACK RSRVD1 RSRVD2 RSRVD3 RSRVD4 RSRVD5 RSRVD6 RSRVD7 RSRVD8 RSRVD9 TV-Out NTSC/PAL Encoder Table 19-38. HW_TVENC_DACSTATUS Bit Field Descriptions BITS LABEL 6 RSRVD6 RSRVD7 5 JACK1_DIS_DET_IRQ 4 RW RESET RO 0x0 RO 0x0 RW 0x0 DEFINITION Always write zero to this bit. Always write zero to this bit. Jack1 disconnect detect interrupt status bit. Reset this bit by writing a one to the SCT clear address space and not by a general write. Always write zero to this bit. Always write zero to this bit. Jack1 detect interrupt status bit. Reset this bit by writing a one to the SCT clear address space and not by a general write. This IRQ goes high if the video output is pulled to ground. It will not trigger if the video output is pulled to HP_VGND in capless mode (VAG voltage). Setting this bit enables all DAC jack detect interrupt sources. 3 2 1 RSRVD8 RSRVD9 JACK1_DET_IRQ RO 0x0 RO 0x0 RW 0x0 0 ENIRQ_JACK RW 0x0 DESCRIPTION: This register contains DAC interrupt control and status bits. EXAMPLE: Empty example. 19.4.20 TV Encoder vDAC Test Register Description This register used to write values directly to the VDACs. HW_TVENC_VDACTEST HW_TVENC_VDACTEST_SET HW_TVENC_VDACTEST_CLR HW_TVENC_VDACTEST_TOG Table 19-39. HW_TVENC_VDACTEST 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 ENABLE_PIX_INT_GAIN 0x1c0 0x1c4 0x1c8 0x1cC 1 2 1 1 BYPASS_PIX_INT_DROOP 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TEST_FIFO_FULL BYPASS_PIX_INT RSRVD1 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice DATA 19-23 TV-Out NTSC/PAL Encoder Table 19-40. HW_TVENC_VDACTEST Bit Field Descriptions BITS LABEL 31:14 RSRVD1 ENABLE_PIX_INT_GAIN 13 RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bit field. Enabling this bit will attenuate the output of the pix_int block to ensure that the frequency response is never greater than 0.0dB, however, the DC gain will then be less than 1. When cleared, the DC response is set to 0 dB, and the maximum gain in the passband is about 0.45dB. When this bit is set, the pixel interpolator is bypassed. Setting this bit will require a higher order analog reconstruction filter outside the chip. This bypasses the droop compensation portion of the pixel interpolator. If set, the pixel interpolator will have approximately 1dB of droop across the pass band. When this bit is asserted then the DAC test fifo is full and the HW_TVENC_DACTEST register should not be written. This bit only has meaning when the DAC_MUX_MODE field equals 11b. Digital data sample going to DAC 0. 12 BYPASS_PIX_INT RW 0x0 11 BYPASS_PIX_INT_DROOP RW 0x0 10 TEST_FIFO_FULL RO 0x0 9:0 DATA RW 0x000 DESCRIPTION: This register contains 10 bit data samples going to the DAC and one status bit. EXAMPLE: Empty example. 19.4.21 TV Encoder Version Register Description This register always returns a known read value for debug purposes it indicates the version of the block. HW_TVENC_VERSION Table 19-41. HW_TVENC_VERSION 3 1 3 0 2 9 2 8 MAJOR 0x1d0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 19-42. HW_TVENC_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x01 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x00 RO 0x0000 i.MX23 Applications Processor Reference Manual, Rev. 1 19-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor TV-Out NTSC/PAL Encoder DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_TVENC_VERSION.B.MAJOR != 1) Error(); TVENC Block v1.1, Revision 1.00 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19-25 TV-Out NTSC/PAL Encoder i.MX23 Applications Processor Reference Manual, Rev. 1 19-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 20 Video DAC 20.1 Overview The i.MX23 provides an on-chip video DAC to drive an external video device. 20.2 Details of Operations The video DAC is designed to directly drive a 75 composite video load. Composite signals have a maximum signal bandwidth of 5.1 MHz. The video DAC uses ~10X oversampling (108 MHz sample rate) to allow for a very simple anti-alias filter at the output. In some applications, it may be acceptable to use a single capacitor at the output for the anti-alias filter. If this does not provide adequate signal quality, a 2-pole LC filter can be used. The video DAC includes a number of power saving features. First, it runs off the 1.62-2.0 V VDDA power rail instead of a more common 3.3 V power rail. Second, in non-Macrovision mode, the power can be reduced by ~25% by setting tvenc_dacctrl_gaindn AND dacctrl_gainup. These bits reduce the peak output signal from 1.3 V (only needed for Macrovision) to 1.02 V. A third power saving feature for the video DAC is the ability to run in single or double termination mode. In single termination mode the power consumption of the video DAC is reduced by 50%. In a typical video driver, the cable is terminated with 75 on the driver side and receiver side of the cable. This minimizes signal reflections and provides the best signal quality. However, the composite video signals have relatively low bandwidth, and the typical video cable is relatively short. Therefore, the signal reflections caused by a single terminated load (only at the receiver end) should not cause a noticeable reduction in signal quality. The video DAC has an integrated/switchable 75 termination resistor. This allows the DAC to run in either low power (single termination mode) or high quality (double termination mode). It is expected that the low power mode of operation will provide video quality that is acceptable for nearly all users. But this can be adjusted in software as desired. To run in the low power, single termination mode, set bits tvenc_dacctrl_no_internal_term AND tvenc_dacctrl_half_current. A fourth low power feature for the video DAC is jack detect. Jack detect enables the video DACs to be turned on only when a video load is present and can allow the video DACs to turn off as soon as the video load is removed. Some video players will choose to use a combined composite & headphone out jack. When these jacks are used, a normal headphone (non-video plug) will cause the video terminal to be i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 20-1 Video DAC shorted to ground. The jack detector includes a short detect to distinguish this grounded load from a 75 video DAC load. The list below describes the expected usage of the video jack detect. 1. Enable jack detect and wait for IRQ 2. When IRQ indicates a jack detect event, if the player supports headphone and composite combined jack, then go to step 3, else jump to step 4. 3. Check status of jack_grounded. If jack_grounded is high (indicates headphone [not video] is plugged in) then set disable_gnd_detect to cut the power consumption and wait in this state until jack_detect goes low (do not disable jack detect). You will probably need to disable the interrupt and just poll the status of jack_detect. When jack_detect goes low (indicating an unplug) then unset the disable_gnd_detect and return to step 1. 4. A video jack has been detected. Unset the jack_detect_en, power-up the video DAC, and set jack_disconn_det_en. Wait in this state until an IRQ for a jack_disconn is detected. It may be desirable to add a special "double check" feature here to make sure it detects twice before proceeding. When jack_disconn is detected, power off the video DAC and return to step1. i.MX23 Applications Processor Reference Manual, Rev. 1 20-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 21 Synchronous Serial Ports (SSP) This chapter describes the two identical synchronous serial ports (SSP) included on the i.MX23. It includes sections on external pins, bit rate generation, frame formats, Winbond SPI mode, Motorola SPI mode, Texas Instruments Synchronous Serial Interface (SSI) mode, and SD/SDIO/MMC mode. Programmable registers are described in Section 21.10, "Programmable Registers. 21.1 Overview The synchronous serial port is a flexible interface for inter-IC and removable media control and communication. The SSP supports master operation of SPI, Texas Instruments SSI and 1-bit, 4-bit, and 8-bit SD/SDIO/MMC. The SPI mode has enhancements to support 1-bit legacy MMC cards. SPI master dual (2-bit) and quad (4-bit) mode reads are also supported. The SSP also supports slave operation for the SPI and SSI modes. The SSP has a dedicated DMA channel in the bridge and can also be controlled directly by the CPU through PIO registers. Figure 21-1 illustrates one of the two SSP ports included on the i.MX23. The only interaction between SSP1 and SSP2 is that they share the same input, SSPCLK. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-1 Synchronous Serial Ports (SSP) ARM Core SRAM System Clock Generator AHB AHB-to-APBH Bridge AHB Slave AHB Master DMA Controller DMA Request APBH Master APBH SPI MS TI SSI 8-Bit SD/SDIO/MMC Modes CE-ATA Mode Synchronous Serial Port GPIO SSP/GPIO Pin MUX Pins Figure 21-1. Synchronous Serial Port Block Diagram 21.2 External Pins Table 21-1 lists the SSP pin placements for all supported modes. MOTOROLA SPI MODE WINBOND SPI MODE TI SSI MODE SD/SDIO/ MMC MODES PIN NAME SSP_SCK SSP_CMD SSP_DATA0 SSP_DATA1 SSP_DATA2 SSP_DATA3 SSP_DATA4 SSP_DATA5 SSP_DATA6 SSP_DATA7 SSP_DETECT SCK MOSI MISO SSn0 SSn1 SSn2 CLK DI (IO0) DO (IO1) WPn (IO2) HOLDn (IO3) SSn0 SSn1 SSn2 CLK MOSI MISO SSn CLK CMD DATA0 DATA1/IRQ DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 CARD_DETECT Table 21-1. SSP Pin Matrix i.MX23 Applications Processor Reference Manual, Rev. 1 21-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor SSPCLK HCLK Synchronous Serial Ports (SSP) The pin control interface on the i.MX23 provides all digital pins with selectable output drive strengths. In addition, all SSP data pins have selectable 47-K pullup resistors, and SSP command pins have 10-K pullups. Configuring the SSP_CMD pad to connect to the internal 10-K pullup is recommended for SD/SDIO/MMC modes during the Card_ID phase. After the Card_ID phase, the 10-K pullup should be disabled, and the weaker external 47-K pullup takes over. The SSP_DATA pads also can be configured to connect to an internal 47-K pullup, which is required for SD/SDIO/MMC modes. 21.3 Bit Rate Generation The serial bit rate is derived by dividing down the internal clock SSPCLK. The clock is first divided by an even prescale value, CLOCK_DIVIDE, from 2 to 254, which is programmed in HW_SSP_TIMING. The clock is further divided by a value from 1 to 256, which is 1 + CLOCK_RATE, where CLOCK_RATE is the value programmed in HW_SSP_TIMING. The frequency of the output signal bit clock SSP_SCK is defined as follows: SSP_SCK= SSPCLK CLOCK_DIVIDE * (1+CLOCK_RATE) For example, if SSPCLK is 3.6864 MHz, and CLOCK_DIVIDE = 2, then SSP_SCK has a frequency range from 7.2 kHz to 1.8432 MHz. See Chapter 4, "Clock Generation and Control," for more clock details. 21.4 Frame Format for SPI and SSI Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. Two basic frame types can be selected: * * Motorola SPI Texas Instruments Synchronous Serial Interface (SSI) For both formats, the serial clock (SSP_SCK) is held inactive while the SSP is idle and transitions at the programmed frequency only during active transmissions or reception of data. The idle state of SSP_SCK is used to provide a receive time-out indication, which occurs when the FIFO still contains data after a time-out period. For Motorola SPI frame format, the serial frame (SSn) pin is active low and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial interface (SSI) frame format, the SSn pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSP and the off-chip slave device drive their output on data on the rising edge of SSP_SCK, and latch data from the other device on the falling edge. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-3 Synchronous Serial Ports (SSP) The SSP master supports up to three combinations of SPI and SSI slave devices connected. Three SSn pins are provided but only one can be active at a time. 21.5 Motorola SPI Mode The SPI mode is used for general inter-component communication and legacy 1-bit MMC cards. 21.5.1 SPI DMA Mode The SPI bus is inherently a full-duplex bidirectional interface. However, as most applications only require half-duplex data transmission, the i.MX23 has a single DMA channel for the SSP. It can be configured for either transmit or receive. In DMA receive mode, the SPI continuously repeats the word written to its data register. In DMA transmit mode, the SPI ignores the incoming data. 21.5.2 Motorola SPI Frame Format The Motorola SPI interface is a four-wire interface where the SSn signal behaves as a slave select. The main feature of the Motorola SPI format is that the inactive state and phase of SSP_SCK signal are programmable through the polarity and phase bits within the HW_SSP_CTRL1. 21.5.2.1 * * Clock Polarity When the clock polarity control bit is low, it produces a steady-state low value on the SSP_SCK pin. When the clock polarity control bit is high, a steady-state high value is placed on the SSP_SCK pin when data is not being transferred. 21.5.2.2 Clock Phase The phase control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted, by either allowing or not allowing a clock transition before the first data-capture edge. * * When the phase control bit is low, data is captured on the first clock-edge transition. When the clock phase control bit is high, data is captured on the second clock-edge transition. 21.5.3 Motorola SPI Format with Polarity=0, Phase=0 SIngle and continuous transmission signal sequences for Motorola SPI format with POLARITY=0, PHASE=0 are shown in Figure 21-2 and Figure 21-3. i.MX23 Applications Processor Reference Manual, Rev. 1 21-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) SSP_SCK SSn MISO MOSI Figure 21-2. Motorola SPI Frame Format (Single Transfer) with POLARITY=0 and PHASE=0 SSP_SCK SSn MOSI/MISO Figure 21-3. Motorola SPI Frame Format with POLARITY=0 and PHASE=0 In this configuration, during idle periods: * * * * * The SSP_SCK signal is forced low. SSn is forced high. The Transmit data line MOSI is arbitrarily forced low. When the SSP is configured as a master, SSP_SCK is an output. When the SSP is configured as a slave, SSP_SCK is an input. If the SSP is enabled and there is valid data within the FIFO, the start of the transmission is signified by the SSn master signal being low. This causes slave data to be enabled onto the MISO input line of the master, and the enables the master MOSI output pad. One-half SSP_SCK period later, valid master data is transferred to the MOSI pin. Now that both the master and slave data have been set, the SSP_SCK master clock pin goes high after one further half SSP_SCK period. The data is now captured on the rising and propagated on the falling edges of the SSP_SCK signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSn line is returned to its idle high state one SSP_SCK period after the last bit has been captured. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-5 Synchronous Serial Ports (SSP) However, in the case of continuous back-to-back transmissions, the SSn signal must be pulsed high between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the PHASE bit is logic 0. Therefore, the master device must raise the SSn pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSn pin is returned to its idle state one SSP_SCK period after the last bit has been captured. 21.5.4 Motorola SPI Format with Polarity=0, Phase=1 The transfer signal sequence for Motorola SPI format with POLARITY=0 and PHASE=1 is shown in Figure 21-4, which covers both single and continuous transfers. SSP_SCK SSn MISO MOSI Figure 21-4. Motorola SPI Frame Format (Single Transfer) with POLARITY=1 and PHASE=0 In this configuration, during idle periods: * * * * * The SSP_SCK signal is forced low. SSn is forced high. The Transmit data line MOSI is arbitrarily forced low. When the SSP is configured as a master, the SSP_SCK pad is an output. When the SSP is configured as a slave, the SSP_SCK is an input. If the SSP is enabled and there is valid data within the FIFO, the start of the transmission is signified by the SSn master signal being low. After a further one-half SSP_SCK period, both master and slave valid data are enabled with a rising-edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSP_SCK signal. In the case of a single word transfer, after all bits have been transferred, the SSn line is returned to its idle high state one SSP_SCK period after the last bit has been captured. For continuous back-to-back transfers, SSPFSOUT (the SSn pin in master mode) is held low between successive data words and termination is the same as that of a single word transfer. i.MX23 Applications Processor Reference Manual, Rev. 1 21-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) 21.5.5 Motorola SPI Format with Polarity=1, Phase=0 Single and continuous transmission signal sequences for Motorola SPI format with POLARITY=1 and PHASE=0 are shown in Figure 21-5 and Figure 21-6. SSP_SCK SSn MISO MOSI Figure 21-5. Motorola SPI Frame Format (Single Transfer) with POLARITY=1 and PHASE=0 Note: In Figure 21-5, Q is an undefined signal. SSP_SCK SSn MOSI/MISO Figure 21-6. Motorola SPI Frame Format (Continuous Transfer) with POLARITY=1 and PHASE=0 In this configuration, during idle periods: * * * * * The SSP_SCK signal is forced high. SSn is forced high. The Transmit data line MOSI is arbitrarily forced low. When the SSP is configured as a master, the SSP_SCK pad is an output. When the SSP is configured as a slave, the SSP_SCK is an input. If the SSP is enabled and there is valid data within the FIFO, the start of transmission is signified by the SSn master signal being driven low, which causes slave data to be immediately transferred onto the MISO line of the master, and enabling the master MOSI output pad. One half-period later, valid master data is transferred to the MOSI line. Now that both master and slave data have been set, the SSP_SCK master clock pin becomes low after one further half SSP_SCK period. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-7 Synchronous Serial Ports (SSP) This means that data is captured on the falling edges and propagated on the rising edges of the SSP_SCK signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSn line is returned to its idle high state one SSP_SCK period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSn signal must be pulsed high between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the PHASE bit is logic 0. Therefore, the master device must raise SSPSFSSIN (the SSn pin in slave mode) of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSn pin is returned to its idle state one SSP_SCK period after the last bit has been captured. 21.5.6 Motorola SPI Format with Polarity=1, Phase=1 The transfer signal sequence for Motorola SPI format with POLARITY=1 and PHASE=1 is shown in Figure 21-7, which covers both single and continuous transfers. SSP_SCK SSn MISO MOSI Figure 21-7. Motorola SPI Frame Format with POLARITY=1 and PHASE=1 Note: In Figure 21-7, Q is an undefined signal. In this configuration, during idle periods: * * * * * The SSP_SCK signal is forced high. SSn is forced high. The Transmit data line MOSI is arbitrarily forced low. When the SSP is configured as a master, the SSP_SCK pad is an output. When the SSP is configured as a slave, the SSP_SCK is an input. If the SSP is enabled and there is valid data within the FIFO, the start of transmission is signified by the SSn master signal being driven low, and MOSI output is enabled. After a further one-half SSP_SCK period, both master and slave are enabled onto their respective transmission lines. At the same time, the SSP_SCK is enabled with a falling edge transition. Data is then captured on the rising edge and propagated on the falling edges of the SSP_SCK signal. i.MX23 Applications Processor Reference Manual, Rev. 1 21-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) After all bits have been transferred, in the case of a single word transmission, the SSn line is returned to its idle high state one SSP_SCK period after the last bit has been captured. For continuous back-to-back transmissions, the SSn pin remains in its active low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. For continuous back-to-back transfers, the SSn pin is held low between successive data words and termination is the same as that of the single word transfer. 21.6 Winbond SPI Mode The Winbond SPI mode is similar to Motorola's SPI mode when POLARITY = PHASE, where data is sampled on the rising edge. In addition to serial 1-bit reads and writes, 2-bit (dual) and 4-bit (quad) reads are supported. Only 8-bit word length is supported for dual and quad read modes. See Figure 21-9. The numbers in the IO signal waveform correspond to the bit position in the byte being transferred. Figure 21-8. Fast Read Dual and Quad Output Diagram 21.7 Texas Instruments Synchronous Serial Interface (SSI) Mode Figure 21-9 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-9 Synchronous Serial Ports (SSP) SSP_SCK SSn MOSI/MISO Figure 21-9. Texas Instruments Synchronous Serial Frame Format (Single Transfer) In this mode, SSP_SCK and SSn are forced low, and the transmit data line MOSI is three-stated whenever the SSP is idle. Once the bottom entry of the FIFO contains data, SSn is pulsed high for one SSP_SCK period. The value to be transmitted is also transferred from the FIFO to the serial shift register of the transmit logic. On the next rising edge of SSP_SCK, the MSB of the 4-to-16-bit data frame is shifted out on the SSPRXD pin by the off-chip serial slave device. Both the SSP and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSP_SCK. The received data is transferred from the serial shifter to the FIFO on the first rising edge of SSP_SCK after the LSB has been latched. Figure 21-10 shows the Texas Instrument synchronous serial frame format when back-to-back frames are transmitted. SSP_SCK SS SSn MOSI/MISO Figure 21-10. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer) 21.8 SD/SDIO/MMC Mode This mode is used to provide high performance with SD, SDIO, MMC, and high-speed (4-bit and 8-bit) MMC cards. SD/MMC mode supports simultaneous command and data transfers. Commands are sent to the card and responses are returned to the host on the CMD line. Register data, such as card information, is sent as a i.MX23 Applications Processor Reference Manual, Rev. 1 21-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) command response and is therefore on the CMD line. Block data read from or written to the card's flash is transferred on the DAT line(s). The SSP also supports the SDIO IRQ. The SSP's SD/MMC controller can automatically perform a single block read/write or card register operation with a single PIO setup and RUN. For example, the SD/MMC controller can perform these steps with a single write to the PIO registers: * * * * * * Send command to the card. Receive response from the card. Check response for errors (and assert a CPU IRQ if there is an error). Wait for the DAT line(s) to be ready to transfer data (while counting for time-out) Transfer multiple blocks of data to/from the card. Check the CRC or CRC status of received/sent data (and assert IRQ if there is an error). The SD/MMC controller is generally used with the DMA. Each DMA descriptor is set up the SD/MMC controller to perform a single complex operation as exemplified above. Multiple DMA descriptors can be chained to perform multiple card block transfers without CPU intervention. A single DMA descriptor can also perform multiple card block transfers. 21.8.1 SD/MMC Command/Response Transfer SD/MMC commands are written to the HW_SSP_CMDn registers and sent on the CMD line. Command tokens consist of a start bit (0), a source bit (1), the actual command, which is padded to 38 bits, a 7-bit CRC and a stop bit (1). The command token format is shown in Table 21-2. Table 21-2. SD/MMC Command/Response Transfer Line CMD Start 0 Source 1 (Host) Data 38-bit Command CRC CRC7 End 1 SD/MMC cards transmit command words with the most significant bit first. After the card receives the command, it checks for CRC errors or invalid commands. If an error occurs, the card withholds the usual response to the command. After transmitting the end bit, the SSP releases the CMD line to the high-impedance state. A pullup resistor on the CMD node keeps it at the 1 state until the response packet is received. The slave waits to issue the reply until the SCK line is clocking again. After the SSP sends an SD/MMC command, it optionally starts looking for a response from the card. It waits for the CMD line to go low, indicating the start of the response token. Once the SSP has received the Start and Source bits, it begins shifting the response content into the receive shift register. The SSP calculates the CRC7 of the incoming data. If the card fails to start sending an expected response packet within 64 SCK cycles, then an error has occurred; the command may be invalid or have a bad CRC. After the SSP detects a time-out, it stops any i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-11 Synchronous Serial Ports (SSP) DMA request activity and sets the RESP_TIMEOUT flag. If RESP_TIMEOUT_IRQ_EN is set, then a CPU IRQ is asserted. The SSP calculates the CRC of the received response and compare it to the CRC received from the card. If they do not match, then the SSP sets the RESP_ERR status flag. If RESP_ERR_IRQ_EN is set, then a CPU IRQ is asserted on a command response CRC mismatch. The SSP can also compare the 32-bit card status word, known as response R1, against a reference to check for errors. If CHECK_RESP in HW_SSP_CTRL0 is set, then the SSP XORs the response with the XOR field in the HW_SSP_COMPREF register. It then masks the results with the MASK field in the HW_SSP_COMPMASK register. If there are any differences between the masked response and the reference, then an error has occurred. The CPU asserts the RESP_ERR status flag. If RESP_ERR_IRQ_EN is set, then the RESP_ERR_IRQ is asserted. In the ISR, the CPU can read the status word to see which error flags are set. The regular and long response tokens are shown in Table 21-3 and Table 21-4: Table 21-3. SD/MMC Command Regular Response Token Line CMD Start 0 Source 0 (Card) Data 38-bit Response CRC CRC7 End 1 Table 21-4. SD/MMC Command Regular Long Response Token Line CMD Start 0 Source 0 (Card) Data 117-bit response CRC CRC16 End 1 21.8.2 SD/MMC Data Block Transfer Block data is transferred on the DATA0 pin. In 1-bit I/O mode, the block data is formatted as shown in Table 21-5. Block data transfers typically have 512 bytes of payload, plus a 16-bit CRC, a Start bit, and an End bit. The block size is programmable with the XFER_COUNT field in the HW_SSP_CTRL0 register. In SD/MMC mode, WORD_LENGTH in the HW_SSP_CTRL1 register field should always be set to 8 bits. Data is always sent Most Significant Bit of the Least Significant Byte first. The SSP is designed to support block transfer modes only. Streaming modes may not be supported. Figure 21-11 shows a flowchart of SD/MMC block read and write transfers. In block write mode, the card holds the DATA0 line low while it is busy. SSP must wait for the DATA0 line to be high for one clock cycle before starting to write a block. In block read mode, the card begins sending the data when it is ready. The first bit transmitted by the card is a Start bit 0. Prior to the 0 Start Bit, the DATA0 bus is high. After the start bit is received, data is shifted in. The SSP bus width is set using the BUS_WIDTH bit in the HW_SSP_CTRL0 register. In 1-bit bus mode, the block data is formatted as shown in Table 21-5. i.MX23 Applications Processor Reference Manual, Rev. 1 21-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) Table 21-5. SD/MMC Data Block Transfer 1-Bit Bus Mode Line DATA0 Start 0 Data Data Bit 7 Byte 0 Data ... Data Data Bit 0 Byte 511 CRC CRC16 End 1 In 4-bit I/O mode, the block data is formatted as shown in Table 21-6. Table 21-6. SD/MMC Data Block Transfer 4-Bit Bus Mode Line DATA3 DATA2 DATA1 DATA0 Start 0 0 0 0 Data Data Bit 7 Byte 0 Data Bit 6 Byte 0 Data Bit 5 Byte 0 Data Bit 4 Byte 0 Data ... ... ... ... Data Data Bit 3 Byte 511 Data Bit 2 Byte 511 Data Bit 1 Byte 511 Data Bit 0 Byte 511 CRC CRC16 CRC16 CRC16 CRC16 End 1 1 1 1 In 8-bit bus mode, the block data is formatted as shown in Table 21-7. Table 21-7. SD/MMC Data Block Transfer 8-Bit Bus Mode Line DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Start 0 0 0 0 0 0 0 0 Data Data Bit 7 Byte 0 Data Bit 6 Byte 0 Data Bit 5 Byte 0 Data Bit 4 Byte 0 Data Bit 3 Byte 0 Data Bit 2Byte 0 Data Bit 1 Byte 0 Data Bit 0 Byte 0 Data ... ... ... ... ... ... ... ... Data Data Bit 7 Byte 511 Data Bit 6 Byte 511 Data Bit 5 Byte 511 Data Bit 4 Byte 511 Data Bit 3 Byte 511 Data Bit 2 Byte 511 Data Bit 1 Byte 511 Data Bit 0 Byte 511 CRC CRC16 CRC16 CRC16 CRC16 CRC16 CRC16 CRC16 CRC16 End 1 1 1 1 1 1 1 1 21.8.2.1 SD/MMC Multiple Block Transfers The SSP supports SD/MMC multiple block transfers. The CPU or DMA will configure the SD/MMC controller to issue a Multi-Block Read or Write command. If DMA is used, then the first descriptor issues the multi-block read/write command and receives/sends the first block (512 bytes) of data. Subsequent DMA descriptors only receive/send blocks of data and do not issue new SD/MMC commands. If the card is configured for an open-ended multi-block transfer, then the last DMA descriptor needs to issue a STOP command to the card. Multiple blocks can also be transferred with a single DMA descriptor. After each block of data has been transferred, the SSP sends/receives the CRC and checks the CRC or the CRC token. If the CRC is okay, then the SSP signals the DMA that it is done. The SSP supports transferring multiple SD/MMC blocks per DMA descriptor. The SSP state machine needs to know the number of blocks and the size of a block. When HW_SSP_CMD0_BLOCK_COUNT is non-zero, the actual block size is: 0x1 shiftleft BLOCK_SIZE i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-13 Synchronous Serial Ports (SSP) For example, setting a value of 9 will result in a block size of 512 bytes. When BLOCK_COUNT is 0, BLOCK_SIZE is ignored and the bit field HW_SSP_CTRL0_XFER_COUNT represents the single block size or the number of byte to transfer. This must satisfy the equation: HW_SSP_CTRL0_XFER_COUNT = (0x1 shiftleft BLOCK_SIZE) x (BLOCK_COUNT+1) for BLOCK_COUNT greater than 0. 21.8.2.2 SD/MMC Block Transfer CRC Protection All block data transferred over the data bus is protected by CRC16. For reads, the SSP calculates the CRC of incoming data and compares it to the CRC16 reference that is provided by the card at the end of the block. If a CRC mismatch occurs, then the block asserts the DATA_CRC_ERR status flag. If DATA_CRC_IRQ_EN is set, then a CPU IRQ is asserted. For block write operations, the card determines if a CRC error has occurred. After the SSP has sent a block of data, it transmits the reference CRC16. The card compares that to its calculated CRC16. The card then sends a CRC status token on the DATA bus. It sends a positive status (`010') if the transfer was good, and a negative status (`101') if the CRC16 did not match. If the SSP receives a CRC bad token, it sets the DATA_CRC_ERROR in the HW_SSP_STATUS register, and then it indicates it to the CPU if DATA_CRC_IRQ_EN is set. 21.8.3 SDIO Interrupts The SSP supports SDIO interrupts. When the SSP is in SD/MMC mode and the SDIO_IRQ bit in the HW_SSP_CTRL0 register is set, the SSP looks for interrupts on DATA1 during the valid IRQ periods. The valid IRQ periods are defined in the SDIO specification. If the card asserts an interrupt and SDIO_IRQ_EN is set, then the SSP sets the SDIO_IRQ status bit and asserts a CPU IRQ. Other than detecting when card IRQs are valid, the SDIO IRQ function operates independently from the rest of the SSP. After the CPU receives an IRQ, it should monitor the SSP and DMA status to determine when it should send commands to the SDIO card to handle the interrupt. 21.8.4 SD/MMC Mode Error Handling There are several errors that can occur during SD/MMC operation. These errors can be caused by normal unexpected events, such as having a card removed or unusual events such as a card failure. The detected error cases are listed below. Please note that in all cases below, a CPU IRQ is only asserted if DATA_CRC_IRQ_EN is set in HW_SSP_CTRL1 register. * Data Receive CRC Error--Detected by the SSP after a block receive. If this occurs, the SSP will not indicate to the DMA that the transfer is complete. It will set the DATA_CRC_ERR status flag and assert a CPU IRQ. The ISR should reset the SSP DMA channel and instruct the DMA to re-try the block read operation. i.MX23 Applications Processor Reference Manual, Rev. 1 21-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) * Data Transmit CRC Error--Transmit CRC error token is received from the SD/MMC card on the DAT line after a block transmit. If this occurs, the SSP will not indicate to the DMA that the transfer is complete. It will set the DATA_CRC_ERR status flag and assert a CPU IRQ. The ISR should reset the SSP DMA channel and instruct the DMA to re-try the block write operation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-15 Synchronous Serial Ports (SSP) S D /M M C B lo c k R e a d E x a m p le D M A P IO cy cle : S D /M M C m ode R ea d M o de X F E R _ C O U N T = 51 2 W rite the B LO C K _R E A D c om m an d to S D C T R L x . D M A se ts S S P R un b it. S D /M M C B lo ck W rite E x a m p le D M A P IO cyc le : S D /M M C m o de W rite M od e X F E R _ C O U N T = 51 2 W rite the B L O C K _ W R IT E co m m a nd to S D C T R Lx . D M A sets S S P R un b it. S S P s en ds ou t th e M M C B lo ck R ea d C o m m and an d be gin s lo oking a t the D A T lin e for a S ta rt B it. A fte r th e B lock R ea d c om m an d is se nt, S S P loo ks at the C M D lin e fo r a R es po ns e . S S P se nd s o ut the M M C B lo ck W rite C om m an d an d b eg in s loo kin g at the D A T line fo r B u sy C on ditio n. S S P w ill sta rt issu in g D M A req ue sts to fill the tra nsm it F IF O . A fter the B lo ck W rite co m m an d is se nt, S S P lo ok s at th e C M D lin e for a R e sp on se . W h en the re sp on se is s en t b y the M M C c ard, th e S S P w ill plac e the res po nse in the R E S P reg ister. T he S S P w ill che ck the C R C 7 o f th e re spo ns e p ac ke t a ga in st th e rec eived C R C 7. If the re is a n erro r, it w ill as se rt a C P U IR Q . W h en th e re sp on se is se nt b y the M M C c ard, the S S P w ill p la ce th e re sp on se in the R E S P re gister. T he S S P w ill c he ck th e C R C 7 o f th e res po ns e pa ck et ag ains t the rec eived C R C 7. If the re is a n e rror, it w ill as sert a C P U IR Q . W h en th e D ata is rea dy , the M M C w ill s en d the start bit a nd the S S P w ill pu t th e d ata into th e rec eive F IF O an d s ta rt as se rting D M A requ es t. T he rec eiv ed d ata w ill als o be ch ec ke d fo r C R C 16 . If th ere is a C R C e rror, the S S P w ill as se rt a C P U IR Q . W hen the D ata lin e is no lon ge r bu sy , the S S P w ill start sen ding d ata . T h e tra ns m itted d ata w ill als o ha ve C R C 16 ca lc ula te d and tra ns m itted a fte r th e d ata. If the ca rd ind ica te s a C R C e rro r, th e S S P w ill a sse rt a C P U IR Q . A fte r the b lo ck ha s be en rea d an d th e C R C che ck ed , th e S S P w ill ind ic ate to th e D M A tha t it is do ne . T he D M A ca n the n iss ue a n ew co m m an d s eq ue nc e , o r tell the C P U tha t it is d one. A fte r the b lo ck ha s bee n se nt a nd th e C R C c he ck ed , th e S S P w ill ind ica te to the D M A th at it is d on e . T he D M A ca n the n iss ue a ne w c om m an d se qu en ce or tell th e C P U tha t it is do ne. Figure 21-11. SD/MMC Block Transfer Flowchart i.MX23 Applications Processor Reference Manual, Rev. 1 21-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) * * * * Data Time-Out Error--The SSP TIMEOUT counter is used to detect a time-out condition during data write or read operations. The time-out counts any time that the SSP is waiting on a busy DAT bus. For read operations, the DAT line(s) indicate busy before the card sends the start bit. For write operations, the DAT line(s) may indicate busy after the block has been sent to the card. If the time-out counter expires before the DAT line(s) become ready, the SSP stops any DMA requests, sets the DATA_TIMEOUT status flag, and asserts a CPU IRQ. The ISR should check the status register to see that a data time-out has occurred. It can then reset the DMA channel and SSP to re-try the operation. DMA Overflow/Underflow--The SSP should stop SCK if the FIFO is full or the FIFO is empty during data transfer. So, a DMA underflow or overflow should not occur. However, if it does due to some unforeseen problem, the FIFO_OVRFLW or FIFO_UNDRFLW status bit is set in the SSP Status Register and asserts a CPU IRQ. Command Response Error--The SD/MMC card returns an R1 status response after most commands. The SSP can compare the R1 response against a mask/reference pair. If any of the enabled bits are set, then an error has occurred. The SSP stops requesting any DMAs, sets the RESP_ERR status flag, and asserts a CPU IRQ. The CPU can read the SSP Status Register to see the RESP_ERR flag and read the HW_SSP_SDRESP0 register to get the actual response from the SD/MMC card. That response contains the specific error information. Once the error is understood, the CPU can reset the DMA channel and SSP and re-try the operation or take some other action to recover or inform the user of a non-recoverable error. Command Response Time-Out--If an expected response is not received within 64 SCK cycles, then the command response has timed out. If this occurs, the SSP stops any DMA requests, stops transferring data to the card, sets the RESP_TIME-OUT status flag, and asserts the RESP_TIME-OUT_IRQ. The ISR should read the status register to find that a command response time-out has occurred. It can then decide to reset the DMA channel and SSP and re-try the operation. 21.8.5 * * SD/MMC Clock Control * * * When SD/MMC block is idle, the serial clock (SCK) toggling will be based on the value of CONT_CLKING_EN and SLOW_CLKING_EN. See HW_SSP_CMD0 register description. SCK runs any time that RUN is set and a data or command is active or pending. If a command has been sent and a response is expected, then SCK continues to run until the response is received. If a data operation is active or if the DAT line is busy, then SCK runs. If CONT_CLKING_EN=0, SCK stops running if received command response status R1 indicates an error. If CONT_CLKING_EN=0, SCK stops running if a data operation has timed out or a CRC error has occurred. If CONT_CLKING_EN=0, SCK stops running after all pending commands and data operations have completed. SCK restarts when a new command or data operation has been requested. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-17 Synchronous Serial Ports (SSP) 21.9 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. 21.10 Programmable Registers The following registers provide control for programmable elements of the SSP1 port. An identical set of registers exists for the SSP2 port, beginning at 0x8003_4000. Note that the register descriptions for SSP2 are not duplicated in this section. 21.10.1 SSP Control Register 0 Description SSP Control Register 0 HW_SSP_CTRL0 HW_SSP_CTRL0_SET HW_SSP_CTRL0_CLR HW_SSP_CTRL0_TOG Table 21-8. HW_SSP_CTRL0 3 1 3 0 2 9 2 8 SDIO_IRQ_CHECK 0x000 0x004 0x008 0x00C 2 7 2 6 IGNORE_CRC 2 5 2 4 DATA_XFER 2 3 BUS_WIDTH 2 2 2 1 WAIT_FOR_IRQ 2 0 WAIT_FOR_CMD 1 9 LONG_RESP 1 8 CHECK_RESP 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 XFER_COUNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 GET_RESP LOCK_CS CLKGATE Table 21-9. HW_SSP_CTRL0 Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION SSP Reset - 0: SSP is not Reset. 1: SSP Held in Reset. After Reset, all registers are returned to their reset state. This will not work if the CLKGATE bit is already set to '1'. CLKGATE must be cleared to '0' before issuing a soft reset. Also the SSPCLK must be running for this to work properly. Gate SSP Clocks - 0: SSP Clocks not gated. 1: SSP Clocks are gated. Set this to save power while the SSP is not actively being used. Configuration state is kept while the clock is gated. 30 CLKGATE RW 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 21-18 Preliminary--Subject to Change Without Notice ENABLE SFTRST READ RUN Freescale Semiconductor Synchronous Serial Ports (SSP) Table 21-9. HW_SSP_CTRL0 Bit Field Descriptions BITS 29 RUN LABEL RW RESET RW 0x0 DEFINITION SSP Run. 0: SSP is not running. 1: SSP is running. Automatically set during DMA operation. In SD/MMC mode: SDIO IRQ: 1= Enable checking for SDIO Card IRQ. In CE_ATA mode: 1= Wait for CCS (Command Completion Signal). 0= ignore CCS. In CE_ATA mode this bit must not be set to 1 if LOCK_CS (Disable CCS) is set to 1; i.e. both bit cannot be set simultaneously. In SPI mode: This affects the SSn output. When set to 1, SSn will be asserted throughout the current command. SSn will remain asserted after the command if IGNORE_CRC = 0. SSn will deassert at the end of the next command that has IGNORE_CRC = 1. In SD/MMC mode: 0= Look for a CRC status token from the card on DATA0 after a block write. 1= Ignore the CRC status response on DATA0 after a write operation. Note that the SD/MMC function should be used when performing MMC BUSTEST_W operation. In CE_ATA mode: 1= Disable/Cancel CCS (Command Completion Signal) from card. In CE_ATA mode, if this bit is set then the DATA_XFER bit must also be set. Ignore CRC - In SD/MMC mode: Ignores the Response CRC when set to 1. In SPI/SSI modes: When set to 1, deassert the chip select (SSn) pin after the command is executed. Read Mode - When this and DATA_XFER are set, the SSP will read data from the device. If this is not set, then the SSP will write data to the device. Data Transfer Mode - When set, transfer XFER_COUNT bytes of data. When not set, the SSP will not transfer any data (command or Wait for IRQ only). Data Bus Width - SD/MMC mode supports all widths. SSI mode supports only 1-bit bus width. In SPI mode 1, 2, and 4-bit bus widths are supported. In SPI mode the Data Bus Width field is redefined: 0 means 1-bit; 1 means 2-bit; 2 means 4-bit. ONE_BIT = 0x0 SD/MMC data bus is 1-bit wide FOUR_BIT = 0x1 SD/MMC data bus is 4-bits wide EIGHT_BIT = 0x2 SD/MMC data bus is 8-bits wide 28 SDIO_IRQ_CHECK RW 0x0 27 LOCK_CS RW 0x0 26 IGNORE_CRC RW 0x0 25 READ RW 0x0 24 DATA_XFER RW 0x0 23:22 BUS_WIDTH RW 0x0 21 WAIT_FOR_IRQ RW 0x0 In SD/MMC mode this signal means wait for MMC ready before sending command. (MMC is busy when databit0 is low.) In SPI/SSI mode this bit and WAIT_FOR_CMD bit select which SSn output to assert: (WAIT_FOR_IRQ,WAIT_FOR_CMD) = b00: SSn0 will assert during access (SSn2, SSn1 inactive); b01: SSn1 will assert during access (SSn2, SSn0 inactive); b10: SSn2 will assert during access (SSn1, SSn0 inactive). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-19 Synchronous Serial Ports (SSP) Table 21-9. HW_SSP_CTRL0 Bit Field Descriptions BITS LABEL 20 WAIT_FOR_CMD RW RESET RW 0x0 DEFINITION Wait for Data Done - SD/MMC - 0: Send commands immediately after they are written. 1: Wait to send command until after the CRC-checking phase of a data transfer has completed successfully. This delays sending a command until a block of data is transferred. This can be used to send a STOP command during an SD/MMC multi-block read. In SD/MMC mode this signal means wait for MMC ready before sending command. (MMC is busy when databit0 is low.) In SPI/SSI mode this bit and WAIT_FOR_IRQ bit select which SSn output to assert: (WAIT_FOR_IRQ,WAIT_FOR_CMD) = b00: SSn0 will assert during access (SSn2, SSn1 inactive); b01: SSn1 will assert during access (SSn2, SSn0 inactive); b10: SSn2 will assert during access (SSn1, SSn0 inactive). Get Long Response - SD/MMC - 0: The card response will be short. 1: The card will provide a 136-bit response. Only valid if GET_RESP is set. A long response cannot be checked using CHECK_RESP. Check Response - SD/MMC. If this bit is set, the SSP will XOR the result with the REFERENCE field and then mask the incoming status word with the MASK field in the COMPARE register. If there is a mismatch, then the SSP will set the RESP_ERR status bit, and, if enabled, the RESP_ERR_IRQ. This should not be used with LONG_RESP. Get Response - SD/MMC - 0: Do not wait for a response from the card. 1: This command should receive a response from the card. Command Transmit Enable - SD/MMC - 0: Commands are not enabled. 1: Data in Command registers will be sent. This is normally enabled in SD/MMC Mode. Number of words to transfer, as referenced in WORD_LENGTH in HW_SSP_CTRL1. The run bit and DMA request will clear after this many words have been transferred. In SD/MMC Mode, this should be a multiple of the block size. 19 LONG_RESP RW 0x0 18 CHECK_RESP RW 0x0 17 GET_RESP RW 0x0 16 ENABLE RW 0x0 15:0 XFER_COUNT RW 0x1 DESCRIPTION: This is the most frequently changed fields. EXAMPLE: No Example. 21.10.2 SD/MMC Command Register 0 Description SD/MMC Command Index and control register HW_SSP_CMD0 HW_SSP_CMD0_SET 0x010 0x014 i.MX23 Applications Processor Reference Manual, Rev. 1 21-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) HW_SSP_CMD0_CLR HW_SSP_CMD0_TOG Table 21-10. HW_SSP_CMD0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 SLOW_CLKING_EN 0x018 0x01C 2 1 CONT_CLKING_EN 2 0 APPEND_8CYC 1 9 1 8 BLOCK_SIZE 1 7 1 6 1 5 1 4 1 3 1 2 BLOCK_COUNT 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSVD0 Table 21-11. HW_SSP_CMD0 Bit Field Descriptions BITS LABEL 31:23 RSVD0 SLOW_CLKING_EN 22 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data. This field is ignored when CONT_CLKING is zero. Set this bit to enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active. This is used in SD/MMC/CE_ATA mode. When set to zero, SCK is idle when no transfer is taking place. Append 8 SCK cycles. This is used in SD/MMC/CE_ATA mode. When set to one, the SCK will toggle for 8 more cycles before going idle. When set to zero SCK will toggle up to 4 cycles before going idle. This should be set to one at the end of a single or multiple block transfer. SD/MMC block size encode. When BLOCK_COUNT is nonzero, the actual block size is (1 shiftleft BLOCK_SIZE). For example setting a value of 9 will result in a block size of 512 bytes. When BLOCK_COUNT is zero, BLOCK_SIZE is ignored and HW_SSP_CTRL0_XFER_COUNT represents the single block size or the number of byte to transfer. This must satisfy equation HW_SSP_CTRL0_XFER_COUNT = (1 shiftleft BLOCK_SIZE) x (BLOCK_COUNT+1) for BLOCK_COUNT greater than zero. 21 CONT_CLKING_EN RW 0x0 20 APPEND_8CYC RW 0x0 19:16 BLOCK_SIZE RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice CMD 21-21 Synchronous Serial Ports (SSP) Table 21-11. HW_SSP_CMD0 Bit Field Descriptions BITS LABEL 15:8 BLOCK_COUNT RW RESET RW 0x0 DEFINITION SD/MMC block count. This value one less than the number of blocks to transfer. For example setting a value of one will transfer two blocks. This must satisfy equation HW_SSP_CTRL0_XFER_COUNT = (1 shiftleft BLOCK_SIZE) x (BLOCK_COUNT+1) for BLOCK_COUNT greater than zero. This is also SPI/SSI control word[15:8] for RX transfers. i.MX23 Applications Processor Reference Manual, Rev. 1 21-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) Table 21-11. HW_SSP_CMD0 Bit Field Descriptions BITS 7:0 CMD LABEL RW RESET RW 0x0 DEFINITION SD/MMC Command Index (uses 5:0) to be sent to card. This is also SPI/SSI control word[7:0] for RX transfers. MMC_GO_IDLE_STATE = 0x00 MMC_SEND_OP_COND = 0x01 MMC_ALL_SEND_CID = 0x02 MMC_SET_RELATIVE_ADDR = 0x03 MMC_SET_DSR = 0x04 MMC_RESERVED_5 = 0x05 MMC_SWITCH = 0x06 MMC_SELECT_DESELECT_CARD = 0x07 MMC_SEND_EXT_CSD = 0x08 MMC_SEND_CSD = 0x09 MMC_SEND_CID = 0x0A MMC_READ_DAT_UNTIL_STOP = 0x0B MMC_STOP_TRANSMISSION = 0x0C MMC_SEND_STATUS = 0x0D MMC_BUSTEST_R = 0x0E MMC_GO_INACTIVE_STATE = 0x0F MMC_SET_BLOCKLEN = 0x10 MMC_READ_SINGLE_BLOCK = 0x11 MMC_READ_MULTIPLE_BLOCK = 0x12 MMC_BUSTEST_W = 0x13 MMC_WRITE_DAT_UNTIL_STOP = 0x14 MMC_SET_BLOCK_COUNT = 0x17 MMC_WRITE_BLOCK = 0x18 MMC_WRITE_MULTIPLE_BLOCK = 0x19 MMC_PROGRAM_CID = 0x1A MMC_PROGRAM_CSD = 0x1B MMC_SET_WRITE_PROT = 0x1C MMC_CLR_WRITE_PROT = 0x1D MMC_SEND_WRITE_PROT = 0x1E MMC_ERASE_GROUP_START = 0x23 MMC_ERASE_GROUP_END = 0x24 MMC_ERASE = 0x26 MMC_FAST_IO = 0x27 MMC_GO_IRQ_STATE = 0x28 MMC_LOCK_UNLOCK = 0x2A MMC_APP_CMD = 0x37 MMC_GEN_CMD = 0x38 SD_GO_IDLE_STATE = 0x00 SD_ALL_SEND_CID = 0x02 SD_SEND_RELATIVE_ADDR = 0x03 SD_SET_DSR = 0x04 SD_IO_SEND_OP_COND = 0x05 SD_SELECT_DESELECT_CARD = 0x07 SD_SEND_CSD = 0x09 SD_SEND_CID = 0x0A SD_STOP_TRANSMISSION = 0x0C SD_SEND_STATUS = 0x0D SD_GO_INACTIVE_STATE = 0x0F SD_SET_BLOCKLEN = 0x10 SD_READ_SINGLE_BLOCK = 0x11 SD_READ_MULTIPLE_BLOCK = 0x12 SD_WRITE_BLOCK = 0x18 SD_WRITE_MULTIPLE_BLOCK = 0x19 SD_PROGRAM_CSD = 0x1B SD_SET_WRITE_PROT = 0x1C SD_CLR_WRITE_PROT = 0x1D SD_SEND_WRITE_PROT = 0x1E SD_ERASE_WR_BLK_START = 0x20 SD_ERASE_WR_BLK_END = 0x21 SD_ERASE_GROUP_START = 0x23 SD_ERASE_GROUP_END = 0x24 SD_ERASE = 0x26 SD_LOCK_UNLOCK = 0x2A SD_IO_RW_DIRECT = 0x34 SD_IO_RW_EXTENDED = 0x35 SD_APP_CMD = 0x37 SD_GEN_CMD = 0x38 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-23 Synchronous Serial Ports (SSP) DESCRIPTION: This is the command code for the SD/MMC devices. See device specification for details. EXAMPLE: No Example. 21.10.3 SD/MMC Command Register 1 Description SD/MMC Command Argument Register HW_SSP_CMD1 Table 21-12. HW_SSP_CMD1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x020 CMD_ARG Table 21-13. HW_SSP_CMD1 Bit Field Descriptions BITS LABEL 31:0 CMD_ARG RW RESET RW 0x0 DEFINITION SD/MMC Command Argument. See SSP_CTRL0_DATA_XFER bit description. DESCRIPTION: This is the SD/MMC argument. See SD/MMC specification for details. EXAMPLE: No Example. 21.10.4 SD/MMC Compare Reference Description MMC/SD Status response reference. HW_SSP_COMPREF Table 21-14. HW_SSP_COMPREF 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x030 REFERENCE Table 21-15. HW_SSP_COMPREF Bit Field Descriptions BITS LABEL 31:0 REFERENCE RW RESET RW 0x0 DEFINITION SD/MMC Compare mode reference. If CHECK_RESP is set, the response will be XOR'd with this value. The results will be masked by the MASK bitfield. If there are any differences, then the SSP will indicate an error state to the DMA. i.MX23 Applications Processor Reference Manual, Rev. 1 21-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) DESCRIPTION: SD/MMC status can be compared with a reference value. EXAMPLE: No Example. 21.10.5 SD/MMC compare mask Description MMC/SD Status response mask . HW_SSP_COMPMASK Table 21-16. HW_SSP_COMPMASK 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x040 MASK Table 21-17. HW_SSP_COMPMASK Bit Field Descriptions BITS 31:0 MASK LABEL RW RESET RW 0x0 DEFINITION SD/MMC Compare mode Mask. If CHECK_RESP is set, the response is compared to REFERENCE, and the results are masked by this bitfield. DESCRIPTION: A mask allows the comparison of one or more bit fields in the reference value. EXAMPLE: No Example. 21.10.6 SSP Timing Register Description SSP Timing Config Register HW_SSP_TIMING Table 21-18. HW_SSP_TIMING 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 TIMEOUT 0x050 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 CLOCK_DIVIDE 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 CLOCK_RATE 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-25 Synchronous Serial Ports (SSP) Table 21-19. HW_SSP_TIMING Bit Field Descriptions BITS LABEL 31:16 TIMEOUT RW RESET RW 0x0 DEFINITION Timeout counter. This specifies the number of SCK cycles multiplied by 4096, to wait before asserting the DATA TIMEOUT IRQ. It is used during timeout is used for data transfer/write operations in SD/MMC mode. Clock Pre-Divider. CLOCK_DIVIDE must be an even value from 2 to 254. Serial Clock Rate. The value CLOCK_RATE is used to generate the transmit and receive bit rate of the SSP. The bit rate is SSPCLK / (CLOCK_DIVIDE x (1+ CLOCK_RATE)). CLOCK_RATE is a value from 0 to 255. 15:8 7:0 CLOCK_DIVIDE CLOCK_RATE RW 0x0 RW 0x0 DESCRIPTION: The Timeout field and the clock dividers are contained in this register. EXAMPLE: No Example. 21.10.7 SSP Control Register 1 Description Control Register 1. HW_SSP_CTRL1 HW_SSP_CTRL1_SET HW_SSP_CTRL1_CLR HW_SSP_CTRL1_TOG Table 21-20. HW_SSP_CTRL1 3 1 3 0 2 9 2 8 RESP_ERR_IRQ_EN 0x060 0x064 0x068 0x06C 2 7 RESP_TIMEOUT_IRQ 2 6 RESP_TIMEOUT_IRQ_EN 2 5 DATA_TIMEOUT_IRQ 2 4 DATA_TIMEOUT_IRQ_EN 2 3 2 2 DATA_CRC_IRQ_EN 2 1 FIFO_UNDERRUN_IRQ 2 0 FIFO_UNDERRUN_EN 1 9 1 8 1 7 RECV_TIMEOUT_IRQ 1 6 RECV_TIMEOUT_IRQ_EN 1 5 FIFO_OVERRUN_IRQ 1 4 FIFO_OVERRUN_IRQ_EN 1 3 1 2 1 1 SLAVE_OUT_DISABLE 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 WORD_LENGTH RESP_ERR_IRQ DATA_CRC_IRQ DMA_ENABLE SLAVE_MODE SDIO_IRQ_EN Table 21-21. HW_SSP_CTRL1 Bit Field Descriptions BITS LABEL 31 SDIO_IRQ RW RESET RW 0x0 DEFINITION If this is set, an SDIO card interrupt has occurred and an IRQ, if enabled, has been sent to the ICOLL. Write a one to the SCT Clear address to reset this interrupt request status bit. SDIO Card Interrupt IRQ Enable. 0: SDIO card IRQs masked. 1: SDIO card IRQs will be sent to the ICOLL. 30 SDIO_IRQ_EN RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 21-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor SSP_MODE POLARITY SDIO_IRQ PHASE RSVD3 RSVD2 RSVD1 Synchronous Serial Ports (SSP) Table 21-21. HW_SSP_CTRL1 Bit Field Descriptions BITS LABEL 29 RESP_ERR_IRQ RW RESET RW 0x0 DEFINITION When the CHECK_RESP bit in CTRL0 is set, if an unexpected response (or response CRC) is received from the card, this bit will be set. Write a one to the SCT Clear address to reset this interrupt request status bit. SD/MMC Card Error IRQ Enable. 0: Card Error IRQ is Masked. 1: Card Error IRQ is enabled. When set to 1, if an SD/MMC card indicates a card error (bit is set in both the SD/MMC Error Mask and R1 Card Status response), then a CPU IRQ will be asserted. If this is set, a command response timeout has occurred, and an IRQ, if enabled, has been sent to the IRQ Collector. This is used for SD/MMC response timeout. Write a one to the SCT Clear address to reset this interrupt request status bit. SD/MMC Card Command Respone Timeout Error IRQ Enable. 0: Response Timeout IRQ is Masked. 1: Response Timeout IRQ is enabled. When set to 1, if an SD/MMC card does not respond to a command within 64 cycles then this CPU IRQ will be asserted. Data Transmit/Receive Timeout Error IRQ. If the timeout counter expires before the DAT bus is ready for write or sends read data, then a data timeout has occurred. Only Valid For SD/MMC Mode. Write a one to the SCT Clear address to reset this interrupt request status bit. Data Transmit/Receive Timeout Error IRQ Enable. If the timeout counter expires before the DAT bus is ready for write or sends read data, then a data timeout has occurred. Only Valid For SD/MMC Mode. Data Transmit/Receive CRC Error IRQ. Only valid for SD/MMC Mode. Write a one to the SCT Clear address to reset this interrupt request status bit. Data Transmit/Receive CRC Error IRQ Enable. Only valid for SD/MMC Mode. FIFO Underrun Interrupt. If the FIFO is read when it is empty this bit will be set. Write a one to the SCT Clear address to reset this interrupt request status bit. FIFO Underrun IRQ Enable. If set and the FIFO_UNDERRUN_IRQ bit is asserted, an IRQ will be generated. Program this field to 0x0. Program this field to 0x0. Data Timeout Interrupt. If enabled and the FIFO is not empty, an IRQ will be generated if 128 HCLK Cycles Pass before the DATA register is read. This is supported for SPI modes only (Modes 0,1,2). Write a one to the SCT Clear address to reset this interrupt request status bit. Receive Timeout. If set and the FIFO is not empty, an IRQ will be generated if 128 HCLK Cycles Pass before the DATA register is read. 28 RESP_ERR_IRQ_EN RW 0x0 27 RESP_TIMEOUT_IRQ RW 0x0 26 RESP_TIMEOUT_IRQ_EN RW 0x0 25 DATA_TIMEOUT_IRQ RW 0x0 24 DATA_TIMEOUT_IRQ_EN RW 0x0 23 DATA_CRC_IRQ RW 0x0 22 21 DATA_CRC_IRQ_EN FIFO_UNDERRUN_IRQ RW 0x0 RW 0x0 20 FIFO_UNDERRUN_EN RW 0x0 19 18 17 RSVD3 RSVD2 RECV_TIMEOUT_IRQ RW 0x0 RW 0x0 RW 0x0 16 RECV_TIMEOUT_IRQ_EN RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-27 Synchronous Serial Ports (SSP) Table 21-21. HW_SSP_CTRL1 Bit Field Descriptions BITS LABEL 15 FIFO_OVERRUN_IRQ RW RESET RW 0x0 DEFINITION FIFO Overrun Interrupt. Indicated that the FIFO has been written to while full. Write a one to the SCT Clear address to reset this interrupt request status bit. FIFO Overrun Interrupt Enable. If set, an IRQ will be generated if the FIFO is written to while full. DMA Enable. This signal enables DMA request and DMA Command End signals to be asserted. Program this field to 0x0. Slave Output Disable. 0: SSP can drive MISO in Slave Mode. 1: SSP does not drive MISO in slave mode. Serial Clock Phase. For SPI mode only. Serial Clock Polarity. In SD/MMC mode, 0: Command and TX data change after rising edge of SCK, 1: Command and TX data change after falling edge of SCK. In SPI mode, 0: Steady-state '0' on SCK when data is not being transferred. 1: Steady-state '1' on SCK when data is not being transferred. Slave Mode. 0: SSP is in Master Mode. 1: SSP is in Slave Mode. Set to zero for SD/MMC mode. Word Length in bits per word. 0x0 to 0x2 are Reserved and Undefined. 0x3 is 4-bits per word...0xF is 16-bits per word. Always use 8 bits per word in SD/MMC Mode. RESERVED0 = 0x0 0x0 is Reserved and Undefined RESERVED1 = 0x1 0x1 is Reserved and Undefined RESERVED2 = 0x2 0x2 is Reserved and Undefined FOUR_BITS = 0x3 use 4-bits per word EIGHT_BITS = 0x7 use 8-bits per word SIXTEEN_BITS = 0xF use 16-bits per word 14 13 12 11 10 9 FIFO_OVERRUN_IRQ_EN DMA_ENABLE RSVD1 SLAVE_OUT_DISABLE PHASE POLARITY RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 8 7:4 SLAVE_MODE WORD_LENGTH RW 0x0 RW 0x8 3:0 SSP_MODE RW 0x0 Operating Mode. 0x0 = Motorola and Winbond SPI Mode, 0x1 = TI syncronous serial mode, 0x3 = SD/MMC Card, All other values are undefined. Before changing ssp_mode, a softreset must be issued to clear the FIFO. SPI = 0x0 Motorola and Winbond SPI mode SSI = 0x1 Texas Instruments SSI mode SD_MMC = 0x3 SD/MMC mode DESCRIPTION: This contains interrupt status and enable fields. EXAMPLE: No Example. 21.10.8 SSP Data Register Description The HW_SSP_DATA register allows user access to the SSP FIFO. HW_SSP_DATA 0x070 i.MX23 Applications Processor Reference Manual, Rev. 1 21-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) Table 21-22. HW_SSP_DATA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DATA Table 21-23. HW_SSP_DATA Bit Field Descriptions BITS 31:0 DATA LABEL RW RESET RW 0x0 DEFINITION Data Register. Holds one, two, three, or four words, depending on the WORD_LENGTH. If WORD_LENGTH is not 8, 16, or 32, the words are padded to those lengths. Data is right justified. When the run bit is set reads will cause the FIFO read pointer to increment and writes will cause the FIFO write pointer to increment. DESCRIPTION: This register is the gateway for data transfer to and from the attached device. EXAMPLE: No Example. 21.10.9 SD/MMC Card Response Register 0 Description SD/SDIO/MMC Card Response Register 0. HW_SSP_SDRESP0 Table 21-24. HW_SSP_SDRESP0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x080 RESP0 Table 21-25. HW_SSP_SDRESP0 Bit Field Descriptions BITS 31:0 RESP0 LABEL RW RESET RO 0x0 DEFINITION SD/MMC Response Status Bits[31:0]. See SSP_CTRL0_DATA_XFER bit description. DESCRIPTION: SD/SDIO/MMC Card Response Register 0. EXAMPLE: No Example. 21.10.10 SD/MMC Card Response Register 1 Description SD/SDIO/MMC Card Response Register 1. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-29 Synchronous Serial Ports (SSP) HW_SSP_SDRESP1 Table 21-26. HW_SSP_SDRESP1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0x090 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RESP1 Table 21-27. HW_SSP_SDRESP1 Bit Field Descriptions BITS 31:0 RESP1 LABEL RW RESET RO 0x0 DEFINITION SD/MMC Long Response [63:32] DESCRIPTION: SD/SDIO/MMC/CE_ATA Card Response Register 1. EXAMPLE: No Example. 21.10.11 SD/MMC Card Response Register 2 Description SD/SDIO/MMC/CE_ATA Card Response Register 2. HW_SSP_SDRESP2 Table 21-28. HW_SSP_SDRESP2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0A0 RESP2 Table 21-29. HW_SSP_SDRESP2 Bit Field Descriptions BITS 31:0 RESP2 LABEL RW RESET RO 0x0 DEFINITION SD/MMC Long Response [95:64] DESCRIPTION: SD/SDIO/MMC/CE_ATA Card Response Register 2. EXAMPLE: No Example. 21.10.12 SD/MMC Card Response Register 3 Description SD/SDIO/MMC/CE_ATA Card Response Register 3. HW_SSP_SDRESP3 0x0B0 i.MX23 Applications Processor Reference Manual, Rev. 1 21-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) Table 21-30. HW_SSP_SDRESP3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RESP3 Table 21-31. HW_SSP_SDRESP3 Bit Field Descriptions BITS 31:0 RESP3 LABEL RW RESET RO 0x0 DEFINITION SD/MMC Long Response [127:96] DESCRIPTION: SD/SDIO/MMC/CE_ATA Card Response Register 3. EXAMPLE: No Example. 21.10.13 SSP Status Register Description SSP Read Only Status Registers. HW_SSP_STATUS Table 21-32. HW_SSP_STATUS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 RESP_CRC_ERR 0x0C0 1 5 1 4 RESP_TIMEOUT 1 3 DATA_CRC_ERR 1 2 1 1 RECV_TIMEOUT_STAT 1 0 0 9 0 8 0 7 0 6 0 5 0 4 FIFO_UNDRFLW 0 3 0 2 0 1 0 0 CARD_DETECT FIFO_OVRFLW SD_PRESENT FIFO_EMPTY DATA_BUSY DMASENSE CMD_BUSY RESP_ERR FIFO_FULL DMATERM SDIO_IRQ PRESENT TIMEOUT DMAREQ DMAEND RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 Table 21-33. HW_SSP_STATUS Bit Field Descriptions BITS LABEL 31 PRESENT RW RESET RO 0x1 DEFINITION SSP Present Bit. 0: SSP is not present in this product. 1: SSP is present. Program this field to 0x1. SD/MMC Controller Present bit. 0: SD/MMC controller is not present in this product. 1: SD/MMC controller is present. Reflects the state of the SSP_DETECT input pin. Reserved Reflects the state of the ssp_dmasense output port. It indicates a DMA error (Timeout or CRC) when asserted high at the end of a DMA command. 30 29 RSVD5 SD_PRESENT RO 0x1 RO 0x1 28 CARD_DETECT 27:22 RSVD4 DMASENSE 21 RO 0x0 RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice BUSY 21-31 Synchronous Serial Ports (SSP) Table 21-33. HW_SSP_STATUS Bit Field Descriptions BITS LABEL 20 DMATERM RW RESET RO 0x0 DEFINITION Reflects the state of the ssp_dmaterm output port. This is a toggle signal. Reflects the state of the ssp_dmareq output port. This is a toggle signal. Reflects the state of the ssp_dmaend output port. This is a toggle signal. SDIO IRQ has been detected. SD/MMC Response failed CRC check. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN. SD/MMC Card Responded to Command with an Error Condition. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN. SD/MMC Card Expected Command Response not received within 64 CLK cycles. This indicates a card error, bad command, or command that failed CRC check. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN. Data CRC Error. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN. SD/MMC - timeout counter expired before data bus was ready. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN. Raw Receive Timeout Status. Indicates that no read has occurred to non-empty receive data FIFO for 128 cycles Program this field to 0x0. FIFO Overflow Interrupt. FIFO FULL Reserved FIFO Empty. FIFO Underflow has occurred. SD/MMC command controller is busy sending a command or receiving a response SD/MMC command controller is busy transferring data. Reserved SSP State Machines are Busy. 19 18 17 16 DMAREQ DMAEND SDIO_IRQ RESP_CRC_ERR RO 0x0 RO 0x0 RO 0x0 RO 0x0 15 RESP_ERR RO 0x0 14 RESP_TIMEOUT RO 0x0 13 12 DATA_CRC_ERR TIMEOUT RO 0x0 RO 0x0 11 RECV_TIMEOUT_STAT RO 0x0 10 9 8 7:6 5 4 3 2 1 0 RSVD3 FIFO_OVRFLW FIFO_FULL RSVD2 FIFO_EMPTY FIFO_UNDRFLW CMD_BUSY DATA_BUSY RSVD1 BUSY RO RO RO RO RO RO RO 0x0 0x0 0x0 0x0 0x1 0x0 0x0 RO 0x0 RO 0x0 RO 0x0 DESCRIPTION: Various SSP status fields are provided in this register. EXAMPLE: No Example. 21.10.14 SSP Debug Register Description SSP Read Only Debug Registers. HW_SSP_DEBUG 0x100 i.MX23 Applications Processor Reference Manual, Rev. 1 21-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Synchronous Serial Ports (SSP) Table 21-34. HW_SSP_DEBUG 3 1 3 0 DATACRC_ERR 2 9 2 8 2 7 DATA_STALL 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 CMD_OE 1 8 1 7 DMA_SM 1 6 1 5 1 4 MMC_SM 1 3 1 2 1 1 CMD_SM 1 0 0 9 SSP_CMD 0 8 SSP_RESP 0 7 0 6 0 5 0 4 SSP_RXD 0 3 0 2 0 1 0 0 DAT_SM Table 21-35. HW_SSP_DEBUG Bit Field Descriptions BITS LABEL 31:28 DATACRC_ERR DATA_STALL 27 26:24 DAT_SM RW RESET RO 0x0 RO 0x0 RO 0x0 DEFINITION Data CRC error MMC mode: FIFO transfer not ready MMC dataxfer state machine DSM_IDLE = 0x0 DSM_WORD = 0x2 DSM_CRC1 = 0x3 DSM_CRC2 = 0x4 DSM_END = 0x5 23:20 RSVD1 RSVD1 RO 0x0 Program this field to 0x0. MSTK_IDLE = 0x0 MSTK_CKON = 0x1 MSTK_BS1 = 0x2 MSTK_TPC = 0x3 MSTK_BS2 = 0x4 MSTK_HDSHK = 0x5 MSTK_BS3 = 0x6 MSTK_RW = 0x7 MSTK_CRC1 = 0x8 MSTK_CRC2 = 0x9 MSTK_BS0 = 0xA MSTK_END1 = 0xB MSTK_END2W = 0xC MSTK_END2R = 0xD MSTK_DONE = 0xE 19 CMD_OE 18:16 DMA_SM RO 0x0 RO 0x0 Enable for SSP_CMD DMA state machine DMA_IDLE = 0x0 DMA_DMAREQ = 0x1 DMA_DMAACK = 0x2 DMA_STALL = 0x3 DMA_BUSY = 0x4 DMA_DONE = 0x5 DMA_COUNT = 0x6 15:12 MMC_SM RO 0x0 MMC_state machine MMC_IDLE = 0x0 MMC_CMD = 0x1 MMC_TRC = 0x2 MMC_RESP = 0x3 MMC_RPRX = 0x4 MMC_TX = 0x5 MMC_CTOK = 0x6 MMC_RX = 0x7 MMC_CCS = 0x8 MMC_PUP = 0x9 MMC_WAIT = 0xA 11:10 CMD_SM RO 0x0 MMC command_state machine CSM_IDLE = 0x0 CSM_INDEX = 0x1 CSM_ARG = 0x2 CSM_CRC = 0x3 9 SSP_CMD RO 0x0 SSP_CMD i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 21-33 Synchronous Serial Ports (SSP) Table 21-35. HW_SSP_DEBUG Bit Field Descriptions BITS LABEL 8 SSP_RESP SSP_RXD 7:0 RW RESET RO 0x0 RO 0x0 DEFINITION SSP_RESP SSP_RXD. DESCRIPTION: Debug Register provide access to State machines. EXAMPLE: No Example. 21.10.15 SSP Version Register Description This register reflects the version number for the SSP. HW_SSP_VERSION Table 21-36. HW_SSP_VERSION 3 1 3 0 2 9 2 8 MAJOR 0x110 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 21-37. HW_SSP_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x03 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x00 RO 0x0000 DESCRIPTION: This register reflects the version number for the SSP. EXAMPLE: No Example. SSP Block v3.0, Revision 2.0 i.MX23 Applications Processor Reference Manual, Rev. 1 21-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 22 Timers and Rotary Decoder This chapter describes the timers and rotary decoder included on the i.MX23. Programmable registers are described in Section 22.4, "Programmable Registers." 22.1 Overview The i.MX23 implements four timers and a rotary decoder, as shown in Figure 22-1. The timers and decoder can take their inputs from any of the pins defined for PWM, rotary encoders, or certain divisions from the 32-kHz clock input. Thus, the PWM pins can be inputs or outputs, depending on the application. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-1 Timers and Rotary Decoder ARM Core SRAM 24-MHz XTAL Osc. AHB AHB Slave AHB Master Divide by n Shared DMA AHB-to-APBX Bridge APBX Master APBX Timer/Rotary Decoder Programmable Registers PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] ROTARY_A ROTARY_B 32-kHz Osc. Timer 0 Timer 1 Timer 2 Timer 3 1/1, 1/ 2, 1/8, 1/16 1/1, 1/ 2, 1/8, 1/16 1/1, 1/ 2, 1/8, 1/16 1/1, 1/ 2, 1/8, 1/16 Rotary Up/Down Counter Timers and Rotary Decoder Figure 22-1. Timers and Rotary Decoder Block Diagram The timer/rotary decoder block is a programmed I/O interface connected to the APBX bus. Recall that the APBX typically runs at a divided clock rate from the 24-MHz crystal clock. Each timer and rotary channel can sample at a rate that is further subdivided from the APBX clock. Each timer can select a different pre-scaler value. 22.2 Timers Each of the four timers consists of a 16-bit fixed count value and a 16-bit free-running count value. In most cases, the free-running count decrements to 0. When it decrements to 0, it sets an interrupt status bit associated with the counter. * * If the RELOAD bit is set to 1, then the fixed count is automatically copied to the free-running counter and the count continues. If the RELOAD bit is not set, the timer stalls when it reaches 0. i.MX23 Applications Processor Reference Manual, Rev. 1 22-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Timers and Rotary Decoder Figure 22-2 shows a detailed view of either Timer 0, Timer 1, or Timer 2. Timer 3 has additional functionality, which is shown in Figure 22-3. Timer I/O ==0 ? 16-Bit Fixed Count 16-Bit Running Count Hold, load, copy Mode Controller ALWAYS TICK PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] ROTARY_A ROTARY_B NEVER TICK Divide by 1, 4, 8, 32 Hold, down, load, copy Edge Tick Detect 32-kHz Input 24-MHz XTAL Osc. Divide APBX clk by n Divide by 1, 2, 4, 8 Gated clk Figure 22-2. Timer 0, Timer 1, or Timer 2 Detail Each timer has an UPDATE bit that controls whether the free-running-counter is loaded at the same time the fixed-count register is written from the CPU. The output of each timer's source select has a polarity control that allows the timer to operate on either edge. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-3 Timers and Rotary Decoder Table 22-1 lists the timer state machine transitions. Table 22-1. Timer State Machine Transitions UPDATE RELOAD 0 0 0 1 RUNNING PIO writes to the fixed-count bit field have no effect on the running count. The value written to the fixed count is used to reload the running count the next time it reaches 0. When the fixed count has been written with a value of 0 and the running count reaches 0, it continuously copies the fixed count value to the running count. Thus, writing a non-zero value to the fixed count register kicks off a continuous count and update operation. The value written to the fixed count bit field is copied, immediately, to the running count, restarting any existing running count operation. When the new running count reaches 0, it freezes. The value written to the fixed count bit field is copied, immediately, to the running count, restarting any existing running count operation. When the new running count reaches 0, it is reloaded from the value in the fixed count bit field, thus running continuously using the newly supplied fixed count. 1 1 0 1 When generating a periodic timer interrupt using the RELOAD bit, the user must compute the proper fixed-count value (count_value) based on clock speeds and clock divider settings. Note that, in this case, the actual value written to the FIXED_COUNT register field should be count_value - 1. For one-shot interrupts (RELOAD bit not set), the value written should be count_value. Any timer interrupt can be programmed as an FIQ or as a regular IRQ. See Chapter 5, "Interrupt Collector," for programming details. For proper detection of the input source signal, it should be much slower than the pre-scaled APBX clock (no greater than one-third the frequency of the pre-scaled APBX clock). Selecting the ALWAYS tick causes the timer to decrement continuously at the rate established by the pre-scaled APBX clock. The NEVER TICK selection causes the timer to stall. Setting the fixed-count to 0xFFFF and setting the RELOAD bit causes the timer to operate in a continuous-count 65536 count mode. The state of the 16-bit free-running count can be read by the CPU for each timer. 22.2.1 Using External Signals as Inputs External signals can be used as inputs to the block. They can be used as either the test signal or sampling input signals (duty cycle or normal timer mode). This can be accomplished by using the rotary input pins or any unused PWM pins. If PWM pins are being used for this purpose, conflicts with the PWM or other blocks that could drive the pins as outputs must be avoided. In this case, the PWM pins being used should be programmed as GPIO inputs. (See Chapter 37, "Pin Control and GPIO," for details.) Then, the external signal can be wired to the pin, and the PWM number selected in the appropriate TIMROT registers. 22.2.2 Timer 3 and Duty Cycle Mode Timer 3 can operate in the same modes as Timer 0, Timer 1, and Timer 2. However, it has an additional duty cycle measurement mode. Figure 22-3 shows a detailed view of Timer 3. i.MX23 Applications Processor Reference Manual, Rev. 1 22-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Timers and Rotary Decoder Timer I/O ==0 ? 16-Bit Low Count 16-Bit Fixed count 16-Bit Running Count Hold, load, copy Mode Controller ALWAYS TICK PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] ROTARY_A ROTARY_B NEVER TICK Divide by 1, 4, 8, 32 Hold, down, load, copy Tick Edge Detect LVL 32-kHz Input 24-MHz XTAL Osc. Divide by n APBX clk Divide by 1, 2, 4, 8 Gated clk Figure 22-3. Timer 3 Detail In the duty cycle mode, Timer 3 samples the free-running counter at the rising and falling edges of the input test signal, resetting the free-running counter on the same clock that is sampled. * * On the rising edge of the test signal, the free-running count is copied to the LOW_RUNNING_COUNT bit field of the HW_TIMROT_TIMCOUNT3 register. On the falling edge of the source clock, the free-running count is copied to the HIGH_FIXED_COUNT bit field (as shown in Figure 22-4). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-5 Timers and Rotary Decoder Low Count High Count Input Figure 22-4. Pulse-Width Measurement Mode * * Once duty cycle mode is programmed and the input signal is stable, software should poll the DUTY_VALID bit in the HW_TIMROT_TIMCTRL3 register. This bit is automatically set and cleared by the hardware. When this bit is set, count values in the HW_TIMROT_TIMCOUNT3 register are stable and ready to be read. Refer to the Timer 3 control and status register, HW_TIMROT_TIMCTRL3, where the DUTY_CYCLE bit controls whether HW_TIMROT_TIMCOUNT3 register's LOW_RUNNING_COUNT bit field reads back the running count or the low count of a duty cycle measurement. The DUTY_CYCLE bit also controls whether the HIGH_FIXED_COUNT bit field reads back the fixed-count value used in normal timer operations or the duty cycle high-time measurement. It should be noted that for duty cycle mode to function properly, the timer "tick" source selected (SELECT field of the HW_TIMROT_TIMCTRL3 register) should be an appropriate frequency to sample the test signal. The NEVER_TICK value should never be used in this mode, as it will yield incorrect count results. 22.2.3 Testing Timer 3 Duty Cycle Modes To test the duty cycle modes of Timer 3, select PWM1 as the input. PWM1 can generate waveforms of arbitrary duty cycle suitable for testing the duty cycle measurement capability. 22.3 Rotary Decoder The rotary decoder uses two input selectors and edge detectors, as shown in Figure 22-5. It includes a debounce circuit for each input, as shown in Figure 22-6. This figure shows the debounce circuit for input A, though the circuit is identical for input B. i.MX23 Applications Processor Reference Manual, Rev. 1 22-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Timers and Rotary Decoder Timer I/O Signed 16-Bit Up/Down Count 32-kHz Input Hold, load, inc/dec Mode Controller and Debounce Circuit NEVER TICK PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] ROTARY_A ROTARY_B ROT SELB Edge Detect NEVER TICK PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] ROTARY_A ROTARY_B ROT SELA Edge Detect APBX Clock Figure 22-5. Detail of Rotary Decoder i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-7 Timers and Rotary Decoder ~oversamp_by_8 Adebounce JQ DQ *Q DQ *Q DQ *Q DQ *Q DQ *Q DQ *Q DQ *Q DQ *Q K Q* ~oversamp_by_8 NEVER TICK PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] ROTARY_A ROTARY_B Flip-flops sample and advance at a divided 32-kHz rate Figure 22-6. Rotary Decoding Mode--Debouncing Rotary A and B Inputs A state machine following rotary decoder transition is provided to detect the direction of rotation and the time at which to increment or decrement the 16-bit signed counter in HW_TIMROT_ROTCOUNT. The updown counter can be treated as either a relative count or an absolute count, depending on the state of the HW_TIMROT_ROTCTRL_RELATIVE bit. When set to the relative mode, each read of the counter has the side effect of resetting it. The edge detectors respond to both edges of each input to determine the self-timed transition inputs to the state machine (see Figure 22-7). i.MX23 Applications Processor Reference Manual, Rev. 1 22-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Timers and Rotary Decoder 11 Input A 00 inc 01 10 Input B 10 11 00 dec 01 Figure 22-7. Rotary Decoding Mode--Input Transitions Figure 22-7 shows that each detected edge causes a transition in the decoder state machine. Not all transitions are legal (see Table 22-2). For example, there is no legal way to transition directly from state 11 to 00 using normal inputs. In the cases where this occurs, the state machine goes to an alternate set of states and follows the input sequence until a valid sequence leading to state 00 is detected. No increment or decrement action is taken from the alternate state sequence. Table 22-2. Rotary Decoder State Machine Transitions CURRENT STATE 00 01 10 11 "INPUT" BA=00 00 00, dec 00, inc error "INPUT" BA=01 01 01 error 01 "INPUT" BA=10 10 error 10 10 "INPUT" BA=11 error 11 11 11 22.3.1 Testing the Rotary Decoder To test the rotary decoder, select PWM1 and PWM2 as inputs to ROTARYA and ROTARYB. Since PWM1 and PWM2 can be started with known phase offsets and duty cycles, a continuous increment or decrement stream can be generated. Since PWM1 and PWM2 can be used as GPIO devices, the final part of the test is to generate and test a sequence of clockwise and counter-clockwise rotations to cover the entire state machine transitions, including the error conditions. 22.3.2 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. 22.4 Programmable Registers The following registers describe the programming interface for the timers and the rotary decoder. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-9 Timers and Rotary Decoder 22.4.1 Rotary Decoder Control Register Description The Rotary Decoder Control Register specifies the reset state and the source selection for the rotary decoder. In addition, it specifies the polarity of any external input source that is used. This register also contains some general block controls including soft reset, clock gate, and present bits. HW_TIMROT_ROTCTRL HW_TIMROT_ROTCTRL_SET HW_TIMROT_ROTCTRL_CLR HW_TIMROT_ROTCTRL_TOG Table 22-3. HW_TIMROT_ROTCTRL 3 1 3 0 2 9 ROTARY_PRESENT 0x000 0x004 0x008 0x00C 2 8 TIM3_PRESENT 2 7 TIM2_PRESENT 2 6 TIM1_PRESENT 2 5 TIM0_PRESENT 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 OVERSAMPLE 1 0 0 9 POLARITY_B 0 8 POLARITY_A 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SELECT_B Table 22-4. HW_TIMROT_ROTCTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION This bit must be set to zero to enable operation of any timer or the rotary decoder. When set to one, it forces a block-level reset and gates off the clocks to the block. This bit must be set to zero for normal operation. When set to one, it gates off the clocks to the block. 0= Rotary decoder is not present in this product. 1= Rotary decoder is present is in this product. 0= Timer 3 is not present in this product. 1= TIMER3 is present is in this product. 0= Timer 2 is not present in this product. 1= TIMER2 is present is in this product. 0= Timer 1 is not present in this product. 1= TIMER1 is present is in this product. 0= Timer 0 is not present in this product. 1= TIMER0 is present is in this product. Read-only view of the rotary decoder transition detecting state machine. This bit field determines the divisor used to divide the 32-kHz on chip clock rate for oversampling (debouncing) the rotary A and B inputs. Note that the divider value is actually the (value of this field+1). Always write zeroes to this bit field. Set this bit to one to cause the rotary decoders updown counter to be reset to zero whenever it is read. 30 29 28 27 26 25 CLKGATE ROTARY_PRESENT TIM3_PRESENT TIM2_PRESENT TIM1_PRESENT TIM0_PRESENT RW 0x1 RO 0x1 RO 0x1 RO 0x1 RO 0x1 RO 0x1 RO 0x0 RW 0x0 24:22 STATE 21:16 DIVIDER 15:13 RSRVD3 12 RELATIVE RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 22-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor SELECT_A RELATIVE CLKGATE DIVIDER RSRVD3 RSRVD2 RSRVD1 SFTRST STATE Timers and Rotary Decoder Table 22-4. HW_TIMROT_ROTCTRL Bit Field Descriptions BITS LABEL 11:10 OVERSAMPLE RW RESET RW 0x0 DEFINITION This bit field determines the oversample rate to use in debouncing Rotary A and B inputs. 8X = 0x0 8x Oversample: 8 successive ones or zeroes to transition. 4X = 0x1 4x Oversample: 4 successive ones or zeroes to transition. 2X = 0x2 2x Oversample: 2 successive ones or zeroes to transition. 1X = 0x3 1x Oversample: Transition on each first input change. 9 8 7 6:4 POLARITY_B POLARITY_A RSRVD2 SELECT_B RW 0x0 RW 0x0 RO 0x0 RW 0x0 Set this bit to one to invert the input to the edge detector. Set this bit to one to invert the input to the edge detector. Always write zeroes to this bit field. Selects the source for the timer "tick" that increments the free-running counter that measures the A2B and B2A overlap counts. NEVER_TICK = 0x0 SelectB: Never tick. PWM0 = 0x1 SelectB: Input from PWM0. PWM1 = 0x2 SelectB: Input from PWM1. PWM2 = 0x3 SelectB: Input from PWM2. PWM3 = 0x4 SelectB: Input from PWM3. PWM4 = 0x5 SelectB: Input from PWM4. ROTARYA = 0x6 SelectB: Input from Rotary A. ROTARYB = 0x7 SelectB: Input from Rotary B. 3 2:0 RSRVD1 SELECT_A RO 0x0 RW 0x0 Always write zeroes to this bit field. Selects the source for the timer "tick" that increments the free-running counter that measures the A2B and B2A overlap counts. NEVER_TICK = 0x0 SelectA: Never tick. PWM0 = 0x1 SelectA: Input from PWM0. PWM1 = 0x2 SelectA: Input from PWM1. PWM2 = 0x3 SelectA: Input from PWM2. PWM3 = 0x4 SelectA: Input from PWM3. PWM4 = 0x5 SelectA: Input from PWM4. ROTARYA = 0x6 SelectA: Input from Rotary A. ROTARYB = 0x7 SelectA: Input from Rotary B. DESCRIPTION: This register contains control parameters to specify the rotary decoder setup. It also contains some general block controls including soft reset, clock gate, and present bits. EXAMPLE: HW_TIMROT_ROTCTRL_WR(0x00000076); // Set up rotary control fields. 22.4.2 Rotary Decoder Up/Down Counter Register Description The Rotary Decoder Up/Down Counter Register contains the timer counter value that counts up or down as the rotary encoder is rotated. HW_TIMROT_ROTCOUNT 0x010 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-11 Timers and Rotary Decoder Table 22-5. HW_TIMROT_ROTCOUNT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RSRVD1 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 UPDOWN 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 22-6. HW_TIMROT_ROTCOUNT Bit Field Descriptions BITS LABEL 31:16 RSRVD1 15:0 UPDOWN RW RESET RO 0x0 RO 0x00 DEFINITION Always write zeroes to this bit field. At each edge of the Rotary A input, the Rotary B value is sampled, similarly at each edge of the Rotary B input, the Rotary A input is sampled. These values drive a rotary decoder state machine that determines when this counter is incremented or decremetned. When set in the RELATIVE mode, reads from this register clear this register as a side effect. Counter values in this register are signed 16-bit values. DESCRIPTION: This register contains the read-only current count for the rotary decoder. EXAMPLE: count = HW_TIMROT_ROTCTRL_RD(); // Read count 22.4.3 Timer 0 Control and Status Register Description The Timer 0 Control and Status Register specifies timer control parameters, as well as interrupt status and the enable for Timer 0. HW_TIMROT_TIMCTRL0 HW_TIMROT_TIMCTRL0_SET HW_TIMROT_TIMCTRL0_CLR HW_TIMROT_TIMCTRL0_TOG Table 22-7. HW_TIMROT_TIMCTRL0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RSRVD2 0x020 0x024 0x028 0x02C 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 IRQ_EN 1 3 1 2 1 1 RSRVD1 1 0 0 9 0 8 POLARITY 0 7 UPDATE 0 6 RELOAD 0 5 PRESCALE 0 4 0 3 0 2 SELECT 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 22-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor IRQ Timers and Rotary Decoder Table 22-8. HW_TIMROT_TIMCTRL0 Bit Field Descriptions BITS 31:16 RSRVD2 15 IRQ 14 IRQ_EN LABEL RW RESET RO 0x0 RW 0x0 RW 0x0 DEFINITION Always write zeroes to this bit field. This bit is set to one when Timer 0 decrements to zero. Write a zero to clear it or use Clear SCT mode. Set this bit to one to enable the generation of a CPU interrupt when the count reaches zero in normal counter mode. Always write zeroes to this bit field. Set this bit to one to invert the input to the edge detector. 0: Positive edge detection. 1: Invert to negative edge detection. Set this bit to one to cause the running count to be written from the CPU at the same time a new fixed count register value is written. Set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. When set to zero, the timer enters a mode that freezes at a count of zero. When the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. Selects the divisor used for clock generation. The APBX clock is divided by the following amount. Note the APBX clock itself is initially divided down from the 24.0-MHz crystal clock frequency. DIV_BY_1 = 0x0 PreScale: Divide the APBX clock by 1. DIV_BY_2 = 0x1 PreScale: Divide the APBX clock by 2. DIV_BY_4 = 0x2 PreScale: Divide the APBX clock by 4. DIV_BY_8 = 0x3 PreScale: Divide the APBX clock by 8. 13:9 8 RSRVD1 POLARITY RO 0x0 RW 0x0 7 UPDATE RW 0x0 6 RELOAD RW 0x0 5:4 PRESCALE RW 0x0 3:0 SELECT RW 0x0 Selects the source for the timer "tick" that decrements the free running counter. Note: programming an undefined value will result in "always tick" behavior. NEVER_TICK = 0x0 Never tick. PWM0 = 0x1 Input from PWM0. PWM1 = 0x2 Input from PWM1. PWM2 = 0x3 Input from PWM2. PWM3 = 0x4 Input from PWM3. PWM4 = 0x5 Input from PWM4. ROTARYA = 0x6 Input from Rotary A. ROTARYB = 0x7 Input from Rotary B. 32KHZ_XTAL = 0x8 Input from 32-kHz crystal. 8KHZ_XTAL = 0x9 Input from 8-kHz (divided from 32-kHz crystal). 4KHZ_XTAL = 0xA Input from 4-kHz (divided from 32-kHz crystal). 1KHZ_XTAL = 0xB Input from 1-kHz (divided from 32-kHz crystal). TICK_ALWAYS = 0xC Always tick. DESCRIPTION: This control register specifies control parameters, as well as interrupt status and the enable for Timer 0. EXAMPLE: HW_TIMROT_TIMCTRLn_WR(0, 0x00000008); // Set up control fields for timer0 22.4.4 Timer 0 Count Register Description HW_TIMROT_TIMCOUNT0 0x030 The Timer 0 Count Register contains the timer counter values for Timer 0. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-13 Timers and Rotary Decoder Table 22-9. HW_TIMROT_TIMCOUNT0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RUNNING_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 FIXED_COUNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 22-10. HW_TIMROT_TIMCOUNT0 Bit Field Descriptions BITS LABEL 31:16 RUNNING_COUNT 15:0 FIXED_COUNT RW RESET RO 0x00 RW 0x00 DEFINITION This bit field shows the current state of the running count as it decrements. Software loads the fixed count bit field with the value to down count. If the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. If the update bit is set to one, then the new value is also copied into the running count, immediately. If both the reload and update bits are set to zero, then the new value is never picked up by the running count. DESCRIPTION: This timer count register contains the programable and readback counter values for Timer 0. EXAMPLE: HW_TIMROT_TIMCOUNTn_WR(0, 0x0000f0dd); // Set up timer count 22.4.5 Timer 1 Control and Status Register Description The Timer 1 Control and Status Register specifies timer control parameters, as well as interrupt status and the enable for Timer 1. HW_TIMROT_TIMCTRL1 HW_TIMROT_TIMCTRL1_SET HW_TIMROT_TIMCTRL1_CLR HW_TIMROT_TIMCTRL1_TOG 0x040 0x044 0x048 0x04C i.MX23 Applications Processor Reference Manual, Rev. 1 22-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Timers and Rotary Decoder Table 22-11. HW_TIMROT_TIMCTRL1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RSRVD2 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 IRQ_EN 1 3 1 2 1 1 RSRVD1 1 0 0 9 0 8 POLARITY 0 7 UPDATE 0 6 RELOAD 0 5 PRESCALE 0 4 0 3 0 2 SELECT 0 1 0 0 Table 22-12. HW_TIMROT_TIMCTRL1 Bit Field Descriptions BITS 31:16 RSRVD2 15 IRQ 14 IRQ_EN LABEL RW RESET RO 0x0 RW 0x0 RW 0x0 DEFINITION Always write zeroes to this bit field. This bit is set to one when Timer 1 decrements to zero. Write a zero to clear it or use Clear SCT mode. Set this bit to one to enable the generation of a CPU interrupt when the count reaches zero in normal counter mode. Always write zeroes to this bit field. Set this bit to one to invert the input to the edge detector. 0: Positive edge detection. 1: Invert to negative edge detection. Set this bit to one to cause the running count to be written from the CPU at the same time a new fixed count register value is written. Set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. When set to zero, the timer enters a mode that freezes at a count of zero. When the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. Selects the divisor used for clock generation. The APBX clock is divided by the following amount. Note the APBX clock itself is initially divided down from the 24.0-MHz crystal clock frequency. DIV_BY_1 = 0x0 PreScale: Divide the APBX clock by 1. DIV_BY_2 = 0x1 PreScale: Divide the APBX clock by 2. DIV_BY_4 = 0x2 PreScale: Divide the APBX clock by 4. DIV_BY_8 = 0x3 PreScale: Divide the APBX clock by 8. 13:9 8 RSRVD1 POLARITY RO 0x0 RW 0x0 7 UPDATE RW 0x0 6 RELOAD RW 0x0 5:4 PRESCALE RW 0x0 3:0 SELECT RW 0x0 IRQ Selects the source for the timer "tick" that decrements the free running counter. Note: programming an undefined value will result in "always tick" behavior. NEVER_TICK = 0x0 Never tick. PWM0 = 0x1 Input from PWM0. PWM1 = 0x2 Input from PWM1. PWM2 = 0x3 Input from PWM2. PWM3 = 0x4 Input from PWM3. PWM4 = 0x5 Input from PWM4. ROTARYA = 0x6 Input from Rotary A. ROTARYB = 0x7 Input from Rotary B. 32KHZ_XTAL = 0x8 Input from 32-kHz crystal. 8KHZ_XTAL = 0x9 Input from 8 kHz (divided from 32-kHz crystal). 4KHZ_XTAL = 0xA Input from 4 kHz (divided from 32-kHz crystal). 1KHZ_XTAL = 0xB Input from 1 kHz (divided from 32-kHz crystal). TICK_ALWAYS = 0xC Always tick. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-15 Timers and Rotary Decoder DESCRIPTION: This control register specifies control parameters, as well as interrupt status and the enable for Timer 1. EXAMPLE: HW_TIMROT_TIMCTRLn_WR(1, 0x00000008); // Set up control fields for timer1 22.4.6 Timer 1 Count Register Description HW_TIMROT_TIMCOUNT1 0x050 The Timer 1 Count Register contains the timer counter values for Timer 1. Table 22-13. HW_TIMROT_TIMCOUNT1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RUNNING_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 FIXED_COUNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 22-14. HW_TIMROT_TIMCOUNT1 Bit Field Descriptions BITS LABEL 31:16 RUNNING_COUNT 15:0 FIXED_COUNT RW RESET RO 0x00 RW 0x00 DEFINITION This bit field shows the current state of the running count as it decrements. Software loads the fixed count bit field with the value to down count. If the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. If the update bit is set to one, then the new value is also copied into the running count, immediately. If both the reload and update bits are set to zero, then the new value is never picked up by the running count. DESCRIPTION: This timer count register contains the programable and readback counter values for Timer 1. EXAMPLE: HW_TIMROT_TIMCOUNTn_WR(1, 0x0000f0dd); // Set up timer count 22.4.7 Timer 2 Control and Status Register Description The Timer 2 Control and Status Register specifies timer control parameters, as well as interrupt status and the enable for Timer 2. HW_TIMROT_TIMCTRL2 HW_TIMROT_TIMCTRL2_SET 0x060 0x064 i.MX23 Applications Processor Reference Manual, Rev. 1 22-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Timers and Rotary Decoder HW_TIMROT_TIMCTRL2_CLR HW_TIMROT_TIMCTRL2_TOG Table 22-15. HW_TIMROT_TIMCTRL2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RSRVD2 0x068 0x06C 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 IRQ_EN 1 3 1 2 1 1 RSRVD1 1 0 0 9 0 8 POLARITY 0 7 UPDATE 0 6 RELOAD 0 5 PRESCALE 0 4 0 3 0 2 SELECT 0 1 0 0 Table 22-16. HW_TIMROT_TIMCTRL2 Bit Field Descriptions BITS 31:16 RSRVD2 15 IRQ 14 IRQ_EN LABEL RW RESET RO 0x0 RW 0x0 RW 0x0 DEFINITION Always write zeroes to this bit field. This bit is set to one when Timer 2 decrements to zero. Write a zero to clear it or use Clear SCT mode. Set this bit to one to enable the generation of a CPU interrupt when the count reaches zero in normal counter mode. Always write zeroes to this bit field. Set this bit to one to invert the input to the edge detector. 0: Positive edge detection. 1: Invert to negative edge detection. Set this bit to one to cause the running count to be written from the CPU at the same time a new fixed count register value is written. Set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. When set to zero, the timer enters a mode that freezes at a count of zero. When the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. 13:9 8 RSRVD1 POLARITY RO 0x0 RW 0x0 7 UPDATE RW 0x0 6 RELOAD RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-17 IRQ Timers and Rotary Decoder Table 22-16. HW_TIMROT_TIMCTRL2 Bit Field Descriptions BITS LABEL 5:4 PRESCALE RW RESET RW 0x0 DEFINITION Selects the divisor used for clock generation. The APBX clock is divided by the following amount. Note the APBX clock itself is initially divided down from the 24.0-MHz crystal clock frequency. DIV_BY_1 = 0x0 PreScale: Divide the APBX clock by 1. DIV_BY_2 = 0x1 PreScale: Divide the APBX clock by 2. DIV_BY_4 = 0x2 PreScale: Divide the APBX clock by 4. DIV_BY_8 = 0x3 PreScale: Divide the APBX clock by 8. 3:0 SELECT RW 0x0 Selects the source for the timer "tick" that decrements the free running counter. Note: programming an undefined value will result in "always tick" behavior. NEVER_TICK = 0x0 Never tick. PWM0 = 0x1 Input from PWM0. PWM1 = 0x2 Input from PWM1. PWM2 = 0x3 Input from PWM2. PWM3 = 0x4 Input from PWM3. PWM4 = 0x5 Input from PWM4. ROTARYA = 0x6 Input from Rotary A. ROTARYB = 0x7 Input from Rotary B. 32KHZ_XTAL = 0x8 Input from 32-kHz crystal. 8KHZ_XTAL = 0x9 Input from 8 kHz (divided from 32-kHz crystal). 4KHZ_XTAL = 0xA Input from 4 kHz (divided from 32-kHz crystal). 1KHZ_XTAL = 0xB Input from 1 kHz (divided from 32-kHz crystal). TICK_ALWAYS = 0xC Always tick. DESCRIPTION: This control register specifies control parameters as well as interrupt status and the enable for Timer 2. EXAMPLE: HW_TIMROT_TIMCTRLn_WR(2, 0x00000008); // Set up control fields for timer2 22.4.8 Timer 2 Count Register Description HW_TIMROT_TIMCOUNT2 0x070 The Timer 2 Count Register contains the timer counter values for Timer 2. Table 22-17. HW_TIMROT_TIMCOUNT2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RUNNING_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 FIXED_COUNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 22-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Timers and Rotary Decoder Table 22-18. HW_TIMROT_TIMCOUNT2 Bit Field Descriptions BITS LABEL 31:16 RUNNING_COUNT 15:0 FIXED_COUNT RW RESET RO 0x00 RW 0x00 DEFINITION This bit field shows the current state of the running count as it decrements. Software loads the fixed count bit field with the value to down count. If the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. If the update bit is set to one, then the new value is also copied into the running count, immediately. If both the reload and update bits are set to zero, then the new value is never picked up by the running count. DESCRIPTION: This timer count register contains the programable and readback counter values for Timer 2. EXAMPLE: HW_TIMROT_TIMCOUNTn_WR(2, 0x0000f0dd); // Set up timer count 22.4.9 Timer 3 Control and Status Register Description The Timer 3 Control and Status Register specifies timer control parameters, as well as interrupt status and the enable for Timer 3. HW_TIMROT_TIMCTRL3 HW_TIMROT_TIMCTRL3_SET HW_TIMROT_TIMCTRL3_CLR HW_TIMROT_TIMCTRL3_TOG Table 22-19. HW_TIMROT_TIMCTRL3 3 1 3 0 2 9 2 8 2 7 2 6 RSRVD2 0x080 0x084 0x088 0x08C 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 TEST_SIGNAL 1 7 1 6 1 5 1 4 IRQ_EN 1 3 1 2 RSRVD1 1 1 1 0 DUTY_VALID 0 9 DUTY_CYCLE 0 8 POLARITY 0 7 UPDATE 0 6 RELOAD 0 5 PRESCALE 0 4 0 3 0 2 SELECT 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-19 IRQ Timers and Rotary Decoder Table 22-20. HW_TIMROT_TIMCTRL3 Bit Field Descriptions BITS LABEL 31:20 RSRVD2 19:16 TEST_SIGNAL RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this bit field. Selects the source of the signal to be measured in duty cycle mode. NEVER_TICK = 0x0 Never tick. Freeze the count. PWM0 = 0x1 Input from PWM0. PWM1 = 0x2 Input from PWM1. PWM2 = 0x3 Input from PWM2. PWM3 = 0x4 Input from PWM3. PWM4 = 0x5 Input from PWM4. ROTARYA = 0x6 Input from Rotary A. ROTARYB = 0x7 Input from Rotary B. 32KHZ_XTAL = 0x8 Input from 32-kHz crystal. 8KHZ_XTAL = 0x9 Input from 8 kHz (divided from 32-kHz crystal). 4KHZ_XTAL = 0xA Input from 4 kHz (divided from 32-kHz crystal). 1KHZ_XTAL = 0xB Input from 1 kHz (divided from 32-kHz crystal). TICK_ALWAYS = 0xC Always tick. 15 14 IRQ IRQ_EN RW 0x0 RW 0x0 13:11 RSRVD1 10 DUTY_VALID RO 0x0 RO 0x0 9 8 DUTY_CYCLE POLARITY RW 0x0 RW 0x0 7 UPDATE RW 0x0 6 RELOAD RW 0x0 This bit is set to one when Timer 3 decrements to zero. Write a zero to clear it or use Clear SCT mode. Set this bit to one to enable the generation of a CPU interrupt when the count reaches zero in normal counter mode. Always write zeroes to this bit field. This bit is set and cleared by the hardware. It is set only when in duty cycle measuring mode and the HW_TIMROT_TIMCOUNT3 has valid duty cycle data to be read. This register will be cleared if not in duty cycle mode or on writes to this register. In the case that it is written while in duty cycle mode, this bit will clear but will again be set at the appropriate time for reading the count register. Set this bit to one to cause the timer to operate in duty cycle measuring mode. Set this bit to one to invert the input to the edge detector. 0: Positive edge detection. 1: Invert to negative edge detection. Set this bit to one to cause the running count to be written from the CPU at the same time a new fixed count register value is written. Set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. When set to zero, the timer enters a mode that freezes at a count of zero. When the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. i.MX23 Applications Processor Reference Manual, Rev. 1 22-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Timers and Rotary Decoder Table 22-20. HW_TIMROT_TIMCTRL3 Bit Field Descriptions BITS LABEL 5:4 PRESCALE RW RESET RW 0x0 DEFINITION Selects the divisor used for clock generation. The APBX clock is divided by the following amount. Note the APBX clock itself is initially divided down from the 24.0-MHz crystal clock frequency. DIV_BY_1 = 0x0 PreScale: Divide the APBX clock by 1. DIV_BY_2 = 0x1 PreScale: Divide the APBX clock by 2. DIV_BY_4 = 0x2 PreScale: Divide the APBX clock by 4. DIV_BY_8 = 0x3 PreScale: Divide the APBX clock by 8. 3:0 SELECT RW 0x0 Selects the source for the timer "tick" that decrements the free running counter. Note: programming an undefined value will result in "always tick" behavior. In duty cycle mode it increments the counter used to calculate the high and low cycle counts. NEVER_TICK = 0x0 Never tick. Freeze the count. PWM0 = 0x1 Input from PWM0. PWM1 = 0x2 Input from PWM1. PWM2 = 0x3 Input from PWM2. PWM3 = 0x4 Input from PWM3. PWM4 = 0x5 Input from PWM4. ROTARYA = 0x6 Input from Rotary A. ROTARYB = 0x7 Input from Rotary B. 32KHZ_XTAL = 0x8 Input from 32-kHz crystal. 8KHZ_XTAL = 0x9 Input from 8 kHz (divided from 32-kHz crystal). 4KHZ_XTAL = 0xA Input from 4 kHz (divided from 32-kHz crystal). 1KHZ_XTAL = 0xB Input from 1 kHz (divided from 32-kHz crystal). TICK_ALWAYS = 0xC Always tick. DESCRIPTION: This control register specifies control parameters, as well as interrupt status and the enable for Timer 3. EXAMPLE: HW_TIMROT_TIMCTRLn_WR(3, 0x00000008); // Set up control fields for timer3 22.4.10 Timer 3 Count Register Description The Timer 3 Count Register contains the timer counter values for Timer 3. NOTE: This timer can be put in a special duty cycle mode that will measure the duty cycle of an input test signal. HW_TIMROT_TIMCOUNT3 0x090 Table 22-21. HW_TIMROT_TIMCOUNT3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 LOW_RUNNING_COUNT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 HIGH_FIXED_COUNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-21 Timers and Rotary Decoder Table 22-22. HW_TIMROT_TIMCOUNT3 Bit Field Descriptions BITS LABEL 31:16 LOW_RUNNING_COUNT RW RESET RO 0x00 DEFINITION In duty cycle mode, this bit field is loaded from the running counter when it has just finished measuring the low portion of the duty cycle. In normal timer mode, it shows the running count as a read-only value. Software loads the fixed count bit field with the value to down count. If the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. If the update bit is set to one, then the new value is also copied into the running count, immediately. If both the reload and update bits are set to zero, then the new value is never picked up by the running count. In duty cycle mode, this bit field is loaded from the running counter when it has finished measuring the high portion of the duty cycle. 15:0 HIGH_FIXED_COUNT RW 0x00 DESCRIPTION: This timer count register contains the programable and readback counter values for Timer 3. The definitions of the fields change depending whether the timer is in normal or duty cycle mode. EXAMPLE: HW_TIMROT_TIMCOUNTn_WR(3, 0x0000f0dd); // Set up timer count 22.4.11 TIMROT Version Register Description This register always returns a known read value for debug purposes it indicates the version of the block. HW_TIMROT_VERSION Table 22-23. HW_TIMROT_VERSION 3 1 3 0 2 9 2 8 MAJOR 0x0a0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 22-24. HW_TIMROT_VERSION Bit Field Descriptions BITS 31:24 MAJOR 23:16 MINOR 15:0 STEP LABEL RW RESET RO 0x01 RO 0x01 RO 0x0000 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. i.MX23 Applications Processor Reference Manual, Rev. 1 22-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Timers and Rotary Decoder DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_TIMROT_VERSION.B.MAJOR != 1) Error(); TIMROT Block v1.1, Revision 1.38 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 22-23 Timers and Rotary Decoder i.MX23 Applications Processor Reference Manual, Rev. 1 22-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 23 Real-Time Clock, Alarm, Watchdog, Persistent Bits This chapter describes the real-time clock, alarm clock, watchdog reset, persistent bits, and millisecond counter included on the i.MX23. Programmable registers are described in Section 23.8, "Programmable Registers." 23.1 Overview The real-time clock (RTC) and alarm share a one-second pulse time domain. The watchdog reset and millisecond counter run on a one-millisecond time domain. The RTC, alarm, and persistent bits use persistent storage and reside in a special power domain (crystal domain) that remains powered up even when the rest of the chip is in its powered-down state. Figure 23-1 illustrates this block. NOTE: The term power-down, as used here, refers to a state in which the DC-DC converter and various parts of the crystal power domain are still powered up, but the rest of the chip is powered down. If the battery is removed, then the persistent bits, the alarm value, and the second counter value will be lost. The crystal power domain powers both the 32-kHz and 24-MHz crystals. Note that the 32 kHz crystal is not available in the 128-pin LQFP package. Upon battery insertion, the crystals (32-kHz and 24-MHz) are in a quiescent state. The activation of these crystals is under software control through the RTC persistent bits, as described later in this chapter. * * The XTAL32KHZ_PWRUP bit in the Persistent Register 0 controls the activity of the 32-kHz crystal at all times (chip power on or off). The XTAL24MHZ_PWRUP bit in the Persistent Register 0 controls the behavior of the 24-MHz crystal during the power-off state. (The 24-MHz crystal is always on when the chip is powered up.) The one-second time base is derived either from the 24.0-MHz crystal oscillator or a 32-kHz crystal oscillator (which can be either exactly 32.0 kHz or 32.768 kHz), as controlled by bits in Persistent Register 0. The time base thus generated is used to increment the value of the persistent seconds count register. Like the values of the other persistent registers, the value of the persistent seconds count register is not lost across a power-down state and will continue to count seconds during that time. Contrary to the one-second time base, no record or count is made of the one-millisecond time base in the crystal power domain. The one-millisecond time base is always derived from the 24.0-MHz crystal oscillator, but is not available when the chip is powered down. The real-time clock seconds counter, alarm functions, and persistent bit storage are kept in the (always on) crystal power domain. Shadow versions of these values are maintained in the CPU's power and i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23-1 Real-Time Clock, Alarm, Watchdog, Persistent Bits APBX clock domain when the chip is in the power-up state. When the chip transitions from power-off to power-on, the master values are copied to shadow registers by the copy controller. Whenever software writes to a shadow register, then the copy controller copies the new value into the master register in the crystal oscillator power domain. Some of the persistent bits are used to control features that can continue to operate after power-down, such as the second counter and the alarm function and bits in the HW_RTC_PERSISTENT0 register. The bits in registers HW_RTC_PERSISTENT1 through HW_RTC_PERSISTENT5 are available to store application state information over power-downs and are completely software-defined. i.MX23 Applications Processor Reference Manual, Rev. 1 23-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Real-Time Clock, Alarm, Watchdog, Persistent Bits ARM Core SRAM AHB AHB Slave AHB Master Divide by n 24-MHz XTAL Osc. Shared DMA AHB-to-APBX Bridge APBX Master 32.768 or 32.000 kHz XTAL Osc. APBX RTC/Watchdog/Alarm/ Persistent I/O 32-Bit Shadow Persistent 0 32-Bit Shadow Persistent 1 32-Bit Shadow Persistent 2 32-Bit Shadow Persistent 3 32-Bit Shadow Persistent 4 32-Bit Shadow Persistent 5 32-Bit Alarm Shadow Copy controller 32-Bit Master Persistent 0 32-Bit Master Persistent 1 32-Bit Master Persistent 2 32-Bit Master Persistent 3 32-Bit Master Persistent 4 32-Bit Master Persistent 5 32-Bit Alarm Master == 32-Bit RTC Shadow Counter 1 Hz Alarm Event 32-Bit RTC Seconds 1 Hz Divide by appropriate value Crystal Power and Clock Domain 1 kHz fixed divide by 24000 Figure 23-1. RTC, Watchdog, Alarm, and Persistent Bits Block Diagram Immediately after reset, it will take approximately three milliseconds for the copy controller to complete the copy process from the analog domain to the digital domain. Software cannot rely on the contents of the seconds counter, alarm, or persistent bits until this copy is complete. Therefore, software must wait until all bits of interest in the HW_RTC_STAT_STALE_REGS field have been reset to 0 by the copy controller before reading the initial state of these values (see Figure 23-2). The order in which registers are updated is Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds. (This list is in bitfield order, from LSB to MSB, i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23-3 1/768 = 31250Hz Real-Time Clock, Alarm, Watchdog, Persistent Bits as they would appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT register. For example, the Seconds register corresponds to STALE_REGS or NEW_REGS containing 0x80.) rtc_init Call during initialization HW_RTC_CTRL_SFTRST_WRITE (BM_RTC_CTRL_SFTRST); HW_RTC_CTRL_CLKGATE_WRITE (BM_RTC_CTRL_CLKGATE); Return Remove soft reset and clock gate. This releases the copy controller. Figure 23-2. RTC Initialization Sequence 23.2 Programming and Enabling the RTC Clock The RTC functions implemented in the crystal power domain are referred to as RTC analog functions. The clock frequency and clock source for the RTC analog functions are programmable. There are three possible clock options. * * If the HW_RTC_PERSISTENT0_CLOCKSOURCE bit is set to 0, these functions operate on a clock domain derived from the 24.0-MHz crystal oscillator divided by 768 to yield 31.250 kHz. If the HW_RTC_PERSISTENT0_CLOCKSOURCE bit is 1 and the HW_RTC_PERSISTENT0_XTAL32_FREQ bit is 0, then the optional external driving crystal clock will be used and its frequency should be 32.768 kHz. However, if the HW_RTC_PERSISTENT0_CLOCKSOURCE is 1 and the HW_RTC_PERSISTENT0_XTAL32_FREQ bit is also 1, then the external crystal generated clock should be 32.000 kHz for correct operation. * Thus, the HW_RTC_PERSISTENT0_XTAL32_FREQ bit gives the systems designer some flexibility as to which external crystal to use on the board. Switching between these two clock domains is handled by a glitch-free clock mux and can be done on the fly. The 1-Hz time base is derived by dividing either 32.768 kHz by 32768 or by dividing 31.250 kHz by 31,250, or by dividing 32.000 kHz by 32000. By reading and examining the HW_RTC_STAT_XTAL32000_PRESENT and HW_RTC_STAT_XTAL32768_PRESENT bits, software can discover if there is an optional crystal clock present and the frequency at which it runs (32.768 kHz or 32.000 kHz). Only one of these fuse bits will be asserted if there is such a crystal attached. If there is no crystal present, both bits will be deasserted. 23.3 RTC Persistent Register Copy Control The copying of a persistent shadow register (digital) to persistent master storage (analog) occurs automatically. This automatic write-back that occurs for each register as the copy controller services writes to the shadow registers can lead to some very long timing loops if efficient write procedures are not used. Writing all eight shadow registers can take several milliseconds to complete. Do not attempt to write to more than one shadow register immediately before power down. Whenever possible, software should ensure i.MX23 Applications Processor Reference Manual, Rev. 1 23-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Real-Time Clock, Alarm, Watchdog, Persistent Bits that the HW_RTC_STAT_NEW_REGS field is 0 before powering down the chip or setting the HW_RTC_CTRL_SFTRST bit. Otherwise, some of the write data could be lost because the shadow registers could be powered down/reset before the new values can be copied to persistent master storage. Registers are copied between the digital and analog sides one by one and in 32-bit words. There are no hardwired uses for any of the bits of Persistent registers 1 through 5. And thus, the bits in these registers can be defined and set by software. Persistent Register 0 is reserved for hardware programming and configuration. Before a new value is written to a shadow register by the CPU, software must first confirm that the corresponding bit of HW_RTC_STAT_NEW_REGS is a 0. This ensures that a value previously written to the register has been completely handled by the copy state machine. Failure to obey this constraint could cause a newer updated value to be lost. NOTE: The HW_RTC_CTRL_SUPPRESS_COPY2ANALOG diagnostic bit is never set while any copy or update operation is underway. Doing so will result in undefined operation of the copy controller. Figure 23-3 shows the copy and test procedure for a single register. However, software can write to any register whose HW_RTC_STAT_NEW_REGS bit is 0 even if the copy controller is currently busy copying a different register. For example, if the copy controller is busy copying Persistent Register 1 from a previous write, software can simultaneously write to Persistent Register 0 during this copy. After the copy controller has finished copying register 1, it will then, in turn, begin the copy process for the new value of Register 0. Thus, registers can thus be written in any order. Again, the main important rule that must be followed is that the HW_RTC_STAT_NEW_REGS bit for a particular register must be 0 before it can be written and is independent of the state of the HW_RTC_STAT_NEW_REGS bits for the other registers. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23-5 Real-Time Clock, Alarm, Watchdog, Persistent Bits How to write a master register. rtc_write2master TestValue = HW_RTC_STAT_NEW_REGS Extract corresponding bit. NO TestValue == 0 YES HW_RTC_PERSISTENT2_WR(0xdeadbeef); Wait for previous write to this register to complete. Write new value to shadow that will be automatically copied to analog side. Use this same technique for milliseconds, alarm, or other persistent registers. TestValue=HW_RTC_STAT_NEW_REGS NO TestValue == 0 Return Figure 23-3. RTC Writing to a Master Register from CPU The digital shadow registers will be updated (copied from analog to digital) with values from their analog persistent counterparts under two conditions: first, whenever the chip is powered on, and secondly, whenever the HW_RTC_CTRL_FORCE_UPDATE bit is set by software. Then, an update occurs, and all persistent registers are updated. Persistent registers cannot be updated singly. 23.4 Real-Time Clock Function The real-time clock is a CPU-accessible, continuously-running 32-bit counter that increments every second and that can be derived from either the 24-MHz clock or the 32-kHz clock, as determined by writable bit values in the RTC Persistent Register 0. A 32-bit second counter has enough resolution to count up to 136 years with one-second increments. The RTC can continue to count time as long as a voltage is applied to the BATT pin, irrespective of whether the rest of the chip is powered up. The normal digital reset has no effect on the master RTC registers located in the crystal power and clock domain. A special first-power-on reset establishes the default value of the master RTC registers when a voltage is first applied to the BATT pin (battery insertion). For consistency across applications, it is recommended that the seconds timer should be referenced to January 1, 1980 at a 32-bit value of 0 (same epoch reference as PC) in applications that use it as a time-of-day clock. If the real-time clock function is not present on a specific chip, as indicated in the coni.MX23 Applications Processor Reference Manual, Rev. 1 23-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Real-Time Clock, Alarm, Watchdog, Persistent Bits trol and status register (HW_RTC_STAT_RTC_PRESENT), then no real-time epoch is maintained over power-down cycles. 23.4.1 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. 23.5 Millisecond Resolution Timing Function A millisecond counter facility is provided based on a 1-kHz signal derived from the 24-MHz clock. The count value is neither maintained nor incremented during power-down cycles. At each power-up, this register is set to its reset state. On each tick of the 1-kHz source, the milliseconds counter increments. With a 32-bit counter, a kernel can run up to 4,294,967,294 milliseconds or 49.7 days before it must deal with a counter wrap. The programmer can change the resolution of the millisecond counter to be 1, 2, 4, 8, or 16 milliseconds. This is programmed through bits in Persistent Register 0. WARNING: When the 32.768-kHz or 32.000-kHz crystal oscillator is selected as the source for the seconds counter, an anomaly is created between the time intervals of the millisecond counter and the seconds counter. That is, the manufacturing tolerance of the two crystals are such that 1000 millisecond counter increments are not exactly one second as measured by the real-time clock seconds counter. 23.6 Alarm Clock Function The alarm clock function allows an application to specify a future instant at which the chip should be awakened, i.e., if powered down, it can be powered up. The alarm clock setting is a CPU-accessible, 32-bit value that is continuously matched against the 32-bit real-time clock seconds counter. When the two values are equal, an alarm event is triggered. Persistent bits indicate whether an alarm event should power up the chip from its powered-down state. In addition to or instead of powering up the chip, the alarm event can also cause a CPU interrupt. Although these two functions can be enabled at the same time, one should remember that the CPU will only be interrupted if the chip is powered up at the time of the alarm event. NOTE: If the alarm is set to power up the chip in the event of an alarm and such an event occurs, then the only record of the cause of the wake-up is located in the analog side. At power-up, the analog side registers are copied to the digital shadow registers and the ALARM_WAKE bit in the Persistent register 0 is visible in the digital shadow register. If an alarm wake event occurs while the chip is powered up, the ALARM_WAKE bit will not be set in the persistent register because the chip was not woken up. The alarm must be "present" on an actual chip to perform this function (see the HW_RTC_STAT_ALARM_PRESENT bit description). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23-7 Real-Time Clock, Alarm, Watchdog, Persistent Bits 23.7 Watchdog Reset Function The watchdog reset is a CPU-configurable device. It is programmed by software to generate a chip-wide reset after HW_RTC_WATCHDOG milliseconds. The watchdog generates this reset if software does not rewrite this register before this time elapses. The watchdog timer decrements the register value once for every tick of the 1-kHz clock supplied from the RTC analog section (see Figure 23-1). The reset generated by the watchdog timer has no effect on the values retained in the master registers of the real-time clock seconds counter, alarm, or persistent registers (analog persistent storage). The watchdog timer is initially disabled and set to count 4,294,967,295 milliseconds before generating a watchdog reset. The watchdog timer does not run when the chip is in its powered-down state. Therefore, there is no master/shadow register pairing for the watchdog timer, and it must be reprogrammed after cycling power or resetting the block. The watchdog timer must be "present" on an actual chip to perform this function (see the HW_RTC_STAT_WATCHDOG_PRESENT bit description). 23.8 Programmable Registers This section describes the programmable registers of the real-time clock, including the watchdog register, alarm register, laser fuse registers, and persistent registers. 23.8.1 Real-Time Clock Control Register Description HW_RTC_CTRL HW_RTC_CTRL_SET HW_RTC_CTRL_CLR HW_RTC_CTRL_TOG 0x000 0x004 0x008 0x00C HW_RTC_CTRL is the control register for the RTC. i.MX23 Applications Processor Reference Manual, Rev. 1 23-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Real-Time Clock, Alarm, Watchdog, Persistent Bits Table 23-1. HW_RTC_CTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 SUPPRESS_COPY2ANALOG 0 5 0 4 0 3 0 2 0 1 0 0 ONEMSEC_IRQ_EN FORCE_UPDATE Table 23-2. HW_RTC_CTRL Bit Field Descriptions BITS 31 SFTRST 30 CLKGATE LABEL RW RESET RW 0x1 RW 0x1 DEFINITION 1= Hold real time clock digital side in soft reset state. This bit has no effect on the RTC analog. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. This bit has no effect on RTC analog. Reserved, write only zeroes. This bit is used for diagnostic purposes. 1= suppress the automatic copy that normally occurs to the analog side, whenever a shadow register is written. 0= Normal operation. Use SCT writes to set, clear, or toggle. This bit is how the software requests the update of the shadow registers from values in RTC analog. When software sets this bit, all eight of the shadow registers are updated from the corresponding values in the persistent registers in RTC analog. The state of this update operation is reflected on the STALEREGS bits on the STAT register, which are set to all ones upon an update request and are cleared by hardware as the update proceeds. Hardware clears this bit immediately after detecting it has been set. Software does not need to clear. Software must NOT look to the state of this bit to determine the status of the update operation, it must look to the STALEREG bits in the STAT register to determine when any given register has been updated and/or when the update operation is complete. Notice that the default value of this bit is 1, so that that a reset (either chip-wide or soft) always results in an update. 1= Enable Watchdog Timer to force chip wide resets. Use SCT writes to set, clear, or toggle. 1= one millisecond interrupt request status. Use SCT writes to clear this interrupt status bit. 1= Alarm Interrupt Status. Use SCT writes to clear this interrupt status bit. 29:7 6 RSVD0 SUPPRESS_COPY2ANALOG RO 0x0 RW 0x0 5 FORCE_UPDATE RW 0x1 4 3 2 WATCHDOGEN ONEMSEC_IRQ ALARM_IRQ RW 0x0 RW 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23-9 ALARM_IRQ_EN ONEMSEC_IRQ WATCHDOGEN ALARM_IRQ CLKGATE SFTRST RSVD0 Real-Time Clock, Alarm, Watchdog, Persistent Bits Table 23-2. HW_RTC_CTRL Bit Field Descriptions BITS LABEL 1 ONEMSEC_IRQ_EN 0 ALARM_IRQ_EN RW RESET RW 0x0 RW 0x0 DEFINITION 1= Enable one millisecond interrupt. Use SCT writes to set, clear, or toggle. 1= Enable Alarm Interrupt. Use SCT writes to set, clear, or toggle. DESCRIPTION: The contents of this register control the operation of the RTC portions implemented as an APBX peripheral running in the APBX clock domain. These functions only operate when the chip is in its full power up state. EXAMPLE: HW_RTC_CTRL_CLR(BM_RTC_CTRL_SFTRST); // remove the soft reset condition HW_RTC_CTRL_CLR(BM_RTC_CTRL_CLKGATE); // enable clocks within the RTC HW_RTC_CTRL_CLR(BM_RTC_CTRL_ALARM_IRQ); // reset the alarm interrupt by clearing its status bit 23.8.2 Real-Time Clock Status Register Description HW_RTC_STAT HW_RTC_STAT_SET HW_RTC_STAT_CLR HW_RTC_STAT_TOG Table 23-3. HW_RTC_STAT HW_RTC_STAT is the status register for the RTC. 0x010 0x014 0x018 0x01C 3 1 3 0 ALARM_PRESENT 2 9 WATCHDOG_PRESENT 2 8 XTAL32000_PRESENT 2 7 XTAL32768_PRESENT 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RTC_PRESENT STALE_REGS NEW_REGS RSVD1 Table 23-4. HW_RTC_STAT Bit Field Descriptions BITS LABEL 31 RTC_PRESENT 30 29 28 ALARM_PRESENT WATCHDOG_PRESENT XTAL32000_PRESENT RW RESET RO 0x1 RO 0x1 RO 0x1 RO 0x0 DEFINITION This read-only bit reads back a one if the RTC is present in the device. This read-only bit reads back a one if the Alarm function is present in the device. This read-only bit reads back a one if the Watchdog Timer function is present in the device. This read-only bit reads back a one if the 32.000-kHz crystal oscillator function is present in the device. i.MX23 Applications Processor Reference Manual, Rev. 1 23-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSVD0 Real-Time Clock, Alarm, Watchdog, Persistent Bits Table 23-4. HW_RTC_STAT Bit Field Descriptions BITS LABEL 27 XTAL32768_PRESENT 26:24 RSVD1 23:16 STALE_REGS RW RESET RO 0x0 RO 0x0 RO 0xFF DEFINITION This read-only bit reads back a one if the 32.768-kHz crystal oscillator function is present in the device. Reserved, write only zeroes. These read-only bits are set to one whenever the corresponding shadow register contents are older than the analog side contents. These bits are set by reset and cleared by the copy controller. They are also set by writing a one to the FORCE_UPDATE bit. These read-only bits are set to one whenever the corresponding shadow register contents are newer than the analog side contents. These bits are set by writing to the corresponding register and cleared by the copy controller. Reserved, write only zeroes. 15:8 NEW_REGS RO 0x00 7:0 RSVD0 RO 0x0 DESCRIPTION: This register reflects the current state of the RTC in terms of its enabled capabilities and the state of the persistent registers. EXAMPLE: while(HW_RTC_STAT.STALE_REGS !=0) { printf(" something is stale in one of the digital side registers // the copy controller will copy analog registers to digtial registers as required, // turning off staleregs bits as it goes about its business. } if(HW_RTC_STAT.WATCHDOG_PRESENT != 0) // then you can use the watchdog timer on this chip 23.8.3 Real-Time Clock Milliseconds Counter Description The millisecond count register provides a reliable elapsed time reference to the kernel with millisecond resolution. HW_RTC_MILLISECONDS HW_RTC_MILLISECONDS_SET HW_RTC_MILLISECONDS_CLR HW_RTC_MILLISECONDS_TOG Table 23-5. HW_RTC_MILLISECONDS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x020 0x024 0x028 0x02C COUNT Table 23-6. HW_RTC_MILLISECONDS Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x00000000 DEFINITION 32 bit milliseconds counter. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23-11 Real-Time Clock, Alarm, Watchdog, Persistent Bits DESCRIPTION: HW_RTC_MILLISECONDS provides access to the 32-bit millisecond counter. This counter is not a shadow register, i.e., the contents of this register are not preserved over power-down states. This counter increments once per millisecond based on a pulse from RTC analog which is derived from the 24.0-MHz crystal clock. This 1-kHz source hence does not vary as the APBX clock frequency is changed. The millisecond counter wraps at 4,294,967,294 milliseconds or 49.7 days. EXAMPLE: HW_RTC_MILLISECONDS_WR(0); // write an initial starting value to the milliseconds counter Count = HW_RTC_MILLISECONDS_RD(); // read the current value of the milliseconds counter. 23.8.4 Real-Time Clock Seconds Counter Description The real-time clock seconds counter is used to maintain real time for applications, even across certain chip power-down states. HW_RTC_SECONDS HW_RTC_SECONDS_SET HW_RTC_SECONDS_CLR HW_RTC_SECONDS_TOG Table 23-7. HW_RTC_SECONDS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x030 0x034 0x038 0x03C COUNT Table 23-8. HW_RTC_SECONDS Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0x00000000 DEFINITION Increments once per second. DESCRIPTION: HW_RTC_SECONDS provides access to the 32-bit real-time seconds counter. Both the shadow register on the digital side and the analog side register update every second. When the chip enters the power-down state, the shadow register is powered down and loses its state value. When the chip powers up, the analog side register contents are automatically copied to the shadow register. The reset value of 0x0 for the digital side register is only visible until the copy controller overwrites with the value from the analog side. The analog side register resets to zero only upon power-on reset (POR), i.e., when the battery is first inserted or whenever a battery-less part is plugged into USB power or into a wall transformer. Note that if a low frequency (32.000khz or 32.768khz) crystal is available in the system, then the seconds count and the milliseconds count will be derived from different clocks. Namely, the msec count is derived from the 24MHz crystal and the seconds count from the low-frequency crystal. This limits the precision of the relation between these two clocks. i.MX23 Applications Processor Reference Manual, Rev. 1 23-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Real-Time Clock, Alarm, Watchdog, Persistent Bits EXAMPLE: HW_RTC_SECONDS_WR(0); // write an initial value to the digital side. This value will // be automatically copied to the analog side rt_clock = HW_RTC_SECONDS_RD(); // read the 32 seconds counter value 23.8.5 Real-Time Clock Alarm Register Description HW_RTC_ALARM HW_RTC_ALARM_SET HW_RTC_ALARM_CLR HW_RTC_ALARM_TOG Table 23-9. HW_RTC_ALARM The 32-bit alarm value is matched against the 32-bit seconds counter to detect an alarm condition. 0x040 0x044 0x048 0x04C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 VALUE Table 23-10. HW_RTC_ALARM Bit Field Descriptions BITS 31:0 VALUE LABEL RW RESET RW 0x00000000 DEFINITION Seconds match-value used to trigger assertion of the RTC alarm. DESCRIPTION: The 32-bit alarm value can be used to awaken the chip from a power-down state or simply to cause an interrupt at a specific time. When the chip enters the power-down state, the shadow register is powered down and loses its state value. When the chip powers up, the analog side register contents are automatically copied to the shadow register. The reset value of 0x0 for the digital side register is only visible until the copy controller overwrites with the value from the analog side. The analog side register resets to zero only upon power-on reset (POR), i.e., when the battery is first inserted or whenever a battery-less part is plugged into a power USB or into a wall transformer. EXAMPLE: HW_RTC_ALARM_WR(60); // generate rtc alarm after 60 seconds 23.8.6 Watchdog Timer Register Description HW_RTC_WATCHDOG HW_RTC_WATCHDOG_SET HW_RTC_WATCHDOG_CLR HW_RTC_WATCHDOG_TOG 0x050 0x054 0x058 0x05C The 32-bit watch dog timer can be used to reset the chip if enabled and not adequately serviced. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23-13 Real-Time Clock, Alarm, Watchdog, Persistent Bits Table 23-11. HW_RTC_WATCHDOG 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 COUNT Table 23-12. HW_RTC_WATCHDOG Bit Field Descriptions BITS 31:0 COUNT LABEL RW RESET RW 0xffffffff DEFINITION If the watchdog timer decrements to zero and the watchdog timer reset is enabled, then the chip will be reset. The watchdog timer decrements once per millisecond, when enabled. DESCRIPTION: The 32-bit watchdog timer will reset the chip upon decrementing to zero, if this function is enabled and present on the chip. The 1-kHz source is based on a msec pulse from RTC analog which is derived from the 24-MHz crystal oscillator and hence does not vary when the APBX clock is changed. EXAMPLE: HW_RTC_WATCHDOG_WR(10000); // reload the watchdog and keep it from resetting the chip 23.8.7 Persistent State Register 0 Description HW_RTC_PERSISTENT0 HW_RTC_PERSISTENT0_SET HW_RTC_PERSISTENT0_CLR HW_RTC_PERSISTENT0_TOG Table 23-13. HW_RTC_PERSISTENT0 The 32-bit persistent registers are used to retain certain control states during chip wide power-down states. 0x060 0x064 0x068 0x06C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 SPARE_ANALOG 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 AUTO_RESTART 1 6 DISABLE_PSWITCH 1 5 1 4 1 3 DISABLE_XTALOK 1 2 1 1 1 0 0 9 0 8 0 7 ALARM_WAKE 0 6 XTAL32_FREQ 0 5 XTAL32KHZ_PWRUP 0 4 XTAL24MHZ_PWRUP 0 3 0 2 0 1 ALARM_WAKE_EN 0 0 CLOCKSOURCE LOWERBIAS i.MX23 Applications Processor Reference Manual, Rev. 1 23-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor ALARM_EN MSEC_RES LCK_SECS Real-Time Clock, Alarm, Watchdog, Persistent Bits Table 23-14. HW_RTC_PERSISTENT0 Bit Field Descriptions BITS LABEL 31:18 SPARE_ANALOG RW RESET RW 0x0 DEFINITION This field is broken into the following fields: ADJ_POSLIMITBUCK - bits [31:28]: This field can be used to allow dcdc startup with lower Liion battery voltages. With the default value of 0x0, the dcdc converter will not startup below 2.83V, and increasing this value will lower the Liion startup voltage. It is not recommended to set a value higher than 0x6. The value of this field effects the minimum startup voltage as follows: 0x0=2.83V, 0x1=2.78V, 0x2=2.73V, 0x3=2.68V, 0x4=2.62V, 0x5=2.57V, 0x6=2.52V, 0x7-0xF=2.48V. SPARE_ANALOG - bits [27:20]: Reserved. RELEASE_GND - bit [19]: Set to one to remove the pulldown resistors on the headphone outputs. This bit should be cleared after powering down the headphone, and before the chip is powered down for optimum anti-pop performance. ENABLE_LRADC_PWRUP - bit [18]: Set to one to enable a low voltage on LRADC0 to powerup the chip. This is to support powerup via open drain pulldowns connected to LRADC0. Ths requires external circuitry and this bit should not be set unless the correct circuitry is present. Freescale will provide information on the external circuitry, if this functionality is required. Set to one to enable the chip to automatically power up approximately 180 ms after powering down. Disables the pswitch pin startup functionality unless the voltage on the pswitch pin goes above the VDDXTAL pin voltage by a threshold voltage. Typically, this voltage is created by pulling pswitch up with a current limiting resistor to a higher voltage, such as the Liion battery voltage. Reduce bias current of 24mhz crystal. b00: nominal, b01: -25%, b10: -25%, b11: -50%, Set to one to disable the circuit that resets the chip if 24-MHz frequency falls below 2 MHz. The circuit defaults to enabled and will power down the device if the 24-MHz stop oscillating for any reason. This bit field encodes the value of the millisecond count resolution in a one-hot format. Resolutions supported are: 1, 2, 4, 8, and 16 msec. The bitfield directly gives the resolution without need for decode. Set when the chip is powered up by an alarm event from rtc_ana. Can then be cleared by software as desired. If CLOCKSOURCE (bit 0 of this register) is one, then this bit gives the exact frequency of the 32kHz crystal. If this bit is zero, the frequency is 32.768kHZ, if it is one, the frequency is 32.000kHz. If CLOCKSOURCE is zero, the value of this bit is immaterial. 17 16 AUTO_RESTART DISABLE_PSWITCH RW 0x0 RW 0x0 15:14 LOWERBIAS RW 0x0 13 DISABLE_XTALOK RW 0x0 12:8 MSEC_RES RW 0x1 7 ALARM_WAKE RW 0x0 6 XTAL32_FREQ RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23-15 Real-Time Clock, Alarm, Watchdog, Persistent Bits Table 23-14. HW_RTC_PERSISTENT0 Bit Field Descriptions BITS LABEL 5 XTAL32KHZ_PWRUP RW RESET RW 0x0 DEFINITION Set to one to power up the 32kHz crystal oscillator. Set to zero to disable the oscillator. This bit controls the oscillator at all times (chip powered on or not). Set to one to keep the 24.0-MHz crystal oscillator powered up while the chip is powered down. Set to zero to disable during chip power down. Note: The oscillator is always on while the chip is powered on. Set to one to lock down the seconds count. Once this bit is written with a 1, the user will not be able to either write to the seconds register or to change this bit back to a zero -- except by removing the battery. Set this bit to one to enable the detection of an alarm event. This bit must be turned on before an alarm event can awaken a powered-down device, or before it can generate an alarm interrupt to a powered-up CPU. When the alarm is not present in the device (as indicated by the fuse bits) the copy of shadow0 to persistent0 will not allow bit[2] to be written and persistent bit[2] will always read back 0, regardless of the values in the shadow register. This bit is set to one to upon the arrival of an alarm event that powers up the chip. ALARM_EN must be set to one to enable the detection of an alarm event. This bit is reset by writing a zero directly to the shadow register, which causes the copy controller to move it across to the analog domain. Set to one to select the 32-kHz crystal oscillator as the source for the 32-kHz clock domain used by the RTC analog domain circuits. Set to zero to select the 24-MHz crystal oscillator as the source for generating the 32-kHz clock domain used by the RTC analog domain circuits. 4 XTAL24MHZ_PWRUP RW 0x0 3 LCK_SECS RW 0x0 2 ALARM_EN RW 0x0 1 ALARM_WAKE_EN RW 0x0 0 CLOCKSOURCE RW 0x0 DESCRIPTION: The general persistent bits are available for software use. The register initalizes to a known reset pattern. The copy controller overwrites the digital reset values very soon after power on, but not in zero time. EXAMPLE: HW_RTC_PERSISTENT0_SET(BM_RTC_PERSISTENT0_ALARM_WAKE_EN); // wake up the chip if the alarm event occurs HW_RTC_PERSISTENT0_SET(BM_RTC_PERSISTENT0_CLOCKSOURCE); // select the 32KHz oscillator as the source for the RTC analog clock 23.8.8 Persistent State Register 1 Description HW_RTC_PERSISTENT1 HW_RTC_PERSISTENT1_SET HW_RTC_PERSISTENT1_CLR HW_RTC_PERSISTENT1_TOG 0x070 0x074 0x078 0x07C The 32-bit persistent registers are used to retain certain control states during chip wide power-down states. i.MX23 Applications Processor Reference Manual, Rev. 1 23-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Real-Time Clock, Alarm, Watchdog, Persistent Bits Table 23-15. HW_RTC_PERSISTENT1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 GENERAL Table 23-16. HW_RTC_PERSISTENT1 Bit Field Descriptions BITS LABEL 31:0 GENERAL RW RESET RW 0x0000 DEFINITION Firmware use, defined as follows: ENUMERATE_500MA_TWICE = 0x1000 Enumerate at 500mA twice before dropping back to 100mA. USB_BOOT_PLAYER_MODE = 0x0800 Boot to player when connected to USB. SKIP_CHECKDISK = 0x0400 Run Checkdisk flag. USB_LOW_POWER_MODE = 0x0200 USB Hi/Lo Current select. OTG_HNP_BIT = 0x0100 HNP has been required if set to one. OTG_ATL_ROLE_BIT = 0x0080 USB role. DESCRIPTION: The register initalizes to a known reset pattern. The copy controller overwrites this digital reset value very soon after power on but not in zero time. EXAMPLE: HW_RTC_PERSISTENT1_WR(0x12345678); // this write will ultimately push data to the analog side via the copy controller 23.8.9 Persistent State Register 2 Description HW_RTC_PERSISTENT2 HW_RTC_PERSISTENT2_SET HW_RTC_PERSISTENT2_CLR HW_RTC_PERSISTENT2_TOG Table 23-17. HW_RTC_PERSISTENT2 The 32-bit persistent registers are used to retain certain control states during chip-wide power-down states. 0x080 0x084 0x088 0x08C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 GENERAL Table 23-18. HW_RTC_PERSISTENT2 Bit Field Descriptions BITS LABEL 31:0 GENERAL RW RESET RW 0x00000000 DEFINITION FIRMWARE/SOFTWARE DESCRIPTION: The register initalizes to a known reset pattern. The copy controller overwrites this digital reset value very soon after power on but not in zero time. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23-17 Real-Time Clock, Alarm, Watchdog, Persistent Bits EXAMPLE: HW_RTC_PERSISTENT2_WR(0x12345678); // this write will ultimately push data to the analog side via the copy controller 23.8.10 Persistent State Register 3 Description The 32-bit persistent registers are used to retain certain control states during chip-wide power-down states. HW_RTC_PERSISTENT3 HW_RTC_PERSISTENT3_SET HW_RTC_PERSISTENT3_CLR HW_RTC_PERSISTENT3_TOG Table 23-19. HW_RTC_PERSISTENT3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x090 0x094 0x098 0x09C GENERAL Table 23-20. HW_RTC_PERSISTENT3 Bit Field Descriptions BITS LABEL 31:0 GENERAL RW RESET RW 0x00000000 DEFINITION FIRMWARE/SOFTWARE DESCRIPTION: The register initalizes to a known reset pattern. The copy controller overwrites this digital reset value very soon after power on but not in zero time. EXAMPLE: HW_RTC_PERSISTENT3_WR(0x12345678); // this write will ultimately push data to the analog side via the copy controller 23.8.11 Persistent State Register 4 Description The 32-bit persistent registers are used to retain certain control states during chip-wide power-down states. HW_RTC_PERSISTENT4 HW_RTC_PERSISTENT4_SET HW_RTC_PERSISTENT4_CLR HW_RTC_PERSISTENT4_TOG Table 23-21. HW_RTC_PERSISTENT4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0A0 0x0A4 0x0A8 0x0AC GENERAL Table 23-22. HW_RTC_PERSISTENT4 Bit Field Descriptions BITS LABEL 31:0 GENERAL RW RESET RW 0x00000000 DEFINITION FIRMWARE/SOFTWARE i.MX23 Applications Processor Reference Manual, Rev. 1 23-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Real-Time Clock, Alarm, Watchdog, Persistent Bits DESCRIPTION: The register initalizes to a known reset pattern. The copy controller overwrites this digital reset value very soon after power on but not in zero time. EXAMPLE: HW_RTC_PERSISTENT4_WR(0x12345678); // this write will ultimately push data to the analog side via the copy controller 23.8.12 Persistent State Register 5 Description The 32-bit persistent registers are used to retain certain control states during chip-wide power-down states. HW_RTC_PERSISTENT5 HW_RTC_PERSISTENT5_SET HW_RTC_PERSISTENT5_CLR HW_RTC_PERSISTENT5_TOG Table 23-23. HW_RTC_PERSISTENT5 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x0B0 0x0B4 0x0B8 0x0BC GENERAL Table 23-24. HW_RTC_PERSISTENT5 Bit Field Descriptions BITS LABEL 31:0 GENERAL RW RESET RW 0x00000000 DEFINITION FIRMWARE/SOFTWARE DESCRIPTION: The register initalizes to a known reset pattern. The copy controller overwrites this digital reset value very soon after power on but not in zero time. EXAMPLE: HW_RTC_PERSISTENT5_WR(0x12345678); // this write will ultimately push data to the analog side via the copy controller 23.8.13 Real-Time Clock Debug Register Description This 32-bit register provides debug read access to various internal states for diagnostic purposes. HW_RTC_DEBUG HW_RTC_DEBUG_SET HW_RTC_DEBUG_CLR HW_RTC_DEBUG_TOG 0x0C0 0x0C4 0x0C8 0x0CC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23-19 Real-Time Clock, Alarm, Watchdog, Persistent Bits Table 23-25. HW_RTC_DEBUG 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 WATCHDOG_RESET_MASK 0 0 Table 23-26. HW_RTC_DEBUG Bit Field Descriptions BITS LABEL 31:2 RSVD0 1 WATCHDOG_RESET_MASK 0 WATCHDOG_RESET RW RESET RO 0x0 RW 0x0 RO 0x0 DEFINITION Debug read-only view of various state machine bits. When set, mask the reset generation by the watchdog timer for testing purposes. Reflects the state of the watchdog reset. Used for testing purposes so the watchdog can be tested without resetting part. When set, Watchdog reset is asserted. DESCRIPTION: Read-only view into the internals of the digital side of the RTC for diagnostic purposes. EXAMPLE: DebugValue = HW_RTC_DEBUG_RD(); // read debug register value 23.8.14 Real-Time Clock Version Register Description Version register. HW_RTC_VERSION Table 23-27. HW_RTC_VERSION 3 1 3 0 2 9 2 8 MAJOR 0x0D0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 i.MX23 Applications Processor Reference Manual, Rev. 1 23-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor WATCHDOG_RESET RSVD0 0 0 Real-Time Clock, Alarm, Watchdog, Persistent Bits Table 23-28. HW_RTC_VERSION Bit Field Descriptions BITS 31:24 MAJOR 23:16 MINOR 15:0 STEP LABEL RW RESET RO 0x02 RO 0x0 RO 0x0 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. EXAMPLE: VersionValue = HW_RTC_VERSION_RD(); // read debug register value RTC Block v2.0, Revision 1.75 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23-21 Real-Time Clock, Alarm, Watchdog, Persistent Bits i.MX23 Applications Processor Reference Manual, Rev. 1 23-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 24 Pulse-Width Modulator (PWM) Controller This chapter describes the pulse-width modulator (PWM) controller included on the i.MX23 and how to use it. Programmable registers are described in Section 24.4, "Programmable Registers." 24.1 Overview The i.MX23 contains five PWM output controllers that can be used in place of GPIO pins. Applications include LED and backlight brightness control. Independent output control of each phase allows 0, 1, or high-impedance to be independently selected for the active and inactive phases. Individual outputs can be run in lock step with guaranteed non-overlapping portions for differential drive applications. Figure 24-1 shows the block diagram of the PWM controller. The controller does not use DMA. Initial values of Period, Active, and Inactive widths are set for each desired channel. The outputs are selected by phase and then the desired PWM channels are simultaneously enabled. This effectively launches the PWM outputs to autonomously drive their loads without further intervention. 24.2 Operation Each PWM channel has two control registers that are used to specify the channel output: HW_PWM_ACTIVEn and HW_PWM_PERIODn. When programming a channel, it is important to remember that there is an order dependence for register writes. * * The HW_PWM_ACTIVEn register must be written first, followed by HW_PWM_PERIODn. If the order is reversed, the parameters written to the HW_PWM_ACTIVEn register will not take effect in the hardware. The hardware waits for a HW_PWM_PERIODn register write to update the hardware with the values in both registers. This register write order dependence allows smooth on-the-fly reprogramming of the channel. Also, when the user reprograms the channel in this manner, the new register values will not take effect until the beginning of a new output period. This eliminates the potential for output glitches that could occur if the registers were updated while the channel was enabled and in the middle of a cycle. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 24-1 Pulse-Width Modulator (PWM) Controller ARM Core AHB SRAM 24-MHz XTAL Osc. AHB Slave AHB Master Divide by n Shared DMA AHB-to-APBX Bridge APBX Master APBX PWM Programmable Registers Act.,Inact. State0 Period0 24-MHz XTAL Osc. Active0,Inactive0 Active0 >= Count0 Count0 < Inactive0 E.L. Backlight PWM0 1/m, m=1,2,4, 8,16, 64, 256,1024 Count0 resets at Period0 ACT E.L. Backlight PWM1 Active1,Inactive1 1/m, m= 1,2,4, 8,16, 64, 256,1024 Count1 resets at Period1 Active1 >= Count1 Count1 < Inactive1 ACT Active2,Inactive2 1/m, m=1,2,4, 8,16, 64, 256,1024 Count2 resets at Period2 Active2 >= Count2 Count2 < Inactive2 E.L. Backlight PWM2 ACT Application PWM3 Active3,Inactive3 1/m, m=1,2,4, 8,16, 64, 256,1024 Count3 resets at Period3 Active3 >= Count3 Count3 < Inactive3 ACT Host Power PWM4 ACT Active4,Inactive4 1/m, m=1,2,4, 8,16, 64, 256,1024 Count4 resets at Period4 Active4 >= Count4 Count4 < Inactive4 Figure 24-1. Pulse-Width Modulation Controller (PWM) Block Diagram i.MX23 Applications Processor Reference Manual, Rev. 1 24-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pulse-Width Modulator (PWM) Controller Each channel has a dedicated internal 16-bit counter that increments once for each divided clock period presented from the clock divider: * The internal counter resets when it reaches the value stored in the channel control registers, e.g., HW_PWM_PERIOD0_PERIOD. * The Active flip-flop is set to 1 when the internal counter reaches the value stored in HW_PWM_ACTIVE0_ACTIVE. * It remains high until the internal counter exceeds the value stored in HW_PWM_ACTIVE0_INACTIVE. These two values define the starting and ending points for the logically "active" portion of the waveform. As shown in Figure 24-2, the actual state on the output for each phase, e.g., active or inactive, is completely controlled by the active and inactive state values in the channel control registers. HW_PWM_ACTIVE0_ACTIVE HW_PWM_ACTIVE0_INACTIVE HW_PWM_PERIOD0_PERIOD PERIOD INACTIVE ACTIVE ACTIVE_FF PWM0 Output inactive_state[1:0] active_state[1:0] inactive_state[1:0] active_state[1:0] HW_PWM_PERIOD0_ACTIVE_STATE HW_PWM_PERIOD0_INACTIVE_STATE Figure 24-2. PWM Output Example The actual values obtainable on the output are shown in Figure 24-2. Notice that one possible state is to turn off the output driver to provide a high-Z output. This is useful for external circuits that drive E.L. backlights and for direct drive of LEDs. By setting up two channels in lock step and by setting their low and high states to opposite values, one can generate a differential signal pair that alternates between pulling to Vss and floating to high-Z. By creating an appropriate offset in the settings of the two channels with the same period and the same enables, one can generate differential drive pulses with digitally guaranteed non-overlapping intervals suitable for controlling high-voltage switches. In Figure 24-3, a differential pair is established using Channel 0 and Channel 1. The period is set for 1280 divided clocks for both channels. All active phases are set for 600 divided clocks. There is a 40 divided clock guaranteed off-time between each active phase. Since this is based on a crystal oscillator, it is a i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 24-3 Pulse-Width Modulator (PWM) Controller very stable non-overlapping period. The total period is also a very stable crystal-oscillator-based time interval. In this example, the active phases are pulled to Vss (ground), while the inactive phases are allowed to float to a high-Z state. 600 40 680 40 600 640 ACTIVE_FF0 ACTIVE_FF1 PWM0 Output hi-Z PWM1 Output digitally guaranteed HW_PWM_PERIOD0_PERIOD = 1280 HW_PWM_ACTIVE0_ACTIVE = 0 HW_PWM_ACTIVE0_INACTIVE = 600 HW_PWM_PERIOD0_ACTIVE_STATE = 10 HW_PWM0BR_INACTIVE_STATE = 00 HW_PWM_PERIOD1= 1280 HW_PWM_ACTIVE1 = 640 HW_PWM_INACTIVE1 = 1240 HW_PWM_ACTIVE1_STATE = 10 HW_PWM_INACTIVE1_STATE = 00 Vss Figure 24-3. PWM Differential Output Pair Example Figure 24-4 shows the generation of the PWM Channel 3 output. This channel controls the output pin when PWM control is selected in PINCTRL block and HW_PWM_CTRL_PWM3_ENABLE is set to 1. The output pin can be set to a 0, a 1, or left to float in the high-impedance state. These choices can be made independently for either the active or inactive phase of the output. 24.2.1 Multi-Chip Attachment Mode The multi-chip attachment mode (MATT) allows a 24-MHz or 32KHz crystal clock that is an input to the i.MX23 to be routed to the PWM output pins. In this case, the normal PWM programming parameters (e.g., PERIOD, ACTIVE, etc.) are ignored. This mode allows for supplying and controlling the crystal clock for external application interfaces, as shown in Figure 24-4. i.MX23 Applications Processor Reference Manual, Rev. 1 24-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pulse-Width Modulator (PWM) Controller 24 MHz or 32 KHz Crystal Clock Divide by 1 PWM ACTIVE_STATE [BIT 0] 1 1 0 0 PWM OUTPUT PWM INACTIVE_STATE [BIT 0] ACTIVE FF MATT mode bit PWM ACTIVE_STATE [BIT 1] PWM INACTIVE_STATE [BIT 1] PWM ENABLE BIT CLOCK GATE 1 0 Figure 24-4. PWM Output Driver 24.2.2 Channel 2 Analog Enable Function The output generation for channel 2 is slightly different than shown in Figure 24-4. In this channel, there is an additional enable that is controlled from the analog LRADC block. This signal is synchronized in the XTAL domain and ANDed with the PWM ENABLE bit. So, in this case, either enable source can disable the output. Also, this analog enable control signal can be disabled through the PWM2_ANA_CTRL_ENABLE bit in the HW_PWM_CTRL register. When disabled, Channel 2 behaves identically to the other channels. 24.2.3 Channel Output Cutoff Using Module Clock Gate Whenever the clkgate is enabled (gated) the output from all PWM channels is hi-Z. If the clock gate is asserted while PWM is enabled and generating an output signal the output is immediately disabled. This will not affect the current state, programming or enables of the pwm channels themselves. When the clkgate is de-asserted, the PWM outputs will resume according to their programmed parameters and current states. Therefore glitches on the enabled channel outputs will likely occur when the clkgate state is changed. All 5 channels will function identically in this regard. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 24-5 Pulse-Width Modulator (PWM) Controller 24.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. 24.4 Programmable Registers The following registers are available for CPU programmer access and control of the PWM controller. 24.4.1 PWM Control and Status Register Description The PWM Control and Status Register specifies the reset state, availability, and the enables for the five PWM units. HW_PWM_CTRL HW_PWM_CTRL_SET HW_PWM_CTRL_CLR HW_PWM_CTRL_TOG Table 24-1. HW_PWM_CTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 OUTPUT_CUTOFF_EN 0x000 0x004 0x008 0x00C 0 5 PWM2_ANA_CTRL_ENABLE 0 4 0 3 0 2 0 1 0 0 PWM4_PRESENT PWM3_PRESENT PWM2_PRESENT PWM1_PRESENT PWM0_PRESENT PWM4_ENABLE PWM3_ENABLE PWM2_ENABLE PWM1_ENABLE Table 24-2. HW_PWM_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION This bit must be cleared to 0 for normal operation. When set to 1, it forces a block-wide reset. This bit must be cleared to 0 for normal operation. When set to 1, it gates off the clocks to the block. 0 = PWM4 is not present in this product. 0 = PWM3 is not present in this product. 0 = PWM2 is not present in this product. 0 = PWM1 is not present in this product. 0 = PWM0 is not present in this product. Reserved. 30 29 28 27 26 25 24:7 CLKGATE PWM4_PRESENT PWM3_PRESENT PWM2_PRESENT PWM1_PRESENT PWM0_PRESENT RSRVD1 RW 0x1 RO RO RO RO RO RO 0x1 0x1 0x1 0x1 0x1 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 24-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor PWM0_ENABLE CLKGATE RSRVD1 SFTRST Pulse-Width Modulator (PWM) Controller Table 24-2. HW_PWM_CTRL Bit Field Descriptions BITS LABEL 6 OUTPUT_CUTOFF_EN RW RESET RW 0x0 DEFINITION When asserted this bit enables the block to automatically Hi-Z state the outputs whenever the clkgate is asserted. The default is enabled. Setting this bit to 1 enables PWM Channel 2 output to be enabled by analog circuitry outside this block much the way the PWM2_ENABLE bit controls it. Note that the PWM2_ENABLE bit must still be set and the channel must still be programmed normally for the PWM output to cycle. The PWM2_ENABLE bit acts like a master switch in this context. Enables PWM channel 4 to begin cycling when set to 1. To enable PWM4 onto the output pin, the pin control registers must programmed accordingly. Enables PWM channel 3 to begin cycling when set to 1. To enable PWM3 onto the output pin, the pin control registers must programmed accordingly. Enables PWM channel 2 to begin cycling when set to 1. To enable PWM2 onto the output pin, the pin control registers must programmed accordingly. Enables PWM channel 1 to begin cycling when set to 1. To enable PWM1 onto the output pin, the pin control registers must programmed accordingly. Enables PWM channel 0 to begin cycling when set to 1. To enable PWM0 onto the output pin, the pin control registers must programmed accordingly. 5 PWM2_ANA_CTRL_ENABLE RW 0x0 4 PWM4_ENABLE RW 0x0 3 PWM3_ENABLE RW 0x0 2 PWM2_ENABLE RW 0x0 1 PWM1_ENABLE RW 0x0 0 PWM0_ENABLE RW 0x0 DESCRIPTION: This register specifies the reset state, availability, and the enables for the five PWM units. EXAMPLE: HW_PWM_CTRL_WR(0x0000001f); // Enable all channels 24.4.2 PWM Channel 0 Active Register Description HW_PWM_ACTIVE0 HW_PWM_ACTIVE0_SET HW_PWM_ACTIVE0_CLR HW_PWM_ACTIVE0_TOG Table 24-3. HW_PWM_ACTIVE0 The PWM Channel 0 Active Register specifies the active time and inactive time for Channel 0. 0x010 0x014 0x018 0x01C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 INACTIVE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 ACTIVE 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 24-7 Pulse-Width Modulator (PWM) Controller Table 24-4. HW_PWM_ACTIVE0 Bit Field Descriptions BITS LABEL 31:16 INACTIVE RW RESET RW 0x0 DEFINITION Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 15:0 ACTIVE RW 0x0 DESCRIPTION: This register contains the active time and inactive time programming parameters for Channel 0. EXAMPLE: HW_PWM_ACTIVEn_WR(0, 0x000000ff); // Set active and inactive counts 24.4.3 PWM Channel 0 Period Register Description The PWM Channel 0 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. HW_PWM_PERIOD0 HW_PWM_PERIOD0_SET HW_PWM_PERIOD0_CLR HW_PWM_PERIOD0_TOG Table 24-5. HW_PWM_PERIOD0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 MATT_SEL 0x020 0x024 0x028 0x02C 2 3 2 2 2 1 2 0 1 9 INACTIVE_STATE 1 8 1 7 ACTIVE_STATE 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD2 Table 24-6. HW_PWM_PERIOD0 Bit Field Descriptions BITS LABEL 31:25 RSRVD2 MATT_SEL 24 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM0 output pin for inter-chip signaling. 23 MATT RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 24-8 Preliminary--Subject to Change Without Notice PERIOD MATT CDIV Freescale Semiconductor Pulse-Width Modulator (PWM) Controller Table 24-6. HW_PWM_PERIOD0 Bit Field Descriptions BITS 22:20 CDIV LABEL RW RESET RW 0x0 DEFINITION Clock divider ratio to apply to the crystal clock frequency (24.0MHz) that times the PWM output signal. DIV_1 = 0x0 Divide by 1. DIV_2 = 0x1 Divide by 2. DIV_4 = 0x2 Divide by 4. DIV_8 = 0x3 Divide by 8. DIV_16 = 0x4 Divide by 16. DIV_64 = 0x5 Divide by 64. DIV_256 = 0x6 Divide by 256. DIV_1024 = 0x7 Divide by 1024. 19:18 INACTIVE_STATE RW 0x0 The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to hi-Z. HI_Z = 0x0 Inactive state sets PWM output to high-impedance. 0 = 0x2 Inactive state sets PWM output to 0 (low). 1 = 0x3 Inactive state sets PWM output to 1 (high). 17:16 ACTIVE_STATE RW 0x0 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z = 0x0 Active state sets PWM output to high-impedance. 0 = 0x2 Active state sets PWM output to 0 (low). 1 = 0x3 Active state sets PWM output to 1 (high). 15:0 PERIOD RW 0x0 Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. DESCRIPTION: This register contains the programming paramters for multi-chip attachment mode, clock divider value, active high, low values and period for channel 0. EXAMPLE: HW_PWM_PERIODn_WR(0, 0x00000b1f); // Set up period and active/inactive output states 24.4.4 PWM Channel 1 Active Register Description HW_PWM_ACTIVE1 HW_PWM_ACTIVE1_SET HW_PWM_ACTIVE1_CLR HW_PWM_ACTIVE1_TOG Table 24-7. HW_PWM_ACTIVE1 The PWM Channel 1 Active Register specifies the active time and inactive time for Channel 1. 0x030 0x034 0x038 0x03C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 INACTIVE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 ACTIVE 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 24-9 Pulse-Width Modulator (PWM) Controller Table 24-8. HW_PWM_ACTIVE1 Bit Field Descriptions BITS LABEL 31:16 INACTIVE RW RESET RW 0x0 DEFINITION Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 15:0 ACTIVE RW 0x0 DESCRIPTION: The PWM Active register specifies the active time and inactive time for channel 1. EXAMPLE: HW_PWM_ACTIVEn_WR(1, 0x000000ff); // Set active and inactive counts 24.4.5 PWM Channel 1 Period Register Description The PWM Channel 1 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. HW_PWM_PERIOD1 HW_PWM_PERIOD1_SET HW_PWM_PERIOD1_CLR HW_PWM_PERIOD1_TOG Table 24-9. HW_PWM_PERIOD1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 MATT_SEL 0x040 0x044 0x048 0x04C 2 3 2 2 2 1 2 0 1 9 INACTIVE_STATE 1 8 1 7 ACTIVE_STATE 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD2 Table 24-10. HW_PWM_PERIOD1 Bit Field Descriptions BITS LABEL 31:25 RSRVD2 MATT_SEL 24 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM1 output pin for inter-chip signaling. 23 MATT RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 24-10 Preliminary--Subject to Change Without Notice PERIOD MATT CDIV Freescale Semiconductor Pulse-Width Modulator (PWM) Controller Table 24-10. HW_PWM_PERIOD1 Bit Field Descriptions BITS 22:20 CDIV LABEL RW RESET RW 0x0 DEFINITION Clock divider ratio to apply to the crystal clock frequency (24.0 MHz) that times the PWM output signal. DIV_1 = 0x0 Divide by 1. DIV_2 = 0x1 Divide by 2. DIV_4 = 0x2 Divide by 4. DIV_8 = 0x3 Divide by 8. DIV_16 = 0x4 Divide by 16. DIV_64 = 0x5 Divide by 64. DIV_256 = 0x6 Divide by 256. DIV_1024 = 0x7 Divide by 1024. 19:18 INACTIVE_STATE RW 0x0 The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z = 0x0 Inactive state sets PWM output to high-impedance. 0 = 0x2 Inactive state sets PWM output to 0 (low). 1 = 0x3 Inactive state sets PWM output to 1 (high). 17:16 ACTIVE_STATE RW 0x0 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z = 0x0 Active state sets PWM output to high-impedance. 0 = 0x2 Active state sets PWM output to 0 (low). 1 = 0x3 Active state sets PWM output to 1 (high). 15:0 PERIOD RW 0x0 Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. DESCRIPTION: This register contains the programming paramters for multi-chip attachment mode, clock divider value, active high, low values and period for channel 1. EXAMPLE: HW_PWM_PERIODn_WR(1, 0x00000b1f); // Set up period and active/inactive output states 24.4.6 PWM Channel 2 Active Register Description HW_PWM_ACTIVE2 HW_PWM_ACTIVE2_SET HW_PWM_ACTIVE2_CLR HW_PWM_ACTIVE2_TOG Table 24-11. HW_PWM_ACTIVE2 The PWM Channel 2 Active Register specifies the active time and inactive time for Channel 2. 0x050 0x054 0x058 0x05C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 INACTIVE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 ACTIVE 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 24-11 Pulse-Width Modulator (PWM) Controller Table 24-12. HW_PWM_ACTIVE2 Bit Field Descriptions BITS LABEL 31:16 INACTIVE RW RESET RW 0x0 DEFINITION Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 15:0 ACTIVE RW 0x0 DESCRIPTION: This register contains the active time and inactive time programming parameters for Channel 2. EXAMPLE: HW_PWM_ACTIVEn_WR(2, 0x000000ff); // Set active and inactive counts 24.4.7 PWM Channel 2 Period Register Description The PWM Channel 2 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. HW_PWM_PERIOD2 HW_PWM_PERIOD2_SET HW_PWM_PERIOD2_CLR HW_PWM_PERIOD2_TOG Table 24-13. HW_PWM_PERIOD2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 MATT_SEL 0x060 0x064 0x068 0x06C 2 3 2 2 2 1 2 0 1 9 INACTIVE_STATE 1 8 1 7 ACTIVE_STATE 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD2 Table 24-14. HW_PWM_PERIOD2 Bit Field Descriptions BITS LABEL 31:25 RSRVD2 MATT_SEL 24 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM2 output pin for inter-chip signaling. 23 MATT RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 24-12 Preliminary--Subject to Change Without Notice PERIOD MATT CDIV Freescale Semiconductor Pulse-Width Modulator (PWM) Controller Table 24-14. HW_PWM_PERIOD2 Bit Field Descriptions BITS 22:20 CDIV LABEL RW RESET RW 0x0 DEFINITION Clock divider ratio to apply to the crystal clock frequency (24.0 MHz) that times the PWM output signal. DIV_1 = 0x0 Divide by 1. DIV_2 = 0x1 Divide by 2. DIV_4 = 0x2 Divide by 4. DIV_8 = 0x3 Divide by 8. DIV_16 = 0x4 Divide by 16. DIV_64 = 0x5 Divide by 64. DIV_256 = 0x6 Divide by 256. DIV_1024 = 0x7 Divide by 1024. 19:18 INACTIVE_STATE RW 0x0 The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z = 0x0 Inactive state sets PWM output to high-impedance. 0 = 0x2 Inactive state sets PWM output to 0 (low). 1 = 0x3 Inactive state sets PWM output to 1 (high). 17:16 ACTIVE_STATE RW 0x0 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z = 0x0 Active state sets PWM output to high-impedance. 0 = 0x2 Active state sets PWM output to 0 (low). 1 = 0x3 Active state sets PWM output to 1 (high). 15:0 PERIOD RW 0x0 Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. DESCRIPTION: This register contains the programming paramters for multi-chip attachment mode, clock divider value, active high, low values and period for channel 2. EXAMPLE: HW_PWM_PERIODn_WR(2, 0x00000b1f); // Set up period and active/inactive output states 24.4.8 PWM Channel 3 Active Register Description HW_PWM_ACTIVE3 HW_PWM_ACTIVE3_SET HW_PWM_ACTIVE3_CLR HW_PWM_ACTIVE3_TOG Table 24-15. HW_PWM_ACTIVE3 The PWM Channel 3 Active Register specifies the active time and inactive time for Channel 3. 0x070 0x074 0x078 0x07C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 INACTIVE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 ACTIVE 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 24-13 Pulse-Width Modulator (PWM) Controller Table 24-16. HW_PWM_ACTIVE3 Bit Field Descriptions BITS LABEL 31:16 INACTIVE RW RESET RW 0x0 DEFINITION Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 15:0 ACTIVE RW 0x0 DESCRIPTION: This register contains the active time and inactive time programming parameters for Channel 3. EXAMPLE: HW_PWM_ACTIVEn_WR(3, 0x000000ff); // Set active and inactive counts 24.4.9 PWM Channel 3 Period Register Description The PWM Channel 3 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. HW_PWM_PERIOD3 HW_PWM_PERIOD3_SET HW_PWM_PERIOD3_CLR HW_PWM_PERIOD3_TOG Table 24-17. HW_PWM_PERIOD3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 MATT_SEL 0x080 0x084 0x088 0x08C 2 3 2 2 2 1 2 0 1 9 INACTIVE_STATE 1 8 1 7 ACTIVE_STATE 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD2 Table 24-18. HW_PWM_PERIOD3 Bit Field Descriptions BITS LABEL 31:25 RSRVD2 MATT_SEL 24 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. Multichip Attachment mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM3 output pin for inter-chip signaling. 23 MATT RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 24-14 Preliminary--Subject to Change Without Notice PERIOD MATT CDIV Freescale Semiconductor Pulse-Width Modulator (PWM) Controller Table 24-18. HW_PWM_PERIOD3 Bit Field Descriptions BITS 22:20 CDIV LABEL RW RESET RW 0x0 DEFINITION Clock divider ratio to apply to the crystal clock frequency (24.0 MHz) that times the PWM output signal. DIV_1 = 0x0 Divide by 1. DIV_2 = 0x1 Divide by 2. DIV_4 = 0x2 Divide by 4. DIV_8 = 0x3 Divide by 8. DIV_16 = 0x4 Divide by 16. DIV_64 = 0x5 Divide by 64. DIV_256 = 0x6 Divide by 256. DIV_1024 = 0x7 Divide by 1024. 19:18 INACTIVE_STATE RW 0x0 The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z = 0x0 Inactive state sets PWM output to high-impedance. 0 = 0x2 Inactive state sets PWM output to 0 (low). 1 = 0x3 Inactive state sets PWM output to 1 (high). 17:16 ACTIVE_STATE RW 0x0 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z = 0x0 Active state sets PWM output to high-impedance. 0 = 0x2 Active state sets PWM output to 0 (low). 1 = 0x3 Active state sets PWM output to 1 (high). 15:0 PERIOD RW 0x0 Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. DESCRIPTION: This register contains the programming paramters for multi-chip attachment mode, clock divider value, active high, low values and period for channel 3. EXAMPLE: HW_PWM_PERIODn_WR(3, 0x00000b1f); // Set up period and active/inactive output states 24.4.10 PWM Channel 4 Active Register Description The PWM Channel 4 Active Register specifies the active time and inactive time for Channel 4. HW_PWM_ACTIVE4 HW_PWM_ACTIVE4_SET HW_PWM_ACTIVE4_CLR HW_PWM_ACTIVE4_TOG Table 24-19. HW_PWM_ACTIVE4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 INACTIVE 0x090 0x094 0x098 0x09C 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 ACTIVE 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 24-15 Pulse-Width Modulator (PWM) Controller Table 24-20. HW_PWM_ACTIVE4 Bit Field Descriptions BITS LABEL 31:16 INACTIVE RW RESET RW 0x0 DEFINITION Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 15:0 ACTIVE RW 0x0 DESCRIPTION: This register contains the active time and inactive time programming parameters for Channel 4. EXAMPLE: HW_PWM_ACTIVEn_WR(4, 0x000000ff); // Set active and inactive counts 24.4.11 PWM Channel 4 Period Register Description The PWM Channel 4 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. HW_PWM_PERIOD4 HW_PWM_PERIOD4_SET HW_PWM_PERIOD4_CLR HW_PWM_PERIOD4_TOG Table 24-21. HW_PWM_PERIOD4 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 MATT_SEL 0x0A0 0x0A4 0x0A8 0x0AC 2 3 2 2 2 1 2 0 1 9 INACTIVE_STATE 1 8 1 7 ACTIVE_STATE 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD2 Table 24-22. HW_PWM_PERIOD4 Bit Field Descriptions BITS LABEL 31:25 RSRVD2 MATT_SEL 24 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved. Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM4 output pin for inter-chip signaling. 23 MATT RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 24-16 Preliminary--Subject to Change Without Notice PERIOD MATT CDIV Freescale Semiconductor Pulse-Width Modulator (PWM) Controller Table 24-22. HW_PWM_PERIOD4 Bit Field Descriptions BITS 22:20 CDIV LABEL RW RESET RW 0x0 DEFINITION Clock divider ratio to apply to the crystal clock frequency (24.0 MHz) that times the PWM output signal. DIV_1 = 0x0 Divide by 1. DIV_2 = 0x1 Divide by 2. DIV_4 = 0x2 Divide by 4. DIV_8 = 0x3 Divide by 8. DIV_16 = 0x4 Divide by 16. DIV_64 = 0x5 Divide by 64. DIV_256 = 0x6 Divide by 256. DIV_1024 = 0x7 Divide by 1024. 19:18 INACTIVE_STATE RW 0x0 The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z = 0x0 Inactive state sets PWM output to high-impedance. 0 = 0x2 Inactive state sets PWM output to 0 (low). 1 = 0x3 Inactive state sets PWM output to 1 (high). 17:16 ACTIVE_STATE RW 0x0 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z = 0x0 Active state sets PWM output to high-impedance. 0 = 0x2 Active state sets PWM output to 0 (low). 1 = 0x3 Active state sets PWM output to 1 (high). 15:0 PERIOD RW 0x0 Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. DESCRIPTION: This register contains the programming paramters for multi-chip attachment mode, clock divider value, active high, low values and period for channel 4. EXAMPLE: HW_PWM_PERIODn_WR(4, 0x00000b1f); // Set up period and active/inactive output states 24.4.12 PWM Version Register Description This register indicates the version of the block for debug purposes. HW_PWM_VERSION Table 24-23. HW_PWM_VERSION 3 1 3 0 2 9 2 8 MAJOR 0x0b0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 24-17 Pulse-Width Modulator (PWM) Controller Table 24-24. HW_PWM_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x01 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x03 RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_PWM_VERSION.B.MAJOR != 1) Error(); PWM Block v1.3, Revision 1.23 i.MX23 Applications Processor Reference Manual, Rev. 1 24-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 25 I2C Interface This chapter describes the I2C interface implemented on the i.MX23. It includes sections on the external pins, interrupt sources, I2C bus protocol, and programming examples. Programmable registers are included in Section 25.4, "Programmable Registers." 25.1 Overview The I2C is a standard two-wire serial interface used to connect the chip with peripherals or host controllers. This interface provides a standard speed (up to 100 kbps), and a fast speed (up to 400 kbps) I2C connection to multiple devices with the chip acting in I2C master. Typical applications for the I2C bus include: EEPROM, LED/LCD, FM tuner, cell phone baseband chip connection, etc. As implemented on the i.MX23, the I2C block includes the following functions: * * The I2C block can be configured as a master device. In master mode, it generates the clock (I2C_SCL) and initiates transactions on the data line (I2C_SDA). The I2C block packs/unpacks data into 8-, 16-, 24-, or 32-bit words for DMA transactions. Data on the I2C bus is always byte-oriented. Short transmission (up to three bytes plus address) can be easily triggered using only PIO operations, i.e., no DMA setup required. The I2C block has programmable device addresses for master transactions. Master transactions are composed of one or more DMA commands chained together. The first byte conveys the slave address and read/write bit for the first command. If the entire transaction is an I2C write command, then it can be sent by a single DMA command. If the command is an I2C read transaction, then at least two DMA commands are required to handle it. * * i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-1 I2C Interface Figure 25-1 shows a block diagram of the I2C interface implemented on the i.MX23. ARM Core SRAM 24-MHz XTAL Osc. AHB AHB Slave AHB Master Divide by n Shared DMA AHB-to-APBX Bridge APBX Master APBX I2C Programmable Registers and FIFOs DMA Interface FSM I2C_SCL I2C_SDA Input Sync and I2C_CK Generation I2C Figure 25-1. I2C Interface Block Diagram 25.2 * * Operation I2C_SDAQ: I2C Serial Data--This pin carries all address and data bits. I2C_SCL: I2C Serial Clock--This pin carries the clock used to time the address and data. The I2C Interface on the i.MX23 includes the following external pins: Pullup resistors are required on both of the I2C lines as all of the I2C drivers are open drain (pulldown only). Typically, external 2k resistors are used to pull the signals up to VddIO for normal and fast speeds. 25.2.1 I2C Interrupt Sources The I2C port can be used in either interrupt-driven or polled modes. An interrupt can be generated by the completion of a DMA command in the APBX DMA. DMA interrupts are the reporting mechanism for I2C transactions that terminate normally. Abnormal terminations or partial completions are signaled by interrupts generated within the I2C controller. i.MX23 Applications Processor Reference Manual, Rev. 1 25-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface If I2C interrupts are enabled, a level-sensitive interrupt will be signaled to the processor upon one of the events listed in Table 25-1. Table 25-1. I2C Interrupt Condition in HW_I2C_CTRL1 SOURCE BIT NAME DESCRIPTION This interrupt is generated when an address match occurs. It indicates that the CPU should read the captured RW bit from the I2C address byte to determine the type of DMA to use for the data transfer phase. This interrupt is generated when a stop condition is detected after a slave address has been matched. Slave Address SLAVE_IRQ Slave Stop Oversize Xfer SLAVE_STOP_IRQ OVERSIZE_XFER_TERM_IRQ The DMA and I2C controller are initialized for an expected transfer size. If the data phase is not terminated within this transfer size then oversize transfer processing goes into effect and the CPU is alerted via this interrupt. EARLY_TERM_IRQ The DMA and I2C controller are initialized for an expected transfer size. If the data phase is terminated before this transfer size then early termination processing goes into effect and the CPU is alerted via this interrupt. A master begins transmission on an idle I2C bus and monitors the data line. If it ever attempts to send a one on the line and notes that a zero has been sent instead, then it notes that it has lost mastership of the I2C bus. It terminates its transfer and reports the condition to the CPU via this interrupt. This detection only happens on master transmit operations. When a start condition is transmitted in master mode, the next byte contains an address for a targeted slave. If the targeted slave does not acknowledge the address byte, then this interrupt is set, no further I2C protocol is processed, and the I2C bus returns to the idle state. This bit is set whenever the DMA interface state machine completes a transaction and resets its run bit. This is useful for PIO mode transmit transactions that are not mediated by the DMA and therefore cannot use the DMA command completion interrupt. This bit is still set for master completions when the DMA is used, but can be ignored in that case. When bus mastership is lost during the I2C arbitration phase, the bus becomes busy running services for another master. This interrupt is set whenever a stop command is detected so the master transaction can attempt a retry. Early Termination Master Loss MASTER_LOSS_IRQ No Slave Ack NO_SLAVE_ACK_IRQ Data Engine Complete DATA_ENGINE_CMPLT_IRQ Bus Free BUS_FREE_IRQ The interrupt lines are tied directly to the bits of Control Register 1. Clearing these bits through software removes the interrupt request. 25.2.2 * * * I2C Bus Protocol The I2C interface operates as shown in Figure 25-2 and Figure 25-3. A START condition is defined as a high-to-low transition on the data line while the I2C_SCL line is held high. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first seven bits, and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-3 I2C Interface * * When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. Data transfer with acknowledge is obligatory. * * * * The transmitter must release the I2C_SDA line during the acknowledge pulse. The receiver must then pull the data line low, so that it remains stable low during the high period of the acknowledge clock pulse. A receiver that has been addressed is obliged to generate an acknowledge after each byte of data has been received. A slave device can terminate a transfer by withholding its acknowledgement. End of the Slave Address Search Engine Processing Beginning of DMA Transfer Engine Processing SCL I2C Clock Held 8 Bits SDA SLAVE Address and R/W 8 Bits DATA Acknowledge Signal START Condition Acknowledge Signal STOP Condition Figure 25-2. I2C Data and Clock Timing The clock is generated by the master, according to parameters set in the HW_I2C_TIMINGn register. This register also provides programmable timing for capturing received data, as well as for changing the transmitted data bit. i.MX23 Applications Processor Reference Manual, Rev. 1 25-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface TDHD TDSU SDAin Bit 2 Bit 1 Bit 0 Grab Read Data Change Write Data SAK SCLin Slave Hold Clock SCLoe Low clk High clk Master Figure 25-3. I2C Data and Clock Timing Generation 25.2.2.1 Simple Device Transactions The simplest transfer of interest on an I2C bus is writing a single data byte from a master to a slave, for example, writing a single byte to an FM tuner. In this transaction, a start condition is transmitted, followed by the device address byte, followed by a single byte of write data. This sequence always ends with a stop condition. Table 25-2. I2C Transfer When the Interface is Transmitting as a Master ST SAD+W SAK DATA SAK SP Table 25-3 defines the symbols used in describing I2C transactions. For example, in the single byte write operation, ST is a start condition, and SP is a stop condition. The data transfer occurs between these two bus events. It starts with a slave address plus write byte (SAD+W) addressing the targeted slave. A slave-generated acknowledge bit (SAK) tells the master that a slave has recognized the address and will accept the transfer. The master sends the data byte (DATA), and the slave acknowledges it with an SAK. Table 25-3. I2C Address Definitions BIT ST SR SAD SAK SUB DATA SP MAK NMAK Start Condition Repeated Start Condition Slave Address Slave Acknowledge Sub-Address, e.g., for EEPROMs Data Stop Condition Master Acknowledge No Master Acknowledge DESCRIPTION i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-5 I2C Interface To receive one data byte from a slave device such as an FM tuner, the following bus transaction takes place. Table 25-4. I2C Transfer "FM Tuner" Read of One Byte ST SAD+R SAK DATA NMAK SP In this transaction: * * * * * * * The master first generates a start condition, ST. It then sends the seven-bit slave address for the FM tuner plus a read bit (SAD+R). The slave in the FM tuner responds with a slave acknowledge bit (SAK). The master then generates I2C clocks for a data byte to be transferred (DATA). The slave provides data to the I2C data bus during the DATA byte transfer. Next, the master generates a master non-acknowledge to the slave (NMAK), indicating the end of the data transfer to the slave. The slave will then release the data line. Finally, the master generates a stop condition (SP), terminating the transaction and freeing the I2C bus for other masters to use. The following example shows a multiple byte read from an FM tuner or other slave device: Table 25-5. I2C Transfer "FM Tuner" Read of Three Bytes ST SAD+R SAK DATA MAK DATA MAK DATA NMAK SP 25.2.2.2 Typical EEPROM Transactions I2C EEPROMs typically have a specific transaction sequence for reading and writing data bytes to and from the EEPROM array. Table 25-6 through Table 25-9 show the first two bytes of data as a sub-address for purposes of illustration. The sub-address is used to address the memory space inside the device. Table 25-3 defines each element of the transactions shown. When writing a single byte of data to the EEPROM, one must first transfer two bytes of sub-address as follows: Table 25-6. I2C Transfer When Master is Writing One Byte of Data to a Slave ST SAD+W SAK SUB SAK SUB SAK DATA SAK SP The sub-address only needs to be specified once for a multibyte transfer, as shown here. Note that the sub-address must be sent for each start condition that initiates a transaction. Table 25-7. I2C Transfer When Master is Writing Multiple Bytes to a Slave ST SAD+W SAK SUB SAK SUB SAK DATA SAK DATA SAK SP One must also provide the sub-address before reading bytes from the EEPROM. The sub-address is transmitted from the master to the slave before it can receive data bytes. The two transfers are joined into a single bus transaction though the use of a repeated start condition (SR). Normally, a stop condition precedes a start condition. However, when a start condition is preceded by another start condition, it is i.MX23 Applications Processor Reference Manual, Rev. 1 25-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface known as a repeated start (SR). Note that the two-byte sub address is transferred using an SAD+W address, while the data is received using a SAD+R address. Table 25-8. I2C Transfer When Master is Receiving One Byte of Data from a Slave ST SAD+W SAK SUB SAK SUB SAK SR SAD+R SAK DATA NMAK SP Table 25-9. I2C Transfer When Master is Receiving Multiple Bytes of Data from a Slave ST SAD+W SAK SUB SAK SUB SAK SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP 25.2.2.3 Master Mode Protocol In master mode, the I2C interface generates the clock and initiates all transfers. 25.2.2.4 * * Clock Generation The I2C clock is generated from the APBX clock, as described in the register description. If another device pulls the clock low before the I2C block has counted the high period, then the I2C block immediately pulls the clock low as well and starts counting its low period. Once the low period has been counted, the I2C block releases the clock line high, but must then check to see if another device stills holds the line low, in which case it enters a high wait state. In this way, the I2C_SCL clock is generated, with its low period determined by the device with the longest clock low period and its high period determined by the one with the shortest clock high period. 25.2.2.5 Master Mode Operation The finite state machine for master mode operation is shown in Figure 25-4 through Figure 25-7. Figure 25-4 shows the generation of the optional start condition. Figure 25-5 shows the receive states, Figure 25-6 shows the transmit states. Figure 25-7 shows the generation of the optional stop state. Table 25-10 through Table 25-13 show examples of Master Mode I2C transactions. Table 25-3 defines each sub-address shown. The following read-after-write transactions are performed using the restart technique. Table 25-10. I2C Transfer When the Interface as Master is Transmitting One Byte of Data ST SAD+W SAK SUB SAK SUB SAK DATA SAK SP Table 25-11. I2C Transfer When the Interface as Master is Receiving >1 Byte of Data from Slave ST SAD+R SAK DATA MAK DATA MAK DATA NMAK SP Table 25-12. I2C Transfer when Master is Receiving 1 Byte of Data from Slave Internal Subaddress ST SAD+W SAK SUB SAK SUB SAK SR SAD+R SAK DATA NMAK SP i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-7 I2C Interface Table 25-13. I2C Transfer When Master is Receiving >1 byte of Data from Slave Internal Subaddress ST SAD+W SAK SUB SAK SUB SAK SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP i.MX23 Applications Processor Reference Manual, Rev. 1 25-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface B u s Id le M a ste r lo ss M u lti M a s te r & S ta rt C ond. ? Yes No B us B usy W a it F o r Run S to p C ond. ? No Y es M u lti M a s te r? No Y es No RUN? Yes P re s e n d S ta rt? No i2 c _ s d a _ e n = 1 s ta rt c o n d itio n R e le a se H e ld C lo c k W a it fo r sta rt h o ld tim e R e le a s e H e ld C lo c k Yes R E C E IV E M ODE? No T R A N S M IT STATES Yes R E C E IV E STATES Figure 25-4. I2C Master Mode Flow Chart--Initial States i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-9 I2C Interface RCV STATES Receive 1 bit No Got 8 Bits? Yes Send data to DMA Check xfer_count and decide on ACK Last byte? No Yes Send ACK, Flush DMA Reset Run Send ACK Hold Clock? No Post Send Stop? Yes Set Hold I2C Clock Low Yes No Send Stop Wait for Run Figure 25-5. I2C Master Mode Flow Chart--Receive States i.MX23 Applications Processor Reference Manual, Rev. 1 25-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface XMIT STATES Get byte from DMA Send 1 Bit 8 bits sent? Yes Check ACK No ACK ? Check xfer_count Last byte? Yes Reset Run No Hold Clock? No Post Send Stop? Yes Set Hold I2C Clock Low Yes No Send Stop Wait for Run Figure 25-6. I2C Master Mode Flow Chart--Transmit States i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-11 I2C Interface SEND STOP I2c_sda_en = 1 Wait for stop setup time Force sda to zero Release Held Clock Release sda I2c_sda_en = 0 Reset Run, Reset post send Wait for Run Figure 25-7. I2C Master Mode Flow Chart--Send Stop States 25.2.3 25.2.3.1 Programming Examples Five Byte Master Write Using DMA The example in Figure 25-8 shows sending five bytes from an i.MX23 operating as an I2C master to another device acting as an I2C slave. i.MX23 Applications Processor Reference Manual, Rev. 1 25-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface 1PIO, no chaining, IRQ,DMA read NEXTCMD_ADDR 6 1 1 1 1 0 10 BUFFER ADDRESS HW_I2C_CTRL0= 0x001B0006 DATA2,DATA1, DATA0, I2CADDR+W 0x0000,DATA4, DATA3 Pointer to next ccw Pointer to DMA buffer Figure 25-8. I2C Writing Five Bytes The DMA command is initialized to send six bytes to the I2C controller and one word of PIO information to the HW_I2C_CTRL0 register. Table 25-14. I2C Transfer When the Master Transmits 5 Bytes of Data to the Slave ST SAD+W SAK DATA0 SAK DATA1 SAK DATA2 SAK DATA3 SAK DATA4 SAK SP The following C code is used to send a five-byte transmission: // SEND: start, 0x56, 0x01,0x02,0x03,0x04,0x05,stop //-----------------------------------------------------#define I2C_CHANNEL_NUM 3 // dma buffer of 6 bytes (i2c address + 5 data bytes) static reg32_t I2C_DATA_BUFFER[2]= { 0x03020156, //slave address 56+W 0x00000504 // last two data bytes }; // DMA command chain const static reg32_t I2C_DMA_CMD[4] = { (reg32_t) I2C_DMA_CMD2, (BF_APBX_CHn_CMD_XFER_COUNT(6) | BF_APBX_CHn_CMD_SEMAPHORE(1) | BF_APBX_CHn_CMD_CMDWORDS(1) | BF_APBX_CHn_CMD_WAIT4ENDCMD(1)| BF_APBX_CHn_CMD_CHAIN(0) | BV_FLD(APBX_CHn_CMD, COMMAND, DMA_READ)), (reg32_t) &eeprom_command_buffer[0], BF_I2C_CTRL0_POST_SEND_STOP(BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP)| BF_I2C_CTRL0_PRE_SEND_START(BV_I2C_CTRL0_PRE_SEND_START__SEND_START) | BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE__MASTER) | BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION__TRANSMIT) | BF_I2C_CTRL0_XFER_COUNT(6) }; void SendFiveBytes(){ // Reset the APBX dma channels associated with I2C. reset_mask = BF_APBX_CTRL0_RESET_CHANNEL((1 << I2C_CHANNEL_NUM)); HW_APBX_CTRL0_SET(reset_mask); i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-13 I2C Interface // Poll for reset to clear the channel. for (retries = 0; retries < RESET_TIMEOUT; retries++) if ((reset_mask & HW_APBX_CTRL0_RD()) == 0) break; if( retries == RESET_TIMEOUT) exit(1); // Setup dma channel configuration. BF_WRn(APBX_CHn_NXTCMDAR,I2C_CHANNEL_NUM, CMD_ADDR,(reg32_t) I2C_DMA_CMD); BF_WR(APBX_CTRL1, CH3_CMDCMPLT_IRQ, 0); // clear interrupt // Start the dma channel by incrementing semaphore. BF_WRn(APBX_CHn_SEMA, I2C_CHANNEL_NUM, INCREMENT_SEMA, 1); // Poll for the semaphore to decrement to zero on the DMA channel. for (retries = 0; retries < SEMAPHORE_TIMEOUT; retries++) if (0 == BF_RDn(APBX_CHn_SEMA, I2C_CHANNEL_NUM, PHORE)) break; // a frame with one byte of address and five bytes of data was just sent } 25.2.3.2 Reading 256 Bytes from an EEPROM 1PIO, chaining, DMA read NEXTCMD_ADDR 3 1 1 0 0 1 10 BUFFER ADDRESS HW _I2C_CTRL0= 0x000B0003 1 PIO,IRQ, no chaining, DMA write NEXTCMD_ADDR=0 256 1 1 1 1 0 01 BUFFER ADDRESS HW_I2C_CTRL0= 0x00120100 0x00,SUB1, SUB0, I2CADDR+W 1PIO, chaining, DMA read NEXTCMD_ADDR 1 1 1 0 0 1 10 BUFFER ADDRESS HW _I2C_CTRL0= 0x002B0001 256-Byte Data Block 0x000000, I2CADDR+R Pointer to next ccw Pointer to DMA buffer Figure 25-9. I2C Reading 256 Bytes from an EEPROM //---------------------------------------------------------------------// dma buffers to hold i2c command string for slave addres+W plus sub0, // sub 1 and the second command, a slave address+R // eePROM write address == 0xA0, read address == 0xA1 //---------------------------------------------------------------------unsigned char eeprom_command_buffer[4] = {0xA0,0x34,0x12,0xA1}; //---------------------------------------------------------------------// I2C DMA chain //---------------------------------------------------------------------const static reg32_t I2C_DMA_CMD3[4] = { 0x0, (BF_APBX_CHn_CMD_XFER_COUNT(256) | BF_APBX_CHn_CMD_WAIT4ENDCMD(1) | i.MX23 Applications Processor Reference Manual, Rev. 1 25-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface BF_APBX_CHn_CMD_SEMAPHORE(1) | BF_APBX_CHn_CMD_CMDWORDS(1) | BF_APBX_CHn_CMD_CHAIN(0) | // last command BV_FLD(APBX_CHn_CMD, COMMAND, DMA_WRITE)), (reg32_t) &eeprom_command_buffer[3], BF_I2C_CTRL0_POST_SEND_STOP(BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP)| BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE__MASTER) | BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION__RECEIVE) | BF_I2C_CTRL0_XFER_COUNT(256) }; const static reg32_t I2C_DMA_CMD2[4] = { (reg32_t) I2C_DMA_CMD3, (BF_APBX_CHn_CMD_XFER_COUNT(1) | BF_APBX_CHn_CMD_CMDWORDS(1) | BF_APBX_CHn_CMD_WAIT4ENDCMD(1)| BF_APBX_CHn_CMD_CHAIN(1) | BV_FLD(APBX_CHn_CMD, COMMAND, DMA_READ)), (reg32_t) &eeprom_command_buffer[3], BF_I2C_CTRL0_RETAIN_CLOCK(BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW)| BF_I2C_CTRL0_PRE_SEND_START(BV_I2C_CTRL0_PRE_SEND_START__SEND_START)| BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE__MASTER) | BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION__TRANSMIT) | BF_I2C_CTRL0_XFER_COUNT(1) }; const static reg32_t I2C_DMA_CMD1[4] = { (reg32_t) I2C_DMA_CMD2, (BF_APBX_CHn_CMD_XFER_COUNT(3) | BF_APBX_CHn_CMD_CMDWORDS(1) | BF_APBX_CHn_CMD_WAIT4ENDCMD(1)| BF_APBX_CHn_CMD_CHAIN(1) | BV_FLD(APBX_CHn_CMD, COMMAND, DMA_READ)), (reg32_t) &eeprom_command_buffer[0], BF_I2C_CTRL0_PRE_SEND_START(BV_I2C_CTRL0_PRE_SEND_START__SEND_START) | BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE__MASTER) | BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION__TRANSMIT) | BF_I2C_CTRL0_XFER_COUNT(3) }; ///////////////////////////////////////////////////// //Read256BytesFromEEPROM returns 1 for errors and 0 for OK ///////////////////////////////////////////////////// int Read256BytesFromEEPROM(unsigned short usAddress){ // insert eePROM addres param into dma command buffer I2C_CMD_BUFFER[1] = (unsigned char) (usAddress &0x00ff); I2C_CMD_BUFFER[2] = (unsigned char) ((usAddress>>8) &0x00ff); // Reset the APBX dma channels associated with I2C. reset_mask = BF_APBX_CTRL0_RESET_CHANNEL((1 << I2C_CHANNEL_NUM)); HW_APBX_CTRL0_SET(reset_mask); // Poll for reset to clear the channel. for (retries = 0; retries < RESET_TIMEOUT; retries++) if ((reset_mask & HW_APBX_CTRL0_RD()) == 0) break; if (retries == RESET_TIMEOUT)exit(1); // Setup dma channel configuration. BF_WRn(APBX_CHn_NXTCMDAR,I2C_CHANNEL_NUM, CMD_ADDR,(reg32_t) I2C_DMA_CMD_SUBADDR); BF_WR(APBX_CTRL1, CH3_CMDCMPLT_IRQ, 0); // Start the dma channel by incrementing semaphore. BF_WRn(APBX_CHn_SEMA, I2C_CHANNEL_NUM, INCREMENT_SEMA, 1); // Poll for the semaphore to decrement to zero on the DMA channel. for (retries = 0; retries < SEMAPHORE_TIMEOUT; retries++)} if (0 == BF_RDn(APBX_CHn_SEMA, I2C_CHANNEL_NUM, PHORE)) break; if (1 == HW_I2C_CTRL1.MASTER_LOSS_IRQ) return 1; // error if (1 == HW_I2C_CTRL1.NO_SLAVE_ACK_IRQ) return 1; // error if (1 == HW_I2C_CTRL1.EARLY_TERM_IRQ) return 1; // error } ferreters == SEMAPHORE_TIMEOUT) exit(2); // the 256 bytes were read from the eePROM so return with no Error i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-15 I2C Interface return 0; } 25.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. 25.3.1 Pinmux Selection During Reset For proper I2C operation, the appropriate pinmux(s) must be selected before taking the block out of reset. Failure to select the I2C pinmux selections before taking the block out of reset will cause the I2C clock to operate incorrectly and will require another I2C hardware reset. 25.3.1.1 Correct and Incorrect Reset Examples Incorrect: Clear I2C SFTRST/CLKGATE ... Setup ... I2C PinMux Selections ** I2C will not operate. Correct: I2C PinMux Selections Clear I2C SFTRST/CLKGATE ... Setup ... ** I2C operates correctly. 25.4 Programmable Registers The following registers describe the programming interface for the master I2C controller. 25.4.1 I2C Control Register 0 Description The I2C Control Register specifies the reset state and the command and transfer size information for the I2C controller. HW_I2C_CTRL0 HW_I2C_CTRL0_SET HW_I2C_CTRL0_CLR HW_I2C_CTRL0_TOG 0x000 0x004 0x008 0x00C i.MX23 Applications Processor Reference Manual, Rev. 1 25-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface Table 25-15. HW_I2C_CTRL0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 SEND_NAK_ON_LAST 2 4 2 3 2 2 2 1 2 0 1 9 1 8 SLAVE_ADDRESS_ENABLE 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 POST_SEND_STOP PRE_SEND_START ACKNOWLEDGE MASTER_MODE RETAIN_CLOCK CLOCK_HELD Table 25-16. HW_I2C_CTRL0 Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Set to zero for normal operation. When this bit is set to one (default), then the entire block is held in its reset state. RUN = 0x0 Allow I2C to operate normally. RESET = 0x1 Hold I2C in reset. 30 CLKGATE RW 0x1 This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. RUN = 0x0 Allow I2C to operate normally. NO_CLKS = 0x1 Do not clock I2C gates in order to minimize power consumption. 29 RUN RW 0x0 Set this bit to one to enable the I2C Controller operation. This bit is automatically set by DMA commands that write to CTRL1 after the last PIO write of the DMA command. For Soft DMA operation, software can set this bit to enable the controller. HALT = 0x0 No I2C command in progress. RUN = 0x1 Process a master I2C command. 28 27 26 RSVD2 PRE_ACK ACKNOWLEDGE RO 0x0 RW 0x0 RW 0x0 Always set this bit field to zero. Reserved for Freescale use. Set this bit to one to cause a pending acknowledge bit (prior to DMA transfer) to be acknowledged. Set it to zero to NAK the pending acknowledge bit. This bit is set to one by the slave search engine if the criteria is met for acknowledging a slave address. Software can reset the bit to slave-not-acknowledge the address. This bit defines the state of the i2c_data line during the address acknowledge bit time. The slave search engine holds the clock at this point for a software decision. This bit has no effect when the presend start option is selected. SNAK = 0x0 slave not acknowledge when the held clock is released. ACK = 0x1 slave acknowledge when the held clock is released. 25 SEND_NAK_ON_LAST RW 0x0 Set this bit to one to cause the DMA transfer engine to send a NAK on the last byte. ACK_IT = 0x0 Send an ACK on the last byte received. NAK_IT = 0x1 Send a NAK on the last byte received. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice XFER_COUNT DIRECTION PIO_MODE PRE_ACK CLKGATE SFTRST RSVD2 RSVD1 RUN 25-17 I2C Interface Table 25-16. HW_I2C_CTRL0 Bit Field Descriptions BITS LABEL 24 PIO_MODE RW RESET RW 0x0 DEFINITION Set this bit to one to enable PIO mode of operation for the I2C master. One can preload up to four bytes into HW_I2C_DATA register before setting the RUN bit. The state machine will not attempt to use the DMA for master transmit operation. The normal start and stop conditions can be sent and the clock can be held at the end of the transfer, if desired. NOTE: all receive operations must use the DMA mode, not the PIO mode. Program this field to 0x0. This bit is set to one by the I2C controller state machines. It holds the I2C clock line low until cleared. It must be cleared by firmware, either by CPU instructions or DMA PIO transactions. It is set high when a slave address is matched by the slave controller. It is also set high at the end of a master or slave transaction that had the RETAIN_CLOCK bit set high. Software should not set this bit to one. RELEASE = 0x0 Release the clock line. HELD_LOW = 0x1 The clock line is currently being held low. 23 22 RSVD1 CLOCK_HELD RW 0x0 RW 0x0 21 RETAIN_CLOCK RW 0x0 Set this bit to one to retain the clock at the end of this transaction. This has the effect of holding the clock low until the start of the next transaction. RELEASE = 0x0 Release the clock line after this data transfer. HOLD_LOW = 0x1 Hold the clock line low after this data transfer. 20 POST_SEND_STOP RW 0x0 Set this bit to one to send a stop condition after transferring the data associated with this transaction. This bit is automatically cleared by the hardware after the operation has been performed. NO_STOP = 0x0 Do not send a stop condition before this transaction. SEND_STOP = 0x1 Send a stop condition before this transaction. 19 PRE_SEND_START RW 0x0 Set this bit to one to send a start condition before transferring the data associated with this transaction. This bit is automatically cleared by the hardware after the operation has been performed. NO_START = 0x0 Do not send a start condition before this transaction. SEND_START = 0x1 Send a start condition before this transaction. 18 SLAVE_ADDRESS_ENABLE RW 0x0 Set this bit to one to enable the slave address decoder. When an address match occurs, the I2C bus clock is frozen, by setting HW_I2C_CTRL0_CLOCK_HELD, and an interrupt is generated. DISABLED = 0x0 Disable the slave address decoder. ENABLED = 0x1 Enable the slave address decoder. 17 16 MASTER_MODE DIRECTION RW 0x0 RW 0x0 Set this bit to one to select master mode. MASTER_DISABLED = 0x0 Master mode disabled. MASTER_ENABLED = 0x1 Operate in master mode. Set this bit to one to select an I2C transmit operation. XMIT = write. Set this bit to zero to select an I2C receive operation. RECEIVE = 0x0 I2C receive operation. TRANSMIT = 0x1 I2C transmit operation. 15:0 XFER_COUNT RW 0x0000 Number of bytes to transfer. This field decrements as bytes are transferred. DESCRIPTION: This register is either written by the DMA or the CPU depending on the state of an I2C transaction. i.MX23 Applications Processor Reference Manual, Rev. 1 25-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface EXAMPLE: // turn off soft reset and clock gating HW_I2C_CTRL0_CLR(BM_I2C_CTRL0_SFTRST | BM_I2C_CTRL0_CLKGATE); 25.4.2 I2C Timing Register 0 Description The timing for various phases of I2C Controller Commands are further defined by fields in the I2C Timing Register 0. HW_I2C_TIMING0 HW_I2C_TIMING0_SET HW_I2C_TIMING0_CLR HW_I2C_TIMING0_TOG Table 25-17. HW_I2C_TIMING0 3 1 3 0 2 9 RSVD2 0x010 0x014 0x018 0x01C 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 HIGH_COUNT 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSVD1 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 RCV_COUNT 0 4 0 3 0 2 0 1 0 0 Table 25-18. HW_I2C_TIMING0 Bit Field Descriptions BITS LABEL 31:26 RSVD2 25:16 HIGH_COUNT RW RESET RO 0x0 RW 0x78 DEFINITION Always set this bit field to zero. Load this bit field with the APBX clock count for the high period of the I2C clock. Always set this bit field to zero. Load this bit field with the APBX clock count for capturing read data after the I2C clock goes high. 15:10 RSVD1 RCV_COUNT 9:0 RO 0x0 RW 0x30 DESCRIPTION: This register is primarily used for clock and timing generation. EXAMPLE: HW_I2C_TIMING0_WR(0x00780030); // high time = 120 clocks, read bit at 48 for 95KHz at 24MHz HW_I2C_TIMING0_WR(0x000F0007); // high time = 15 clocks, read bit at 7 for 400KHz at 24MHz 25.4.3 I2C Timing Register 1 Description The timing for various phases of I2C Controller Commands are further defined by fields in the I2C Timing Register 1. HW_I2C_TIMING1 HW_I2C_TIMING1_SET HW_I2C_TIMING1_CLR HW_I2C_TIMING1_TOG 0x020 0x024 0x028 0x02C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-19 I2C Interface Table 25-19. HW_I2C_TIMING1 3 1 3 0 2 9 RSVD2 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 LOW_COUNT 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSVD1 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 XMIT_COUNT 0 4 0 3 0 2 0 1 0 0 Table 25-20. HW_I2C_TIMING1 Bit Field Descriptions BITS LABEL 31:26 RSVD2 25:16 LOW_COUNT RW RESET RO 0x0 RW 0x80 DEFINITION Always set this bit field to zero. Load this bit field with the APBX clock count for the low period of the I2C clock. Always set this bit field to zero. Load this bit field with the APBX clock count for changing transmitted data after the I2C clock goes low. Set this value to produce valid i2c setup and hold times at the desired bit rate for the current APBX clock rate. 15:10 RSVD1 XMIT_COUNT 9:0 RO 0x0 RW 0x30 DESCRIPTION: This register is primarily used for clock and timing generation. EXAMPLE: HW_I2C_TIMING1_WR(0x00800030); // low time at 128, write bit at 48 for 95 kHz at 24 MHz HW_I2C_TIMING1_WR(0x001F000F); // low time at 31, write bit at 15 for 400 kHz at 24 MHz 25.4.4 I2C Timing Register 2 Description The timing for various phases of I2C Controller Commands are further defined by fields in the I2C Timing Register 2. HW_I2C_TIMING2 HW_I2C_TIMING2_SET HW_I2C_TIMING2_CLR HW_I2C_TIMING2_TOG Table 25-21. HW_I2C_TIMING2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 BUS_FREE 0x030 0x034 0x038 0x03C 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 LEADIN_COUNT 0 4 0 3 0 2 0 1 0 0 RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 25-20 Preliminary--Subject to Change Without Notice RSVD1 Freescale Semiconductor I2C Interface Table 25-22. HW_I2C_TIMING2 Bit Field Descriptions BITS LABEL 31:26 RSVD2 25:16 BUS_FREE RW RESET RO 0x0 RW 0x30 DEFINITION Always set this bit field to zero. Load this bit field with the APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator. Always set this bit field to zero. Load this bit field with the APBX clock count for delaying the rising edge of i2c_sck after the kick. 15:10 RSVD1 LEADIN_COUNT 9:0 RO 0x0 RW 0x30 DESCRIPTION: This register is primarily used for clock and timing generation. EXAMPLE: HW_I2C_TIMING2_WR(0x0015000d); // bus free count of 21 lead in count of 13 25.4.5 I2C Control Register 1 Description The I2C Controller Command is further defined by fields in this control extension register. The I2C Control Register 1 is where the I2C slave address is specified. Fast or normal mode is selected here. HW_I2C_CTRL1 HW_I2C_CTRL1_SET HW_I2C_CTRL1_CLR HW_I2C_CTRL1_TOG Table 25-23. HW_I2C_CTRL1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 DATA_ENGINE_CMPLT_IRQ_EN 0x040 0x044 0x048 0x04C 1 3 1 2 OVERSIZE_XFER_TERM_IRQ_EN 1 1 1 0 0 9 0 8 0 7 0 6 DATA_ENGINE_CMPLT_IRQ 0 5 0 4 OVERSIZE_XFER_TERM_IRQ 0 3 0 2 0 1 0 0 NO_SLAVE_ACK_IRQ_EN MASTER_LOSS_IRQ_EN EARLY_TERM_IRQ_EN SLAVE_STOP_IRQ_EN NO_SLAVE_ACK_IRQ MASTER_LOSS_IRQ BUS_FREE_IRQ_EN FORCE_DATA_IDLE BCAST_SLAVE_EN EARLY_TERM_IRQ FORCE_CLK_IDLE SLAVE_STOP_IRQ CLR_GOT_A_NAK BUS_FREE_IRQ SLAVE_IRQ_EN ACK_MODE Table 25-24. HW_I2C_CTRL1 Bit Field Descriptions BITS LABEL 31:29 RSVD2 CLR_GOT_A_NAK 28 RW RESET RO 0x0 RW 0x0 DEFINITION Always set this bit field to zero. Setting this bit will clear the got_a_nak. DO_NOTHING = 0x0 CLEAR = 0x1 Clear got_a_nak. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice SLAVE_IRQ RSVD2 RSVD1 25-21 I2C Interface Table 25-24. HW_I2C_CTRL1 Bit Field Descriptions BITS LABEL 27 ACK_MODE RW RESET RW 0x0 DEFINITION This setting affects the behavior of the ACK pulse when RETAIN_CLOCK=1. ACK_AFTER_HOLD_LOW = 0x0 ACK will occur after clock is held low at start of next access. ACK_BEFORE_HOLD_LOW = 0x1 ACK will occur at end of access before clock is held low. 26 25 24 FORCE_DATA_IDLE FORCE_CLK_IDLE BCAST_SLAVE_EN RW 0x0 RW 0x0 RW 0x0 Writing a one to this bit will force the data state machine to return to its idle state and stay there. Writing a one to this bit will force the clock generator state machine to return to its idle state and stay there. Set this bit to one to enable the slave address search machine to look for both a match to the programmed slave address as well as a match to the broadcast address of all zeroes. NO_BCAST = 0x0 Do not watch for broadcast address while matching programmed slave address. WATCH_BCAST = 0x1 Watch for the all zeroes broadcast address while matching programmed slave address. 23:16 RSVD1 BUS_FREE_IRQ_EN 15 RW 0x86 RW 0x0 Program this field to 0x86. Set this bit to one to enable bus free interrupt requests to be routed to the interrupt collector. Set to zero to disable interrupts from the I2C controller. DISABLED = 0x0 No Interrupt Request Pending. ENABLED = 0x1 Interrupt Request Pending. 14 DATA_ENGINE_CMPLT_IRQ_ RW 0x0 EN Set this bit to one to enable data engine complete interrupt requests to be routed to the interrupt collector. Set to zero to disable interrupts from the I2C controller. DISABLED = 0x0 No Interrupt Request Pending. ENABLED = 0x1 Interrupt Request Pending. 13 NO_SLAVE_ACK_IRQ_EN RW 0x0 Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable interrupts from the I2C controller. DISABLED = 0x0 No Interrupt Request Pending. ENABLED = 0x1 Interrupt Request Pending. 12 OVERSIZE_XFER_TERM_IRQ RW 0x0 _EN Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable interrupts from the I2C controller. DISABLED = 0x0 No Interrupt Request Pending. ENABLED = 0x1 Interrupt Request Pending. 11 EARLY_TERM_IRQ_EN RW 0x0 Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable interrupts from the I2C controller. DISABLED = 0x0 No Interrupt Request Pending. ENABLED = 0x1 Interrupt Request Pending. 10 MASTER_LOSS_IRQ_EN RW 0x0 Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable interrupts from the I2C controller. DISABLED = 0x0 No Interrupt Request Pending. ENABLED = 0x1 Interrupt Request Pending. 9 SLAVE_STOP_IRQ_EN RW 0x0 Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable interrupts from the I2C controller. DISABLED = 0x0 No Interrupt Request Pending. ENABLED = 0x1 Interrupt Request Pending. i.MX23 Applications Processor Reference Manual, Rev. 1 25-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface Table 25-24. HW_I2C_CTRL1 Bit Field Descriptions BITS LABEL 8 SLAVE_IRQ_EN RW RESET RW 0x0 DEFINITION Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable interrupts from the I2C controller. The corresponding HW_I2C_CTRL1_SLAVE_IRQ interrupt bit is set by the slave search engine to indicate that it has stopped searching due to an address match or error. DISABLED = 0x0 No Interrupt Request Pending. ENABLED = 0x1 Interrupt Request Pending. 7 BUS_FREE_IRQ RW 0x0 This bit is set to indicate that an interrupt is requested by the I2C controller because the bus has become free. This bit is cleared by software by writing a one to its SCT clear address. This interrupt indicates that the I2C bus, which was busy, has just become free. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 6 DATA_ENGINE_CMPLT_IRQ RW 0x0 This bit is set to indicate that an interrupt is requested by the I2C controller because the data engine transfer has completed. This bit is cleared by software by writing a one to its SCT clear address. This interrupt indicates that the data engine has completed a DMA transfer in either master or slave mode. This notification is useful for pio mode master write (transmit) or slave read (transmit) operations, i.e., data engine transmit operations. PIO receive operations are not supported. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 5 NO_SLAVE_ACK_IRQ RW 0x0 This bit is set to indicate that an interrupt is requested by the I2C controller because the slave addressed by a master transfer did not respond with an acknowledge. This bit is cleared by software by writing a one to its SCT clear address. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 4 OVERSIZE_XFER_TERM_IRQ RW 0x0 This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software by writing a one to its SCT clear address. This interrupt indicates that a master DMA transfer did not complete by the end of the transfer size. This is indicated by the slave acknowledging the last byte of a write transfer instead of NAKing it. The master should then send additional bytes of data if desired. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 3 EARLY_TERM_IRQ RW 0x0 This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software by writing a one to its SCT clear address. This interrupt indicates that a master write transfrom from the SoC to a slave device was NAKed by the slave before the transfer was completed. In slave mode, it indicates that the master NAKed a byte transmitted by the slave causing early termination of the expected transfer. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-23 I2C Interface Table 25-24. HW_I2C_CTRL1 Bit Field Descriptions BITS LABEL 2 MASTER_LOSS_IRQ RW RESET RW 0x0 DEFINITION This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software by writing a one to its SCT clear address. This interrupt indicates that a master read or write transaction lost an arbitration with another master. Master loss is indicated by the master attempting to transmit a one to the bus at the same time as another master writes a zero. The wired and bus produces a zero on the bus which is detected by the lossing master. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 1 SLAVE_STOP_IRQ RW 0x0 This bit is set to indicate that an I2C Stop Condition was received by the slave address search engine after it had found a start command addressed to its slave address. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 0 SLAVE_IRQ RW 0x0 This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software by writing a one to its SCT clear address. This bit is set by the slave search engine to indicate that it has stopped searching due to an address match or error. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. DESCRIPTION: This control register is primarily used for interrupt management. It also controls the special slave address matching mode. In addition, it controls the protocol speed, i.e fast or 400KHz versus normal or 100KHz operation. EXAMPLE: HW_I2C_CTRL1_CLR(BM_I2C_CTRL1_SLAVE_IRQ); // clear the slave interrupt 25.4.6 I2C Status Register Description HW_I2C_STAT 0x050 The I2C Controller reports status information in the I2C Status Register. i.MX23 Applications Processor Reference Manual, Rev. 1 25-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface Table 25-25. HW_I2C_STAT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 DATA_ENGINE_CMPLT_IRQ_SUMMARY 0 5 0 4 OVERSIZE_XFER_TERM_IRQ_SUMMARY 0 3 0 2 0 1 0 0 NO_SLAVE_ACK_IRQ_SUMMARY MASTER_LOSS_IRQ_SUMMARY EARLY_TERM_IRQ_SUMMARY SLAVE_STOP_IRQ_SUMMARY BUS_FREE_IRQ_SUMMARY DATA_ENGINE_DMA_WAIT SLAVE_ADDR_EQ_ZERO Table 25-26. HW_I2C_STAT Bit Field Descriptions BITS LABEL 31 MASTER_PRESENT RW RESET RO 0x1 DEFINITION This read-only bit indicates that the I2C master function is present when it reads back a one. This I2C function is not available on a device that returns a zero for this bit field. UNAVAILABLE = 0x0 I2C is not present in this product. AVAILABLE = 0x1 I2C is present in this product. 30 29 RSVD2 ANY_ENABLED_IRQ RO 0x1 RO 0x0 Program this field to 0x1. This read-only bit indicates that the I2C controller has at least one enable interrupt requesting service. It is the logic OR of all of the IRQ summary bits. NO_REQUESTS = 0x0 No enabled interrupts are requesting service. AT_LEAST_ONE_REQUEST = 0x1 At least one of the summary interrupt bits is set. 28 GOT_A_NAK RO 0x0 RO 0x0 RO 0x00 Read-only view of the got-a-nak signal. NO_NAK = 0x0 I2C master has not detected a NAK. DETECTED_NAK = 0x1 I2C master has detected a NAK. 27:24 RSVD1 23:16 RCVD_SLAVE_ADDR 15 SLAVE_ADDR_EQ_ZERO RO 0x0 Always set this bit field to zero. This read-only byte indicates that the state of the slave I2C address byte received, including the read/write bit received from an address byte that matched our slave address. This read-only bit indicates that the I2C slave function was searching for a transaction that matches the current slave address. When set to one, it indicates that an address match was found for the exact adderss 0x00. ZERO_NOT_MATCHED = 0x0 I2C slave search did not match a zero. WAS_ZERO = 0x1 I2C has found an address match against address 0x00. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice SLAVE_IRQ_SUMMARY DATA_ENGINE_BUSY RCVD_SLAVE_ADDR ANY_ENABLED_IRQ SLAVE_SEARCHING MASTER_PRESENT CLK_GEN_BUSY SLAVE_FOUND SLAVE_BUSY GOT_A_NAK BUS_BUSY RSVD2 RSVD1 25-25 I2C Interface Table 25-26. HW_I2C_STAT Bit Field Descriptions BITS LABEL 14 SLAVE_FOUND RW RESET RO 0x0 DEFINITION This read-only bit indicates that the I2C slave function was searching for a transaction that matches the current slave address. When set to one, it indicates that an address match was found and the I2C clock is frozen by the slave search. This bit is cleared by starting the appropriate slave DMA transfer or restarting a slave search. IDLE = 0x0 I2C slave search is idle. WAITING = 0x1 I2C has found an address match and is holding the I2C clock line low. 13 SLAVE_SEARCHING RO 0x0 This read-only bit indicates that the I2C slave function is searching for a transaction that matches the current slave address. IDLE = 0x0 I2C slave search is idle. ACTIVE = 0x1 I2C is actively searching for an address match. 12 DATA_ENGINE_DMA_WAIT RO 0x0 This read-only bit is set to one when the data engine is waitng for data from a DMA device. This bit can be used to transmit short I2C transactions without using a DMA channel. This generally works for up to three data bytes transmitted with one address byte. CONTINUE = 0x0 I2C master is not waiting on data from the DMA. WAITING = 0x1 I2C master is waiting on data from the DMA. 11 BUS_BUSY RO 0x0 This read-only bit indicates that the I2C bus is busy with a transaction. It is set by a start condition and reset by a detected stop condition. IDLE = 0x0 I2C bus is idle, i.e. reset state or at least one stop condition detected. BUSY = 0x1 I2C bus is busy, i.e. at least one start condition has been detected. 10 CLK_GEN_BUSY RO 0x0 This read-only bit indicates that the I2C clock generator is busy with a transaction. IDLE = 0x0 I2C clock generator is idle. BUSY = 0x1 I2C clock generator is busy performing a command. 9 DATA_ENGINE_BUSY RO 0x0 This read-only bit indicates that the I2C data transfer engine is busy with a data transmit or recieve opertion. In addition, it can be busy, as a master, sending a start or stop condition. IDLE = 0x0 I2C Data Engine is idle. BUSY = 0x1 I2C is Data Engine busy performing a data transfer. 8 SLAVE_BUSY RO 0x0 This read-only bit indicates that the I2C slave address search engine is busy with a transaction. This bit will go high when an address search is started and will remain high until the slave search engine returns to its idle state. IDLE = 0x0 I2C slave search engine is idle. BUSY = 0x1 I2C slave search engine is busy searching for an address match. 7 BUS_FREE_IRQ_SUMMARY RO 0x0 This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the corresponding interrupt status bit and interrupt enable bit. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 6 DATA_ENGINE_CMPLT_IRQ_ RO 0x0 SUMMARY This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the corresponding interrupt status bit and interrupt enable bit. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. i.MX23 Applications Processor Reference Manual, Rev. 1 25-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface Table 25-26. HW_I2C_STAT Bit Field Descriptions BITS LABEL RW RESET 5 NO_SLAVE_ACK_IRQ_SUMM RO 0x0 ARY DEFINITION This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the corresponding interrupt status bit and interrupt enable bit. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 4 OVERSIZE_XFER_TERM_IRQ RO 0x0 _SUMMARY This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the corresponding interrupt status bit and interrupt enable bit. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 3 EARLY_TERM_IRQ_SUMMA RY RO 0x0 This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the corresponding interrupt status bit and interrupt enable bit. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 2 MASTER_LOSS_IRQ_SUMM ARY RO 0x0 This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the corresponding interrupt status bit and interrupt enable bit. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 1 SLAVE_STOP_IRQ_SUMMAR RO 0x0 Y This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the corresponding interrupt status bit and interrupt enable bit. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. 0 SLAVE_IRQ_SUMMARY RO 0x0 This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the corresponding interrupt status bit and interrupt enable bit. NO_REQUEST = 0x0 No Interrupt Request Pending. REQUEST = 0x1 Interrupt Request Pending. DESCRIPTION: The status register provides read-only access to the function presence bits, as well as the busy indicators for the state machines. EXAMPLE: while(HW_I2C_STAT.SLAVE_BUSY != BV_I2C_STAT_SLAVE_BUSY__IDLE_VAL);// then wait till it finishes 25.4.7 I2C Controller DMA Read and Write Data Register Description The I2C Controller DMA Read and Write Data Register is the target for both source and destination DMA transfers. This register is backed by an eight-deep FIFO. HW_I2C_DATA 0x060 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-27 I2C Interface Table 25-27. HW_I2C_DATA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DATA Table 25-28. HW_I2C_DATA Bit Field Descriptions BITS 31:0 DATA LABEL RW RESET RW 0x00000000 DEFINITION The source DMA channel writes to this address. The Destination DMA channel reads from this address. DESCRIPTION: DMA reads and writes are directed to this register. EXAMPLE: The DMA data register is used by the DMA to read or write data from the I2C controller, as mediated by the I2C controllers DMA request signal. 25.4.8 I2C Device Debug Register 0 Description The I2C Device Debug Register 0 provides a diagnostic view into the internal state machine and states of the I2C device. HW_I2C_DEBUG0 HW_I2C_DEBUG0_SET HW_I2C_DEBUG0_CLR HW_I2C_DEBUG0_TOG Table 25-29. HW_I2C_DEBUG0 3 1 3 0 DMAENDCMD 0x070 0x074 0x078 0x07C 2 9 2 8 DMATERMINATE 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 START_TOGGLE 1 4 STOP_TOGGLE 1 3 GRAB_TOGGLE 1 2 CHANGE_TOGGLE 1 1 1 0 SLAVE_HOLD_CLK 0 9 0 8 0 7 0 6 0 5 SLAVE_STATE 0 4 0 3 0 2 0 1 0 0 DMA_STATE Table 25-30. HW_I2C_DEBUG0 Bit Field Descriptions BITS LABEL 31 DMAREQ RW RESET RO 0x0 DEFINITION Read-only view of the toggle state of the DMA request signal. Read-only view of the toggle state of the DMA End Command signal. Read-only view of the toggle state of the DMA Kick signal. 30 29 DMAENDCMD DMAKICK RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 25-28 Preliminary--Subject to Change Without Notice TESTMODE DMAKICK DMAREQ TBD Freescale Semiconductor I2C Interface Table 25-30. HW_I2C_DEBUG0 Bit Field Descriptions BITS LABEL 28 DMATERMINATE RW RESET RO 0x0 DEFINITION Read-only view of the toggle state of the DMA Terminate signal. Reserved Current state of the DMA state machine. Read-only view of the start detector. Toggles once for each detected start condition. Read-only view of the stop detector. Toggles once for each detected stop condition. Read-only view of the grab receive data timing point. Toggles once for each read timing point, as delayed from rising clock. Read-only view of the change xmit data timing point. Toggles once for each change xmit data timing point, as delayed from falling clock. To be completed by designer. Current State of the Slave Address Search FSM clock hold register. Current State of the Slave Address Search FSM. 27:26 TBD 25:16 DMA_STATE START_TOGGLE 15 14 13 STOP_TOGGLE GRAB_TOGGLE RW 0x0 RO 0x010 RO 0x0 RO 0x0 RO 0x0 12 CHANGE_TOGGLE RO 0x0 11 10 9:0 TESTMODE SLAVE_HOLD_CLK SLAVE_STATE RW 0x0 RO 0x0 RO 0x0000 DESCRIPTION: This register provides access to various internal states and controls that are used in diagnostic modes of operation. EXAMPLE: while(HW_I2C_DEBUG0.DMAREQ == old_dma_req_value); // wait for next dma request toggle old_dma_req_value = HW_I2C_DEBUG0.DMAREQ; // remember the new state of the dma request toggle 25.4.9 I2C Device Debug Register 1 Description The I2C Device Debug Register 1 provides a diagnostic view of the external bus and provides OE control for the clock and data. HW_I2C_DEBUG1 HW_I2C_DEBUG1_SET HW_I2C_DEBUG1_CLR HW_I2C_DEBUG1_TOG Table 25-31. HW_I2C_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 DMA_BYTE_ENABLES 0x080 0x084 0x088 0x08C 2 5 2 4 2 3 2 2 2 1 2 0 CLK_GEN_STATE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 LOCAL_SLAVE_TEST 0 7 0 6 0 5 0 4 FORCE_CLK_ON 0 3 FORCE_ARB_LOSS 0 2 FORCE_RCV_ACK 0 1 FORCE_I2C_DATA_OE 0 0 FORCE_I2C_CLK_OE I2C_DATA_IN I2C_CLK_IN LST_MODE RSVD4 RSVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 25-29 I2C Interface Table 25-32. HW_I2C_DEBUG1 Bit Field Descriptions BITS 31 30 29:28 27:24 LABEL I2C_CLK_IN I2C_DATA_IN RSVD4 DMA_BYTE_ENABLES RW RO RO RO RO RESET 0x1 0x1 0x0 0x0 DEFINITION A copy of the pad input signal for the I2C clock pad. A copy of the pad input signal for the I2C clock pad. Always set this bit field to zero. A read-only view of the byte enables for HW_I2C_DATA register writes. These bits are used in the I2C DMA state machine to track the number of bytes written by the DMA. Individual bits are cleared as they are consummed. A read-only view of the byte enables for HW_I2C_DATA register writes. These bits are used in the I2C DMA state machine to track the number of bytes written by the DMA. Individual bits are cleared as they are consummed. Always set this bit field to zero. When in local slave test mode, this bit field defines the type of address generated for the slave. BCAST = 0x0 Broadcast, i.e. i2c address 0x00. MY_WRITE = 0x1 Send to my slave address with a RW bit equal 0. MY_READ = 0x2 Send to my slave address with a RW bit equal 1. NOT_ME = 0x3 Send to an address that is not mine, i.e. bit four is complemented. 23:16 CLK_GEN_STATE RO 0x0 15:11 RSVD2 10:9 LST_MODE RO 0x0 RW 0x0 8 LOCAL_SLAVE_TEST RW 0x0 7:5 4 3 RSVD1 FORCE_CLK_ON FORCE_ARB_LOSS RO 0x0 RW 0x0 RW 0x0 2 FORCE_RCV_ACK RW 0x0 1 FORCE_I2C_DATA_OE RW 0x0 0 FORCE_I2C_CLK_OE RW 0x0 Writting a one to this bit places the slave in local test mode. one of three slave address can be sent in either read or write mode. Always set this bit field to zero. Writing a one to this bit will force the clock generator to send a continuous stream of clocks on the I2C bus. Writing a one to this bit will force the appearance of an arbitration loss on the next one a master attempts to transmit. Writing a one to this bit will force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer. Writting a one to this bit will force an output enable at the pad. The pad data line is tied to zero. Thus the I2C data line will either be hi-z or zero. Writing a one to this bit will force an output enable at the pad. The pad data line is tied to zero. Thus the I2C clock line will either be hi-z or zero. DESCRIPTION: This register provides access to the I2C clock and data pad cell state that are used in diagnostic modes of operation. EXAMPLE: while(HW_I2C_DEBUG1.I2C_CLK_IN == 0); // wait for I2C clock line to go high 25.4.10 I2C Version Register Description This register always returns a known read value for debug purposes it indicates the version of the block. HW_I2C_VERSION 0x090 i.MX23 Applications Processor Reference Manual, Rev. 1 25-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor I2C Interface Table 25-33. HW_I2C_VERSION 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 25-34. HW_I2C_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x01 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x02 RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_I2C_VERSION.B.MAJOR != 1) Error(); I2C Block v1.3, Revision 1.54 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25-31 I2C Interface i.MX23 Applications Processor Reference Manual, Rev. 1 25-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 26 Application UART This chapter describes the Application UART included on the i.MX23, how to operate it, and how to disable the FIFOs. Programmable registers are described in Section 26.4, "Programmable Registers." 26.1 * * * * * * Overview Performs serial-to-parallel conversion on data received from a peripheral device. Performs parallel-to-serial conversion on data transmitted to the peripheral device. Operates up to 3.25 Mb/s. IrDA is not supported. Application UART2 is only available in the 169-pin BGA package. Application UART1 flow control is not avaiable in the 128-pin LQFP package. The Application UART: The Application UART has certain package dependencies: The CPU or DMA controller reads and writes data and control/status information through the APBX interface. The transmit and receive paths are buffered with internal FIFO memories, enabling up to 16-bytes to be stored independently in both transmit and receive modes. The Application UART includes a programmable baud rate generator that generates a transmit and receive internal clock from the 24-MHz UART internal reference clock input UARTCLK. XCLK is not tied to the UARTCLK in the i.MX23. It offers similar functionality to the industry-standard 16C550 UART device and supports baud rates of up to 3.25 Mbits/s (in high-speed configuration with a minimum XCLK frequency of 1.5 MHz). Figure 26-1 shows a block diagram of the Application UART. The Application UART operation and baud rate values are controlled by the line control register (HW_UARTAPP_LINECTRL). The HW_UARTAPP_LINECTRL register controls both receive and transmit operations. However, when HW_UARTAPP_CTRL2_USE_LCR2 is set, then HW_UARTAPP_LINECTRL controls receive operations and HW_UARTAPP_LINECTRL2 controls transmit operations. The Application UART can generate a single combined interrupt, so that the output is asserted if any of the individual interrupts are asserted and unmasked. Interrupt sources include the receive (including timeout), transmit, modem status, and error conditions. Two DMA channels are supported, one for transmit and one for receive. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 26-1 Application UART If a timeout condition occurs in the middle of a receive DMA block transfer, then the UART ends the DMA transfer and signals the end of the DMA block transfer. A receive DMA can be setup to get the status of the previous receive DMA block transfer. The status indicates the amount of valid data bytes in the previous receive DMA block transfer. If a framing, parity, or break error occurs during reception, the appropriate error bit is set and stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and FIFO data is prevented from being overwritten. You can program the FIFOs to be one-byte deep, providing a conventional double-buffered UART interface. The modem status input signal Clear To Send (CTS) and output modem control line Request To Send (RTS) are supported. A programmable hardware flow control feature uses the nUARTCTS input and the nUARTRTS output to automatically control the serial data flow. ARM Core SRAM 24-MHz XTAL Osc. AHB AHB Slave AHB Master XCLK Divide by n APBX Master AHB-to-APBX Bridge APBX UART Programmable Registers and FIFOs UART2RX UART2RTS UART2CTS UART2TX RX FSM TX FSM BAUDRATE UART Figure 26-1. Application UART Block Diagram 26.2 * * * Operation Transmission parameters Word length Buffer mode i.MX23 Applications Processor Reference Manual, Rev. 1 Control data is written to the Application UART line control register. This register defines: 26-2 Preliminary--Subject to Change Without Notice UARTCLK Shared DMA XCLK Freescale Semiconductor Application UART * * * * Number of transmitted stop bits Parity mode Break generation Baud rate divisor If USE_LCR2 is set, the Application UART Line Control Register applies to the receive operation, and similar control data written to the Application UART Line Control 2 Register applies to the transmit operation. 26.2.1 Fractional Baud Rate Divider The baud rate divisor is calculated from the frequency of UARTCLK and the desired baud rate by using the following formula: divisor = (UARTCLK * 32) / baud rate, rounded to the nearest integer The divisor must be between 0x000000EC and 0x003FFFC0, inclusive. Program the lowest 6 bits of the divisor into BAUD_DIVFRAC, and the next 16 bits of the divisor into BAUD_DIVINT. 26.2.2 UART Character Frame Figure 26-2 illustrates the UART character frame. UARTTXD lsb msb 1-2 stop bits 1 0 n Start 5-8 data bits Parity bit if enabled Figure 26-2. Application UART Character Frame 26.2.3 DMA Operation The Application UART can generate a DMA request signal for interfacing with a Direct Memory Access (DMA) controller. Two DMA channels are supported, one for transmit and one for receive. Each channel has an associated 16-bit transfer counter for the number of bytes to transfer. Each DMA request is associated with one to four data bytes. For APBX DMA Channel 6, which is the UART RX channel, the first PIO word in the DMA command is CTRL0. However, for APBX DMA Channel 7, which is the UART TX, the first PIO word in a DMA command is CTRL1. At the end of a receive DMA block transfer, the status register indicates any error conditions. If a timeout condition occurs in the middle of a receive DMA block transfer, then the UART sends dummy data to the DMA controller until the transfer counter is decremented to zero. A receive DMA can be setup to get the i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 26-3 Application UART status of the previous receive DMA block transfer. The status indicates the amount of valid data bytes in the previous receive DMA block transfer. 26.2.4 Data Transmission or Reception Data received or transmitted is stored in two 16-byte FIFOs, although the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the Application UART is enabled, it causes a data frame to start transmitting with the parameters indicated in UARTLCR_H or UARTLCR2_H (if USE_LCR2 is set). Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY signal goes HIGH as soon as data is written to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted HIGH while data is being transmitted. BUSY is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. BUSY can be asserted HIGH, even though the Application UART might no longer be enabled. For each sample of data, three readings are taken and the majority value is kept. In the following paragraphs, the middle sampling point is defined, and one sample is taken on either side of it. * When the receiver is idle (UARTRXD continuously 1, in the marking state) and a LOW is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by BaudClk, begins running and data is sampled on the first cycle of that counter in normal UART mode to allow for the shorter logic 0 pulses (half way through a bit period). The start bit is valid if UARTRXD is still LOW on the first cycle of BaudClk, otherwise a false start bit is detected and it is ignored. If the start bit was valid, successive data bits are sampled on every second cycle of BaudClk (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Lastly, a valid stop bit is confirmed if UARTRXD is HIGH, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word (see Table 26-1). * * 26.2.5 Error Bits Three error bits are stored in bits [10:8] of the receive FIFO and are associated with a particular character. An additional error indicating an overrun error is stored in bit 11 of the receive FIFO. 26.2.6 Overrun Bit The overrun bit is not associated with the character in the receive FIFO. The overrun error is set when the FIFO is full and the next character is completely received in the shift register. The data in the shift register is overwritten, but it is not written into the FIFO. When an empty location is available in the receive FIFO and another character is received, the state of the overrun bit is copied into the receive FIFO along with i.MX23 Applications Processor Reference Manual, Rev. 1 26-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Application UART the received character. The overrun state is then cleared. Table 26-1 shows the bit functions of the receive FIFO. Table 26-1. Receive FIFO Bit Functions FIFO BIT FUNCTION 11 10 9 8 7:0 Overrun indicator Break error Parity error Framing error Received data 26.2.7 Disabling the FIFOs FIFOs can be disabled. In this case, the transmit and receive sides of the Application UART have one-byte holding registers (the bottom entry of the FIFOs). The overrun bit is set when a word has been received and the previous one was not yet read. In this implementation, the FIFOs are not physically disabled, but the flags are manipulated to give the illusion of a one-byte register. 26.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block." for additional information on using the SFTRST and CLKGATE bit fields. 26.4 Programmable Registers This section describes the Application UART's programable registers. 26.4.1 UART Receive DMA Control Register Description The UART Receive DMA Control Register contains the dynamic information associated with the receive command. HW_UARTAPP_CTRL0 HW_UARTAPP_CTRL0_SET HW_UARTAPP_CTRL0_CLR HW_UARTAPP_CTRL0_TOG 0x000 0x004 0x008 0x00C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 26-5 Application UART Table 26-2. HW_UARTAPP_CTRL0 3 1 3 0 CLKGATE 2 9 2 8 RX_SOURCE 2 7 RXTO_ENABLE 2 6 2 5 2 4 2 3 2 2 2 1 RXTIMEOUT 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 XFER_COUNT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SFTRST RUN Table 26-3. HW_UARTAPP_CTRL0 Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Set to zero for normal operation. When this bit is set to one (default), then the entire block is held in its reset state. Set this bit zero for normal operation. Setting this bit to one (default), gates all of the block level clocks off for miniminizing AC energy consumption. Tell the UART to execute the RX DMA Command. The UART will clear this bit at the end of receive execution. Source of Receive Data. If this bit is set to 1, the status register will be the source of the DMA, otherwise RX data will be the source. RXTIMEOUT Enable: If this bit is set to 0, the RX timeout will not affect receive DMA operation. If this bit is set to 1, a receive timeout will cause the receive DMA logic to terminate. Receive Timeout Counter Value: number of 8-bit-time to wait before asserting timeout on the RX input. If the RXFIFO is not empty and the RX input is idle, then the watchdog counter will decrement each bit-time. Note 7-bit-time is added to the programmed value, so a value of zero will set the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also note that the counter is reloaded at the end of each frame, so if the frame is 10 bits long and the timeout counter value is zero, then timeout will occur (when FIFO is not empty) even if the RX input is not idle. The default value is 0x3 (31 bit-time). Number of bytes to receive. This must be a multiple of 4. 30 CLKGATE RW 0x1 29 28 RUN RX_SOURCE RW 0x0 RW 0x0 27 RXTO_ENABLE RW 0x0 26:16 RXTIMEOUT RW 0x03 15:0 XFER_COUNT RW 0x00 DESCRIPTION: This register contains the main DMA controls for Receiving data. EXAMPLE: No Example. i.MX23 Applications Processor Reference Manual, Rev. 1 26-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Application UART 26.4.2 UART Transmit DMA Control Register Description The UART Transmit DMA Control Register contains the dynamic information associated with the transmit command. HW_UARTAPP_CTRL1 HW_UARTAPP_CTRL1_SET HW_UARTAPP_CTRL1_CLR HW_UARTAPP_CTRL1_TOG Table 26-4. HW_UARTAPP_CTRL1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 XFER_COUNT 0x010 0x014 0x018 0x01C 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSVD2 Table 26-5. HW_UARTAPP_CTRL1 Bit Field Descriptions BITS 31:29 RSVD2 RUN 28 LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Reserved, read as zero, do not modify. Tell the UART to execute the TX DMA Command. The UART will clear this bit at the end of transmit execution. Reserved, read as zero, do not modify. Number of bytes to transmit. RSVD1 RUN 27:16 RSVD1 15:0 XFER_COUNT RO 0x0 RW 0x00 DESCRIPTION: This register contains the main DMA controls for Transmitting data. EXAMPLE: No Example. 26.4.3 UART Control Register Description The UART Control Register contains configuation, including interrupt FIFO level select and the DMA control. HW_UARTAPP_CTRL2 HW_UARTAPP_CTRL2_SET HW_UARTAPP_CTRL2_CLR HW_UARTAPP_CTRL2_TOG 0x020 0x024 0x028 0x02C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 26-7 Application UART Table 26-6. HW_UARTAPP_CTRL2 3 1 INVERT_RTS 3 0 INVERT_CTS 2 9 2 8 2 7 RTS_SEMAPHORE 2 6 DMAONERR 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 INVERT_RX INVERT_TX USE_LCR2 RXIFLSEL TXIFLSEL RXDMAE TXDMAE Table 26-7. HW_UARTAPP_CTRL2 Bit Field Descriptions BITS LABEL 31 INVERT_RTS RW RESET RW 0x0 DEFINITION Invert RTS signal. If this bit is set to 1, the RTS output is inverted before transmitted. Invert CTS signal. If this bit is set to 1, the CTS input is inverted before sampled. Invert TX signal. If this bit is set to 1, the TX output is inverted before transmitted. Invert RX signal. If this bit is set to 1, the RX input is inverted before sampled. If this bit is set to 1, RTS is deasserted when the semaphore threshold is less than 2. DMA On Error. If this bit is set to 1, receive dma will terminate on error. (Cmd_end signal may not be asserted when this occurs.) Transmit DMA Enable. Data Register can be loaded with up to 4 bytes per write. TXFIFO must be enabled in TXDMA mode. Receive DMA Enable. Data Register can be contain up to 4 bytes per read. RXFIFO must be enabled in RXDMA mode. Reserved, do not modify, read as zero. Receive Interrupt FIFO Level Select. The trigger points for the receive interrupt are as follows: NOT_EMPTY = 0x0 Trigger on FIFO not empty, i.e., at least 1 of 16 entries. ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries. ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries. THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries. SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries. INVALID5 = 0x5 Reserved. INVALID6 = 0x6 Reserved. INVALID7 = 0x7 Reserved. 30 29 28 27 26 INVERT_CTS INVERT_TX INVERT_RX RTS_SEMAPHORE DMAONERR RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 25 TXDMAE RW 0x0 24 RXDMAE RW 0x0 RSVD5 23 22:20 RXIFLSEL RO 0x0 RW 0x2 19 RSVD4 18:16 TXIFLSEL RO 0x0 RW 0x2 Reserved, do not modify, read as zero. Transmit Interrupt FIFO Level Select. The trigger points for the transmit interrupt are as follows: EMPTY = 0x0 Trigger on FIFO empty, i.e., no entries. ONE_QUARTER = 0x1 Trigger on FIFO less than 4 of 16 entries. ONE_HALF = 0x2 Trigger on FIFO less than 8 of 16 entries. THREE_QUARTERS = 0x3 Trigger on FIFO less than 12 of 16 entries. SEVEN_EIGHTHS = 0x4 Trigger on FIFO less than 14 of 16 entries. INVALID5 = 0x5 Reserved. INVALID6 = 0x6 Reserved. INVALID7 = 0x7 Reserved. i.MX23 Applications Processor Reference Manual, Rev. 1 26-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor UARTEN CTSEN RTSEN RSVD3 RSVD2 RSVD5 RSVD4 RSVD1 OUT2 OUT1 DTR RXE RTS LBE TXE Application UART Table 26-7. HW_UARTAPP_CTRL2 Bit Field Descriptions BITS 15 CTSEN LABEL RW RESET RW 0x0 DEFINITION CTS Hardware Flow Control Enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. RTS Hardware Flow Control Enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. The FIFO space is controlled by RXIFLSEL value. This bit is the complement of the UART Out2 (nUARTOut2) modem status output. This bit is not supported. This bit is the complement of the UART Out1 (nUARTOut1) modem status output. This bit is not supported. Request To Send. Software can manually control the nUARTRTS pin via this bit when RTSEN = 0. This bit is the complement of the UART request to send (nUARTRTS) modem status output. That is, when the bit is programmed to a 1, the output is 0. Data Transmit Ready. This bit is the complement of the UART data transmit ready (nUARTDTR) modem status output. This bit is not supported. Receive Enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for the UART signals. When the UART is disabled in the middle of reception, it completes the current character before stopping. Transmit Enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for the UART signals. When the UART is disabled in the middle of transmission, it completes the current character before stopping. Loop Back Enable. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, the UARTTXD path is fed through to the UARTRXD path. When this bit is set, the modem outputs are also fed through to the modem inputs. =If this bit is set to 1, the Line Control 2 Register values are used. Reserved, do not modify, read as zero. Program this field to 0x0. Program this field to 0x0. UART Enable. If this bit is set to 1, the UART is enabled. Data transmission and reception occurs for the UART signals. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 14 RTSEN RW 0x0 13 OUT2 RW 0x0 12 OUT1 RW 0x0 11 RTS RW 0x0 10 DTR RW 0x0 9 RXE RW 0x1 8 TXE RW 0x1 7 LBE RW 0x0 6 5:3 2 1 0 USE_LCR2 RSVD3 RSVD2 RSVD1 UARTEN RW 0x0 RO RW RW RW 0x0 0x0 0x0 0x0 DESCRIPTION: Use this register to define the FIFO level at which the UARTTXINTR and UARTRXINTR are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 26-9 Application UART is, the design is such that the interrupts are generated when the fill level progresses through the trigger level. The bits are reset so that the trigger level is when the FIFOs are at the half-way mark. EXAMPLE: No Example. 26.4.4 UART Line Control Register Description The UART Line Control Register contains integer and fractional part of the baud rate divisor value. It also contains the line control bits. HW_UARTAPP_LINECTRL HW_UARTAPP_LINECTRL_SET HW_UARTAPP_LINECTRL_CLR HW_UARTAPP_LINECTRL_TOG Table 26-8. HW_UARTAPP_LINECTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 BAUD_DIVINT 0x030 0x034 0x038 0x03C 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 BAUD_DIVFRAC 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 WLEN RSVD STP2 Table 26-9. HW_UARTAPP_LINECTRL Bit Field Descriptions BITS LABEL 31:16 BAUD_DIVINT 15:14 RSVD 13:8 BAUD_DIVFRAC RW RESET RW 0x0 RO 0x0 RW 0x0 DEFINITION Baud Rate Integer [15:0]. The integer baud rate divisor. Reserved, do not modify, read as zero. Baud Rate Fraction [5:0]. The fractional baud rate divisor. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this bit is cleared stick parity is disabled. Word length [1:0]. The select bits indicate the number of data bits transmitted or received in a frame as follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits. Enable FIFOs. If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, the FIFOs are disabled (character mode); that is, the FIFOs become 1-byte-deep holding registers. Two Stop Bits Select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. 7 SPS RW 0x0 6:5 WLEN RW 0x0 4 FEN RW 0x0 3 STP2 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 26-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor BRK PEN FEN SPS EPS Application UART Table 26-9. HW_UARTAPP_LINECTRL Bit Field Descriptions BITS 2 EPS LABEL RW RESET RW 0x0 DEFINITION Even Parity Select. If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed which checks for an odd number of 1s. This bit has no effect when parity is disabled by Parity Enable (PEN, bit 1) being cleared to 0. Parity Enable. If this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no parity bit added to the data frame. Send Break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. 1 PEN RW 0x0 0 BRK RW 0x0 DESCRIPTION: The UART Line Control Register contains integer and fractional part of the baud rate divisor value. It also contains the line control bits. EXAMPLE: No Example. 26.4.5 UART Line Control 2 Register Description The UART Line Control 2 Register contains integer and fractional part of the baud rate divisor value. It also contains the line control bits. HW_UARTAPP_LINECTRL2 HW_UARTAPP_LINECTRL2_SET HW_UARTAPP_LINECTRL2_CLR HW_UARTAPP_LINECTRL2_TOG 0x040 0x044 0x048 0x04C Table 26-10. HW_UARTAPP_LINECTRL2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 BAUD_DIVINT 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 BAUD_DIVFRAC 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 WLEN RSVD STP2 PEN FEN SPS EPS 26-11 Application UART Table 26-11. HW_UARTAPP_LINECTRL2 Bit Field Descriptions BITS LABEL 31:16 BAUD_DIVINT 15:14 RSVD 13:8 BAUD_DIVFRAC RW RESET RW 0x0 RO 0x0 RW 0x0 DEFINITION Baud Rate Integer [15:0]. The integer baud rate divisor. Reserved, do not modify, read as zero. Baud Rate Fraction [5:0]. The fractional baud rate divisor. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this bit is cleared stick parity is disabled. Word length [1:0]. The select bits indicate the number of data bits transmitted or received in a frame as follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits. Enable FIFOs. If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, the FIFOs are disabled (character mode); that is, the FIFOs become 1-byte-deep holding registers. Two Stop Bits Select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. Even Parity Select. If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed which checks for an odd number of 1s. This bit has no effect when parity is disabled by Parity Enable (PEN, bit 1) being cleared to 0. Parity Enable. If this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no parity bit added to the data frame. Reserved, do not modify, read as zero. 7 SPS RW 0x0 6:5 WLEN RW 0x0 4 FEN RW 0x0 3 STP2 RW 0x0 2 EPS RW 0x0 1 PEN RW 0x0 0 RSVD1 RO 0x0 DESCRIPTION: The UART Line Control 2 Register contains integer and fractional part of the baud rate divisor value. It also contains the line control bits. EXAMPLE: No Example. 26.4.6 UART Interrupt Register Description The UART Interrupt Register contains the interrupt enables and the interrupt status. The interrupt status bits report the unmasked state of the interrupts. To clear a particular interrupt status bit, write the bit-clear address with the particular bit set to 1. The enable bits control the UART interrupt output: a 1 will enable a particular interrupt to assert the UART interrupt output, while a 0 will disable the particular interrupt from affecting the interrupt output. All the bits, except for the modem status interrupt bits, are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. HW_UARTAPP_INTR 0x050 i.MX23 Applications Processor Reference Manual, Rev. 1 26-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Application UART HW_UARTAPP_INTR_SET HW_UARTAPP_INTR_CLR HW_UARTAPP_INTR_TOG Table 26-12. HW_UARTAPP_INTR 3 1 3 0 2 9 RSVD1 0x054 0x058 0x05C 2 8 2 7 2 6 OEIEN 2 5 BEIEN 2 4 PEIEN 2 3 FEIEN 2 2 RTIEN 2 1 TXIEN 2 0 RXIEN 1 9 DSRMIEN 1 8 DCDMIEN 1 7 CTSMIEN 1 6 RIMIEN 1 5 1 4 1 3 RSVD2 1 2 1 1 1 0 OEIS 0 9 BEIS 0 8 PEIS 0 7 FEIS 0 6 RTIS 0 5 TXIS 0 4 RXIS 0 3 DSRMIS 0 2 DCDMIS 0 1 CTSMIS 0 0 RIMIS Table 26-13. HW_UARTAPP_INTR Bit Field Descriptions BITS 31:27 26 25 24 23 22 21 20 19 LABEL RSVD1 OEIEN BEIEN PEIEN FEIEN RTIEN TXIEN RXIEN DSRMIEN DCDMIEN CTSMIEN RIMIEN RW RO RW RW RW RW RW RW RW RW RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 DEFINITION Reserved, read as zero, do not modify. Overrun Error Interrupt Enable. Break Error Interrupt Enable. Parity Error Interrupt Enable. Framing Error Interrupt Enable. Receive Timeout Interrupt Enable. Transmit Interrupt Enable. Receive Interrupt Enable. nUARTDSR Modem Interrupt Enable. This bit is not supported. nUARTDCD Modem Interrupt Enable. This bit is not supported. nUARTCTS Modem Interrupt Enable. nUARTRI Modem Interrupt Enable. This bit is not supported. Reserved, read as zero, do not modify. Overrun Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. Break Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. Parity Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. Framing Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. Receive Timeout Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. Transmit Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. Receive Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. nUARTDSR Modem Interrupt Status. This bit is not supported. nUARTDCD Modem Interrupt Status. This bit is not supported. 18 17 16 RW 0x0 RW 0x0 RW 0x0 RO 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 15:11 RSVD2 OEIS 10 9 8 7 6 BEIS PEIS FEIS RTIS 5 4 3 2 TXIS RXIS DSRMIS DCDMIS RW 0x0 RW 0x0 RW 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 26-13 Application UART Table 26-13. HW_UARTAPP_INTR Bit Field Descriptions BITS 1 CTSMIS LABEL RW RESET RW 0x0 DEFINITION nUARTCTS Modem Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. nUARTRI Modem Interrupt Status. This bit is not supported. 0 RIMIS RW 0x0 DESCRIPTION: The UART Interrupt Register contains the interrupt enables and the interrupt status. The interrupt status bits report the unmasked state of the interrupts. To clear a particular interrupt status bit, write the bit-clear address with the particular bit set to 1. The enable bits control the UART interrupt output: a 1 will enable a particular interrupt to assert the UART interrupt output, while a 0 will disable the particular interrupt from affecting the interrupt output. All the bits, except for the modem status interrupt bits, are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. EXAMPLE: No Example. 26.4.7 UART Data Register Description The UART Data Register is the receive and transmit data register. Receive (read) and transmit (write) up to four data characters per APB cycle. HW_UARTAPP_DATA Table 26-14. HW_UARTAPP_DATA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x060 DATA Table 26-15. HW_UARTAPP_DATA Bit Field Descriptions BITS 31:0 DATA LABEL RW RESET RW 0x0 DEFINITION In DMA mode, up to 4 Received/Transmit characters can be accessed at a time. In PIO mode, only one character can be accessed at a time. The status register contains the receive data flags and valid bits. DESCRIPTION: For words to be transmitted: 1) If the FIFOs are enabled, data written to this location is pushed onto the transmit FIFO; 2) If the FIFOs are not enabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the PrimeCell UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. Note: With the use of APB byte-enables you can write 1, 2, or 4 valid bytes sumultaneously to the TXFIFO. The invalid bytes will also take up space in the TXFIFO. So every write cycle will consume 4 bytes in the TXFIFO. If TXFIFO is disabled, you must only write the LSByte of the DATA register. i.MX23 Applications Processor Reference Manual, Rev. 1 26-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Application UART For received words: 1) If the FIFOs are enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO; 2) if the FIFOs are not enabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data bytes (up to 4) are read by performing reads from the 32-bit DATA register. The status information can be read by a read of the UART Status register. The Overrun Error bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. The Break Error bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. When the Parity Error bit is set to 1, it indicates that the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the LCR_H register. In FIFO mode, this error is associated with the character at the top of the FIFO. When the Framing Error bit is set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. EXAMPLE: No Example. 26.4.8 UART Status Register Description The UART Status Register contains the various flags and receive status. If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the UART Data Register prior to reading the UART Status Register. The status information for overrun is set immediately when an overrun condition occurs. HW_UARTAPP_STAT Table 26-16. HW_UARTAPP_STAT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 RXBYTE_INVALID 0x070 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RXCOUNT PRESENT HISPEED OERR BERR PERR BUSY FERR RXFE RXFF TXFE TXFF CTS 26-15 Application UART Table 26-17. HW_UARTAPP_STAT Bit Field Descriptions BITS LABEL 31 PRESENT RW RESET RO 0x1 DEFINITION This read-only bit indicates that the Application UART function is present when it reads back a one. This Application UART function is not available on a device that returns a zero for this bit field. UNAVAILABLE = 0x0 UARTAPP is not present in this product. AVAILABLE = 0x1 UARTAPP is present in this product. 30 HISPEED RO 0x1 This read-only bit indicates that the high-speed function is present when it reads back a one. This high speed function is not available on a device that returns a zero for this bit field. UNAVAILABLE = 0x0 HISPEED is not present in this product. AVAILABLE = 0x1 HISPEED is present in this product. 29 28 27 BUSY CTS TXFE RO 0x0 RO 0x0 RO 0x1 26 25 24 23:20 RXFF TXFF RXFE RXBYTE_INVALID RO RO RO RW 0x0 0x0 0x1 0xf 19 OERR RO 0x0 18 BERR RW 0x0 17 PERR RW 0x0 UART Busy. Clear To Send. Transmit FIFO Empty. The meaning of this bit depends on the state of the FEN bit in the UART Line Control Register. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. Receive FIFO Full. Transmit FIFO Full. Receive FIFO Empty. The invalid state of the last read of Receive Data. Each bit corresponds to one byte of the RX data. (1 = invalid.) Overrun Error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by any write to the Status Register. The FIFO contents remain valid since no further data is written when the FIFO is full; only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. Break Error. For PIO mode, this is for the last character read from the data register. For DMA mode, it will be set to 1 if any received character for a particular RXDMA command had a Break Error. To clear this bit, write a zero to it. Note that clearing this bit does not affect the interrupt status, which must be cleared by writing the interrupt register. Parity Error. For PIO mode, this is for the last character read from the data register. For DMA mode, it will be set to 1 if any received character for a particular RXDMA command had a Parity Error. To clear this bit, write a zero to it. Note that clearing this bit does not affect the interrupt status, which must be cleared by writing the interrupt register. i.MX23 Applications Processor Reference Manual, Rev. 1 26-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Application UART Table 26-17. HW_UARTAPP_STAT Bit Field Descriptions BITS 16 FERR LABEL RW RESET RW 0x0 DEFINITION Framing Error. For PIO mode, this is for the last character read from the data register. For DMA mode, it will be set to 1 if any received character for a particular RXDMA command had a Framing Error. To clear this bit, write a zero to it. Note that clearing this bit does not affect the interrupt status, which must be cleared by writing the interrupt register. Number of bytes received during a Receive DMA command. 15:0 RXCOUNT RO 0x0 DESCRIPTION: Various UART status information is available in this register. EXAMPLE: No Example. 26.4.9 UART Debug Register Description HW_UARTAPP_DEBUG Table 26-18. HW_UARTAPP_DEBUG The UART Debug Register contains the state of the DMA signals. 0x080 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 RXIBAUD_DIV 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RXFBAUD_DIV 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 TXDMARUN 0 4 RXDMARUN 0 3 TXCMDEND 0 2 RXCMDEND 0 1 TXDMARQ 0 0 RXDMARQ Table 26-19. HW_UARTAPP_DEBUG Bit Field Descriptions BITS 31:16 15:10 9:6 5 LABEL RXIBAUD_DIV RXFBAUD_DIV RSVD1 TXDMARUN RXDMARUN TXCMDEND RXCMDEND RW RO RO RO RO RESET 0x0 0x0 0x0 0x0 DEFINITION RX Integer Baud Divisor. RX Fractional Baud Divisor. Reserved, read as zero, do not modify. DMA Command Run Status: This bit reflects the state of the toggle signal for TXDMARUN. DMA Command Run Status: This bit reflects the state of the toggle signal for RXDMARUN. DMA Command End Status: This bit reflects the state of the toggle signal for UART_TXCMDEND. DMA Command End Status: This bit reflects the state of the toggle signal for UART_RXCMDEND. 4 3 2 RO 0x0 RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSVD1 26-17 Application UART Table 26-19. HW_UARTAPP_DEBUG Bit Field Descriptions BITS LABEL 1 TXDMARQ RW RESET RO 0x0 DEFINITION DMA Request Status: This bit reflects the state of the toggle signal for UART_TXDMAREQ. Note that TX burst request is not supported. DMA Request Status: This bit reflects the state of the toggle signal for UART_RXDMAREQ. Note that RX burst request is not supported. 0 RXDMARQ RO 0x0 DESCRIPTION: The UART Debug Register contains the state of the DMA signals. EXAMPLE: No Example. 26.4.10 UART Version Register Description The UART version register can be used to read the version of the UARTAPP IP being used in this chip. HW_UARTAPP_VERSION Table 26-20. HW_UARTAPP_VERSION 3 1 3 0 2 9 2 8 MAJOR 0x090 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 26-21. HW_UARTAPP_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x3 DEFINITION Fixed read-only value reflecting the MAJOR field of RTL version. Fixed read-only value reflecting the MINOR field of RTL version. Fixed read-only value reflecting the stepping of RTL version. 23:16 MINOR 15:0 STEP RO 0x0 RO 0x0 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: No Example. 26.4.11 UART AutoBaud Register Description The UART AutoBaud register provides the reference characters and control info for the automatic baudrate detection logic. HW_UARTAPP_AUTOBAUD 0x0A0 i.MX23 Applications Processor Reference Manual, Rev. 1 26-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Application UART Table 26-22. HW_UARTAPP_AUTOBAUD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 TWO_REF_CHARS 0 2 START_WITH_RUNBIT 0 1 START_BAUD_DETECT 0 0 BAUD_DETECT_ENABLE Table 26-23. HW_UARTAPP_AUTOBAUD Bit Field Descriptions BITS LABEL 31:24 REFCHAR1 RW RESET RW 0x0 DEFINITION Second reference character used in baud rate detection. During autobaud detection of the second reference character received is available for reading, and is placed in the RXFIFO if TWO_REF_CHARS is a 1. This is ignored when TWO_REF_CHARS is 0. First reference character used in baud rate detection. During autobaud detection of the first character received is not available for reading. The UART receiver does not get this character and the RXFIFO is not updated. Reserved, read as zero, do not modify. Set this bit to 1 will cause the TX baud rate divisor to be updated when the RX baud rate divisor is updated by the autobaud detection logic. This should not be set if it is possible that transmit function may be busy. Set this bit to 1 when using 2 reference characters for baud detection, and set to 0 for 1 reference character. Set this bit to 1 will cause the assertion of HW_UARTAPP_CTRL0_RUN to start the autobaud detection logic. Set this bit to 0 will cause the assertion of START_BAUD_DETECT to start the autobaud detection logic. Set to 1 to start automatic baudrate detection. This bit is ignored when START_WITH_RUNBIT is set to 1. Each time a 1 is written to START_BAUD_DETECT it toggles the read value if START_WITH_RUNBIT is zero. Enable automatic baudrate detection. 23:16 REFCHAR0 RW 0x0 15:5 4 RSVD1 UPDATE_TX RO 0x0 RW 0x0 3 2 TWO_REF_CHARS START_WITH_RUNBIT RW 0x0 RW 0x0 1 START_BAUD_DETECT RW 0x0 0 BAUD_DETECT_ENABLE RW 0x0 DESCRIPTION: This automatic baudrate detection logic used one or two reference character to dectect the baud rate of the received data. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice UPDATE_TX REFCHAR1 REFCHAR0 RSVD1 26-19 Application UART EXAMPLE: No Example. UARTAPP Block v3.0, Revision 1.42 i.MX23 Applications Processor Reference Manual, Rev. 1 26-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 27 Debug UART This chapter describes the debug UART included on the i.MX23, how to operate it, and how to disable the FIFOs. Programmable registers are described in Section 27.3, "Programmable Registers." 27.1 * * Overview Serial-to-parallel conversion on data received from a peripheral device Parallel-to-serial conversion on data transmitted to the peripheral device The debug UART performs: The CPU reads and writes data and control/status information through the APBX interface. The transmit and receive paths are buffered with internal FIFO memories, enabling up to 16 bytes to be stored independently in both transmit and receive modes. The debug UART includes a programmable baud rate generator that creates a transmit and receive internal clock from the 24-MHz UART internal reference clock input UARTCLK. XCLK is not tied to the UARTCLK in the i.MX23. It offers similar functionality to the industry-standard 16C550 UART device and supports baud rates of up to 115 Kb/s. Figure 27-2 shows a block diagram of the debug UART. The debug UART operation and baud rate values are controlled by the line control register (HW_UARTDBGLCR_H, HW_UARTDBGIBRD, and HW_UARTDBGFBRD). The debug UART can generate a single combined interrupt, so output is asserted if any individual interrupt is asserted and unmasked. Interrupt sources include the receive (including time-out), transmit, modem status, and error conditions. If a framing, parity, or break error occurs during reception, the appropriate error bit is set, and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately, and FIFO data is prevented from being overwritten. You can program the FIFOs to be one-byte deep, providing a conventional double-buffered UART interface. Note: Names for the external pins used by the debug UART begin with "UART1". Pin names beginning with "UART2" are used by the Application UART. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27-1 Debug UART ARM Core SRAM 24-MHz XTAL Osc. AHB AHB Slave XCLK Divide by n AHB-to-APBX Bridge APBX Master APBX UART Programmable Registers and FIFOs UART1_RX UART1_TX RX FSM TX FSM BAUDRATE UART Figure 27-1. Debug UART Block Diagram 27.2 * * * * * * * Operation Transmission parameters Word length Buffer mode Number of transmitted stop bits Parity mode Break generation Baud rate divisor Control data is written to the debug UART line control register. This register defines: 27.2.1 Fractional Baud Rate Divider The baud rate divisor is calculated from the frequency of UARTCLK and the desired baud rate by using the following formula: divisor = (UARTCLK * 4) / baud rate, rounded to the nearest integer The divisor must be between 0x00000040 and 0x003FFFC0, inclusive. Program the lowest 6 bits of the divisor into BAUD_DIVFRAC, and the next 16 bits of the divisor into BAUD_DIVINT. i.MX23 Applications Processor Reference Manual, Rev. 1 27-2 Preliminary--Subject to Change Without Notice UARTCLK XCLK Freescale Semiconductor Debug UART In the debug UART, HW_UARTDBGLCR_H, HW_UARTDBGIBRD and HW_UARTDBGFBRD form a single 30-bit wide register (UARTLCR) that is updated on a single write strobe generated by an HW_UARTDBGLCR_H write. So, in order to internally update the contents of HW_UARTDBGIBRD or HW_UARTDBGFBRD, a write to HW_UARTDBGLCR_H must always be performed at the end. 27.2.2 UART Character Frame Figure 27-2 illustrates the UART character frame. UARTTXD lsb msb 1-2 stop bits 1 0 n Start 5-8 data bits Parity bit if enabled Figure 27-2. Debug UART Character Frame 27.2.3 Data Transmission or Reception Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the debug UART is enabled, it causes a data frame to start transmitting with the parameters indicated in UARTLCR_H. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY signal goes HIGH as soon as data is written to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted HIGH while data is being transmitted. BUSY is negated only when the transmit FIFO is empty and the last character has been transmitted from the shift register, including the stop bits. BUSY can be asserted HIGH even though the debug UART might no longer be enabled. For each sample of data, three readings are taken and the majority value is kept. In the following paragraphs, the middle sampling point is defined and one sample is taken either side of it. * When the receiver is idle (UARTRXD continuously 1, in the marking state) and a LOW is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by Baud16, begins running and data is sampled on the eighth cycle of that counter in normal UART mode to allow for the shorter logic 0 pulses (half way through a bit period). The start bit is valid if UARTRXD is still LOW on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked, if parity mode was enabled. * i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27-3 Debug UART * Lastly, a valid stop bit is confirmed if UARTRXD is HIGH, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word (see Table 27-1). 27.2.4 Error Bits Three error bits are stored in bits [10:8] of the receive FIFO and are associated with a particular character. An additional error indicating an overrun error is stored in bit 11 of the receive FIFO. 27.2.5 Overrun Bit The overrun bit is not associated with the character in the receive FIFO. The overrun error is set when the FIFO is full, and the next character is completely received in the shift register. The data in the shift register is overwritten, but it is not written into the FIFO. When an empty location is available in the receive FIFO, and another character is received, the state of the overrun bit is copied into the receive FIFO along with the received character. The overrun state is then cleared. Table 27-1 shows the bit functions of the receive FIFO. Table 27-1. Receive FIFO Bit Functions FIFO BIT FUNCTION 11 10 9 8 7:0 Overrun indicator Break error Parity error Framing error Received data 27.2.6 Disabling the FIFOs FIFOs can be disabled. In this case, the transmit and receive sides of the UART have one-byte holding registers (the bottom entry of the FIFOs). The overrun bit is set when a word has been received and the previous one was not yet read. In this implementation, the FIFOs are not physically disabled, but the flags are manipulated to give the illusion of a one-byte register. 27.3 Programmable Registers This section describes the debug UART's programable registers. i.MX23 Applications Processor Reference Manual, Rev. 1 27-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Debug UART 27.3.1 UART Data Register Description Debug Uart Data Register. For words to be transmitted: 1) If the FIFOs are enabled, data written to this location is pushed onto the transmit FIFO 2) If the FIFOs are not enabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the PrimeCell UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: 1) If the FIFOs are enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO 2) If the FIFOs are not enabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data byte is read by performing reads from the DR register along with the corresponding status information. The status information can also be read by a read of the RSR_ECR register. HW_UARTDBGDR Table 27-2. HW_UARTDBGDR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNAVAILABLE 0x000 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 RESERVED 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 27-3. HW_UARTDBGDR Bit Field Descriptions BITS LABEL 31:16 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Reserved. Overrun Error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. Break Error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. Parity Error. When this bit is set to 1, it indicates that the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the LCR_H register. In FIFO mode, this error is associated with the character at the top of the FIFO. 15:12 RESERVED OE 11 RO 0x0 RO 0x0 10 BE RO 0x0 9 PE RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice DATA OE BE PE FE 27-5 Debug UART Table 27-3. HW_UARTDBGDR Bit Field Descriptions BITS 8 FE LABEL RW RESET RO 0x0 DEFINITION Framing Error. When this bit is set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. Receive (read) data character. Transmit (write) data character. 7:0 DATA RW 0x0 DESCRIPTION: Debug Uart Data Register. For words to be transmitted: 1) If the FIFOs are enabled, data written to this location is pushed onto the transmit FIFO 2) If the FIFOs are not enabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the PrimeCell UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: 1) If the FIFOs are enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO 2) If the FIFOs are not enabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data byte is read by performing reads from the DR register along with the corresponding status information. The status information can also be read by a read of the RSR_ECR register. EXAMPLE: No Example. 27.3.2 UART Receive Status Register (Read) / Error Clear Register (Write) Description The RSR_ECR register is the receive status register/error clear register. Receive status can also be read from RSR_ECR. If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from DR prior to reading RSR_ECR. The status information for overrun is set immediately when an overrun condition occurs. A write to RSR_ECR clears the framing, parity, break, and overrun errors. HW_UARTDBGRSR_ECR Table 27-4. HW_UARTDBGRSR_ECR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 UNAVAILABLE 0x004 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 OE EC BE PE i.MX23 Applications Processor Reference Manual, Rev. 1 27-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor FE Debug UART Table 27-5. HW_UARTDBGRSR_ECR Bit Field Descriptions BITS LABEL 31:8 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Error Clear. Any write to this bitfield clears the framing, parity, break, and overrun errors. The value is unpredictable when read. Overrun Error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by any write to RSR_ECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. Break Error. Parity Error. Framing Error. 7:4 EC RW 0x0 3 OE RW 0x0 2 1 0 BE PE FE RW 0x0 RW 0x0 RW 0x0 DESCRIPTION: The RSR_ECR register is the receive status register/error clear register. Receive status can also be read from RSR_ECR. If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from DR prior to reading RSR_ECR. The status information for overrun is set immediately when an overrun condition occurs. A write to RSR_ECR clears the framing, parity, break, and overrun errors. EXAMPLE: No Example. 27.3.3 UART Flag Register Description HW_UARTDBGFR Table 27-6. HW_UARTDBGFR The FR register is the flag register. 0x018 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNAVAILABLE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RESERVED 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BUSY RXFE RXFF TXFE TXFF DCD DSR i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice CTS RI 27-7 Debug UART Table 27-7. HW_UARTDBGFR Bit Field Descriptions BITS LABEL 31:16 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Reserved, do not modify, read as zero. Ring Indicator. This bit is the complement of the UART ring indicator (nUARTRI) modem status input. That is, the bit is 1 when the modem status input is 0. Transmit FIFO Empty. The meaning of this bit depends on the state of the FEN bit in the LCR_H register. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. Receive FIFO Full. Transmit FIFO Full. Receive FIFO Empty. UART Busy. Data Carrier Detect. Data Set Ready. Clear To Send. 15:9 8 RESERVED RI RO 0x0 RO 0x0 7 TXFE RO 0x1 6 5 4 3 2 1 0 RXFF TXFF RXFE BUSY DCD DSR CTS RO RO RO RO RO RO RO 0x0 0x0 0x1 0x0 0x0 0x0 0x0 DESCRIPTION: The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. EXAMPLE: No Example. 27.3.4 UART IrDA Low-Power Counter Register Description The ILPR register is the IrDA Low-Power Counter Register. This is an 8-bit read/write register which stores a low-power counter divisor value used to divde down the UARTCLK to generate the IrLPBaud16 signal. HW_UARTDBGILPR Table 27-8. HW_UARTDBGILPR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 UNAVAILABLE 0x020 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ILPDVSR 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 27-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Debug UART Table 27-9. HW_UARTDBGILPR Bit Field Descriptions BITS LABEL 31:8 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. IrDA Low Power Divisor [7:0]. 8-bit low-power divisor value. 7:0 ILPDVSR RW 0x0 DESCRIPTION: The ILPR register is the IrDA Low-Power Counter Register. This is an 8-bit read/write register which stores a low-power counter divisor value used to divde down the UARTCLK to generate the IrLPBaud16 signal. EXAMPLE: No Example. 27.3.5 UART Integer Baud Rate Divisor Register Description HW_UARTDBGIBRD Table 27-10. HW_UARTDBGIBRD The IBRD register is the integer part of the baud rate divisor value. 0x024 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNAVAILABLE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 BAUD_DIVINT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 27-11. HW_UARTDBGIBRD Bit Field Descriptions BITS LABEL 31:16 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Baud Rate Integer [15:0]. The integer baud rate divisor. 15:0 BAUD_DIVINT RW 0x0 DESCRIPTION: The IBRD register is the integer part of the baud rate divisor value. EXAMPLE: No Example. 27.3.6 UART Fractional Baud Rate Divisor Register Description The FBRD register is the fractional part of the baud rate divisor value. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27-9 Debug UART HW_UARTDBGFBRD Table 27-12. HW_UARTDBGFBRD 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 UNAVAILABLE 0x028 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 RESERVED 0 6 0 5 0 4 0 3 BAUD_DIVFRAC 0 2 0 1 0 0 Table 27-13. HW_UARTDBGFBRD Bit Field Descriptions BITS LABEL 31:8 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Not documented. Baud Rate Fraction [5:0]. The fractional baud rate divisor. 7:6 5:0 RESERVED BAUD_DIVFRAC RO 0x0 RW 0x0 DESCRIPTION: The FBRD register is the fractional part of the baud rate divisor value. EXAMPLE: No Example. 27.3.7 UART Line Control Register, HIGH Byte Description HW_UARTDBGLCR_H Table 27-14. HW_UARTDBGLCR_H The LCR_H is the Line Control Register. 0x02C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNAVAILABLE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 RESERVED 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 WLEN STP2 i.MX23 Applications Processor Reference Manual, Rev. 1 27-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor BRK PEN FEN EPS SPS Debug UART Table 27-15. HW_UARTDBGLCR_H Bit Field Descriptions BITS LABEL 31:16 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Reserved, do not modify, read as zero. Stick Parity Select. When bits 1, 2, and 7 of the LCR_H register are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this bit is cleared stick parity is disabled. Word length [1:0]. The select bits indicate the number of data bits transmitted or received in a frame as follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits. Enable FIFOs. If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, the FIFOs are disabled (character mode); that is, the FIFOs become 1-byte-deep holding registers. Two Stop Bits Select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. Even Parity Select. If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed which checks for an odd number of 1s. This bit has no effect when parity is disabled by Parity Enable (PEN, bit 1) being cleared to 0. Parity Enable. If this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no parity bit added to the data frame. Send Break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. 15:8 7 RESERVED SPS RO 0x0 RW 0x0 6:5 WLEN RW 0x0 4 FEN RW 0x0 3 STP2 RW 0x0 2 EPS RW 0x0 1 PEN RW 0x0 0 BRK RW 0x0 DESCRIPTION: The LCR_H is the Line Control Register. EXAMPLE: No Example. 27.3.8 UART Control Register Description HW_UARTDBGCR 0x030 The CR is the Control Register. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27-11 Debug UART Table 27-16. HW_UARTDBGCR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNAVAILABLE 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 RESERVED 0 4 0 3 0 2 0 1 0 0 UARTEN CTSEN RTSEN Table 27-17. HW_UARTDBGCR Bit Field Descriptions BITS LABEL 31:16 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. CTS Hardware Flow Control Enable. RTS Hardware Flow Control Enable. This bit is the complement of the UART Out2 (nUARTOut2) modem status output. Not Implemented. This bit is the complement of the UART Out1 (nUARTOut1) modem status output. Not Implemented. Request To Send. Data Transmit Ready. Not Implemented. Receive Enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for the UART signals. When the UART is disabled in the middle of reception, it completes the current character before stopping. Transmit Enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for the UART signals. When the UART is disabled in the middle of transmission, it completes the current character before stopping. Loop Back Enable. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, the UARTTXD path is fed through to the UARTRXD path. When this bit is set, the modem outputs are also fed through to the modem inputs. Reserved, do not modify, read as zero. IrDA SIR low-power mode. Not Supported. SIR Enable. Not Supported. UART Enable. If this bit is set to 1, the UART is enabled. Data transmission and reception occurs for the UART signals. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 15 14 13 12 11 10 9 CTSEN RTSEN OUT2 OUT1 RTS DTR RXE RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x1 8 TXE RW 0x1 7 LBE RW 0x0 6:3 2 1 0 RESERVED SIRLP SIREN UARTEN RO RW RW RW 0x0 0x0 0x0 0x0 DESCRIPTION: The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. i.MX23 Applications Processor Reference Manual, Rev. 1 27-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor SIREN SIRLP OUT2 OUT1 DTR RXE RTS LBE TXE Debug UART EXAMPLE: No Example. 27.3.9 UART Interrupt FIFO Level Select Register Description The IFLS register is the Interrupt FIFO Level Select Register. You can use the IFLS register to define the FIFO level at which the UARTTXINTR and UARTRXINTR are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the design is such that the interrupts are generated when the fill level progresses through the trigger level. The bits are reset so that the trigger level is when the FIFOs are at the half-way mark. HW_UARTDBGIFLS Table 27-18. HW_UARTDBGIFLS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNAVAILABLE 0x034 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 RESERVED 1 0 0 9 0 8 0 7 0 6 0 5 0 4 RXIFLSEL 0 3 0 2 0 1 TXIFLSEL 0 0 Table 27-19. HW_UARTDBGIFLS Bit Field Descriptions BITS LABEL 31:16 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Reserved, do not modify, read as zero. Receive Interrupt FIFO Level Select. The trigger points for the receive interrupt are as follows: NOT_EMPTY = 0x0 Trigger on FIFO not empty, i.e. at least 1 of 8 entries. ONE_QUARTER = 0x1 Trigger on FIFO full to at least 2 of 8 entries. ONE_HALF = 0x2 Trigger on FIFO full to at least 4 of 8 entries. THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 6 of 8 entries. SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 7 of 8 entries. INVALID5 = 0x5 Reserved. INVALID6 = 0x6 Reserved. INVALID7 = 0x7 Reserved. 15:6 5:3 RESERVED RXIFLSEL RO 0x0 RW 0x2 2:0 TXIFLSEL RW 0x2 Transmit Interrupt FIFO Level Select. The trigger points for the transmit interrupt are as follows: EMPTY = 0x0 Trigger on FIFO empty, i.e. no entries. ONE_QUARTER = 0x1 Trigger on FIFO less than 2 of 8 entries. ONE_HALF = 0x2 Trigger on FIFO less than 4 of 8 entries. THREE_QUARTERS = 0x3 Trigger on FIFO less than 6 of 8 entries. SEVEN_EIGHTHS = 0x4 Trigger on FIFO less than 7 of 8 entries. INVALID5 = 0x5 Reserved. INVALID6 = 0x6 Reserved. INVALID7 = 0x7 Reserved. DESCRIPTION: The IFLS register is the Interrupt FIFO Level Select Register. You can use the IFLS register to define the FIFO level at which the UARTTXINTR and UARTRXINTR are triggered. The interrupts are generated i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27-13 Debug UART based on a transition through a level rather than being based on the level. That is, the design is such that the interrupts are generated when the fill level progresses through the trigger level. The bits are reset so that the trigger level is when the FIFOs are at the half-way mark. EXAMPLE: No Example. 27.3.10 UART Interrupt Mask Set/Clear Register Description The IMSC register is the Interrupt Mask Set/Clear Register. On a read, this register gives the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask. HW_UARTDBGIMSC Table 27-20. HW_UARTDBGIMSC 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNAVAILABLE 0x038 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RESERVED 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 DSRMIM 0 2 DCDMIM 0 1 CTSMIM 0 0 Table 27-21. HW_UARTDBGIMSC Bit Field Descriptions BITS LABEL 31:16 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Reserved, do not modify, read as zero. Overrun Error Interrupt Mask. On a read, the current mask for the OEIM interrupt is returned. On a write of 1, the mask of the OEIM interrupt is set. A write of 0 clears the mask. Break Error Interrupt Mask. Parity Error Interrupt Mask. Framing Error Interrupt Mask. Receive Timeout Interrupt Mask. Transmit Interrupt Mask. Receive Interrupt Mask. nUARTDSR Modem Interrupt Mask. nUARTDCD Modem Interrupt Mask. nUARTCTS Modem Interrupt Mask. nUARTRI Modem Interrupt Mask. 15:11 RESERVED OEIM 10 RO 0x0 RW 0x0 9 8 7 6 5 4 3 2 1 0 BEIM PEIM FEIM RTIM TXIM RXIM DSRMIM DCDMIM CTSMIM RIMIM RW RW RW RW RW RW RW RW RW RW 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 27-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor RIMIM OEIM BEIM RXIM PEIM RTIM FEIM TXIM Debug UART DESCRIPTION: The IMSC register is the Interrupt Mask Set/Clear Register. On a read, this register gives the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask. EXAMPLE: No Example. 27.3.11 UART Raw Interrupt Status Register Description The RIS register is the Raw Interrupt Status Register. It is a read-only register. On a read this register gives the current raw status value of the corresponding interrupt. A write has no effect. All the bits, except for the modem status interrupt bits (bits 3 to 0), are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. HW_UARTDBGRIS Table 27-22. HW_UARTDBGRIS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNAVAILABLE 0x03C 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RESERVED 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 DSRRMIS 0 2 DCDRMIS 0 1 CTSRMIS 0 0 Table 27-23. HW_UARTDBGRIS Bit Field Descriptions BITS LABEL 31:16 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Reserved, read as zero, do not modify. Overrun Error Interrupt Status. Break Error Interrupt Status. Parity Error Interrupt Status. Framing Error Interrupt Status. Receive Timeout Interrupt Status. Transmit Interrupt Status. Receive Interrupt Status. nUARTDSR Modem Interrupt Status. nUARTDCD Modem Interrupt Status. nUARTCTS Modem Interrupt Status. nUARTRI Modem Interrupt Status. 15:11 10 9 8 7 6 5 4 3 2 1 0 RESERVED OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS DSRRMIS DCDRMIS CTSRMIS RIRMIS RO RO RO RO RO RO RO RO RO RO RO RO 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 DESCRIPTION: The RIS register is the Raw Interrupt Status Register. It is a read-only register. On a read this register gives the current raw status value of the corresponding interrupt. A write has no effect. All the bits, except for i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RIRMIS OERIS BERIS RXRIS PERIS RTRIS FERIS TXRIS 27-15 Debug UART the modem status interrupt bits (bits 3 to 0), are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. EXAMPLE: No Example. 27.3.12 UART Masked Interrupt Status Register Description The MIS register is the Masked Interrupt Status Register. It is a read-only register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. All the bits except for the modem status interrupt bits (bits 3 to 0) are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. HW_UARTDBGMIS Table 27-24. HW_UARTDBGMIS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNAVAILABLE 0x040 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RESERVED 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 DSRMMIS 0 2 DCDMMIS 0 1 CTSMMIS 0 0 Table 27-25. HW_UARTDBGMIS Bit Field Descriptions BITS LABEL 31:16 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Reserved, read as zero, do not modify. Overrun Error Masked Interrupt Status. Break Error Masked Interrupt Status. Parity Error Masked Interrupt Status. Framing Error Masked Interrupt Status. Receive Timeout Masked Interrupt Status. Transmit Masked Interrupt Status. Receive Masked Interrupt Status. nUARTDSR Modem Masked Interrupt Status. nUARTDCD Modem Masked Interrupt Status. nUARTCTS Modem Masked Interrupt Status. nUARTRI Modem Masked Interrupt Status. 15:11 10 9 8 7 6 5 4 3 2 1 0 RESERVED OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS DSRMMIS DCDMMIS CTSMMIS RIMMIS RO RO RO RO RO RO RO RO RO RO RO RO 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 DESCRIPTION: The MIS register is the Masked Interrupt Status Register. It is a read-only register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. All the bits except for the modem status interrupt bits (bits 3 to 0) are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. i.MX23 Applications Processor Reference Manual, Rev. 1 27-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor RIMMIS OEMIS BEMIS RXMIS PEMIS RTMIS FEMIS TXMIS Debug UART EXAMPLE: No Example. 27.3.13 UART Interrupt Clear Register Description The ICR register is the Interrupt Clear Register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. HW_UARTDBGICR Table 27-26. HW_UARTDBGICR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNAVAILABLE 0x044 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RESERVED 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 DSRMIC 0 2 DCDMIC 0 1 CTSMIC 0 0 Table 27-27. HW_UARTDBGICR Bit Field Descriptions BITS LABEL 31:16 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Reserved, read as zero, do not modify. Overrun Error Interrupt Clear. 15:11 RESERVED OEIC 10 9 8 7 6 5 4 3 2 1 0 BEIC PEIC FEIC RTIC TXIC RXIC DSRMIC DCDMIC CTSMIC RIMIC RO W O W O W O W O W O W O W O W O W O W O W O 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Break Error Interrupt Clear. Parity Error Interrupt Clear. Framing Error Interrupt Clear. Receive Timeout Interrupt Clear. Transmit Interrupt Clear. Receive Interrupt Clear. nUARTDSR Modem Interrupt Clear. nUARTDCD Modem Interrupt Clear. nUARTCTS Modem Interrupt Clear. nUARTRI Modem Interrupt Clear. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RIMIC OEIC BEIC RXIC PEIC RTIC FEIC TXIC 27-17 Debug UART DESCRIPTION: The ICR register is the Interrupt Clear Register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. EXAMPLE: No Example. 27.3.14 UART DMA Control Register Description This register is reserved. HW_UARTDBGDMACR Table 27-28. HW_UARTDBGDMACR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNAVAILABLE 0x048 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 RESERVED 0 8 0 7 0 6 0 5 0 4 0 3 0 2 DMAONERR 0 1 TXDMAE 0 0 RXDMAE Table 27-29. HW_UARTDBGDMACR Bit Field Descriptions BITS LABEL 31:16 UNAVAILABLE RW RESET RO 0x0 DEFINITION The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Reserved. Reserved. Reserved. Reserved. 15:3 2 1 0 RESERVED DMAONERR TXDMAE RXDMAE RO RW RW RW 0x0 0x0 0x0 0x0 DESCRIPTION: This register is reserved. EXAMPLE: No Example. UARTDBG Block v2.0, Revision 1.21 i.MX23 Applications Processor Reference Manual, Rev. 1 27-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 28 AUDIOIN/ADC This chapter describes the AUDIOIN/ADC module implemented on the i.MX23, including DMA, sample rate conversion, and internal operation. Programmable registers are described in Section 28.4, "Programmable Registers." 28.1 Overview The i.MX23 features an audio record path that consists of a sigma-delta analog-to-digital converter (ADC), followed by the AUDIOIN digital multi-stage Finite Impulse Response (FIR) filter. The microphone or line input is oversampled by the ADC, and the 1-bit digital stream is input to a cascaded-integrator comb filter, where the signal is parallelized, sent through a high-pass filter to remove DC offset, and the sample rate is converted to the AUDIOIN's internal rate. Next, the signal is filtered using a three-stage FIR filter. The resultant parallel PCM samples are then transferred to a buffer in memory using the APBX bridge DMA, where it can be read by system software. The analog audio source can be selected from one of three possible inputs: * * * * * * * Mono microphone input, with settings for 0dB, 20dB, 30dB and 40dB gain. Stereo line inputs, with 0dB to 22.5dB gain, in 1.5dB steps. Looped back from the stereo headphone amplifier Serial to parallel bit-stream integrator/averager Sample rate converting (SRC) cascaded-integrator comb (CIC) filter High-pass filter (HPF) Three-stage downsampling FIR filter: 7-tap (8:4), 11-tap (4:2), 33-tap (2:1) supporting conversion from quarter, half, full, double, and quad sample rates that are multiples of the standard 32 kHz, 44.1 kHz, and 48 kHz rates 16- or 32-bit PCM sample widths APBX bridge DMA interface Independent control of each channel's volume (including mute) DAC-to-ADC internal loopback for product development Control bit fields used for analog ADC settings The AUDIOIN module implements the following functions: * * * * * i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 28-1 AUDIOIN/ADC Figure 28-1 shows a high-level block diagram of the AUDIOIN module. See Figure 1-4 for a diagram of the audio path and control options. ARM Core SRAM 24-MHz XTAL Osc. AHB AHB Slave AHB Master Divide by n Clock Control Shared DMA DMA Request APBX Master AHB-to-APBX Bridge APBX ADC Programmable Registers ADC Digital Filtering, Decimation, Sample Rate Conversion Analog-to-1-Bit Conversion Line or Mic In Figure 28-1. AUDIOIN/ADC Block Diagram 28.2 Operation The first step in receiving audio to the AUDIOIN module requires the analog-to-digital converter (ADC). The i.MX23 includes a high-performance analog stereo sigma-delta ADC. It converts analog audio to two (left and right channel) single-bit digital streams that are input to the AUDIOIN module, along with a clock that runs at the sigma-delta oversampling clock rate. The AUDIOIN module includes hardware for oversampling, decimation, and arbitrary sample rate conversion. The 1-bit stream is input to a cascaded-integrator comb filter where serial-to-parallel data conversion, as well as sample rate conversion, takes place, along with a high-pass filter to eliminate DC offset. Serial audio is first input to an averager that initially converts samples to 8-bit values. The CIC then interpolates/decimates as well as sign-extends the parallel data, converting the samples from the programmed standard external sample i.MX23 Applications Processor Reference Manual, Rev. 1 28-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOIN/ADC rate to the AUDIOIN module's internal rate. The resultant 24-bit PCM samples are then stored to the module's RAM. These 24-bit samples are then filtered using a three-stage FIR filter, consisting of 7, 11, and 33 taps, respectively. The AUDIOIN contains a sequencer, multiply-accumulate hardware, and a set of filter coefficients that performs successive iterations on the data stored in RAM. Intermediate data that is calculated along the taps/stages of the FIR are also stored in the AUDIOIN's RAM. The resultant filtered PCM data is then stored in a FIFO that can either be directly accessed by the host CPU or read by the i.MX23's AHB-APBX bridge DMA engine to store the data in on- or off-chip memory to allow access to system software. In most cases, access to the AUDIOIN's data is made by the AHB-APBX bridge DMA. DMA channel 0 is dedicated to the AUDIOIN module. The DMA moves data from the AUDIOIN's memory-mapped data register to a RAM buffer every time a request is made. The buffer may be in on- or off-chip RAM. It is also possible for the CPU to manually move data from the AUDIOIN data register (HW_AUDIOIN_DATA) while monitoring either the FIFO or DMA request status bits in the AUDIOIN debug register (HW_AUDIOIN_ADCDEBUG). Also present on the i.MX23 is an audio playback path called AUDIOOUT/DAC. Although each functions independently of one another, both the AUDIOIN and AUDIOOUT blocks share their FIR filter (sequencer/RAM/coefficients) and DMA controller. This combined module is titled the "digital filter" or DIGFILT. The register descriptions that follow both refer to each path independently (AUDIOIN and AUDIOOUT) as well as a whole (DIGFILT), due to the fact that clocks and resets affect either the shared resources or the design as a whole. In order to configure the AUDIOIN/ADC for operation, the user must first clear the clock gate (CLKGATE) and soft reset (SFTRST) bits within the AUDIOIN control register (HW_AUDIOIN_CTRL). The run bit should remain off (zero), while all other control bits are initialized. It is important to note that there are also a number of control bits within the AUDIOOUT's address space that control functions within the analog ADC. The user must clear the clock gate and soft reset of the AUDIOOUT block in order to program these bits. Next, the bridge DMA controller channel 0 should be programmed and enabled to collect input audio samples to one or more RAM buffers. Finally, the run bit should be set to start AUDIOIN/ADC operation. Each 32-bit register within the AUDIOIN's address space is aliased to four adjacent words. The first word is used for normal read-write access while the subsequent three words are contained within the register's set-clear-toggle (SCT) address space. Only bits that are written to with a one in this space are affected. For example, writing a one to bit using the register's set address sets that particular bit, while maintaining the state of all other bits. This convention allows easy bit manipulation without requiring the standard read-modify-write procedure. Bits that are written with a one to the register's clear address clear the bit, while the toggle address causes bits to invert their current state. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 28-3 AUDIOIN/ADC From Headphone Left From Headphone Right LRADC3 /LINE2R LINE1R MIC 4 4 ADC Right Input Mux ADC GAIN AUDIOIN 1 ADC R ADC Left Input Mux 2 FIFO To ADC DMA X X X 3 LRADC2 /LINE2L LINE1L LRADC0 LRADC1 Notes: X X 4 4 ADC GAIN 1 ADC L FIFO X X 2 Mic Bias 5 To ADC DMA 1. HW_AUDIOIN_ADCVOLUME: Digital volume control. -0.5 dB to -100 dB in 0.5 dB steps. 2. HW_AUDIOIN_ADCVOL: Analog volume control that controls the ADC gain block. 0 dB to 22.5 dB gain in 1.5 dB steps. 3. HW_AUDIOIN_MICLINE_MICGAIN: Analog volume control that controls the microphone amplifier. 0, 20, 30, 40 dB gain. 4. HW_AUDIOIN_MICLINE_DIVIDE_LINE1/2. 5. HW_AUDIOOUT_MICLINE_MIC_BIAS, HW_AUDIOOUT_MICLINE_MIC_RESISTOR, HW_AUDIOOUT_MICLINE_MIC_SELECT. Figure 28-2. AUDIOIn/ADC Block Diagram 28.2.1 AUDIOIN DMA The DMA is typically controlled by a linked list of descriptors. The descriptors are usually circularly linked, causing the DMA to cycle through the set of DMA buffers. The DMA can be programmed to assert an IRQ when some or all of the buffers have been filled. For example, AUDIOIN DMA descriptor 0 may program the DMA to fill a buffer, set the done IRQ, and fetch descriptor 1. Descriptor 1 programs the DMA to fill the next buffer. The DMA continues to operate normally while the IRQ is asserted. The CPU needs to respond to the IRQ before the DMA has filled all of the buffers. The DMA ISR clears the IRQ flag and informs the operating system that the buffers are filled. In general, software copies data out of the buffers or adjusts the descriptors to point to other empty buffers. Software should also take advantage of the DMA's counting semaphore feature to synchronize the addition of new descriptors to the chain. The DMA can put the AUDIOIN's PCM data into any memory-mapped location. For 32-bit PCM data, the left-channel sample is stored first in the lowest address, followed by the corresponding right-channel sample in the next word address (+4 bytes). For 16-bit mode, sample pairs are stored in each word. Right samples are stored in the upper half-word while left samples are stored in the lower half-word. Because the AUDIOIN always operates on stereo data, the PCM buffer should always have an integer number of i.MX23 Applications Processor Reference Manual, Rev. 1 28-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOIN/ADC words. The audio data values are in two's complement format, where full-scale values range from 0x7FFFFFFF to 0x80000000 for 32-bit data or 0x7FFF to 0x8000 for 16-bit data. In addition to the DMA IRQ used to indicate a filled AUDIOIN buffer, the module also has an overflow and underflow IRQ. Underflows should never occur, because (by design) the DMA should never attempt to read more data than is present within the AUDIOIN's FIFO. However, if the AUDIOIN ever attempts to write data into a full FIFO, an overflow occurs. This causes the overflow flag to be set in the AUDIOIN control register (HW_AUDIOIN_CTRL). If the overflow/underflow IRQ enable bit is set, then this condition also asserts an interrupt. The interrupt is cleared by writing a one to the overflow flag in the HW_AUDIOIN_CTRL's SCT clear address space. An AUDIOIN underflow is typically caused by the DMA running out of new buffers, or if the AHB or APBX is stalled or are otherwise unable to meet the bandwidth requirements at the current operating frequency. If the counting semaphore reaches 0, the DMA stops processing new descriptors and stops moving data from the AUDIOIN's data register (HW_AUDIOIN_DATA). 28.2.2 ADC Sample Rate Converter and Internal Operation Table 28-1 contains the required value of the HW_AUDIOIN_ADCSRR register for various common sample rates. To make small sample rate adjustments (for example to track Fs fluctuations during a mix with an FM output to the DAC), the user may change the last few LSBs of the SRC_FRAC bit field to speed or slow the rate of sample consumption until equilibrium between the ADC's sample rate and the rate of another audio stream is met. Note that, unlike the DAC, only small deviations to SRC_FRAC can be made. The only valid values for BASEMULT, SRC_HOLD, and SRC_INT are listed in Table 28-1. Table 28-1. Bit Field Values for Standard Sample Rates SAMPLE RATE HW_AUDIOIN_ADCSRR BASEMULT SRC_HOLD SRC_INT SRC_FRAC FsampleADC 192,000 Hz 176,400 Hz 128,000 Hz 96,000 Hz 88,200 Hz 64,000 Hz 48,000 Hz 44,100 Hz 32,000 Hz 24,000 Hz 22,050 Hz 16,000 Hz 12,000 Hz 11,025 Hz 8,000 Hz 0x4 0x4 0x4 0x2 0x2 0x2 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x3 0x3 0x3 0x0F 0x11 0x17 0x0F 0x11 0x17 0x0F 0x11 0x17 0x0F 0x11 0x17 0x0F 0x11 0x17 0x13FF 0x0037 0x0E00 0x13FF 0x0037 0x0E00 0x13FF 0x0037 0x0E00 0x13FF 0x0037 0x0E00 0x13FF 0x0037 0x0E00 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 28-5 AUDIOIN/ADC Note: Sample rates greater than 48 kHz can only be used when the AUDIOOUT is disabled, and 44.1 kHz is the maximum sample rate at which both the AUDIOIN and AUDIOOUT can operate simultaneously. For any of the desired sample rates, the internal sample-rate conversion factor is calculated according to the following formula: SRConvADC = 65536 * [(FanalogADC)/ (8 * FsampleADC)] The 1-bit sigma delta A/D converter is always sampled on a submultiple of the 24.0-MHz crystal oscillator frequency, as specified in the HW_AUDIOIN_ANACLKCTRL_ADCDIV register (see Figure 28-3). This divider generates sample strobes at FanalogADC where the divisors available come from the set {4,6,8,12,16,24}. It is recommended that ADCDIV always be set to 000 so that a 6.0-MHz 1-bit A/D sample rate is used. The sample strobe is used to integrate the 1-bit A/D values. As shown in Figure 28-3, these integrated values are filtered and then delivered to the ADC DMA to write into on-chip RAM. Notice that the integrators run continuously while the filters produce samples at the decimated rate. Depending on the decimation or over-sample ratio of the CIC filter engine, the integrators will produce samples of various precisions and scale factors. The filtered values written to the ADC FIFO are signed 16-bit or 24-bit numbers with the conversion data LSB-justified, i.e., downscaled in the lower end of the word. The scale factor column of the 48-kHz family of sample rates satisfies the property: 24.576 MHz = Q * FsampleADC where Q comes from the set of integers These sample rates include 48 kHz, 32 kHz, 24 kHz, 16 kHz, 12 kHz, and 8 kHz. There are also the members of the 44.1-kHz family, whose members satisfy the property: 16.9344 MHz = Q * FsampleADC where Q comes from the set of integers These sample rates include 44.1 kHz, 22.05 kHz, and 11.025 kHz. Since 24.576 kHz and 16.9344 MHz are relatively prime to 24.0 MHz, members of the 48-kHz family and 44.1-kHz family are related to the 24.0-MHz source clock by the relationship: 24.0 MHz = P * FsampleADC, where P is a rational number The A/D block includes a variable rate or rational decimator as shown in Figure 28-3 to accommodate these sample rates. Rational numbers in the ADC are approximated with a scaled fixed-point 24-bit value. In this case, the decimal point falls between bit 15 and bit 16. Therefore, the lower two bytes hold the fractional part, while the upper byte holds the whole number portion of the scaled fixed point. The position register uses this scaled fixed-point representation to hold the number of 1-bit samples to be i.MX23 Applications Processor Reference Manual, Rev. 1 28-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOIN/ADC dropped (decimated) to find the next sample at which to produce a filtered multibit sigma delta A/D value to send to the DMA. Whenever the whole number part (bits 23:16) is zero, then a sample is produced. analog_R 1-Bit A/D rsamp_in +/- 1 Integrator lsamp_in +/- 1 Integrator CIC Filter and Interpolators High-Pass Filter lsamp_out[23:0] CIC Filter and Interpolators High-Pass Filter rsamp_out[23:0] analog_L 1-Bit A/D HW_AUDIOIN_ANACLKCTRL_ADCDIV AD_DIV table 6.0-MHz sample strobe Variable Rate Decimator /AD_DIV 24.0 MHz CIC State Matchine DMA_request XTAL OSC XTAL_CLK position_reg[31:0] HW_AUDIOIN_ADCSRR 24'hFF0000 1 + samp_strobe 1 31 16 15 Position Reg whole fraction # frac[15:0] pos_zero pos_zero= (position_reg[31:16] == 16'h0000) Variable Rate Decimator Figure 28-3. Variable-Rate A/D Converter The range of values of the samples stored into the on-chip RAM is proportional to the square of the over-sample rate (OSR) used in the capture process. The larger the OSR, the longer period the integrators run in the ADC. As a result, the range of values seen for the same signal wave form captured at the same sample rate but with two different OSR will be different. For example: * * * * * An 8-kHz microphone captured at FADC = 6.0 MHz will be 36 times smaller than the values resulting from capturing the same source signal at FADC = 1.0 MHz. The peak range of values seen in a capture of a signal at 44.1 kHz with FanalogADC = 6.0 MHz is 3200. The oversample ratio in this case is OSR= 136.054. Calculate a magnitude constant, Kfilter for ADC's filter from this as Kfilter = OSR2/Peak Value = (136.054)2/3200 = 5.7846. For any OSR in any sample rate, the peak value can be approximated by Valuepeak = OSR2 /Kfilter. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 28-7 AUDIOIN/ADC In signal processing, one frequently normalizes the range of values to 1.0, as seen in a fixed-point scaled integer1. For a 24-bit DSP, the fixed point is placed between bit 23 and the sign bit (bit 24) (bit 1 = 20). So the desired maximum excursion is then 223 or 8388608. One can calculate a normalization constant to multiply all incoming samples for each sampling condition from the following equation (note that OSR is fixed at 6 MHz for the i.MX23): ScaleFactor = 223 * Kfilter / OSR2 If the incoming sample stream is multiplied, sample by sample, by ScaleFactor, then normalized 1.0 samples result. All data output from the DIGFILT ADC are scaled according to this equation. 28.2.3 Line-In The line inputs should be AC-coupled with 1 F, X7R capacitors to isolate the source DC bias from the ADC's internal bias. 28.2.4 Microphone The external microphone needs a bias voltage to enable it to operate. This bias voltage can be generated externally using discrete components as shown in Figure 28-4. Or, if either the LRADC0 or LRADC1 pin is available, it can be used to supply a bias voltage from an on-chip generator, as shown in Figure 28-5. To enable the generation of the microphone bias voltage on pin LRADC0 or LRADC1, the two MIC_RESISTOR bits in the HW_AUDIOIN_MICLINE register need to be written with required values for desired internal resistor selection. To select either pin LRADC1 or LRADC0 as the microphone bias source, write the MIC_SELECT bit in the HW_AUDIOIN_MICLINE register as follows: 0 for pin LRADC0, 1 for pin LRADC1. MIC 0.1F Microphone 2.2k VDDIO 2.2k 0.1F 10F Figure 28-4. External Microphone Bias Generation 1.A normalized two's complement 24-bit number cannot actually express a value of +1.0 without overflowing. i.MX23 Applications Processor Reference Manual, Rev. 1 28-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOIN/ADC MIC 0.1 F Microphone HW_AUDIOIN_MICLINE_MIC_SELECT LRADC1 (opt.) HW_AUDIOIN_MICLINE _MIC_RESISTOR LRADC0 (opt.) 2k 4k 8k Adjustable voltage from 1.21 to 2.96 V with HW_AUDIOIN_MICLINE_MIC_BIAS Figure 28-5. Internal Microphone Bias Generation 28.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. Note that the SFTRST and CLKGATE bits of both AUDIOOUT and AUDIOIN must be cleared before doing any operation with this block. 28.4 Programmable Registers The following registers provide control for programmable elements of the AUDIOIN/ACD block. 28.4.1 AUDIOIN Control Register Description The AUDIOIN Control Register provides overall control of the digital portion of the analog-to-digital converter. HW_AUDIOIN_CTRL HW_AUDIOIN_CTRL_SET HW_AUDIOIN_CTRL_CLR HW_AUDIOIN_CTRL_TOG 0x000 0x004 0x008 0x00C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 2.2 K 1 F 28-9 AUDIOIN/ADC Table 28-2. HW_AUDIOIN_CTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 DMAWAIT_COUNT 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 OFFSET_ENABLE 0 6 0 5 0 4 0 3 FIFO_UNDERFLOW_IRQ 0 2 FIFO_OVERFLOW_IRQ 0 1 FIFO_ERROR_IRQ_EN 0 0 WORD_LENGTH HPF_ENABLE INVERT_1BIT EDGE_SYNC LOOPBACK LR_SWAP CLKGATE RSRVD3 RSRVD1 SFTRST Table 28-3. HW_AUDIOIN_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION AUDIOIN Module Soft Reset. Setting this bit to one forces a reset to portions of DIGFILT that control audio input and then gates the clocks off because the CLKGATE bit's reset state is to disable clocks. This bit must be cleared to zero for normal operation. Note that the CLKGATE bit does not affect SFTRST, because it must remain writeable during clock gating. AUDIOIN Clock Gate Enable. When this bit is set to 1, it gates off the clocks to the portions of the DIGFILT block that control only input audio functions. It does not affect portions of the block that control AUDIOOUT. Clear the bit to zero for normal AUDIOIN operation. Note that when this bit is set, it remains writeable during clock gating so that it may be disabled by the user. Reserved DMA Request Delay Count. This bit field specifies the number of APBX clock cycles (0 to 31) to delay before each DMA request. This field acts as a throttle on the bandwidth consumed by the DIGFILT block. This field can be loaded by the DMA. Reserved Left/Right Input Channel Swap Enable. Setting this bit to one swaps the left and right serial audio inputs from the ADC before being parallelized and having the sample rate converted by the AUDIOIN's CIC block. Serial Input Clock Edge Sync Select. This bit selects the edge of the ADC's serial input clock upon which the CIC-filter synchronizes for data receive. 0=Rising edge. 1=Falling edge Invert Serial Audio Input Enable. When set, this bit inverts the 1-bit serial input of both left and right channels from the ADC's sigma-delta modulator. 0=Normal operation. 1=Invert L/R serial audio input to the CIC block. 30 CLKGATE RW 0x1 29:21 RSRVD3 20:16 DMAWAIT_COUNT RO 0x0 RW 0x0 15:11 RSRVD1 10 LR_SWAP RO 0x0 RW 0x0 9 EDGE_SYNC RW 0x0 8 INVERT_1BIT RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 28-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor RUN AUDIOIN/ADC Table 28-3. HW_AUDIOIN_CTRL Bit Field Descriptions BITS LABEL 7 OFFSET_ENABLE RW RESET RW 0x1 DEFINITION ADC Analog High-Pass Filter Offset Calculation Enable. When this bit is set, the ADC's high pass filter actively adjusts the serial audio input, removing DC offset present within the signal. Active DC offset only takes place when the HPF_ENABLE bit is set. Once DC offset has been achieved, this bit can be cleared to maintain a constant level of offset. After clearing this bit, the HPF_ENABLE bit should remain set to maintain a constant DC offset. ADC High-Pass Filter Enable. When this bit is set, the ADC's analog high pass filter is enabled. Once enabled, the OFFSET_ENABLE bit can be set to cause the filter to begin removing DC offset from the incoming serial analog data. Once DC offset has been removed, the OFFSET_ENABLE bit should be cleared while the HPF_ENABLE bit remains set. PCM Audio Bit Size Select. This bit selects the size of the parallel PCM data collected by the AUDIOIN's input FIFO. 0=32-bit PCM samples. 1=16 bit samples. Note that the PCM audio data output from the FIR filter stages is 24 bits. For 16-bit operation, the resultant data is normalized by dropping the least significant 8 bits. For 32-bit mode, the two's complement PCM data is sign extended to 32 bits. AUDIOOUT-to-AUDIOIN Loopback Enable. Setting this bit to one connects the AUDIOOUT's digital serial data from the SDM module to the AUDIOIN's serial digital input to the CIC module, bypassing the analog DAC and ADC. This test mode provides a digital-only loopback which ties the output filter chain back to the input filter chain. This bit should be cleared to zero for normal operation. FIFO Underflow Interrupt Status Bit. This bit is set by hardware if the AUDIOIN's FIFO underflows any time during operation. It is reset by software by writing a one to the SCT clear address space. An interrupt is issued to the host processor if this bit is set and FIFO_ERROR_IRQ_EN=1. Note that underflows should not occur by design because requests to the DMA are not made unless there is data present within the FIFO, and would indicate a serious DMA error. FIFO Overflow Interrupt Status Bit. This bit is set by hardware if the AUDIOIN's FIFO overflows due to a DMA request that is not serviced in time. It is reset by software writing a one to the SCT clear address space. An interrupt is issued to the host processor if this bit is set and FIFO_ERROR_IRQ_EN=1. 6 HPF_ENABLE RW 0x1 5 WORD_LENGTH RW 0x0 4 LOOPBACK RW 0x0 3 FIFO_UNDERFLOW_IRQ RW 0x0 2 FIFO_OVERFLOW_IRQ RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 28-11 AUDIOIN/ADC Table 28-3. HW_AUDIOIN_CTRL Bit Field Descriptions BITS LABEL 1 FIFO_ERROR_IRQ_EN RW RESET RW 0x0 DEFINITION FIFO Error Interrupt Enable. Set this bit to one to enable an AUDIOIN interrupt request to the host processor when either the FIFO overflow or underflow status bits are set. Note that this bit does not affect the state of the underflow/overflow status bits, but rather their ability to signal an interrupt to the CPU. AUDIOIN Enable. Setting this bit to one causes the AUDIOIN to begin converting data. Once 8 words of audio input samples are collected in its FIFO, it makes a DMA service request. Clearing this bit to zero stops data conversion and also causes the CLKGATE bit to be set. 0 RUN RW 0x0 DESCRIPTION: The AUDIOIN Control Register contains bit fields used to control and monitor AUDIOIN operation including: reset, clocks, DMA transfers, analog ADC signal interface, high-pass filter operation, PCM data size, test, and interrupt control. EXAMPLE: HW_AUDIOIN_CTRL.RUN = 1; // start AUDIOIN conversion 28.4.2 AUDIOIN Status Register Description HW_AUDIOIN_STAT HW_AUDIOIN_STAT_SET HW_AUDIOIN_STAT_CLR HW_AUDIOIN_STAT_TOG Table 28-4. HW_AUDIOIN_STAT The AUDIOIN Status Register is used to determine if the digital-to-analog converter is operational. 0x010 0x014 0x018 0x01C 3 1 ADC_PRESENT 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 28-5. HW_AUDIOIN_STAT Bit Field Descriptions BITS LABEL 31 ADC_PRESENT RW RESET RO 0x1 DEFINITION AUDIOIN Functionality Present. This status bit is set to one in products that include the AUDIOIN/ADC. If this bit is zero, the AUDIOIN/ADC is permanently disabled and cannot be operated by the user. Reserved 30:0 RSRVD3 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 28-12 Preliminary--Subject to Change Without Notice RSRVD3 Freescale Semiconductor AUDIOIN/ADC DESCRIPTION: The AUDIOIN Status Register provides an indication of the presence of the ADC functionality. EXAMPLE: unsigned TestValue= HW_AUDIOIN_STAT.ADC_PRESENT; 28.4.3 AUDIOIN Sample Rate Register Description The AUDIOIN Sample Rate Register is used to specify the sample rate from which the incoming serial audio data is converted as it is received by the CIC module from the analog ADC. HW_AUDIOIN_ADCSRR HW_AUDIOIN_ADCSRR_SET HW_AUDIOIN_ADCSRR_CLR HW_AUDIOIN_ADCSRR_TOG Table 28-6. HW_AUDIOIN_ADCSRR 3 1 3 0 2 9 BASEMULT 0x020 0x024 0x028 0x02C 2 8 2 7 RSRVD2 2 6 2 5 SRC_HOLD 2 4 2 3 2 2 RSRVD1 2 1 2 0 1 9 1 8 SRC_INT 1 7 1 6 1 5 1 4 RSRVD0 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 SRC_FRAC 0 5 0 4 0 3 0 2 0 1 0 0 OSR Table 28-7. HW_AUDIOIN_ADCSRR Bit Field Descriptions BITS 31 OSR LABEL RW RESET RO 0x0 DEFINITION AUDIOIN Oversample Rate. Note that the oversample rate is fixed at 6 MHz. OSR6 = 0x0 AUDIOIN oversample rate at 6 MHz. OSR12 = 0x1 AUDIOIN oversample rate at 12 MHz. 30:28 BASEMULT RW 0x1 Base Sample Rate Multiplier. This bit field is used to configure the ADC's sample rate to one of three ranges: single, double, or quad. This multiply factor is used to achieve sample rates greater than the standard rates of 32/44.1/48 kHz. A value of 0x1 should be used when selecting half and quarter sample rates. Note that sample rates greater than 48 kHz may only be used when the AUDIOOUT is disabled, and 44.1 kHz is the maximum sample rate at which both the AUDIOIN and AUDIOOUT can operate simultaneously. SINGLE_RATE = 0x1 Single-rate multiplier (for 48/44.1/32 kHz as well as half and quarter rates). DOUBLE_RATE = 0x2 Double-rate multiplier (for 96/88.2/64 kHz). QUAD_RATE = 0x4 Quad-rate multiplier (for 192/176.4/128 kHz). 27 RSRVD2 RO 0x0 Reserved. Always write a zero to this bit field. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 28-13 AUDIOIN/ADC Table 28-7. HW_AUDIOIN_ADCSRR Bit Field Descriptions BITS LABEL 26:24 SRC_HOLD RW RESET RW 0x0 DEFINITION Sample Rate Conversion Hold Factor. This bit is used to hold a sample of a variable number of clock cycles in order to generate half and quarter sample rates when dividing down the AUDIOIN's internal rate using the equation: output_sample_rate = (6x10^6 * BASEMULT) / (SRC_INT.SRC_FRAC * 8 * (SRC_HOLD + 1)). Refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. Reserved. Always write zeros to this bit field. Sample Rate Conversion Integer Factor. This bit field is the integer portion of a divide term used to sample-rate-convert the AUDIOIN's internal rate using the equation; output_sample_rate = (6x10^6 * BASEMULT) / (SRC_INT.SRC_FRAC * 8 * (SRC_HOLD + 1)). Refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. Reserved. Always write zeros to this bit field. Sample Rate Conversion Fraction Factor. This bit field is the fractional portion of a divide term used to sample-rate-convert the AUDIOIN's internal rate using the equation; output_sample_rate = (6x10^6 * BASEMULT) / (SRC_INT.SRC_FRAC * 8 * (SRC_HOLD + 1)). Refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. 23:21 RSRVD1 20:16 SRC_INT RO 0x0 RW 0x11 15:13 RSRVD0 12:0 SRC_FRAC RO 0x0 RW 0x37 DESCRIPTION: The AUDIOIN Sample Rate Register contains bit fields used to specify the rate at which the ADC samples incoming analog audio. EXAMPLE: // Program the DAC to output a sample rate of 48 kHz: HW_AUDIOIN_ADCSRR.BASEMULT = 0x1; // quad-rate HW_AUDIOIN_ADCSRR.SRC_HOLD = 0x0; // 0 for full- double- quad-rates HW_AUDIOIN_ADCSRR.SRC_INT = 0xF; // 15 for the integer portion HW_AUDIOIN_ADCSRR.SRC_FRAC = 0x13FF; // the fractional portion 28.4.4 AUDIOIN Volume Register Description The AUDIOIN Volume Register is used to adjust the signal level of the recorded audio input from the ADC. HW_AUDIOIN_ADCVOLUME HW_AUDIOIN_ADCVOLUME_SET HW_AUDIOIN_ADCVOLUME_CLR HW_AUDIOIN_ADCVOLUME_TOG 0x030 0x034 0x038 0x03C i.MX23 Applications Processor Reference Manual, Rev. 1 28-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOIN/ADC Table 28-8. HW_AUDIOIN_ADCVOLUME 3 1 3 0 2 9 2 8 VOLUME_UPDATE_LEFT 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 VOLUME_UPDATE_RIGHT 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 28-9. HW_AUDIOIN_ADCVOLUME Bit Field Descriptions BITS LABEL 31:29 RSRVD5 VOLUME_UPDATE_LEFT 28 RW RESET RO 0x00 RO 0x0 DEFINITION 27:26 RSRVD4 EN_ZCD 25 RO 0x00 RW 0x0 RSRVD3 24 23:16 VOLUME_LEFT RO 0x0 RW 0xfe 15:13 RSRVD2 VOLUME_UPDATE_RIGHT 12 RO 0x00 RO 0x0 Reserved Left Channel Volume Update Pending. This bit is set to one by the hardware when an AUDIOIN volume update is pending, i.e., waiting on a zero crossing on the left channel. The bit is set following a write to the VOLUME_LEFT bit field and is cleared when the attenuation value is applied to the PCM input stream (at a zero-crossing). This status bit is not used when EN_ZCD=0. Reserved Enable Zero Cross Detect. This bit enables/disables use of the zero cross detect circuit in the ADC (rather than enabling the circuit itself). When enabled, changes to the volume bit fields are not applied until it is detected that the input signal's sign bit toggles (crosses zero amplitude). When disabled, changes to the volume bit fields take effect immediately when written. Reserved Left Channel Volume Setting. This bit field is used to establish the incoming audio signal strength during record. Volume ranges from -0.5 dB (0xFE) to -100 dB (0x37). Each increment of this bit field causes a half-dB increase in volume. Note that values 0x00-0x37 all produce the same attenuation level of -100 dB. Also note that a setting of 0xFF is reserved. Reserved Right Channel Volume Update Pending. This bit is set to one by the hardware when an AUDIOIN volume update is pending, i.e., waiting on a zero crossing on the right channel. The bit is set following a write to the VOLUME_RIGHT bit field and is cleared when the attenuation value is applied to the PCM input stream (at a zero-crossing). This status bit is not used when EN_ZCD=0. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice VOLUME_RIGHT VOLUME_LEFT RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 EN_ZCD 28-15 AUDIOIN/ADC Table 28-9. HW_AUDIOIN_ADCVOLUME Bit Field Descriptions BITS LABEL 11:8 RSRVD1 VOLUME_RIGHT 7:0 RW RESET RO 0x0 RW 0xfe DEFINITION Reserved Right Channel Volume Setting. This bit field is used to establish the incoming audio signal strength during record. Volume ranges from -0.5 dB (0xFF) to -100 dB (0x37). Each increment of this bit field causes a half-dB increase in volume. Note that values 0x00-0x37 all produce the same attenuation level of -100 dB. Also note that a setting of 0xFF is reserved. DESCRIPTION: The AUDIOIN Volume Register allows independent volume control of the left and right channels. Input audio can be attenuated in 0.5-dB steps, from full scale down to a minimum of -100 dB. This register is also used to enable/control volume updates such that they are only applied when PCM values cross zero to prevent unwanted audio artifacts. EXAMPLE: HW_AUDIOIN_ADCVOLUME.U = 0x00ff00ff; maximum volume for left and right channels. 28.4.5 AUDIOIN Debug Register Description HW_AUDIOIN_ADCDEBUG HW_AUDIOIN_ADCDEBUG_SET HW_AUDIOIN_ADCDEBUG_CLR HW_AUDIOIN_ADCDEBUG_TOG 0x040 0x044 0x048 0x04C The AUDIOIN Debug Register is used for testing and debugging the AUDIOIN block. Table 28-10. HW_AUDIOIN_ADCDEBUG 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0 2 0 1 0 0 SET_INTERRUPT3_HAND_SHAKE ENABLE_ADCDMA i.MX23 Applications Processor Reference Manual, Rev. 1 28-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor FIFO_STATUS DMA_PREQ RSRVD1 AUDIOIN/ADC Table 28-11. HW_AUDIOIN_ADCDEBUG Bit Field Descriptions BITS LABEL 31 ENABLE_ADCDMA RW RESET RW 0x0 DEFINITION AUDIOIN Digital Path Test Enable. This bit is used solely for development and debug and is not functional on production parts. When enabled, it causes the AUDIOIN's serial audio data input to bypass the CIC block, to be assembled into 32-bit words and transferred out to memory using the AUDIOOUT's DMA Channel 1. Unlike loopback, this test mode provides a means of verifying the digital portion of the AUDIOIN/ADC logic without causing the audio data to pass through the AUDIOOUT's FIR filter stages. Reserved DMA Request Sync Status. This bit reflects the current state of the second flop on the chain of three flip-flops used to synchronize the AUDIOIN's DMA request signal from the module's internal 24-MHz clock to the APBX's memory clock domain. This bit is only intended for test. Interrupt[3] Status. This bit reflects the current state of the APBX interface state machine's internal interrupt[3] signal used to prioritize channels 0 and 1 DMA requests from the DIGFILT. This bit is only intended for test. DMA Request Status. This bit reflects the current state of the AUDIOIN's DMA request signal. DMA requests are issued any time the request signal toggles. This bit can be polled by software, in order to manually move samples from the AUDIOIN's FIFO to a memory buffer when the AUDIOIN's DMA channel is not used. FIFO Status. This bit is set when the AUDIOIN's FIFO contains any amount of valid data and is cleared when the FIFO is empty. 30:4 3 RSRVD1 RO 0x00 ADC_DMA_REQ_HAND_SHA RO 0x0 KE_CLK_CROSS 2 SET_INTERRUPT3_HAND_S HAKE RO 0x0 1 DMA_PREQ RO 0x0 0 FIFO_STATUS RO 0x0 DESCRIPTION: The AUDIOIN Debug Register provides read-only access of various internal AUDIOIN module signals to assist in debug and validation, as well as control of ADCDMA test mode. EXAMPLE: unsigned tempStatus = HW_AUDIOIN_ADCDEBUG.FIFO_STATUS; 28.4.6 ADC Mux Volume and Select Control Register Description HW_AUDIOIN_ADCVOL HW_AUDIOIN_ADCVOL_SET HW_AUDIOIN_ADCVOL_CLR HW_AUDIOIN_ADCVOL_TOG 0x050 0x054 0x058 0x05C This register controls operation of the analog ADC input mux. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 28-17 AUDIOIN/ADC Table 28-12. HW_AUDIOIN_ADCVOL 3 1 3 0 2 9 2 8 VOLUME_UPDATE_PENDING 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 SELECT_RIGHT SELECT_LEFT EN_ADC_ZCD Table 28-13. HW_AUDIOIN_ADCVOL Bit Field Descriptions BITS LABEL RW RESET 31:29 RSRVD4 RO 0x0 VOLUME_UPDATE_PENDING RO 0x0 28 DEFINITION Reserved Volume Update Pending. This bit is set to one by the hardware when either an ADC left or right volume update is pending, i.e., waiting on a zero crossing. The bit is set following a write to either the GAIN_LEFT or GAIN_RIGHT bit fields and is cleared when both gain values are applied to the input coincident with zero-crossings in both the right and left channels. This status bit is not used when EN_ADC_ZCD=0. Reserved Enable Zero Cross Detect for ADC Amplifier. ADC Mute. When set, this bit mutes both the left and right channel analog inputs. 1=Mute. 0=Unmute. Reserved ADC Left Channel Input Source Select. This bit field is used to select the analog input source of the ADC's left channel. 00=Microphone. 01=Line1. 10=Headphone. 11=Line2 (169-BGA only). Line2 left input is LRADC2. Left Channel ADC Gain. This bit selects the level of gain applied to the left channel analog input. Each increment of this field represents a 1.5dB gain. Programming a value of 0x0, applies a 0dB gain, 0x1 applies a 1.5dB gain, and so on up to a maximum gain of 22.5dB when a value of 0xF is used. Reserved ADC Right Channel Input Source Select. This bit field is used to select the analog input source of the ADC's right channel. 00=Microphone. 01=Line1. 10=Headphone. 11=Line2 (169-BGA only). Right Channel ADC Gain. This bit selects the level of gain applied to the right channel analog input. Each increment of this field represents a 1.5-dB gain. Programming a value of 0x0, applies a 0-dB gain, 0x1 applies a 1.5-dB gain, and so on up to a maximum gain of 22.5 dB when a value of 0xF is used. 27:26 RSRVD3 EN_ADC_ZCD 25 MUTE 24 23:14 RSRVD2 13:12 SELECT_LEFT RO 0x0 RW 0x0 RW 0x1 RO 0x000 RW 0x0 11:8 GAIN_LEFT RW 0x0 7:6 5:4 RSRVD1 SELECT_RIGHT RO 0x0 RW 0x0 3:0 GAIN_RIGHT RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 28-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor GAIN_RIGHT GAIN_LEFT RSRVD4 RSRVD3 RSRVD2 RSRVD1 MUTE AUDIOIN/ADC DESCRIPTION: This register supplies the volume, mute, and input select controls for the analog ADC mux/gain amplifier. EXAMPLE: HW_AUDIOIN_ADCVOL.MUTE = 0; 28.4.7 Microphone and Line Control Register Description HW_AUDIOIN_MICLINE HW_AUDIOIN_MICLINE_SET HW_AUDIOIN_MICLINE_CLR HW_AUDIOIN_MICLINE_TOG Table 28-14. HW_AUDIOIN_MICLINE This register provides the microphone and line control bits. 0x060 0x064 0x068 0x06C 3 1 3 0 2 9 DIVIDE_LINE1 2 8 DIVIDE_LINE2 2 7 2 6 2 5 2 4 MIC_SELECT 2 3 2 2 2 1 MIC_RESISTOR 2 0 1 9 1 8 1 7 MIC_BIAS 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 MIC_CHOPCLK 0 4 0 3 0 2 0 1 MIC_GAIN 0 0 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 Table 28-15. HW_AUDIOIN_MICLINE Bit Field Descriptions BITS LABEL 31:30 RSRVD6 DIVIDE_LINE1 29 RW RESET RO 0x0 RW 0x0 DEFINITION 28 DIVIDE_LINE2 RW 0x0 27:25 RSRVD5 MIC_SELECT 24 RO 0x0 RW 0x0 23:22 RSRVD4 RO 0x0 Reserved Attenuate Line1 Input. When used in conjunction with a 10K series external resistor on the Line1 pin, this bit causes the Line1 input signal to be attenuated by 9.5dB (+/-1.5 dB) t o allow a 2-Vrms input signal. This bit affects the left and right channels of both the ADC and headphone. Attenuate Line2 Input. When used in conjunction with a 10K series external resistor on the line2 pin, this bit causes the Line2 input signal to be attenuated by 9.5 dB (+/-1.5 dB) to allow a 2-Vrms input signal. This bit affects the left and right channels of the ADC. Reserved Microphone Bias Pin Select. When MIC_RESISTOR is enabled (non-zero), this bit is used to select the pin source for the Micbias input voltage reference. 0=LRADC0. 1=LRADC1. Note that the LRADC pin that is selected for Micbias cannot also be used as an LRADC input. Reserved i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD1 28-19 AUDIOIN/ADC Table 28-15. HW_AUDIOIN_MICLINE Bit Field Descriptions BITS LABEL 21:20 MIC_RESISTOR RW RESET RW 0x0 DEFINITION Microphone Bias Resistor Select. Note that the analog ADC block must be powered on before turning on the Micbias circuit (ADC bit within the HW_AUDIOOUT_PWRDN register must be cleared to zero) 00=Off. 01=2 KOhm. 10=4 KOhm. 11=8 KOhm. Reserved Microphone Bias Voltage Select. 0=1.21 V, 1=1.46 V, up to 7=2.96 V (0.25-V increments) Reserved Enable chopping in the microphone amplifier: 00=Disabled. 01=192 kHz. 10=96 kHz. 11=48 kHz. Reserved Microphone Gain. 00=0 dB, 01=20 dB, 10=30 dB, 11=40 dB. RSRVD3 19 18:16 MIC_BIAS RO 0x0 RW 0x0 RO 0x00 RW 0x0 RO 0x00 RW 0x0 15:6 5:4 3:2 1:0 RSRVD2 MIC_CHOPCLK RSRVD1 MIC_GAIN DESCRIPTION: This register provides the microphone and line control bits. EXAMPLE: HW_AUDIOIN_MICLINE.MIC_GAIN = 0x2; // 30 dB 28.4.8 Analog Clock Control Register Description HW_AUDIOIN_ANACLKCTRL HW_AUDIOIN_ANACLKCTRL_SET HW_AUDIOIN_ANACLKCTRL_CLR HW_AUDIOIN_ANACLKCTRL_TOG 0x070 0x074 0x078 0x07C This register provides analog clock control. Table 28-16. HW_AUDIOIN_ANACLKCTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 DITHER_OFF 0 9 SLOW_DITHER 0 8 INVERT_ADCCLK 0 7 0 6 0 5 ADCCLK_SHIFT 0 4 0 3 0 2 0 1 0 0 CLKGATE RSRVD4 RSRVD3 RSRVD2 Table 28-17. HW_AUDIOIN_ANACLKCTRL Bit Field Descriptions BITS LABEL 31 CLKGATE RW RESET RW 0x1 DEFINITION Analog Clock Gate. Set this bit to gate the clocks for the ADC converter and associated digital filter. Reserved ADC Dither Disable. When this bit is set, dither is disabled within the ADC. 30:11 RSRVD4 DITHER_OFF 10 RO 0x0 RW 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 28-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor ADCDIV AUDIOIN/ADC Table 28-17. HW_AUDIOIN_ANACLKCTRL Bit Field Descriptions BITS LABEL 9 SLOW_DITHER RW RESET RW 0x0 DEFINITION Slow Dither. When dither is enabled (DITHER_OFF=0), and this bit is set, ADC input signal dithering is slowed to half its normal rate. ADC clock invert. Set this bit to invert the ADC_CLK for the ADC sigma-delta converter and associated digital filters. Reserved ADC Analog Clock Phase Shift. This bit field is used to shift the phase of the adc clock realtive to the switching of the dcdc converter. This bit field should only be changed per Freescale. 00=no shift. 01=20ns shift 10=40ns shift 11=60ns shift. Reserved ADC Analog Clock Divider. This bit field is used to select the oversampling clock rate used by the ADC. This bit field should only be changed per Freescale. 000=6 MHz. 001=4 MHz. 010/100=3 MHz. 011/101=2 MHz. 110=1.5 MHz. 111=1 MHz. 8 INVERT_ADCCLK RW 0x0 7:6 5:4 RSRVD3 ADCCLK_SHIFT RO 0x0 RW 0x0 3 2:0 RSRVD2 ADCDIV RO 0x0 RW 0x0 DESCRIPTION: This register provides analog clock control. EXAMPLE: HW_AUDIOIN_ANACLKCTRL.ADCDIV = 0x2; // 3 MHz 28.4.9 AUDIOIN Read Data Register Description HW_AUDIOIN_DATA HW_AUDIOIN_DATA_SET HW_AUDIOIN_DATA_CLR HW_AUDIOIN_DATA_TOG Table 28-18. HW_AUDIOIN_DATA The AUDIOIN Read Data Register provides access to incoming PCM audio samples. 0x080 0x084 0x088 0x08C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 HIGH 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 LOW 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 28-21 AUDIOIN/ADC Table 28-19. HW_AUDIOIN_DATA Bit Field Descriptions BITS 31:16 HIGH LABEL RW RESET RO 0x0000 DEFINITION Right Sample or Sample High Half-Word. For 16-bit sample mode, this field contains the right channel sample. For 32-bit sample mode, this field contains the most significant 16 bits of the 32-bit sample (either left or right). Left Sample or Sample Low Half-Word. For 16-bit sample mode, this field contains the left channel sample. For 32-bit per sample mode, this field contains the least significant 16 bits of the 32-bit sample (either left or right). 15:0 LOW RO 0x0000 DESCRIPTION: The AUDIOIN Read Data Register provides 32-bit data transfers for the DMA, or, alternatively, can be directly read by the CPU. Each data value read from the register is transferred from the AUDIOIN's FIFO that contains the resultant audio data that has passed through it's digital FIR filter stages. These 32-bit values contain either one 32-bit sample or two 16-bit samples, depending on how the data size is programmed. Note that the PCM audio data output from the FIR filter stages is 24-bit. For 16-bit operation, the resultant data is normalized by dropping the least significant 8 bits. For 32-bit mode, the two's complement PCM data is sign extended to 32 bits. EXAMPLE: unsigned long TestValue= HW_AUDIOIN_DATA.U; // read a 32 bit value from the read data register in CPU diagnostic (non-DMA) mode AUDIOIN Block v1.3, Revision 1.52 i.MX23 Applications Processor Reference Manual, Rev. 1 28-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 29 AUDIOOUT/DAC This chapter describes the AUDIOOUT/DAC module implemented on the i.MX23, including DMA, sample rate conversion, internal operation, reference control settings, and headphone amplifier operation. Programmable registers are described in Section 29.4, "Programmable Registers." 29.1 Overview The i.MX23 features an audio playback path that consists of the AUDIOOUT digital multi-stage FIR filter, followed by a sigma-delta digital-to-analog converter (DAC). PCM audio samples are transferred from a buffer in memory using the APBX bridge DMA to the AUDIOOUT's FIFO. Sample pairs are processed by a three-stage finite impulse response filter. The resultant PCM samples are input to the sigma-delta modulation (SDM) block, where they are serialized, sample rate converted to the desired output rate, and output to the analog DAC. The analog audio destination can be selected from one of two possible outputs: * * * * Stereo Headphone Amplifier Output Speaker Amplifier Output 1-bit sigma-delta DAC Three stage upsampling FIR filter: 33-tap (1:2), 11-tap (2:4), 7-tap (4:8), supporting conversion from quarter, half, full, double and quad sample rates that are multiples of the standard 32K, 44.1K, and 48K Hz rates Parallel-to-serial bit-stream decimator Sample rate converter (SRC) 16- or 32-bit PCM sample widths APBX bridge DMA interface Independent control of each channel's volume (including mute) Freescale 3D virtualization ADC-to-DAC internal loopback for product development Control bit fields used for analog DAC settings The AUDIOOUT module provides the following functions: * * * * * * * * i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-1 AUDIOOUT/DAC Figure 29-1 shows a high-level diagram of the AUDIOOUT module. See Figure 1-4 for a diagram of the audio path and control options. ARM Core SRAM 24-MHz XTAL Osc. AHB AHB Slave AHB Master Divide by n Clock Control Shared DMA DMA Request APBX Master AHB-to-APBX Bridge APBX DAC Programmable Registers DAC Digital Filtering, Interpolation, Sample Rate Conversion, Digital Volume, Zero Cross Detect 1-Bit-Digital-to-Analog Conversion to Headphone or LineOut Figure 29-1. Functional AUDIOOUT/DAC Block Diagram 29.2 Operation Audio data conversion begins by either using the i.MX23's AHB-APBX bridge DMA engine to write two's complement PCM data to the AUDIOOUT's input FIFO, or by writing the data directly to the AUDIOOUT's data register via the host CPU. The data is then normalized to 24-bit samples and then filtered using a 3-stage FIR filter, consisting of 33, 11, and 7 taps, respectively. The AUDIOOUT contains a sequencer, multiply-accumulate hardware, and a set of filter coefficients that performs successive iterations on the data stored in RAM. Intermediate data calculated along the taps/stages of the FIR are also stored in the AUDIOOUT's RAM. The AUDIOOUT module includes hardware for interpolation, sample i.MX23 Applications Processor Reference Manual, Rev. 1 29-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC and hold, and sigma-delta modulation that is applied to the filtered parallel PCM data. The resultant oversampled 1-bit serial stream is then output to the high-performance analog stereo sigma-delta DAC. In most cases, the AUDIOOUT's PCM data is transferred by the AHB-APBX bridge DMA. DMA channel 1 is dedicated to the AUDIOOUT module. The DMA moves data to the AUDIOOUT's memory-mapped data register from a RAM buffer every time a request is made. The buffer may be in on-chip or off-chip RAM. It is also possible for the CPU to manually move data to the AUDIOOUT data register (HW_AUDIOOUT_DATA) while monitoring either the FIFO or DMA request status bits in the AUDIOOUT debug register (HW_AUDIOOUT_DACDEBUG). Also present on the i.MX23 is an audio record path called AUDIOIN/ADC. Although each functions independently of one another, both the AUDIOOUT and AUDIOIN blocks share their FIR filter (sequencer/RAM/coefficients) and DMA controller. This combined module is titled the "digital filter" or DIGFILT. The register descriptions that follow refer both to each path independently (AUDIOOUT and AUDIOIN) as well as a whole (DIGFILT), due to the fact that clocks and resets affect either the shared resources or the design as a whole. In order to configure the AUDIOOUT/DAC for operation, the user must first clear the clock gate (CLKGATE) and soft reset (SFTRST) bits within the AUDIOOUT control register (HW_AUDIOOUT_CTRL). The run bit should remain off (zero), while all other control bits are initialized. It is important to note that there are also a number of control bits within the AUDIOOUT's address space that control functions within the analog DAC. Next, the bridge DMA controller channel 1 should be programmed and enabled to supply output audio samples from one or more RAM buffers. Finally, the run bit should be set to start AUDIOOUT/DAC operation. After the 8-word AUDIOOUT FIFO is filled, conversion begins. Each 32-bit register within the AUDIOOUT's address space is aliased to four adjacent words. The first word is used for normal read-write access, while the subsequent three words are contained within the register's set-clear-toggle (SCT) address space. Only bits that are written to with a one in this space are affected. For example, writing a one to a bit using the register's set address, sets that particular bit while maintaining the state of all other bits. This convention allows easy bit manipulation without requiring the standard read-modify-write procedure. Bits that are written with a one to the register's clear address clear the bit, while the toggle address causes bits to invert their current state. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-3 AUDIOOUT/DAC From DAC DMA 1 FIFO DAC R VAG 5 X HP_VGND 2 LINE1R From DAC DMA X 4 Headphone Right X HPR 1 FIFO DAC L 3 Speaker Amp X X SPEAKERN SPEAKERP 6 2 LINE1L X 4 Headphone Left X HPL Notes: From Headphone Left From Headphone Right 1. HW_AUDIOOUT_DACVOLUME: Digital volume control. -0.5 dB to -100 dB in 0.5 dB steps. 2. HW_AUDIOOUT_HPVOL: Analog volume control. 6 dB to -57.5 dB in 0.5 dB steps. 3. HW_AUDIOOUT_SPEAKERCTRL: Analog control for speaker amplifier, fixed gain of 9.5 dB from each DAC, 15.5dB total. 4. HW_AUDIOIN_MICLINE_DIVIDE_LINE1/2. 5. HW_AUDIOOUT_PWDN: Enable capless headphone common amplifier. 6. The speaker amplifier mixes the left and right DAC outputs and provides a fixed gain of 6x (or 15.5dB). Figure 29-2. AUDIOOUT/DAC Block Diagram 29.2.1 AUDIOOUT DMA The DMA is typically controlled by a linked list of descriptors. Generally, the descriptors are circularly linked to cause the DMA to cycle through the set of DMA buffers. The DMA can be programmed to assert an IRQ when some or all of the buffers have been transmitted. For example, AUDIOOUT DMA descriptor 0 may program the DMA to transmit a buffer, set the done IRQ, and fetch descriptor 1. Descriptor 1 programs the DMA to transmit the next buffer. The DMA continues to operate normally while the IRQ is asserted. The CPU needs to respond to the IRQ before the DMA has transmitted all of the buffers with new data. The DMA ISR clears the IRQ flag and prepares buffers and/or descriptors with new data. In general, software copies new data into the buffers or adjust the descriptors to point to existing buffers. Software should also take advantage of the DMA's counting semaphore feature to synchronize the addition of new descriptors to the chain. The DMA can take PCM data from any memory-mapped location. For 32-bit PCM data, the left channel sample is stored first in the lowest address, followed by the corresponding right channel sample in the i.MX23 Applications Processor Reference Manual, Rev. 1 29-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC next word address (+4 bytes). For 16-bit mode, sample pairs are stored in each word. Right samples are stored in the upper half word, while left samples are stored in the lower half word. Because the AUDIOOUT always operates on stereo data, the PCM buffer should always have an integer number of words. It is not possible to play mono data unless the mono samples are each repeated twice in memory, once for the left channel and once for the right channel. The audio data values are in two's complement format, where full scale values range from 0x7FFFFFFF to 0x80000000 for 32-bit data or 0x7FFF to 0x8000 for 16-bit data. In addition to the DMA IRQ used for AUDIOOUT buffer refill, the AUDIOOUT also has an underflow and overflow IRQ. Overflows should never occur, because (by design) the DMA should never attempt to write more data than there is space available within the AUDIOOUT's FIFO. However, if the DMA does not keep up with requests and the FIFO is emptied by the AUDIOOUT's filter stages, an underflow occurs. This causes the underflow flag to be set in the AUDIOOUT control register (HW_AUDIOOUT_CTRL). If the overflow/underflow IRQ enable bit is set, then this condition also asserts an interrupt. The interrupt is cleared by writing a one to the underflow flag in the HW_AUDIOOUT_CTRL's SCT clear address space. An AUDIOOUT underflow is typically caused by the DMA running out of new buffers, or if the AHB or APBX is stalled or is otherwise unable to meet the bandwidth requirements at the current operating frequency. If the counting semaphore reaches 0, the DMA stops processing new descriptors and stops moving data to the AUDIOOUT's data register (HW_AUDIOOUT_DATA). In some cases, it may be desirable to synchronize the DAC clock speed with some other reference. Examples include a system playing from a network stream or digital FM receiver. In these cases, the AUDIOOUT sample rate register can be adjusted to speed up or slow down the data rate. Software needs to periodically monitor the buffer positions to make corrections as necessary. 29.2.2 DAC Sample Rate Converter and Internal Operation Table 29-1 contains the required value of the HW_AUDIOOUT_DACSRR register for various common sample rates. Although these are the standard rates, any sample rate from 8K to 192 kHz can be programmed. Table 29-1. Bit Field Values for Standard Sample Rates Sample Rate FsampleDAC BASEMULT HW_audioout_dacsRr SRC_HOLD SRC_INT SRC_FRAC 192,000 Hz 176,400 Hz 128,000 Hz 96,000 Hz 88,200 Hz 64,000 Hz 48,000 Hz 44,100 Hz 0x4 0x4 0x4 0x2 0x2 0x2 0x1 0x1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0F 0x11 0x17 0x0F 0x11 0x17 0x0F 0x11 0x13FF 0x0037 0x0E00 0x13FF 0x0037 0x0E00 0x13FF 0x0037 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-5 AUDIOOUT/DAC Table 29-1. Bit Field Values for Standard Sample Rates (continued) Sample Rate FsampleDAC BASEMULT HW_audioout_dacsRr SRC_HOLD SRC_INT SRC_FRAC 32,000 Hz 24,000 Hz 22,050 Hz 16,000 Hz 12,000 Hz 11,025 Hz 8,000 Hz 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x1 0x1 0x1 0x3 0x3 0x3 0x17 0x0F 0x11 0x17 0x0F 0x11 0x17 0x0E00 0x13FF 0x0037 0x0E00 0x13FF 0x0037 0x0E00 NOTE: Sample-rates greater than 48 kHz can only be used when the AUDIOIN is disabled, and 44.1 kHz is the maximum sample rate at which both the AUDIOOUT and AUDIOIN can operate simultaneously. For any of the desired sample rates, a fractional sample-rate conversion factor is calculated within the DIGFILT according to the following equation SRConvDAC = 65536 * [(FanalogDAC)/ (8 * HoldDAC * FsampleDAC)] If computed with the above explicit operator precedence, the resulting sample-rate conversion factor (SRConvDAC) will be a 24-bit scaled fixed-point representation of the desired decimation factor. The 1-bit sigma delta D/A converter is always sampled on a submultiple of the 24.0-MHz crystal oscillator frequency, as specified in the HW_AUDIOOUT_ANACLKCTRL_DACDIV register (see Figure 29-3). This divider generates sample strobes at FanalogDAC where the divisors available come from the set {4,6,8,12,16,24}. With HW_AUDIOOUT_ANACLKCTRL_DACDIV cleared to 0, to divide by 4, FanalogDAC becomes 6.0 MHz for a 24.0-MHz crystal. The sample strobe derived from this divider is used to interpolate the 1-bit D/A values. The 1-bit sigma delta modulator is effectively running at FanalogDAC. As shown in Figure 29-3, the 16-bit or 32-bit D/A values are extracted from on-chip RAM via the DMA. They are filtered to band-limit the audio stream. This filter runs on xtal_clk, but filters samples at the source sample rate, which is slower than the output D/A sample rate. In the process, this filter performs a fixed 1:8 interpolation or up-sample input stream. A single 24-bit sample at the output of the fixed filter is further interpolated up to the 1-bit D/A rate. The variable rate sample, hold and interpolate block performs this function. It stalls the filter pipeline and DMA source, using the handshake lines that connect with the previous filter stage to supply samples at the correct over-sample ratio. The 1-bit DAC runs at the fixed sample rate of FanalogDAC while the DMA fetches samples in burst at irregular intervals to maintain the required input to the modulator. In this case, the 1-bit D/A is running at 6 MHz. The sample hold and interpolate block accepts a new sample from the filter at a (44.1 kHz * 8) = 352.8 kHz. It passes interpolated samples to the modulator at a 6.0-MHz rate. The sample, hold and interpolate block passes a source sample from the fixed 1:8 interpo- i.MX23 Applications Processor Reference Manual, Rev. 1 29-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC lation filter to the sigma delta modulator corresponding to every 8.503 FanalogDAC samples. Recall that this is a variable rate interpolation stage that changes for every Over Sample Rate (OSR) setting in use. If the desired sample rate FsampleDAC= 44.1 kHz, for example, the sample hold and interpolate block will accept samples from fixed interpolation filter at 352.8 kHz, i.e., 8x the desired sample rate. There is a handshake pair (request/ack) between the variable rate sample hold and interpolate block and the fixed interpolating filter block. This handshake is used to pace the samples from the FIFO to 44.1 kHz. 1 x FsampleDAC Handshake Right Channel from DMA Handshake Left Channel from DMA 1:8 Fixed Interp. Filter 8 x FsampleDAC Sample Hold & Interpolate Sigma dac_rsamp Delta Modulator Sigma dac_lsamp Delta Modulator 1-Bit Analog D/A 1-Bit Analog D/A 3D Effect R handshake 3D Effect 1:8 Fixed Interp. Filter Sample Hold & Interpolate L HW_AUDIOOUT_ANACLKCTRL_DACDIV 24.0 MHz XTAL OSC /DA_DIV samp_strobe FanalogDAC XTAL_CLK position_reg[31:0] HW_AUDIOOUT_DACSRR 24'hFF0000 1 + samp_strobe 1 31 16 15 Position Reg whole fraction # frac[15:0] pos_zero pos_zero= (position_reg[23:16] == 8'h00) Variable Rate Interpolator Figure 29-3. Stereo Sigma Delta D/A Converter There are also members of the 48-kHz family whose members satisfy the property: 24.576 MHz = Q * FsampleDAC These sample rates include 48 kHz, 32 kHz, 24 kHz, 16 kHz, and 12 kHz. There are also the members of the 44.1-kHz family whose members satisfy the property: 16.9344 MHz = Q * FsampleADC where Q comes from the set of integers. These sample rates include 44.1 kHz, 22.05 kHz, and 11.025 kHz. The D/A converter block includes a variable rate or rational interpolator to accommodate these sample rates, as shown in Figure 29-3. Rational numbers in the DAC are approximated with a scaled fixed-point 24-bit value. In this case, the decimal point falls between bit 15 and bit 16. Therefore, the lower two bytes i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-7 AUDIOOUT/DAC hold the fractional part, while the upper byte holds the whole number portion of the scaled fixed point. The position register uses this scaled fixed-point representation for the number of 1-bit samples to be interpolated (generated) to find the next sample to be sent to the sigma delta modulator. Whenever the whole number part (bits 23:16) is zero, then the next DMA sample is consumed. For playback at 44.1 kHz, set the interpolator to generate 67.027 new interpolated samples between every DMA sample. 29.2.3 Reference Control Settings The reference control register allows adjustment of reference voltages and currents. VBG is the internal bandgap voltage (no external pin). This is a stable voltage reference used to establish all other voltage and current references for the chip, including VAG, vrefp, the Li-Ion charge termination voltage, etc. All the voltage and current references on the chip are proportional to VBG. VAG is the analog ground voltage. It sets the DC bias on the input and output of all of the audio pins. This is typically set near VDDA/2. VAG also affects the peak output swing of the DAC. As VAG is lowered, the output swing of the DAC scales with it. However, at low VDDA levels, the analog performance can be improved by setting VAG somewhat below VDDA/2. The DAC is particularly susceptible to power supply noise if VDDA-VAG is not large enough. 29.2.4 Headphone The i.MX23 supports a conventional stereo headphone drive, as shown in Figure 29-4. Headphone leads with an impedance of 16 or greater are recommended. Headphones 16 16 220 F 61 HPR 220 F 65 HPL Figure 29-4. Conventional Stereo Headphone Application Circuit i.MX23 Applications Processor Reference Manual, Rev. 1 29-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC In addition, as shown in Figure 29-5-Figure 29-7, the chip can generate an optional headphone common node circuit for the headphones that eliminates the need for the large and expensive DC blocking capacitors. It also improves the anti-pop performance. These benefits are obtained at a slight increase in power consumption, i.e., at 30 mV rms output, the resultant increase in power consumption is approximately 2.7 mW. H eadphones tie at headphone jack 16 16 61 H PR 63 H P_VG ND 65 H PL M a ke this trace very low im peda nce for g ood crosstalk perform ance . Figure 29-5. Stereo Headphone Application Circuit with Common Node i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-9 AUDIOOUT/DAC HP AMP Headphone Common HW_AUDIOOUT_ANACTRL_SHORTMODE_CM != 00' HW_AUDIOOUT_ANACTRL_SHORTMODE_CM == 01' IRQA SHORT DETECT 0 HW_AUDIOOUT_ANACTRL_SHORT_CM_STS HW_AUDIOOUT_ANACTRL_SHORTMODE_CM == 00' R Latch S 1 0 1 Powerdown Headphone Amp HW_AUDIOOUT_ANACTRL_SHORTMODE_CM == 01' HW_AUDIOOUT_ANACTRL_SHORTMODE_CM != 11' Figure 29-6. Stereo Headphone Common Short Detection and Powerdown Circuit HP AMP Headphone Common HW_AUDIOOUT_ANACTRL_SHORTMODE_LR != 00' HW_AUDIOOUT_ANACTRL_SHORTMODE_LR == 01' || HW_AUDIOOUT_ANACTRL_SHORTMODE_LR == 10' IRQA 0 HW_AUDIOOUT_ANACTRL_SHORT_LR_STS SHORT DETECT HW_AUDIOOUT_ANACTRL_SHORTMODE_LR == 00' R Latch S 1 HW_AUDIOOUT_ANACTRL_SHORTMODE_LR != 01' Powerdown Headphone Amp Figure 29-7. Stereo Headphone L/R Short Detection and Powerdown Circuit 29.2.4.1 Board Components The headphone amplifier output requires a few external resistors and capacitors. There is also a 100 resistor to the headphone ground, which has multiple functions: * In cap mode operation (a DC blocking cap is present), the 100 resistor improves startup pop suppression. i.MX23 Applications Processor Reference Manual, Rev. 1 29-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC * * * In capless mode operation (no DC blocking cap), the resistor avoids 60-Hz hum into a powered set of speakers plugged into the headphone jack when the player is turned off. In capless and cap mode players, the 100 resistor minimizes the power-off signal feedthrough from line-in to headphone out. In powerdown mode, there is a 100k resistor between line-in and headphone out. The 100 load resistor keeps the power-down feedthrough level at -60 dB. When the part is powered up, there is no signal path between line-in and headphone out, thus no bleedthrough. 29.2.4.2 Capless Mode Operation The headphone amplifier is designed to work with or without a DC blocking cap. In capless mode, an amplifier is used to bias the headphone ground at the analog ground level (VAG), which is typically near VDDA/2. This avoids any DC signal across the output load. Capless operation provides slight improvement to PSRR and low frequency performance. It slightly degrades SNR and THD (approximately 1 dB). The biggest advantage is the savings in cost and area by eliminating the large DC blocking caps. The biggest disadvantage is extra power consumption. The capless mode of operation doubles the power consumed in the headphone amps. At normal listening levels, this has a fairly small effect on battery life. But with a full scale sine wave, it can significantly reduce the battery life. With a sinusoidal signal, the headphone power consumption per channel with a 16 load is roughly: Power = 1mW + Vpeak * VDDA / (16ohm * PI) This number is doubled in capless mode. However, normal music files have a much higher peak-to-average ratio than a sinusoid. A PAR of 10 is typical in a music file, compared to a PAR of 1.414 for a sinusoid. So headphone power for a normal music file is: Power = 1mW + Vpeak * VDDA * 2.8mW (per channel) Again, this number is doubled in capless mode. (per channel) 29.2.5 29.2.5.1 Speaker Amplifier Overview The i.MX23 provides an on-chip amplifier that can be used to drive an external speaker (see Figure 29-8). The external speaker must be bridge tied. Single ended (half-bridge) speakers are not supported. If ferrite beads are used they should have very low DC resistance and high saturation current to avoid causing power loss or distortion in the speaker. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-11 AUDIOOUT/DAC On Chip VDDS Headphone Left 3R + Volume Control DAC-L - R + R R VCM Speaker P Speaker 4 to 16 Ohms Speaker N Speaker Amplifier + VCMREF + Volume Control DAC-R - R 3R Headphone Right GNDA Figure 29-8. Speaker Amplifier with External Speaker 29.2.5.2 Details of Operations The speaker driver is designed to handle a wide range of speaker impedances but it is assumed that the speaker will be in the range of 4 to 16 . The speaker driver can also tolerate multiple speakers in parallel. If the total speaker load is less than 4 it will be necessary to limit the signal such that the peak current does not exceed 1.1 A. Care should be taken to minimize board trace impedances for the speaker outputs and for the power and ground. It is also necessary to minimize the audio band (20-20KHz) impedance of the speaker power supply to avoid reducing the maximum output power of the speaker. Due to the differential output, the speaker can be powered up or down nearly instantaneously without any pop problems. This makes it easy to save power by shutting off the speaker amplifier when the speaker is idle. The speaker amplifier does not have output short circuit protection. However, battery brown-out or VDD4P2 LDO current limit can act as a short circuit protection if those supplies are used to power the speaker amplifier. The power supply for the speaker amplifier can be set to any level between 2.7 V and 4.2 V. The speaker amplifier power supply can be tied directly to a Li-Ion battery to avoid losses in DC-DC voltage conversion. There are no constraints on the speaker (VDDS) supply vs. the VDDIO supply. The speaker amplifier supply can be higher, lower, or tied to the VDDIO supply externally. When plugged into an external power source, that source must be able to provide the peak currents of the speaker amplifier or the speaker amplifier current draw could cause the power supply to brownout. If necessary, the peak currents can be reduced by lowering the maximum speaker volume. The on-chip 4.2 V regulator (used when an external supply is provided) can only supply a total of 780 mA peak current. If it is desired to use the maximum output power of the speaker amplifier when plugged into an external power source, it will be necessary to provide an external power supply for the speaker amplifier (2.7 - 4.2 V that doesn't pass through the on-chip 4.2 V regulator). i.MX23 Applications Processor Reference Manual, Rev. 1 29-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC Volume control for the speaker is provided through the digital DAC volume. It is presumed that the headphone outputs will be disabled or muted while the speaker is driving. If they are not disabled, the digital DAC volume control will affect the headphone volume as well as the speaker. Additionally, the analog mix in the speaker amplifier will cause some reduced channel separation in the headphone. When the speaker is turned off, there is NO degradation of headphone performance. If the speaker amplifier is connected to the battery, it should be recognized that the maximum output swing without clipping will drop as the battery voltage drops. If desired, it is possible to monitor the battery level and reduce the maximum volume with the battery voltage level (to limit the amount of clipping). The speaker amplifier mixes the right and left DAC outputs and provides a fixed gain of 6X (15.5dB). This high gain allows for the voltage shift from the low VDDA power rail to the speaker amplifier power rail and also allows the speaker outputs to be overdriven to provide more power output. The high peak-to-average ratio of most voice or music signals usually allows for 3-6dB of overdrive without substantial audio quality degradation (the clips happen rarely enough). Maximum output power levels can reach 1.9 Watts with a 4 load. The worst case on-chip power dissipation is expected to be 0.9 Watts (when using a 4.2 V rail and a 4 load). The package thermal impedance is ~50 C/Watt. So at the maximum output level the chip junction temperature can increase by up to 45 C. This alone should not be a problem. But if the battery charger is also activated (another high dissipation circuit), use the on-chip temperature sensor to ensure that the temperature stays within an acceptable range. 29.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. Note that the SFTRST and CLKGATE bits of both AUDIOOUT and AUDIOIN must be cleared before doing any operation with this block. 29.4 Programmable Registers The following registers provide control for programmable elements of the AUDIOOUT/DAC block. 29.4.1 AUDIOOUT Control Register Description The AUDIOOUT Control Register provides overall control of the digital portion of the digital-to-analog converter. HW_AUDIOOUT_CTRL HW_AUDIOOUT_CTRL_SET HW_AUDIOOUT_CTRL_CLR 0x000 0x004 0x008 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-13 AUDIOOUT/DAC HW_AUDIOOUT_CTRL_TOG Table 29-2. HW_AUDIOOUT_CTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 DMAWAIT_COUNT 0x00C 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 DAC_ZERO_ENABLE 0 4 0 3 FIFO_UNDERFLOW_IRQ 0 2 FIFO_OVERFLOW_IRQ 0 1 FIFO_ERROR_IRQ_EN 0 0 WORD_LENGTH SS3D_EFFECT INVERT_1BIT EDGE_SYNC LOOPBACK LR_SWAP CLKGATE RSRVD4 RSRVD3 RSRVD2 RSRVD1 SFTRST Table 29-3. HW_AUDIOOUT_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION AUDIOOUT Module Soft Reset. Setting this bit to one forces a reset to portions of DIGFILT that control audio output and then gates the clocks off since the CLKGATE bit's reset state is to disable clocks. This bit must be cleared to zero for normal operation. Note that the CLKGATE bit does not affect SFTRST since it must remain writeable during clock gating. A note is included in the bit field descriptions below for those bits that are not affected by the AUDIOOUT's soft reset bit. These bits either control AUDIOIN or both AUDIOIN and AUDIOOUT functions. AUDIOOUT Clock Gate Enable. When this bit is set to 1, it gates off the clocks to the portions of the DIGFILT block that control only output audio functions. It does not affect portions of the block that control AUDIOIN. Clear this bit to zero for normal AUDIOOUT operation. Note that when this bit is set, it remains writeable during clock gating so that it may be disabled by the user. Reserved. Always write zeroes to this bit field. DMA Request Delay Count. This bit field specifies the number of APBX clock cycles (0 to 31) to delay before each DMA request. This field acts as a throttle on the bandwidth consumed by the DIGFILT block. This field can be loaded by the DMA. Reserved. Always write zeroes to this bit field. Left/Right Output Channel Swap Enable. Setting this bit to one swaps the left and right serial audio outputs from the SDM block to the analog DAC . Serial Output Clock Edge Sync Select. This bit selects the edge of the DAC's serial output clock upon which the SDM synchronizes for data transmit. 0=Rising edge. 1=Falling edge. 30 CLKGATE RW 0x1 29:21 RSRVD4 20:16 DMAWAIT_COUNT RO 0x0 RW 0x0 15 14 RSRVD3 LR_SWAP RO 0x0 RW 0x0 13 EDGE_SYNC RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 29-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor RUN AUDIOOUT/DAC Table 29-3. HW_AUDIOOUT_CTRL Bit Field Descriptions BITS LABEL INVERT_1BIT 12 RW RESET RW 0x0 DEFINITION Invert Serial Audio Output Enable. When set, this bit inverts the 1-bit serial output of both the left and right channels to the DAC's sigma-delta modulator. 0=Normal operation. 1=Invert L/R serial audio output from the SDM block. Reserved. Always write zeroes to this bit field. Virtual 3D Effect Enable. This bit field provides a virtual 3D effect for a two channel system by subtracting a portion of the opposite channel's content for each channel. Three reduction ratios are available (dB value represents amount of opposite channel content subtracted). 00=Off 01=Low (3 dB) 10=Medium (4.5 dB) 11=High (6 dB) Reserved. Always write zeroes to this bit field. PCM Audio Bit Size Select. This bit selects the size of the parallel PCM data that is input to the AUDIOOUT's FIFO. 0=32-bit PCM samples. 1=16-bit samples. Note that the PCM audio data input to the FIR filter stages is 24 bit. For 16-bit operation, the data is first sign-extended to 24 bits. For 32-bit operation, the data is first normalized by dropping the least significant 8 bits. 11:10 RSRVD2 9:8 SS3D_EFFECT RO 0x0 RW 0x0 7 6 RSRVD1 WORD_LENGTH RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-15 AUDIOOUT/DAC Table 29-3. HW_AUDIOOUT_CTRL Bit Field Descriptions BITS LABEL DAC_ZERO_ENABLE 5 RW RESET RW 0x0 DEFINITION Never set DAC_ZERO_ENABLE! Make sure it is always cleared. (Since this bit is clear on reset, you'll be fine if you never touch it at all.) If you want to silence the audio output, but not go into a lower power mode, set HW_AUDIOOUT_DACVOLUME.MUTE_LEFT and HW_AUDIOOUT_DACVOLUME.MUTE_RIGHT simultaneously. This will immediately mute the digital audio signal sent to the DAC. There are two important things to note: 1. These bits ignore zero-crossing detection. They immediately mute the digital audio signal, so this can cause a "pop." The "pop" can be avoided by ramping the volume. 2. These bits cannot be toggled when clock gated. If you want to minimize power consumption, mute the amplifiers first, and then power down the DAC. Reverse these operations to come back out of the low power state. The amplifiers will hold the output signal to VAG so everything will be quiet, and the DAC can power back up very quickly when you have to start playing sound again. To enter the low-power state: 1. Set HW_AUDIOOUT_HPVOL.MUTE and HW_AUDIOOUT_LINEOUTCTRL.MUTE to mute the Headphone and Line Out amplifiers, respectively. 2. Set HW_AUDIOOUT_PWRDN.DAC to power down the DAC. To exit the low-power state: 1. Clear HW_AUDIOOUT_PWRDN.DAC to power up the DAC. 2. Clear HW_AUDIOOUT_HPVOL.MUTE and HW_AUDIOOUT_LINEOUTCTRL.MUTE to un-mute the Headphone and Line Out amplifiers, respectively. AUDIOIN-to-AUDIOOUT Loopback Enable. Setting this bit to one routes the audio data received by the AUDIOIN's FIFO to the AUDIOOUT's FIFO. This test mode provides a loopback that does not use the DIGFILT's DMA memory inteface. This bit should be cleared to zero for normal operation. FIFO Underflow Interrupt Status Bit. This bit is set by hardware if the AUDIOOUT's FIFO underflows any time during operation due to a DMA request that is not serviced in time. It is reset by software by writing a one to the corresponding bit in the HW_AUDIOOUT_CTRL_CLR register. An interrupt is issued to the host processor if this bit is set and FIFO_ERROR_IRQ_EN=1. 4 LOOPBACK RW 0x0 3 FIFO_UNDERFLOW_IRQ RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 29-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC Table 29-3. HW_AUDIOOUT_CTRL Bit Field Descriptions BITS LABEL 2 FIFO_OVERFLOW_IRQ RW RESET RW 0x0 DEFINITION FIFO Overflow Interrupt Status Bit. This bit is set by hardware if the AUDIOOUT's FIFO overflows. It is reset by software by writing a one to the corresponding bit in the HW_AUDIOOUT_CTRL_CLR register. An interrupt is issued to the host processor if this bit is set, and FIFO_ERROR_IRQ_EN=1. Note that overflows should not occur by design since requests to the DMA are not made unless there is adequate space present within the FIFO. Therefore, this condition would indicate a serious DMA error. FIFO Error Interrupt Enable. Set this bit to one to enable an AUDIOOUT interrupt request to the host processor when either the FIFO overflow or underflow status bits are set. Note that this bit does not affect the state of the underflow/overflow status bits, but rather their ability to signal an interrupt to the CPU. AUDIOOUT Enable. Setting this bit to one causes AUDIOOUT operation to start, beginning with a DMA request to fill its 8-word FIFO. Clearing this bit to zero stops data conversion and also causes the CLKGATE bit to be set. 1 FIFO_ERROR_IRQ_EN RW 0x0 0 RUN RW 0x0 DESCRIPTION: The AUDIOOUT Control Register contains bit fields used to control and monitor AUDIOOUT operation including: reset, clocks, DMA transfers, data to the analog DAC module, PCM data size, test, and interrupt control. EXAMPLE: HW_AUDIOOUT_CTRL.RUN = 1; // start DAC conversion 29.4.2 AUDIOOUT Status Register Description HW_AUDIOOUT_STAT HW_AUDIOOUT_STAT_SET HW_AUDIOOUT_STAT_CLR HW_AUDIOOUT_STAT_TOG Table 29-4. HW_AUDIOOUT_STAT The AUDIOOUT Status Register is used to determine if the digital-to-analog converter is operational. 0x010 0x014 0x018 0x01C 3 1 DAC_PRESENT 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD1 29-17 AUDIOOUT/DAC Table 29-5. HW_AUDIOOUT_STAT Bit Field Descriptions BITS LABEL 31 DAC_PRESENT RW RESET RO 0x1 DEFINITION AUDIOOUT Functionality Present. This status bit is set to one in products that include the AUDIOOUT/DAC. If this bit is zero, the AUDIOOUT/DAC is permanently disabled and cannot be operated by the user. Reserved. Always write zeroes to this bit field. 30:0 RSRVD1 RO 0x0 DESCRIPTION: The AUDIOOUT Status Register provides an indication of the presence of the DAC functionality. EXAMPLE: unsigned statusValue = HW_AUDIOOUT_STAT.DAC_PRESENT; 29.4.3 AUDIOOUT Sample Rate Register Description The AUDIOOUT Sample Rate Register is used to specify the sample rate that the parallel PCM audio data is converted to within the SDM module before being output to the analog DAC. HW_AUDIOOUT_DACSRR HW_AUDIOOUT_DACSRR_SET HW_AUDIOOUT_DACSRR_CLR HW_AUDIOOUT_DACSRR_TOG Table 29-6. HW_AUDIOOUT_DACSRR 3 1 3 0 2 9 BASEMULT 0x020 0x024 0x028 0x02C 2 8 2 7 RSRVD2 2 6 2 5 SRC_HOLD 2 4 2 3 2 2 RSRVD1 2 1 2 0 1 9 1 8 SRC_INT 1 7 1 6 1 5 1 4 RSRVD0 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 SRC_FRAC 0 5 0 4 0 3 0 2 0 1 0 0 OSR i.MX23 Applications Processor Reference Manual, Rev. 1 29-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC Table 29-7. HW_AUDIOOUT_DACSRR Bit Field Descriptions BITS 31 OSR LABEL RW RESET RO 0x0 DEFINITION AUDIOOUT Oversample Rate. Note that the oversample rate is fixed at 6 MHz. OSR6 = 0x0 AUDIOOUT oversample rate at 6 MHz. OSR12 = 0x1 AUDIOOUT oversample rate at 12 MHz. 30:28 BASEMULT RW 0x1 Base Sample Rate Multiplier. This bit field is used to configure the DAC's sample rate to one of three ranges: single, double, or quad. This multiply factor is used to achieve sample rates greater than the standard rates of 32/44.1/48 kHz. A value of 0x1 should be used when selecting half and quarter sample rates. Note that sample rates greater than 48 kHz may only be used when the AUDIOIN is disabled, and 44.1 kHz is the maximum sample rate at which both the AUDIOIN and AUDIOOUT can operate simultaneously. SINGLE_RATE = 0x1 Single rate multiplier (for 48/44.1/32 kHz as well as half and quarter rates). DOUBLE_RATE = 0x2 Double rate multiplier (for 96/88.2/64 kHz). QUAD_RATE = 0x4 Quad rate multiplier (for 192/176.4/128 kHz). 27 RSRVD2 26:24 SRC_HOLD RO 0x0 RW 0x0 23:21 RSRVD1 20:16 SRC_INT RO 0x0 RW 0x11 15:13 RSRVD0 12:0 SRC_FRAC RO 0x0 RW 0x37 Reserved. Always write a zero to this bit field. Sample Rate Conversion Hold Factor. This bit is used to hold a sample of a variable number of clock cycles in order to generate half and quarter sample rates when dividing down the AUDIOOUT's internal rate using the equation: output_sample_rate = (6x10^6 * BASEMULT) / (SRC_INT.SRC_FRAC * 8 * (SRC_HOLD + 1)). Refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. Reserved. Always write zeros to this bit field. Sample Rate Conversion Integer Factor. This bit field is the integer portion of a divide term used to sample rate convert the AUDIOOUT's internal rate using the equation: output_sample_rate = (6x10^6 * BASEMULT) / (SRC_INT.SRC_FRAC * 8 * (SRC_HOLD + 1)). Refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. Reserved. Always write zeros to this bit field. Sample Rate Conversion Fraction Factor. This bit field is the fractional portion of a divide term used to sample rate convert the AUDIOOUT's internal rate using the equation: output_sample_rate = (6x10^6 * BASEMULT) / (SRC_INT.SRC_FRAC * 8 * (SRC_HOLD + 1)). Refer to the sample rate table earlier in this chapter that provides a list of bit field values required to achieve all common sample rates. DESCRIPTION: The AUDIOOUT Sample Rate Register provides a number of bit fields to direct the SDM module's hardware to sample-rate-convert the audio stream output to one of a number of common sample rates. Note that these values can also be dynamically altered in small amounts in order to track variations in the outgoing audio stream from sources such as FM digital radio. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-19 AUDIOOUT/DAC EXAMPLE: // Program the DAC to output a sample rate of 48 kHz: HW_AUDIOOUT_DACSRR.BASEMULT = 0x1; // quad-rate HW_AUDIOOUT_DACSRR.SRC_HOLD = 0x0; // 0 for full- double- quad-rates HW_AUDIOOUT_DACSRR.SRC_INT = 0xF; // 15 for the integer portion HW_AUDIOOUT_DACSRR.SRC_FRAC = 0x13FF; // the fractional portion 29.4.4 AUDIOOUT Volume Register Description The AUDIOOUT Volume Register is used to adjust the signal level of the playback audio output to the DAC. HW_AUDIOOUT_DACVOLUME HW_AUDIOOUT_DACVOLUME_SET HW_AUDIOOUT_DACVOLUME_CLR HW_AUDIOOUT_DACVOLUME_TOG 0x030 0x034 0x038 0x03C Table 29-8. HW_AUDIOOUT_DACVOLUME 3 1 3 0 2 9 2 8 VOLUME_UPDATE_LEFT 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 VOLUME_UPDATE_RIGHT 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 29-9. HW_AUDIOOUT_DACVOLUME Bit Field Descriptions BITS LABEL 31:29 RSRVD4 28 VOLUME_UPDATE_LEFT RW RESET RO 0x00 RO 0x0 DEFINITION Reserved. Always write zeroes to this bit field. Left Channel Volume Update Pending. This bit is set to one by the hardware when an AUDIOOUT volume update is pending, i.e., waiting on a zero crossing on the left channel. The bit is set following a write to the VOLUME_LEFT bit field and is cleared when the attenuation value is applied to the PCM output stream (at a zero-crossing). This status bit is not used when EN_ZCD=0. Reserved. Always write zeroes to this bit field. Enable Zero Cross Detect. This bit enables/disables use of the zero cross detect circuit in the DAC (rather than enabling the circuit itself). When enabled, changes to the volume bit fields are not applied until it is detected that the output signal's sign bit toggles (crosses zero amplitude). When disabled, changes to the volume bit fields take effect immediately when written. 27:26 RSRVD3 25 EN_ZCD RO 0x00 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 29-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor VOLUME_RIGHT VOLUME_LEFT MUTE_RIGHT MUTE_LEFT RSRVD2 RSRVD4 RSRVD3 EN_ZCD RSRVD1 AUDIOOUT/DAC Table 29-9. HW_AUDIOOUT_DACVOLUME Bit Field Descriptions BITS LABEL 24 MUTE_LEFT RW RESET RW 0x1 DEFINITION Mute Left Channel. 0=unmute, 1=mute. Note that mute is always applied immediately when written (unlike volume when EN_ZCD=1). The channel volume should always be ramped down to the minimum level (-100dB) before setting the mute bit. Left Channel Volume Setting. Establishes the outgoing audio signal strength during playback. Volume ranges from -0.5 dB (0xFE) to -100 dB (0x37). Each increment of this bit field causes a half-dB increase in volume. The values 0x00-0x37 all produce the same attenuation level of -100 dB. Note: Do not change the DAC volume into or from the 0xFF state or else it will create a large pop. Remaining in the 0xFF state is acceptable if all of the volume control is done in the headphone. Reserved. Always write zeroes to this bit field. Right Channel Volume Update Pending. This bit is set to one by the hardware when an AUDIOOUT volume update is pending, i.e., waiting on a zero crossing on the right channel. The bit is set following a write to the VOLUME_RIGHT bit field and is cleared when the attenuation value is applied to the PCM output stream (at a zero-crossing). This status bit is not used when EN_ZCD=0. Reserved. Always write zeroes to this bit field. Mute Right Channel. 0=Unmute, 1=Mute. Note that mute is always applied immediately when written (unlike volume when EN_ZCD=1), therefore the user should always ramp down the channel's volume to the minimum level (-100 dB) before setting the mute bit. Right Channel Volume Setting. Establishes the outgoing audio signal strength during playback. Volume ranges from -0.5 dB (0xFE) to -100 dB (0x37). Each increment of this bit field causes a half-dB increase in volume. The values 0x00-0x37 all produce the same attenuation level of -100 dB. Note: Do not change the DAC volume into or from the 0xFF state or else it will create a large pop. Remaining in the 0xFF state is acceptable if all of the volume control is done in the headphone. 23:16 VOLUME_LEFT RW 0xfe 15:13 RSRVD2 12 VOLUME_UPDATE_RIGHT RO 0x00 RO 0x0 11:9 8 RSRVD1 MUTE_RIGHT RO 0x00 RW 0x1 7:0 VOLUME_RIGHT RW 0xfe DESCRIPTION: The AUDIOOUT Volume Register allows independent volume and mute control of the left and right channels. Output audio can be attenuated in 0.5-dB steps, from full-scale down to a minimum of -100 dB. This register is also used to enable/control volume updates such that they are only applied when PCM values cross zero to prevent unwanted audio artifacts. EXAMPLE: HW_AUDIOOUT_DACVOLUME.U = 0x01ff01ff; // mute both left and right channels HW_AUDIOOUT_DACVOLUME.U = 0x00ff00ff; // maximum volume for left and right channels. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-21 AUDIOOUT/DAC 29.4.5 AUDIOOUT Debug Register Description HW_AUDIOOUT_DACDEBUG HW_AUDIOOUT_DACDEBUG_SET HW_AUDIOOUT_DACDEBUG_CLR HW_AUDIOOUT_DACDEBUG_TOG 0x040 0x044 0x048 0x04C The AUDIOOUT Debug Register is used for test and debug of the AUDIOOUT block. Table 29-10. HW_AUDIOOUT_DACDEBUG 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 SET_INTERRUPT1_CLK_CROSS 0 4 SET_INTERRUPT0_CLK_CROSS 0 3 SET_INTERRUPT1_HAND_SHAKE 0 2 SET_INTERRUPT0_HAND_SHAKE 0 1 0 0 ENABLE_DACDMA Table 29-11. HW_AUDIOOUT_DACDEBUG Bit Field Descriptions BITS LABEL 31 ENABLE_DACDMA RW RESET RW 0x0 DEFINITION AUDIOOUT Digital Path Test Enable. This bit is used solely for development and debugging, and is not functional on production parts. When enabled, it causes the AUDIOIOUT's serial audio data output to bypass the DAC analog block, to be assembled into 32-bit words and transferred out to memory using the AUDIOIN's DMA Channel 0. Unlike loopback, this test mode provides a means of verifying the digital portion of the AUDIOOOUT logic without causing the audio data to pass through the AUDIOIN's FIR filter stages. Reserved. Always write zeroes to this bit field. DIGFILT RAM Speed Select. Sense AMP Timing Control for DIGFILT 208x24 RAM. Do not alter unless instructed by Freescale. Reserved. Always write zeroes to this bit field. Interrupt[1] Sync Status. This bit reflects the current state of the second flop on the chain of three flip-flops used to synchronize the AUDIOOUT's interrupt[1] signal used to prioritize channels 0 and 1 DMA requests from the DIGFILT. This signal is synchronized from the module's internal 24-MHz clock to the APBX's memory clock domain. This bit is intended for test only. 30:12 RSRVD2 11:8 RAM_SS RO 0x00 RW 0x0 7:6 5 RSRVD1 SET_INTERRUPT1_CLK_CR OSS RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 29-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor FIFO_STATUS DMA_PREQ RAM_SS RSRVD2 RSRVD1 AUDIOOUT/DAC Table 29-11. HW_AUDIOOUT_DACDEBUG Bit Field Descriptions BITS LABEL 4 SET_INTERRUPT0_CLK_CR OSS RW RESET RO 0x0 DEFINITION Interrupt[0] Sync Status. This bit reflects the current state of the second flop on the chain of three flip-flops used to synchronize the AUDIOOUT's interrupt[0] signal used to prioritize channel 0 and 1 DMA requests from the DIGFILT. This signal is synchronized from the module's internal 24-MHz clock to the APBX's memory clock domain. This bit is intended for test only. Interrupt[1] Status. This bit reflects the current state of the APBX interface state machine's internal interrupt[1] signal used to prioritize channel 0 and 1 DMA requests from the DIGFILT. This bit is intended for test only. Interrupt[0] Status. This bit reflects the current state of the APBX interface state machine's internal interrupt[0] signal used to prioritize channel 0 and 1 DMA requests from the DIGFILT. This bit is intended for test only. DMA Request Status. This bit reflects the current state of the AUDIOOUT's DMA request signal. DMA requests are issued any time the request signal toggles. This bit can be polled by software, in order to manually move samples to the AUDIOOUT's FIFO from a memory buffer when the AUDIOOUT's DMA channel is not used. FIFO Status. This bit is set by hardware when the AUDIOOUT's FIFO contains any empty entries and is cleared when the FIFO is full. 3 SET_INTERRUPT1_HAND_S HAKE RO 0x0 2 SET_INTERRUPT0_HAND_S HAKE RO 0x0 1 DMA_PREQ RO 0x0 0 FIFO_STATUS RO 0x1 DESCRIPTION: The AUDIOOUT Debug Register provides read-only access of various internal AUDIOOUT module signals to assist in debug and validation, as well as control of DACDMA test mode. EXAMPLE: unsigned tempStatus = HW_AUDIOOUT_DACDEBUG.FIFO_STATUS; 29.4.6 Headphone Volume and Select Control Register Description The Headphone Volume and Select Control Register provides volume, mute, and input select controls for the headphone. HW_AUDIOOUT_HPVOL HW_AUDIOOUT_HPVOL_SET HW_AUDIOOUT_HPVOL_CLR HW_AUDIOOUT_HPVOL_TOG 0x050 0x054 0x058 0x05C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-23 AUDIOOUT/DAC Table 29-12. HW_AUDIOOUT_HPVOL 3 1 3 0 2 9 2 8 VOLUME_UPDATE_PENDING 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 EN_MSTR_ZCD Table 29-13. HW_AUDIOOUT_HPVOL Bit Field Descriptions BITS LABEL RW RESET 31:29 RSRVD5 RO 0x0 28 VOLUME_UPDATE_PENDING RO 0x0 DEFINITION Reserved. Always write zeroes to this bit field. Volume Update Pending. This bit is set to one by the hardware when either a headphone left or right volume update is pending, i.e., waiting on a zero crossing. The bit is set following a write to either the VOL_LEFT or VOL_RIGHT bit fields and is cleared when both attenuation values are applied to the output coincident with zero-crossings in both the right and left channels. This status bit is not used when EN_MSTR_ZCD=0. Reserved. Always write zeroes to this bit field. Enable Zero Cross Detect for Headphone Amplifier. Headphone Mute. It is reset by a power-on reset only. Reserved. Always write zeroes to this bit field. Input Signal Select. 0=DAC, 1=Line1. It is reset by a power-on reset only. Reserved. Always write zeroes to this bit field. Left Headphone Volume Control. 0.5 dB volume steps. Volume range depends on HW_AUDIOOUT_HPVOL_SELECT setting. In DAC mode 0x00=+6dB and 0x7F=-57.5dB. In Line1 mode 0x00=+12dB and 0x7F=-51.5dB. Reset state is DAC mode 0x0C=0dB. It is reset by a power-on reset only. Reserved. Always write zeroes to this bit field. Right Headphone Volume Control. 0.5 dB volume steps. Volume range depends on HW_AUDIOOUT_HPVOL_SELECT setting. In DAC mode 0x00=+6dB and 0x7F=-57.5dB. In Line1 mode 0x00=+12dB and 0x7F=-51.5dB. Reset state is DAC mode 0x0C=0dB. It is reset by a power-on reset only. 27:26 25 24 23:17 16 15 14:8 RSRVD4 EN_MSTR_ZCD MUTE RSRVD3 SELECT RSRVD2 VOL_LEFT RO RW RW RO RW 0x0 0x0 0x1 0x00 0x0 RO 0x0 RW 0x0C 7 6:0 RSRVD1 VOL_RIGHT RO 0x0 RW 0x0C DESCRIPTION: This register provides volume, mute, and input select controls for the headphone. i.MX23 Applications Processor Reference Manual, Rev. 1 29-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor VOL_RIGHT VOL_LEFT RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 SELECT MUTE AUDIOOUT/DAC EXAMPLE: HW_AUDIOOUT_HPVOL.MUTE = 0; 29.4.7 Reserved Register Description HW_AUDIOOUT_RESERVED HW_AUDIOOUT_RESERVED_SET HW_AUDIOOUT_RESERVED_CLR HW_AUDIOOUT_RESERVED_TOG 0x060 0x064 0x068 0x06C This register is reserved. Table 29-14. HW_AUDIOOUT_RESERVED 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD1 Table 29-15. HW_AUDIOOUT_RESERVED Bit Field Descriptions BITS 31:0 RSRVD1 LABEL RW RESET RO 0x00000000 DEFINITION Reserved. Always write zeroes to this bit field. DESCRIPTION: This register is reserved. EXAMPLE: EMPTY 29.4.8 Audio Power-Down Control Register Description HW_AUDIOOUT_PWRDN HW_AUDIOOUT_PWRDN_SET HW_AUDIOOUT_PWRDN_CLR HW_AUDIOOUT_PWRDN_TOG Table 29-16. HW_AUDIOOUT_PWRDN The Audio Power-Down Control Register provides all power-down control bits. 0x070 0x074 0x078 0x07C 3 1 3 0 2 9 2 8 RSRVD7 2 7 2 6 2 5 2 4 SPEAKER 2 3 2 2 RSRVD6 2 1 2 0 SELFBIAS 1 9 1 8 RSRVD5 1 7 1 6 RIGHT_ADC 1 5 1 4 RSRVD4 1 3 1 2 1 1 1 0 RSRVD3 0 9 0 8 0 7 0 6 RSRVD2 0 5 0 4 CAPLESS 0 3 0 2 RSRVD1 0 1 0 0 HEADPHONE DAC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice ADC 29-25 AUDIOOUT/DAC Table 29-17. HW_AUDIOOUT_PWRDN Bit Field Descriptions BITS LABEL 31:25 RSRVD7 24 SPEAKER RW RESET RO 0x00 RW 0x1 DEFINITION Reserved. Always write zeroes to this bit field. Speaker Power-Down. It is reset by a power-on reset only. Reserved. Always write zeroes to this bit field. This bit currently does not control any logic, altering it's value has no effect. Reserved. Always write zeroes to this bit field. Right ADC Power Down. When enabled, powers down the ADC's right channel while allowing the left to function normally (mono). Note that while this bit is located in the AUDIOOUT address space, it is an ADC function controlled by the AUDIOIN's SFTRST and CLKGATE bits. Reserved. Always write zeroes to this bit field. Power Down DAC Analog Circuitry. It is reset by a power-on reset only. Reserved. Always write zeroes to this bit field. Power Down ADC and Input Mux Circuitry. 1=power down, 0=power up. Before clearing this bit you must set rtc_persistent0_release_gnd. Note that while this bit is located in the AUDIOOUT address space, it is an ADC function controlled by the AUDIOIN's SFTRST and CLKGATE bits. Reserved. Always write zeroes to this bit field. Power Down Headphone Common Amplifier Used in Capless Headphone. It is reset by a power-on reset only. Reserved. Always write zeroes to this bit field. Master (Headphone) Power Down. 1=power down, 0=power up. Before clearing this bit you must set rtc_persistent0_release_gnd bit otherwise there will be large current draw in the vag buffer amp. Before setting the persistent bit during powerup to avoid antipop you should set audioout_anactrl_hp_hold_gnd this will hold the headphone outputs at ground. It is reset by a power-on reset only. 23:21 RSRVD6 20 SELFBIAS 19:17 RSRVD5 16 RIGHT_ADC RO 0x00 RW 0x0 RO 0x00 RW 0x0 15:13 RSRVD4 12 DAC 11:9 8 RSRVD3 ADC RO 0x00 RW 0x1 RO 0x00 RW 0x1 7:5 4 RSRVD2 CAPLESS RO 0x00 RW 0x1 3:1 0 RSRVD1 HEADPHONE RO 0x00 RW 0x1 DESCRIPTION: The Audio Power-Down Register provides control to power-down sections of the audio analog circuit. EXAMPLE: HW_AUDIOOUT_PWRDN.DAC = 0; 29.4.9 AUDIOOUT Reference Control Register Description HW_AUDIOOUT_REFCTRL HW_AUDIOOUT_REFCTRL_SET HW_AUDIOOUT_REFCTRL_CLR HW_AUDIOOUT_REFCTRL_TOG 0x080 0x084 0x088 0x08C This register provides the voltage and current reference control bits. i.MX23 Applications Processor Reference Manual, Rev. 1 29-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC Table 29-18. HW_AUDIOOUT_REFCTRL 3 1 3 0 2 9 2 8 2 7 2 6 FASTSETTLING 2 5 2 4 XTAL_BGR_BIAS 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 VDDXTAL_TO_VDDD 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ADC_REFVAL RAISE_REF BIAS_CTRL LOW_PWR ADJ_ADC VBG_ADJ Table 29-19. HW_AUDIOOUT_REFCTRL Bit Field Descriptions BITS LABEL 31:27 RSRVD4 26 FASTSETTLING RW RESET RO 0x00 RW 0x0 DEFINITION Reserved. Always write zeroes to this bit field. Increases the output current for vag buffer by 2X to 20uA to improve the startup settling time. Startup settling time is roughly vag_cap*vag_value/current. Note that while this bit is located in the AUDIOOUT address space, since it controls both DAC and ADC functions, it is not reset by the AUDIOOUT's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. This must be low when VDDA is less than ~1.7V. When it is low the VAG and ADC reference voltages all drop by 1.4V/1.6V=0.875. Note that while this bit is located in the AUDIOOUT address space, since it controls both DAC and ADC functions, it is not reset by the AUDIOOUT's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. Switch the XTAL bias from self-bias to bandgap-based bias current. Also switches the source of the XTAL supply in series AA or LiIon to core supply to save power. Note that while this bit is located in the AUDIOOUT address space, since it controls both DAC and ADC functions, it is not reset by the AUDIOOUT's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. Reserved. Always write zeroes to this bit field. Small adjustment for VBG value. Will affect ALL reference voltages. Expected to be used to tweak final Li-Ion charge voltage. 000=Nominal. 001=+0.3%. 010=+0.6%. 011=0.85%. 100=-0.3%. 101=-0.6%. 110=-0.9%. 111=-1.2%. Note that while this bit is located in the AUDIOOUT address space, since it controls both DAC and ADC functions, it is not reset by the AUDIOOUT's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. 25 RAISE_REF RW 0x0 24 XTAL_BGR_BIAS RW 0x0 RSRVD3 23 22:20 VBG_ADJ RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice DAC_ADJ ADJ_VAG VAG_VAL LW_REF RSRVD4 RSRVD3 RSRVD2 RSRVD1 29-27 AUDIOOUT/DAC Table 29-19. HW_AUDIOOUT_REFCTRL Bit Field Descriptions BITS LABEL LOW_PWR 19 RW RESET RW 0x0 DEFINITION Lowers power (~100 uA) in the bandgap amplifier. This mode is useful in USB suspend or standby when bandgap accuracy is not critical. Note that while this bit is located in the AUDIOOUT address space, since it controls both DAC and ADC functions, it is not reset by the AUDIOOUT's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. This bit currently does not control any logic, altering it's value has no effect. It is reset by power-on reset, and CLKGATE has no effect on reads/writes. Bias current control for all analog blocks: 00=Nominal. 01=-20%. 10=-10%. 11=+10%. Note that while this bit is located in the AUDIOOUT address space, since it controls both DAC and ADC functions, it is not reset by the AUDIOOUT's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. These bits should only be used for test/debug, and not in an application. Reserved. Always write zeroes to this bit field. Shorts the supply of the XTAL oscillator to VDDD. This bit may be used to reduce power consumption, but should only be used on the advice of Freescale. Note that while this bit is located in the AUDIOOUT address space, it is an ADC function controlled by the AUDIOIN's SFTRST and CLKGATE bits. ADC Reference Voltage Adjust. When set the bias current in the ADC drop by 20% to save power. Note that while this bit is located in the AUDIOOUT address space, it is an ADC function controlled by the AUDIOIN's SFTRST and CLKGATE bits. When cleared, VAG is VDD/2 (resistor divider). When set, VAG is controlled by VAGVAL 7:4. Note that while this bit is located in the AUDIOOUT address space, since it controls both DAC and ADC functions, it is not reset by the AUDIOOUT SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. ADC Reference Value. These bits set the reference voltage for the ADC as a ratio of the VAG voltage. 0x0=1.75*VAG, 0x1=1.85*VAG, 0x2=1.97*VAG. Codes 0x3-0xF are invalid. Note that while this bit is located in the AUDIOOUT address space, it is an ADC function controlled by the AUDIOIN's SFTRST and CLKGATE bits. 18 LW_REF RW 0x0 17:16 BIAS_CTRL RW 0x0 15 14 RSRVD2 VDDXTAL_TO_VDDD RO 0x0 RW 0x0 13 ADJ_ADC RW 0x0 12 ADJ_VAG RW 0x0 11:8 ADC_REFVAL RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 29-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC Table 29-19. HW_AUDIOOUT_REFCTRL Bit Field Descriptions BITS LABEL 7:4 VAG_VAL RW RESET RW 0x0 DEFINITION VAG Reference Value (when ADJVAG set): MSB is NOT used for voltage control. 0x7=1.0 V, 0x0=0.825 V, 25-mV steps, also affected by RAISE_REF. If RAISE_REF=0, 0x7=0.875, 0x0=0.722 V. If the MSB is high the DAC reference buffer is bypassed which can improve SNR performance. See section on selecting the VAG level earlier in this chapter. Note that while this bit is located in the AUDIOOUT address space, since it controls both DAC and ADC functions, it is not reset by the AUDIOOUT's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. Reserved. Always write zeroes to this bit field. Adjusts the reference current (signal swing) in the DAC : 000=Nominal. 001=+0.25 dB. 010=+0.5 dB. 011=+0.75 dB. 100==-0.25 dB. 101=-0.5 dB. 110=-0.75 dB. 111=-6.0 dB. It is reset by a power-on reset only. 3 2:0 RSRVD1 DAC_ADJ RO 0x0 RW 0x0 DESCRIPTION: The AUDIOOUT Reference Control Register provides control over the voltage and power for the audio analog circuits. EXAMPLE: HW_AUDIOOUT_REFCTRL.ADJ_VAG = 1; 29.4.10 Miscellaneous Audio Controls Register Description This register provides miscellenous audio control bits. HW_AUDIOOUT_ANACTRL HW_AUDIOOUT_ANACTRL_SET HW_AUDIOOUT_ANACTRL_CLR HW_AUDIOOUT_ANACTRL_TOG 0x090 0x094 0x098 0x09C Table 29-20. HW_AUDIOOUT_ANACTRL 3 1 3 0 2 9 2 8 SHORT_CM_STS 2 7 2 6 2 5 2 4 SHORT_LR_STS 2 3 2 2 2 1 SHORTMODE_CM 2 0 1 9 1 8 SHORTMODE_LR 1 7 1 6 1 5 1 4 1 3 SHORT_LVLADJL 1 2 1 1 1 0 0 9 SHORT_LVLADJR 0 8 0 7 0 6 0 5 HP_HOLD_GND 0 4 HP_CLASSAB 0 3 0 2 0 1 0 0 RSRVD8 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD1 29-29 AUDIOOUT/DAC Table 29-21. HW_AUDIOOUT_ANACTRL Bit Field Descriptions BITS 31:29 RSRVD8 LABEL RW RESET RO 0x00 DEFINITION Reserved. Always write zeroes to this bit field. It is reset by a power-on reset only. Status of common mode amplifier short detection: 0=No short. To clear this interrupt and then rearm it: (1) Set HW_AUDIOOUT_ANACTRL_SHORTMODE_CM to 00. (2) Clear this bit. (3) Set HW_AUDIOOUT_ANACTRL_SHORTMODE_CM to 01. There are two sets of edge-triggered latches in this path. All three steps must be executed to rearm the short detect. Reserved. Always write zeroes to this bit field. Status of headphone amplifier short detection: 0=No short. To clear this interrupt and then rearm it: (1) Set HW_AUDIOOUT_ANACTRL_SHORTMODE_LR to 00. (2) Clear this bit. (3) Set HW_AUDIOOUT_ANACTRL_SHORTMODE_LR to 01. There are two sets of edge-triggered latches in this path. All three steps must be executed to rearm the short detect. Reserved. Always write zeroes to this bit field. Headphone Common Mode Amplifier Short Control Mode. 00=Reset analog latch, HW power down on unlatched short signal. 01=Latch short signal. HW power down on latched signal. 10=Do not use. 11=Do not use. Reserved. Always write zeroes to this bit field. Headphone Left and Right Channel Short Control mode. 00=Reset analog latch, HW power-down disabled. 01=Latch short signal, HW power-down enabled. 10=Do not use. 11=Do not use. Reserved. Always write zeroes to this bit field. Adjust the left headphone current short detect trip point: 000=Nominal. 001=-25%. 010=-50%. 011=-75%. 100=+25%. 101=+50%. 110=+75%. 111=+100%. It is reset by a power-on reset only. Reserved. Always write zeroes to this bit field. Adjust the right headphone current short detect trip point: 000=Nominal. 001=-25%. 010=-50%. 011=-75%. 100=+25%. 101=+50%. 110=+75%. 111=+100%. It is reset by a power-on reset only. Reserved. Always write zeroes to this bit field. Hold Headphone Output to Ground (used for power-up/power-down procedures). It is reset by a power-on reset only. Default is 0 (ClassA mode). ClassA mode can be useful for power-up/power-down and short handling. This bit should be set (ClassAB mode) before starting audio signal. It is reset by a power-on reset only. Reserved. Always write zeroes to this bit field. 28 SHORT_CM_STS RW 0x0 27:25 RSRVD7 24 SHORT_LR_STS RO 0x0 RW 0x0 23:22 RSRVD6 21:20 SHORTMODE_CM RO 0x0 RW 0x0 RSRVD5 19 18:17 SHORTMODE_LR RO 0x00 RW 0x0 16:15 RSRVD4 14:12 SHORT_LVLADJL RO 0x0 RW 0x0 11 10:8 RSRVD3 SHORT_LVLADJR RO 0x0 RW 0x0 7:6 5 RSRVD2 HP_HOLD_GND RO 0x0 RW 0x0 4 HP_CLASSAB RW 0x0 3:0 RSRVD1 RO 0x0 DESCRIPTION: This register provides miscellaneous audio control bits. i.MX23 Applications Processor Reference Manual, Rev. 1 29-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC EXAMPLE: HW_AUDIOOUT_ANACTRL.EN_ZCD = 1; // Enable zero cross detect. 29.4.11 Miscellaneous Test Audio Controls Register Description This register provides miscellaneous audio test bits. HW_AUDIOOUT_TEST HW_AUDIOOUT_TEST_SET HW_AUDIOOUT_TEST_CLR HW_AUDIOOUT_TEST_TOG Table 29-22. HW_AUDIOOUT_TEST 3 1 3 0 2 9 HP_ANTIPOP 0x0a0 0x0a4 0x0a8 0x0aC 2 8 2 7 2 6 TM_ADCIN_TOHP 2 5 2 4 TM_HPCOMMON 2 3 2 2 2 1 HP_IALL_ADJ 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 VAG_CLASSA 1 2 VAG_DOUBLE_I 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 ADCTODAC_LOOP 0 2 DAC_CLASSA 0 1 DAC_DOUBLE_I 0 0 DAC_DIS_RTZ HP_I1_ADJ TM_LOOP RSRVD2 RSRVD4 RSRVD3 Table 29-23. HW_AUDIOOUT_TEST Bit Field Descriptions BITS 31 30:28 27 26 LABEL RSRVD4 HP_ANTIPOP RSRVD3 TM_ADCIN_TOHP RW RO RW RO RW RESET 0x0 0x0 0x0 0x0 DEFINITION Reserved. Always write zeroes to this bit field. Reserved Reserved. Always write zeroes to this bit field. Testmode to pipe ADC Mux Out (ADC In) to Headphone Output pins. No longer have ADC filter pins, this allows visibility to ADC Mux amp performance. To use this mode, the headphone load and the headphone board compensation must be removed (the ADC amp cannot drive it). Note that while this bit is located in the AUDIOOUT address space, it is an ADC function controlled by the AUDIOIN's SFTRST and CLKGATE bits. Testmode to connect headphone out left to the microphone input to the ADC, and speakerp to the ADC. This is used for analog loopback DAC-speaker-Mix-ADC Mode. There should be no load on the microphone input pin during this mode. Uses headphone common VAG, instead of vaggate in ADC Mux. This is used for analog loopback DAC-HP-ADC mode to include common amp in path. Adjusts bias current in first stage of headphone amplifier : 00=Nominal. 01=-50%. 10=+100%. 11=+50%. It is reset by a power-on reset only. Adjusts all bias current in headphone amplifier : 00=nom, 01=-50%, 10=+50%, 11=-40%. It is reset by a power-on reset only. Reserved. Always write zeroes to this bit field. 25 TM_LOOP RW 0x0 24 TM_HPCOMMON RW 0x0 23:22 HP_I1_ADJ RW 0x0 21:20 HP_IALL_ADJ RW 0x0 19:14 RSRVD2 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD1 29-31 AUDIOOUT/DAC Table 29-23. HW_AUDIOOUT_TEST Bit Field Descriptions BITS LABEL 13 VAG_CLASSA RW RESET RW 0x0 DEFINITION Set to one to disable ClassAB mode in VAG Amp. Will increase current by ~200 uA. Note that while this bit is located in the AUDIOOUT address space, since it controls both DAC and ADC functions, it is not reset by the AUDIOOUT's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. Set to one to double ClassA current in VAG amplifier (+240uA). Note that while this bit is located in the AUDIOOUT address space, since it controls both DAC and ADC functions, it is not reset by the AUDIOOUT's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. Reserved. Always write zeroes to this bit field. Set to one to loop the 1-bit SDM ADC data in to the 1-bit SDM DAC data out for test. Set to one to disable ClassAB mode in DAC. Will increase power by ~600 uA. Set to one to double ClassA current in DAC amplifier (+360 uA in each DAC). Set to one to disable DAC RTZ mode. Test-only bit that disables the return-to-zero function. This bit should remain cleared. 12 VAG_DOUBLE_I RW 0x0 11:4 3 2 1 0 RSRVD1 ADCTODAC_LOOP DAC_CLASSA DAC_DOUBLE_I DAC_DIS_RTZ RO 0x00 RW 0x0 RW 0x0 RW 0x0 RW 0x0 DESCRIPTION: This register provides miscellaneous audio test bits.. EXAMPLE: HW_AUDIOOUT_TEST.TM_HPCOMMON = 1; // Use headphone common VAG. 29.4.12 BIST Control and Status Register Description The BIST Control and Status Register provides overall control of the integrated BIST engine. HW_AUDIOOUT_BISTCTRL HW_AUDIOOUT_BISTCTRL_SET HW_AUDIOOUT_BISTCTRL_CLR HW_AUDIOOUT_BISTCTRL_TOG 0x0b0 0x0b4 0x0b8 0x0bC Table 29-24. HW_AUDIOOUT_BISTCTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSVD0 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 FAIL 0 2 PASS 0 1 DONE 0 0 START i.MX23 Applications Processor Reference Manual, Rev. 1 29-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC Table 29-25. HW_AUDIOOUT_BISTCTRL Bit Field Descriptions BITS 31:4 3 2 1 0 LABEL RSVD0 FAIL PASS DONE START RW RO RO RO RO RW RESET 0x0 0x0 0x0 0x0 0x0 DEFINITION Reserved BIST has failed. BIST has passed BIST has completed. Initiate BIST of internal memory. DESCRIPTION: The BISTCTRL Register provides overall control of the integrated BIST engine. EXAMPLE: HW_AUDIOUT_BISTCTRL.U = 0x00000000; 29.4.13 Hardware BIST Status 0 Register Description This register provides visibility into memory failures detected by the BIST engine. HW_AUDIOOUT_BISTSTAT0 HW_AUDIOOUT_BISTSTAT0_SET HW_AUDIOOUT_BISTSTAT0_CLR HW_AUDIOOUT_BISTSTAT0_TOG 0x0c0 0x0c4 0x0c8 0x0cC Table 29-26. HW_AUDIOOUT_BISTSTAT0 3 1 3 0 2 9 2 8 RSVD0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 DATA 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 29-27. HW_AUDIOOUT_BISTSTAT0 Bit Field Descriptions BITS 31:24 RSVD0 23:0 DATA LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Reserved Failing data at the failing address. DESCRIPTION: The AUDIOOUT BISTSTAT0 provides visibility into memory failures detected by the BIST engine. EXAMPLE: HW_AUDIOUT_BISTSTAT0.U = 0x00000000; 29.4.14 Hardware AUDIOUT BIST Status 1 Register Description The AUDIOOUT BISTATTS1 provides visibility into memory failures detected by the BIST engine. HW_AUDIOOUT_BISTSTAT1 HW_AUDIOOUT_BISTSTAT1_SET HW_AUDIOOUT_BISTSTAT1_CLR HW_AUDIOOUT_BISTSTAT1_TOG 0x0d0 0x0d4 0x0d8 0x0dC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-33 AUDIOOUT/DAC Table 29-28. HW_AUDIOOUT_BISTSTAT1 3 1 3 0 RSVD1 2 9 2 8 2 7 2 6 STATE 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 RSVD0 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 ADDR 0 3 0 2 0 1 0 0 Table 29-29. HW_AUDIOOUT_BISTSTAT1 Bit Field Descriptions BITS 31:29 28:24 23:8 7:0 LABEL RSVD1 STATE RSVD0 ADDR RW RO RO RO RO RESET 0x0 0x0 0x0 0x0 DEFINITION Reserved Fail state of the BIST engine. Failing data at the failing address. Failing data at the failing address. DESCRIPTION: The AUDIOOUT BISTATTS1 provides visibility into memory failures detected by the BIST engine. EXAMPLE: HW_AUDIOUT_BISTATTS1.U = 0x00000000; 29.4.15 Analog Clock Control Register Description This register provides analog clock control. HW_AUDIOOUT_ANACLKCTRL HW_AUDIOOUT_ANACLKCTRL_SET HW_AUDIOOUT_ANACLKCTRL_CLR HW_AUDIOOUT_ANACLKCTRL_TOG 0x0e0 0x0e4 0x0e8 0x0eC Table 29-30. HW_AUDIOOUT_ANACLKCTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 INVERT_DACCLK 0 3 0 2 0 1 0 0 CLKGATE RSRVD3 RSRVD2 Table 29-31. HW_AUDIOOUT_ANACLKCTRL Bit Field Descriptions BITS LABEL 31 CLKGATE RW RESET RW 0x1 DEFINITION Analog clock Gate. Set this bit to gate the clocks for the DAC converter and associated digital filter. It is reset by a power-on reset only. Reserved 30:5 RSRVD3 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 29-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor DACDIV AUDIOOUT/DAC Table 29-31. HW_AUDIOOUT_ANACLKCTRL Bit Field Descriptions BITS LABEL 4 INVERT_DACCLK RW RESET RW 0x0 DEFINITION DAC Clock Invert. Set this bit to invert the DAC_CLK for the DAC sigma-delta converter and associated digital filters. Reserved DAC Analog Clock Divider. This bit field is used to select the oversampling clock rate used by the ADC. This bit field should only be changed per Freescale. 000=6 MHz. 001=4 MHz. 010/100=3 MHz. 011/101=2 MHz. 110=1.5 MHz. 111=1 MHz. 3 2:0 RSRVD2 DACDIV RO 0x0 RW 0x0 DESCRIPTION: This register provides analog clock control. EXAMPLE: HW_AUDIOOUT_ANACLKCTRL.INVERT_DACCLK = 1; // Invert DAC clock. 29.4.16 AUDIOOUT Write Data Register Description The AUDIOOUT Write Data Register provides a means to output PCM audio samples. HW_AUDIOOUT_DATA HW_AUDIOOUT_DATA_SET HW_AUDIOOUT_DATA_CLR HW_AUDIOOUT_DATA_TOG Table 29-32. HW_AUDIOOUT_DATA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 HIGH 0x0f0 0x0f4 0x0f8 0x0fC 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 LOW 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 29-33. HW_AUDIOOUT_DATA Bit Field Descriptions BITS 31:16 HIGH LABEL RW RESET RW 0x0000 DEFINITION Right Sample or Sample High Half-Word. For 16-bit sample mode, this field contains the right channel sample. For 32-bit sample mode, this field contains the most significant 16 bits of the 32-bit sample (either left or right). Left Sample or Sample Low Half-Word. For 16-bit sample mode, this field contains the left channel sample. For 32-bit per sample mode, this field contains the least significant 16 bits of the 32-bit sample (either left or right). 15:0 LOW RW 0x0000 DESCRIPTION: The AUDIOOUT Write Data Register provides 32-bit data transfers for the DMA or alternatively can be directly written by the CPU. Each data value written to the register is placed in the AUDIOOUT's FIFO, i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-35 AUDIOOUT/DAC which in turn is used by the digital FIR filter stages. These 32-bit values contain either one 32-bit sample or two 16-bit samples, depending on how the data size is programmed. Note that the PCM audio data input to the FIR filter stages is 24 bit. For 16-bit operation, the input data is sign extended to 24 bits. For 32-bit mode, it is normalized by dropping the least significant 8 bits. EXAMPLE: HW_AUDIOOUT_DATA.U = 0x12345678; // write 0x1234 to the right channel and 0x5678 to the left channel in 16 bit per sample mode HW_AUDIOOUT_DATA.U = 0x12345678; // write 0x12345678 to either the left or right channel in 32 bit per sample mode. 29.4.17 AUDIOOUT Speaker Control Register Description The AUDIOOUT Speaker Control Register contains bit-fields to control the Speaker analog block. HW_AUDIOOUT_SPEAKERCTRL HW_AUDIOOUT_SPEAKERCTRL_SET HW_AUDIOOUT_SPEAKERCTRL_CLR HW_AUDIOOUT_SPEAKERCTRL_TOG 0x100 0x104 0x108 0x10C Table 29-34. HW_AUDIOOUT_SPEAKERCTRL 3 1 3 0 2 9 2 8 RSRVD2 2 7 2 6 2 5 2 4 MUTE 2 3 I1_ADJ 2 2 2 1 IALL_ADJ 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 POSDRIVER 1 4 1 3 NEGDRIVER 1 2 1 1 1 0 0 9 0 8 0 7 0 6 RSRVD0 0 5 0 4 0 3 0 2 0 1 0 0 Table 29-35. HW_AUDIOOUT_SPEAKERCTRL Bit Field Descriptions BITS 31:25 RSRVD2 24 MUTE LABEL RW RESET RO 0x00 RW 0x1 DEFINITION Reserved This bit mutes the speaker outputs, SPEAKERP and SPEAKERN. The speaker antipop startup/shutdown sequence should be followed before toggling this bit. Adjusts bias current in first stage of speaker amplifier : 00=Nominal. 01=-50%. 10=+100%. 11=+50%. It is reset by a power-on reset only. Adjusts all bias current in speaker amplifier : 00=Nominal, 01=-50%, 10=+50%, 11=-40%. It is reset by a power-on reset only. Reserved SPEAKERP pin control: 00=Normal speaker mode, 01=Drive SPEAKERP low, 10=Drive SPEAKERP high, 11=Tri-state SPEAKERP. It is reset by a power-on reset only. SPEAKERN pin control: 00=Normal speaker mode, 01=Drive SPEAKERN low, 10=Drive SPEAKERN high, 11=Tri-state SPEAKERN. It is reset by a power-on reset only. Reserved 23:22 I1_ADJ RW 0x0 21:20 IALL_ADJ RW 0x0 19:16 RSRVD1 15:14 POSDRIVER RO 0x0000 RW 0x0 13:12 NEGDRIVER RW 0x0 11:0 RSRVD0 RO 0x000 i.MX23 Applications Processor Reference Manual, Rev. 1 29-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor AUDIOOUT/DAC DESCRIPTION: The AUDIOOUT Speaker Control Register controls the analog speaker module. It provides programmability for the amplifier bia current and a mute. EXAMPLE: HW_AUDIOOUT_MUTE= 0x1; // mute line out channel 29.4.18 AUDIOOUT Version Register Description The AUDIOOUT Version Register is read-only and is used for debug to determine the implementation version number for the block. HW_AUDIOOUT_VERSION 0x200 Table 29-36. HW_AUDIOOUT_VERSION 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 29-37. HW_AUDIOOUT_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x01 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x01 RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_AUDIOOUT_VERSION.B.MAJOR != 1) Error(); AUDIOOUT Block v1.3, Revision 1.65 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29-37 AUDIOOUT/DAC i.MX23 Applications Processor Reference Manual, Rev. 1 29-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 30 SPDIF Transmitter This chapter describes the SPDIF transmitter provided on the i.MX23. It includes sections on interrupts, clocking, DMA operation, and PIO debug mode. Programmable registers are described in Section 30.3, "Programmable Registers." 30.1 Overview The Sony-Philips Digital Interface Format (SPDIF) transmitter module transmits data according to the SPDIF digital audio interface standard (IEC-60958). Figure 30-1 shows a block diagram of the SPDIF transmitter module. Data samples are transmitted as blocks of 192 frames, each frame consisting of two 32-bit sub-frames. A 32-bit sub-frame is composed of a 4-bit preamble, a 24-bit data payload (e.g., a left- or right-channel PCM sample), and a 4-bit status field. The status fields are encoded according to the IEC-60958 consumer specification, reflecting the contents of the HW_SPDIF_FRAMECTRL and HW_SPDIF_CTRL registers. See the IEC-60958 specification for proper programming of these fields. The sub-frame is transmitted serially, LSB-first, using a biphase-mark channel-coding scheme. This encoding allows an SPDIF receiver to recover the embedded clock signal. NOTE: Sub-frame information can be changed "on-the-fly" but is not reflected in the serial stream until the current frame is transmitted. This ensures consistency of the frame and the generated parity appended to that frame. 30.2 Operation The SPDIF transmitter operates at one of three register-selectable base sample rates: 32 kHz, 44.1 kHz, or 48 kHz. Double-rate output (64 kHz, 88.2 kHz, and 96 kHz) can also be selected using HW_SPDIF_SRR_BASEMULT. The data-clock required to transmit an SPDIF frame at these sample-rates is generated using a fractional clock-divider. This divider uses both edges of a 120-MHz clock, which is derived from a divide-by-4 of the PLL 480-MHz clock. This divider is located in the CLKCTRL module where all system clocks are generated; the resultant clock (pcm_spdif_clk) is output to the SPDIF module to be used for data transmission. Programming the HW_SPDIF_SRR register automatically generates the right frequency of pcm_spdif_clk from the divider in the clock controller block. There are no separate registers to control these dividers. Make sure that the CLKGATE bit in HW_CLKCTRL_SPDIF is cleared before starting the transmission. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 30-1 SPDIF Transmitter The SPDIF module receives data by one of two methods: * * Software-directed PIO writes to the HW_SPDIF_DATA register Appropriate programming of the DMA-engine. (See Chapter 11, "AHB-to-APBX Bridge with DMA," for a detailed description of the DMA module and how to perform DMA data transfers to/from modules and memory.) Once provided by the DMA, the received data is placed in a 2x24 word FIFO for each channel, left and right. At initialization, the FIFO is filled before SPDIF data transfer occurs. After this, data is requested whenever this FIFO has an empty entry or at a nominal rate corresponding to the programmed sample-rate in HW_SPDIF_SRR. ARM Core SRAM 24-MHz XTAL Osc. AHB AHB Slave AHB Master Divide by n CLKCTRL Module PLL 480 MHz Divide by 4 Shared DMA Dual-Edge Fractional Clock Divider Divide Ratio ROM Clock Divider AHB-to-APBX Bridge APBX Master APBX pcm_spdif_clk SPDIF Data Encoding SPDIF Programmable Registers DMA Data Flow Control DMA Request Engine HW_SPDIF_SRR HW_SPDIF_SRR_RATE HW_SPDIF_FRAMECTRL HW_SPDIF_CTRL SPDIF Stream Control 2x24 Left-Channel FIFO 2x24 Right-Channel FIFO FIFO Control and Request Generation Clock Crossing Data Formatting (16-Bit/24-Bit) SPDIF Data APBX Clock Domain pcm_spdif_clk Domain Figure 30-1. SPDIF Transmitter Block Diagram i.MX23 Applications Processor Reference Manual, Rev. 1 30-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor SPDIF Transmitter The behavior of the SPDIF module during or after a FIFO underflow is programmable. On detection of an underflow event, the SPDIF module sends the current sample for four frames before muting (sending zeros) the data stream based on the configuration of HW_SPDIF_FRAMECTRL_AUTO_MUTE. The final validity unit embedded within each frame dictates whether the receiver processes the data within that frame. HW_SPDIF_FRAMECTRL determines the behavior of this bit. SPDIF Normal Operation 0 1 HW_SPDIF_ FRAMECTRL_V Underflow asserted after 4-frames consecutive frames w/empty FIFO 0 HW_SPDIF_CTRL_FIFO _UNDERFLOW_IRQ 1 HW_SPDIF_FRAMECTRL_AUTO_MUTE HW_SPDIF_DATA = 0 HW_SPDIF_DATA = LAST_VALUE HW_SPDIF_FRAMECTRL_V_CONFIG 0 Final Validity=0 Final Validity=0 1 Final Validity=1 Final Validity=1 Figure 30-2. SPDIF Flow Chart SPDIF data can be transmitted in one of two modes: 32-bit mode and 16-bit mode. Selection between these modes is done with the WORD_LENGTH bit in the HW_SPDIF_CTR register. In either case, data samples must be interleaved in main memory for proper behavior, although in 32-bit mode, 32-bit words are interleaved and in 16-bit mode, 16-bit words are interleaved. * When WORD_LENGTH = 0, 32-bit mode is enabled, and HW_SPDIF_DATA contains either the left or right data sample. Since the SPDIF frame allows for transmission of only 24 bits, only the 24 MSBs stored in the HW_SPDIF_DATA register will be transmitted. Alternately, when WORD_LENGTH = 1, 16-bit mode is enabled, and the HW_SPDIF_DATA register will contain one of each left AND right samples. The data transmitted in the SPDIF frame will be these 16 MSBs with 8 zeros appended in the LSB positions. i.MX23 Applications Processor Reference Manual, Rev. 1 * Freescale Semiconductor Preliminary--Subject to Change Without Notice 30-3 SPDIF Transmitter NOTE: If the data supplied actually represents a lower resolution analog-to-digital conversion, this information is not captured by the SPDIF transmitter, which always reports a 24-bit sample-size. 30.2.1 Interrupts The SPDIF module contains a single interrupt source that is asserted on FIFO overflows and/or FIFO underflows. This interrupt is enabled by setting HW_SPDIF_CTRL_FIFO_ERROR_IRQ_EN. On interrupt detection, the HW_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ and HW_SPDIF_CTRL_FIFO_OVERFLOW_IRQ fields can be polled for the exact cause of the interrupt and appropriate action taken. Note: These bits remain valid for polling, regardless of the state of the interrupt enable. 30.2.2 Clocking The IEC-60958 specification outlines the requirements for SPDIF clocking. The SPDIF module is designed according to the Consumer Audio requirements. These dictate that: * * Average Sample-Rate Error must not exceed 1000 ppm Maximum Instantaneous Jitter must not exceed ~4.4 ns. The jitter requirement implies either a single-phase of a >240-MHz clock or both phases of a 120-MHz clock. It also implies the use of a fractional divider for which the divisors are maintained to sufficient significant digits to yield the required ppm tolerance. The SPDIF module in the i.MX23 uses nine-bit fractional coefficients that yield an average frequency error of 52 ppm. These coefficients are determined according to the required clock-rates that are dictated by the sample rates implemented. The required clock frequencies provided by the CLKCTRL module for the implemented sample-rates are: F(48 kHz) 6.144 MHz F(44.1 kHz) 5.6448 MHz F(32 kHz) F(96 kHz) 4.096 MHz 12.288 MHz F(88.2 kHz) 11.2896 MHz F(64 kHz) 8.192 MHz All clocks within the SPDIF module are gated according to the state of HW_SPDIF_CTRL_CLKGATE. When set, all clocks derived from the apb_clk are gated. Gating of the pcm_spdif_clk is accomplished through HW_CLKCTRL_SPDIF_CLKGATE. A module-level reset is also provided in HW_SPDIF_CTRL_SFTRST. Setting this bit performs a module-wide reset and subsequent assertion of the HW_SPDIF_CTRL_CLKGATE. i.MX23 Applications Processor Reference Manual, Rev. 1 30-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor SPDIF Transmitter NOTE: A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. 30.2.3 DMA Operation Using the SPDIF module in DMA mode involves configuring the appropriate DMA channel to provide the interleaved data blocks stored in memory. See Chapter 11, "AHB-to-APBX Bridge with DMA," for detailed information on DMA programming. Once programmed, the DMA engine references a set of linked DMA descriptors stored by the CPU in main memory. These descriptors point to data blocks stored in system memory and also provide a mechanism for automated PIO writes before transfer of a data-block. Figure 30-3 describes a typical set of descriptors required to transmit two data-blocks. NEXTCMD_ADDR 512 2 0 0 1 10 BUFFER ADDRESS HW_SPDIF_CTRL=0x00000001 HW_SPDIF_FRAMECTRL= 0x00030000 NEXTCMD_ADDR 512 2 0 0 1 10 BUFFER ADDRESS HW_SPDIF_CTRL=0x00000001 read HW_SPDIF_FRAMECTRL= 0x00030000 512-Byte Data Block 0 read NEXTCMD_ADDR 0 1 0 0 1 10 BUFFER ADDRESS HW_SPDIF_CTRL=0xC0000000 512-Byte Data Block 1 Figure 30-3. SPDIF DMA Two-Block Transmit Example Here, the DMA is instructed to perform two PIO writes prior to toggling the DMA_PCMDKICK signal: * * HW_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ_EN is set to enable interrupts on FIFO underflow detect HW_SPDIF_FRAMECTRL_AUTO_MUTE and HW_SPDIF_FRAMECTRL_V_CONFIG are set to mute and tag the data stream as invalid on a FIFO underflow. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 30-5 SPDIF Transmitter The DMA engine is then programmed to transfer 512-bytes to the SPDIF module. Additionally, the SPDIF module contains a mechanism for "throttling" DMA requests to the DMA engine. This circuit is programmed using the HW_SPDIF_CTRL_DMAWAIT_COUNT field and corresponds to the number of cycles of the apb_clk to wait before toggling the DMA_PREQ signal to the DMA engine. NOTE: Considering that the bandwidth requirements of the SPDIF module are minimal (not in excess of 96 kHz) and burst requests occur only in pairs, this field can be ignored for most, if not all, applications. There is a floor APBX frequency below which the SPDIF cannot work without errors. That frequency can be calculated as follows: * Assume that there are 6 other blocks apart from SPDIF on the APBX bus, and it takes 4 APBX clock cycles to service each block. If the number of clock cycles required to service each block changes, change the equations accordingly. Assume that HW_SPDIF_CTRL_DMAWAIT_COUNT is less than DMA LATENCY. If this is not true, then even DMA WAIT has to be added to the calculation and the floor APBX frequency increases further. Floor APBX freq = (DMA latency + 9) * sample rate. For max DMA latency = (6 blocks) x (4 cycles per block) = 24 cycles and max SPDIF sample rate = 96 kHz, min APBX freq = 3.168 MHz. * In 16-bit Mode: In 32-bit Mode: (A) Ideal Calculation: min freq = [2*(DMA latency+4) + 7] * sample rate. For max DMA latency = 24 cycles and max SPDIF sample rate = 96 kHz, min APBX freq = 6.048 MHz. (B) Simpler Calculation: Floor APBX freq = 2*(latency + 9) * sample rate = twice that of 16-bit mode. For max latency = 24 cycles and max sample rate = 96 kHz, min APBX freq = 6.336 MHz. Option A is ideal as it allows a lower floor frequency; option B can be used to keep it simple and avoid confusion. 30.2.4 PIO Debug Mode The block is connected only as a PIO device to the APBX bus. Even though it is designed to work with the DMA controller integrated in the APBX bridge, all transfers to and from the block are programmed I/O (PIO) read or write cycles. When the DMA is ready to write to the HW_SPDIF_DATA register, it does so with standard APB write cycles. There are four DMA related signals that connect the SPDIF transmitter to the DMA, but all data transfers are standard PIO cycles on the APB. The state of these four signals can be seen in the HW_SPDIF_DEBUG register. i.MX23 Applications Processor Reference Manual, Rev. 1 30-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor SPDIF Transmitter Thus, it is possible to completely exercise the SPDIF block for diagnostic purposes, using only load and store instructions from the CPU without ever starting the DMA controller. This section describes how to interact with the block using PIO operations, and also defines the block's detailed behavior. Whenever the HW_SPDIF_CTRL register is written to, by either the CPU or the DMA, it establishes the basic operation mode for the block. If the HW_SPDIF_CTRL register is written with a 1 in the RUN bit, then the operation begins and the SPDIF attempts to read the data block by toggling its PDMAREQ signal to the DMA. Notice that the PDMAREQ signal is defined as a "toggle" signal. This changes state to signify either a request for another DMA word or a notification that the current command transfer has been ended by the SPDIF. Diagnostic software should poll these signals to determine when the SPDIF is ready for another DMA write, and can then supply data by storing a 32-bit word to the HW_SPDIF_DATA register, just as the DMA would do in normal operation. To perform SPDIF transfers in PIO debug mode, diagnostic software should perform the following: 1. Clear CLKGATE in the HW_CLKCTRL_SPDIF register. 2. Turn off the Soft Reset bit, HW_SPDIF_CTRL_SFTRST, and the Clock Gate bit, HW_SPDIF_CTRL_CLKGATE. 3. Properly configure the subcode information by writing the HW_SPDIF_FRAMECTRL register. NOTE: See IEC-60958 for proper coding of these fields. 4. Enable the SPDIF transmitter by setting HW_SPDIF_CTRL_RUN. 5. Wait for HW_SPDIF_DEBUG_DMA_PREQ status bit to toggle. 6. Write one sample of the left/right DATA block data to the HW_SPDIF_DATA register. 7. Repeat 5 and 6 until all samples have been written to HW_SPDIF_DATA. 30.3 Programmable Registers The following registers provide control for programmable elements of the SPDIF module. 30.3.1 SPDIF Control Register Description HW_SPDIF_CTRL HW_SPDIF_CTRL_SET HW_SPDIF_CTRL_CLR HW_SPDIF_CTRL_TOG 0x000 0x004 0x008 0x00C The SPDIF Control Register provides overall control of the SPDIF converter. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 30-7 SPDIF Transmitter Table 30-1. HW_SPDIF_CTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 DMAWAIT_COUNT 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 WAIT_END_XFER 0 4 0 3 FIFO_UNDERFLOW_IRQ 0 2 FIFO_OVERFLOW_IRQ 0 1 FIFO_ERROR_IRQ_EN 0 0 WORD_LENGTH CLKGATE RSRVD1 RSRVD0 SFTRST Table 30-2. HW_SPDIF_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Setting this bit to one forces a reset to the entire block and then gates the clocks off. This bit must be set to zero for normal operation. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. WARNING: First set the CLKGATE bit in the HW_CLKCTRL_SPDIF register to 1. Only then, set this bit to 1 to prevent any extra samples from being transmitted. When removing clock gating, follow the reverse order: First reset this CLKGATE bit to 0, and then reset the CLKGATE bit in the HW_CLKCTRL_SPDIF register to 0 . Reserved DMA Request Delay Count. This bit field specifies the number of APBX clock cycles (0 to 31) to delay before each DMA request. This field acts as a throttle on the bandwidth consumed by the SPDIF block. This field can be loaded by the DMA. Reserved Set this bit to a one if the SPDIF Transmitter should wait until the internal FIFO is empty before halting transmission based on deassertion of RUN. Use in conjuntion with HW_SPDIF_STAT_END_XFER to determine transfer completion Set this bit to one to enable 16-bit mode. Set this bit to zero for 32-bit mode. In either case, the SPDIF frame allows transmission of only 24 bits. In 16-bit mode, eight zeros will be appended to the LSB's of the input sample; in 32-bit mode, the 24 MSB's of HW_SPDIF_DATA will be transmitted. This bit is set by hardware if the FIFO underflows during SPDIF transmission. Reset this bit by writing a one to the SCT clear address space and not by a general write. 30 CLKGATE RW 0x1 29:21 RSRVD1 20:16 DMAWAIT_COUNT RO 0x00 RW 0x00 15:6 5 RSRVD0 WAIT_END_XFER RO 0x000 RW 0x1 4 WORD_LENGTH RW 0x0 3 FIFO_UNDERFLOW_IRQ RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 30-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor RUN SPDIF Transmitter Table 30-2. HW_SPDIF_CTRL Bit Field Descriptions BITS LABEL 2 FIFO_OVERFLOW_IRQ RW RESET RW 0x0 DEFINITION This bit is set by hardware if the FIFO overflows during SPDIF transmission. Reset this bit by writing a one to the SCT clear address space and not by a general write. Set this bit to one to enable a SPDIF interrupt request on FIFO overflow or underflow status conditions. Setting this bit to one causes the SPDIF to begin converting data. The actual conversion will begin when the SPDIF FIFO is filled (4 or 8 words written, depending upon sample word format, i.e., 16 or 32 bits). 1 0 FIFO_ERROR_IRQ_EN RUN RW 0x0 RW 0x0 DESCRIPTION: The SPDIF Control Register contains the overall control for SPDIF sample formats, loopback mode, and interrupt controls. EXAMPLE: HW_SPDIF_CTRL.RUN = 1; // start SPDIF conversion 30.3.2 SPDIF Status Register Description HW_SPDIF_STAT HW_SPDIF_STAT_SET HW_SPDIF_STAT_CLR HW_SPDIF_STAT_TOG Table 30-3. HW_SPDIF_STAT The SPDIF Status Register reflects overall status of the SPDIF converter. 0x010 0x014 0x018 0x01C 3 1 PRESENT 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 RSRVD1 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 END_XFER Table 30-4. HW_SPDIF_STAT Bit Field Descriptions BITS LABEL 31 PRESENT RW RESET RO 0x1 DEFINITION This bit is set to 1 in products in which SPDIF is present. Reserved When set, indicates that the SPDIF module has completed transfer of all data, including data stored in internal FIFOs. Used in conjunction with HW_SPDIF_CTRL_WAIT_END_XFER. 30:1 0 RSRVD1 END_XFER RO 0x0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 30-9 SPDIF Transmitter DESCRIPTION: The SPDIF Status Register provides the status of the SPDIF converter. EXAMPLE: unsigned TestBit = HW_SPDIF_STAT.PRESENT; 30.3.3 SPDIF Frame Control Register Description The SPDIF Frame Control Register provides direct control of the control bits transmitted over an SPDIF frame. HW_SPDIF_FRAMECTRL HW_SPDIF_FRAMECTRL_SET HW_SPDIF_FRAMECTRL_CLR HW_SPDIF_FRAMECTRL_TOG Table 30-5. HW_SPDIF_FRAMECTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 RSRVD2 0x020 0x024 0x028 0x02C 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 V_CONFIG 1 6 AUTO_MUTE 1 5 RSRVD1 1 4 USER_DATA 1 3 1 2 1 1 RSRVD0 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 AUDIO 0 0 COPY Table 30-6. HW_SPDIF_FRAMECTRL Bit Field Descriptions BITS LABEL 31:18 RSRVD2 17 V_CONFIG RW RESET RO 0x0 RW 0x1 DEFINITION Reserved Defines SPDIF behavior when sending invalid frames. 0:Do NOT tag frame as invalid. 1: Tag frame as invalid. Auto-Mute Stream on stream-suspend detect. Reserved User data transmitted during each sub-frame. Consult IEC Standard for additional details. Indicates that a sub-frame's samples are invalid. If V=0, the sub-frame is indicated as valid, that is, correctly transmitted and received by the interface. If V=1, the subframe is indicated as invalid. Generation level is defined by the IEC standard, or as appropriate. Reserved Category code is defined by the IEC standard, or as appropriate. 0: No Pre-Emphasis. 1: Pre-Emphasis is 50/15 usec. 0: Copyright bit NOT asserted. 1: Copyright bit asserted. AUDIO=0:PCM Data;1. AUDIO=Non-PCM Data 0: Consumer use of the channel. 1: Professional use of the channel. 16 15 14 13 AUTO_MUTE RSRVD1 USER_DATA V RW 0x0 RO 0x0 RW 0x0 RW 0x0 12 11 10:4 3 2 1 0 L RSRVD0 CC PRE COPY AUDIO PRO RW 0x0 RO 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 30-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor PRO PRE CC V L SPDIF Transmitter DESCRIPTION: The SPDIF Frame Control Register provides direct control of the control bits transmitted over an SPDIF frame. EXAMPLE: HW_SPDIF_FRAMECTRL.COPY=1 //SPDIF frame contains copyrighted material 30.3.4 SPDIF Sample Rate Register Description The SPDIF Sample Rate Register controls the sample rate of the data stream played back from the circular buffer. HW_SPDIF_SRR HW_SPDIF_SRR_SET HW_SPDIF_SRR_CLR HW_SPDIF_SRR_TOG Table 30-7. HW_SPDIF_SRR 3 1 RSRVD1 0x030 0x034 0x038 0x03C 3 0 2 9 BASEMULT 2 8 2 7 2 6 2 5 2 4 RSRVD0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 RATE 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 30-8. HW_SPDIF_SRR Bit Field Descriptions BITS LABEL 31 RSRVD1 30:28 BASEMULT RW RESET RO 0x0 RW 0x1 DEFINITION Reserved Base-Rate Multiplier. 1 = Single-Rate (48 kHz). 2 = Double-Rate (96 kHz). Reserved Sample-Rate Conversion Factor. The only valid entries are: 0x07D00, 0x0AC44, 0x0BB80 // 32k, 44.1k, 48k 27:20 RSRVD0 19:0 RATE RO 0x0 RW 0x00000 DESCRIPTION: The SPDIF Sample Rate Register provides a RATE field for specifying the sample rate conversion factor to use in outputting the current SPDIF stream. EXAMPLE: HW_SPDIF_SRR.B.RATE = 0x0AC44; // 44.1KHz 30.3.5 SPDIF Debug Register Description The SPDIF Debug Register provides read-only access to various internal state information that may be useful for block debugging and validation. HW_SPDIF_DEBUG HW_SPDIF_DEBUG_SET 0x040 0x044 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 30-11 SPDIF Transmitter HW_SPDIF_DEBUG_CLR HW_SPDIF_DEBUG_TOG Table 30-9. HW_SPDIF_DEBUG 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 RSRVD1 0x048 0x04C 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 DMA_PREQ 0 0 FIFO_STATUS Table 30-10. HW_SPDIF_DEBUG Bit Field Descriptions BITS LABEL 31:2 RSRVD1 1 DMA_PREQ RW RESET RO 0x00 RO 0x0 DEFINITION Reserved DMA request status. This read-only bit reflects the current state of the SPDIF's DMA request signal. DMA requests are issued any time the request signal toggles. This bit can be polled by software, in order to manually move samples to the SPDIF's FIFO from a memory buffer when the SPDIF's DMA channel is not used This bit is set when the FIFO has empty space. This reflects a DMA request being generated. 0 FIFO_STATUS RO 0x1 DESCRIPTION: This is a read-only register used for checking FIFO status and PIO mode of operation. EXAMPLE: unsigned TestBit = HW_SPDIF_DEBUG.DMA_PREQ; 30.3.6 SPDIF Write Data Register Description The SPDIF Write Data Register receives 32-bit data transfers from the DMA. It deposits the data into an internal FIFO and from there into the SPDIF stream. These 32-bit writes contain either one 32-bit sample or two 16-bit samples. HW_SPDIF_DATA HW_SPDIF_DATA_SET HW_SPDIF_DATA_CLR HW_SPDIF_DATA_TOG Table 30-11. HW_SPDIF_DATA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 HIGH 0x050 0x054 0x058 0x05C 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 LOW 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 30-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor SPDIF Transmitter Table 30-12. HW_SPDIF_DATA Bit Field Descriptions BITS 31:16 HIGH LABEL RW RESET RW 0x0000 DEFINITION For 16-bit mode, this field contains the entire right channel sample. For 32-bit mode, this field contains the 16 MSBs of the 32-bit sample (either left or right). For 16-bit mode, this field contains the entire left channel sample. For 32-bit mode, this field contains the 16 LSBs of the 32-bit sample (either left or right). 15:0 LOW RW 0x0000 DESCRIPTION: Writing a 32-bit value to the register corresponds to pushing that 32-bit value into the SPDIF FIFO. The DMA writes 32-bit values to this register. In 32-bit-per-sample mode, the DMA is writing either one full left sample or one full right sample for each write to this register. For 16-bit mode, the DMA is writing a 16-bit left sample and a 16-bit right sample for each 32-bit write to this register. EXAMPLE: HW_SPDIF_DATA = 0x12345678; // write 0x1234 to the right channel and 0x5678 to the left channel in 16-bit mode HW_SPDIF_DATA = 0x12345678; // write 0x12345678 to either the left or right channel in 32-bit per sample mode. 30.3.7 SPDIF Version Register Description The SPDIF Version Register is read-only and is used for debug to determine the implementation version number for the block. HW_SPDIF_VERSION Table 30-13. HW_SPDIF_VERSION 3 1 3 0 2 9 2 8 MAJOR 0x060 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 30-14. HW_SPDIF_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x01 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x01 RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_SPDIF_VERSION.B.MAJOR != 1) i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 30-13 SPDIF Transmitter Error(); SPDIF Block v1.1, Revision 1.26 i.MX23 Applications Processor Reference Manual, Rev. 1 30-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 31 Serial Audio Interface (SAIF) (BGA169 Only) This chapter describes the two instances of the serial audio interface (SAIF) included on the i.MX23 and how to use them. Programmable registers are described in Section 31.3, "Programmable Registers." 31.1 * * * * * * * * * * Overview 3-, 4-, or 5-wire serial interface to industry's most common analog codecs. Transmit or receive (half-duplex). 16-bit to 24-bit serial stereo digital audio PCM receive/transmit. Two, four, or six channels supported--three stereo pairs (mono supported in two-channel mode). Generic frame control supports I2S, left- and right-justified frame formats, as well as other non-standard variants of these formats. Master and slave BITCLK and LRCLK modes (clocks driven to codec or received from codec), as well as optional master MCLK mode. Supports a continuous range of sample rates from 8 kHz to 192 kHz using a high-resolution fractional divider driven by the PLL. Programmable over-sample rate for MCLK output (32x, 48x, 64x, 96x, 128x, 192x, 256x, 384x, and 512x) supports codecs found in systems with both audio and video. Four-entry FIFOs (per sample pair) buffer either two-channel sample pairs (17-bit through 24-bit PCM) or four-packed-channel sample pairs (16-bit PCM). Samples transferred to/from the FIFO via the APBX DMA interface, a FIFO service interrupt, or software polling. The SAIF provides the following functions: i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31-1 Serial Audio Interface (SAIF) (BGA169 Only) Figure 31-1 shows the major functional blocks within the SAIF. APBX DMA Interface MCLK/ BITCLK/ LRCLK Dividers SAIF__MCLK_BITCLK Pin SAIF_ALT_BITCLK Pin SAIF_LRCLK Pin saif_clk CLKCTRL (IFRAC reg) Registers FIFOs Front Surround Center/ LFE Serial Frame Control SAIF_SDATA Pins 1, 2, or 3 Figure 31-1. Serial Audio Interface (SAIF) Block Diagram 31.2 Operation The SAIF is a half-duplex port, meaning it can either transmit or receive PCM audio, but not simultaneously. Data is communicated serially one sample at a time, alternating between left and right samples. One to three serial data lines (SDATA0-SDATA2) can be used to transmit either two (stereo/mono), four (stereo/surround), or six (stereo/surround/center/LFE) channels of digital PCM audio data. Samples boundaries are delineated by a left/right clock (LRCLK) pin, and individual bits within each sample are delineated by a bit clock (BITCLK) pin. The LRCLK can be programmed to toggle every 16, 24, or 32 BITCLK transitions, and, because data ranges from 16 to 24 bits, serial data within each LRCLK period can either fully occupy the LRCLK cycle or cause the LRCLK period to contain BITCLK cycles in which no data is being communicated. Because of this, three basic types of sample frame formats can be programmed: I2S, left-justified, and right-justified. However, many programming options exist to alter these basic frame types, such as the LRCLK signal polarity, BITCLK edge selection to drive/sample serial data, and sample justification/delay within an LRCLK period. i.MX23 Applications Processor Reference Manual, Rev. 1 31-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Serial Audio Interface (SAIF) (BGA169 Only) For codecs that do not contain their own PLL, or in applications where including a crystal oscillator to drive the codec is not desired, the SAIF can provide a master clock (MCLK) reference that can be configured from 512x down to 32x the audio data's sample rate. This master clock is used by the off-chip codec for all of its internal logic and to synchronize the BITCLK/LRCLK/SDATA inputs for DAC operation. The digital PCM audio sample rate is determined by programming a fractional divider within the clock controller module. 31.2.1 * * * Sample Rate Programming and Codec Clocking Operation SAIF clocking is programmed in three blocks of the i.MX23: Clock control module (CLKCTRL) SAIF module Digital control module (DIGCTL) The saif_clk (shown in Figure 31-1) is generated by the CLKCTRL block with a 16-bit fractional divider that divides down the 480-MHz PLL reference. The fractional divider minimizes system cost and power by eliminating the need for a second on-chip PLL. This fractional divider continuously selects which edge of the PLL reference clock (positive or negative) to use to best represent the oversample rate, such that less than 2 ns of correlated jitter occurs in saif_clk (jitter of the PLL plus periodic jitter of the fractional divide). This low level of jitter is required by most codec manufacturers to ensure a high SNR. Table 31-1 shows the values to program the HW_CLKCTRL_SAIF_DIV bit field for all standard sample rates with either a base oversample rate of 512 or 384 times the sample rate. These two base oversample values are the base rates typically required by codecs for the master clock (MCLK). An additional divider exists within the SAIF to generate sub-multiples of these two base rates if MCLK is required by the codec. * * The sub-rates that can be generated from 512x are: 256x, 128x, 64x, and 32x. The sub-rates for the 384x base rate are: 192x, 96x, and 48x. The 384xFs base rate is common among systems that include MPEG1/2/4 audio and video, and AAC and AC-3 (Dolby Digital) audio. These MCLK rates are generated by programming the HW_SAIF_CTRL_BITCLK_BASE_RATE and HW_SAIF_CTRL_BITCLK_MULT_RATE bit fields. Because there is a small amount of error in the sample rates generated by the fractional divider, software needs to periodically alter the HW_CLKCTRL_SAIF_DIV value higher or lower, depending on the difference between the required and actual sample rates. For an audio-only playback application, this adjustment need not ever be performed, because the frequency phase shift is imperceptible. However, it is needed for applications such as locking to and playing from an FM tuner, or audio/video applications where AV synchronization is required. For an audio/video application, it is typically accepted that audio and video cannot diverge any greater than 20 ms. Table 31-1 contains a column that lists the average elapsed time between each DIV adjustment required to keep within this 20-ms limit. Note that the smalli.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31-3 Serial Audio Interface (SAIF) (BGA169 Only) est elapsed time is just under 20 seconds. Typically, software can be configured to periodically monitor the read and write pointers for the digital PCM audio buffer in OCRAM or SDRAM. When the pointers either become close to overrunning each other or close to the 20-ms AV divergence point, the DIV value should be increased or decreased incrementally (LSBs). Table 31-1. HW_CLKCTRL_SAIF_DIV Values for Standard Sample Rates/ Oversample Base Rates DIV Adjustment Frequency (seconds) (Notes 1 and 2) Sample Rate (Hz) Oversample Base Rate Multiplier 512 saif_clk Required (MHz) 98.304 73.728 90.2144 67.6608 65.536 49.152 49.152 36.864 45.1072 33.8304 32.768 24.576 24.576 18.432 22.5792 16.9344 16.384 12.288 12.288 9.216 11.2896 8.4672 8.192 6.144 6.144 4.608 Desired Fractional Divisor 0.2048000000 0.1536000000 0.1879466667 0.1409600000 0.1365333333 0.1024000000 0.1024000000 0.0768000000 0.0939733333 0.0704800000 0.0682666667 0.0512000000 0.0512000000 0.0384000000 0.0470400000 0.0352800000 0.0341333333 0.0256000000 0.0256000000 0.0192000000 0.0235200000 0.0176400000 0.0170666667 0.0128000000 0.0128000000 0.0096000000 Closest Actual Fractional Divisor 0.2048034668 0.1535949707 0.1879425049 0.1409606934 0.1365356445 0.1024017334 0.1024017334 0.0767974854 0.0939788818 0.0704803467 0.0682678223 0.0511932373 0.0511932373 0.0384063721 0.0470428467 0.0352783203 0.0341339111 0.0256042480 0.0256042480 0.0191955566 0.0235137939 0.0176391602 0.0170593262 0.0128021240 0.0128021240 0.0095977783 DIV Binary Value 0011010001101110 0010011101010010 0011000000011101 0010010000010110 0010001011110100 0001101000110111 0001101000110111 0001001110101001 0001100000001111 0001001000001011 0001000101111010 0000110100011011 0000110100011011 0000100111010101 0000110000001011 0000100100001000 0000100010111101 0000011010001110 0000011010001110 0000010011101010 0000011000000101 0000010010000100 0000010001011110 0000001101000111 0000001101000111 0000001001110101 DIV Hex Value 0x346E 0x2752 0x301D 0x2416 0x22F4 0x1A37 0x1A38 0x13A9 0x180F 0x120B 0x117A 0x0D1B 0x0D1B 0x09D5 0x0C0B 0x0908 0x08BD 0x068E 0x068E 0x04EA 0x0605 0x0484 0x045E 0x0347 0x0347 0x0275 Error (ppm) 16.9 32.7 22.1 4.9 16.9 16.9 16.9 32.7 59.0 4.9 16.9 132.1 132.1 165.9 60.5 47.6 16.9 165.9 165.9 231.4 263.9 47.6 430.1 165.9 165.9 231.4 DIV < Actual 347.3 610.8 903.2 193.5 210.9 151.4 151.4 610.8 193.5 94.5 96.8 151.4 151.4 86.4 75.8 420.1 46.5 46.5 46.5 86.4 75.8 420.1 46.5 19.5 19.5 86.4 DIV > Actual 1181.5 300.3 338.8 4066.0 1181.5 1181.5 1181.5 120.5 338.8 4066.0 1181.5 120.5 120.5 120.5 330.5 52.0 1181.5 120.5 120.5 35.5 52.0 24.5 43.1 120.5 120.5 14.7 192000 384 512 176200 384 512 128000 384 512 96000 384 512 88100 384 512 64000 384 512 48000 384 512 44100 384 512 32000 384 512 24000 384 512 22050 384 512 16000 384 512 12000 384 i.MX23 Applications Processor Reference Manual, Rev. 1 31-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Serial Audio Interface (SAIF) (BGA169 Only) Table 31-1. HW_CLKCTRL_SAIF_DIV Values for Standard Sample Rates/ Oversample Base Rates (continued) 512 11025 384 512 8000 384 3.072 0.0064000000 0.0063934326 0000000110100011 0x01A3 1026.2 19.5 14.7 4.2336 4.096 0.0088200000 0.0085333333 0.0088195801 0.0085296631 0000001001000010 0000001000101111 0x0242 0x022F 47.6 430.1 420.1 46.5 11.9 14.7 5.6448 0.0117600000 0.0117645264 0000001100000011 0x0303 384.9 21.9 52.0 1 2 HW_CLKCTRL_SAIF_DIV_FRAC_EN=1 Average elapsed time between each DIV adjustment to maintain audio within 20 ms of sample rate. BITCLK is used to launch or capture each bit of the serial PCM data, while LRCLK clocks the individual left/right samples (transitions at every sample boundary). For transmit, BITCLK and LRCLK are always driven by the SAIF. However, there are two different clocking modes for receive. In master mode, the SAIF drives both BITCLK and LRCLK, while in slave clock mode it is the responsibility of the codec to drive BITCLK and LRCLK to the SAIF. Note that, for any of these modes, an alternate MCLK reference can be multiplexed out to a pin to drive the codec's main system clock. In slave clocking mode, the SAIF configures the BITCLK and LRCLK pins as inputs, and the off-chip codec is responsible for driving both clocks to the SAIF. The SAIF synchronizes these inputs and uses them to determine when to latch serial PCM data from the ADC for receive. The codec must be configured to run BITCLK either at 32xFs for 16-bit operation, 64xFs for 17-bit through 24-bit operation, or 48xFs for certain codecs for 16-bit through 24-bit operation. In master clocking mode, it is the responsibility of the SAIF to drive both BITCLK and LRCLK out to the off-chip codec. In this mode, BITCLK is again programmed to transition at a the standard 32x, 48x, or 64x the sample rate. On the i.MX23, two SAIF modules are instantiated on-chip. However, due to pin multiplexing constraints, only one set of clock pins is provided for both ports. This means that only one of the two SAIFs can master or drive the clock pins at a time, and the other SAIF becomes a slave to the master. This also means that both SAIFs must operate at the same sample rate. Following are the valid configurations for SAIF1 and SAIF2 on the i.MX23: * * * * One SAIF in TX mode (is the default clock master) while the other SAIF is in RX slave mode and is internally controlled by the TX SAIF's BITCLK and LRCLK. One SAIF in RX master mode while the other SAIF is in RX slave mode and again is internally controlled by the RX master SAIF's BITCLK and LRCLK. Both SAIFs in RX slave mode, with BITCLK and LRCLK controlled by the off-chip codec. Only one SAIF used (any configuration). For any of these configurations, MCLK can also be output via a multiplexed pin to provide the clock reference for the off-chip codec. Configuring the SAIF for transmit makes it the master by default. However, for receive, the SAIF can either be master or slave. For master mode, it drives BITCLK and LRCLK to the pins the off-chip codec, i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31-5 Serial Audio Interface (SAIF) (BGA169 Only) which uses the clocks to time when to serially transmit PCM data back to the SAIF. For slave mode, the BITCLK and LRCLK are pin inputs driven by the off-chip codec, and the SAIF uses these clocks to determine when to latch each incoming bit and push the assembled PCM data to the FIFO. The DIGCTL module contains a number of register bits to define which of the two SAIFs is master, as well as the pin configuration for BITCLK, LRCLK, and the optional MCLK output. The HW_DIGCTL_CTRL_SAIF_CLKMST_SEL bit simply selects which of the two SAIFs is to function as clock master (0 = SAIF1 is clock master, 1 = SAIF2 is clock master). The HW_DIGCTL_CTRL_SAIF_CLKMUX_SEL bit field selects the clock direction as well as what pins (either BITCLK-only or both BITCLK and MCLK) are used (see Table 31-2). Table 31-2. HW_DIGCTL_CTRL_SAIF_CLKMUX_SEL Programming PIN HW_SAIF_CLKMUX_SEL SAIF_MCLK_BITCLK SAIF_ALT_BITCLK SAIF_LRCLK MODE 00 01 10 11 MCLK OUT BITCLK OUT MCLK OUT BITCLK IN BITCLK OUT BITCLK IN - LRCLK OUT LRCLK OUT LRCLK IN LRCLK IN TX/RX Master TX/RX Master RX Slave RX Slave HW_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL selects what pin BITCLK uses when both BITCLK and MCLK are selected. See Chapter 37, "Pin Control and GPIO," for instructions on which pins the two SAIFs use and how to configure them for operation. The SAIF contains a four-entry FIFO for each channel pair that buffers data between the SAIF and the on-chip or off-chip RAM buffer used to supply or collect serial PCM audio data. Both the SAIF's register and DMA interface are clocked by APBX clock. To ensure the SAIF FIFO does not overrun or underrun, the minimum APBX clock frequency to sample rate frequency ratio is 22:1. Therefore, if the sample rate is configured to 192 kHz, then APBX must be set to 4.224 MHz or greater. 31.2.2 Transmit Operation If the APBX DMA is to supply PCM data to the SAIF FIFO, the user first configures its corresponding DMA channel and initializes the buffer(s) of PCM data that are to be played. Next the SAIF control register is initialized, selecting the frame format and number of channel pairs, clearing the CLKGATE bit, and setting the RUN bit. Once running, the BITCLK, LRCLK, and optional MCLK pins begin to transition, and null data is output to the off-chip analog DAC. The SAIF DMA interface requests PCM samples until the FIFO(s) is/are filled, and continues to request a sample (or sample pair for 16-bit operation) whenever an empty FIFO i.MX23 Applications Processor Reference Manual, Rev. 1 31-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Serial Audio Interface (SAIF) (BGA169 Only) entry is available. Once valid PCM data resides within the bottom of the front channel pair FIFO, the current null sample left/right pair(s) are allowed to complete. At this point, the serialization frame control logic begins to output the first valid left sample. In 16-bit operation, sample pairs are packed with the right samples occupying the upper halfword and left samples the lower halfword of the FIFO entries. For 17-bit to 24-bit operation, each FIFO entry contains a sample that is right-justified (LSB in bit 0). The first sample DMA-ed to the FIFO at the start of operation should always be a left sample, followed by a right, and so on. If four or six channel pairs are enabled, samples should be grouped with all left samples first, followed by all right samples (e.g., front left, surround left, then center, followed by front right, surround right then LFE, and so on). As long as data resides within the FIFO(s), valid sample pairs continue to be output. If the FIFO(s) ever underflow or overflow, an interrupt occurs. At this point, the system software should shut down the SAIF, clear the FIFO(s), and then cleanly resume operation because there is not a way to prevent left/right swap of the PCM channels after this point. If the FIFO does underflow, null samples are output until valid data once again resides within the bottom of the FIFO. Any PCM value that is written to a full FIFO is discarded, preventing the top entry from be overwritten. When the RUN bit is cleared at the end of operation, all PCM data corresponding to one sample collection (either two, four, or six channel pairs) that are currently being transmitted are allowed to complete before operation ceases and the BITCLK, LRCLK, and SDATA pins stop transitioning. Alternately, software can be used to maintain the FIFO(s) if the DMA is not used, either by responding to an interrupt that is issued whenever an empty FIFO entry exists, or by polling a FIFO status bit. 31.2.3 Receive Operation If the APBX DMA is to collect PCM data from the SAIF FIFO(s), the user first configures its corresponding DMA channel and allocates the buffer(s) where PCM data is to be recorded. Next the SAIF control register is initialized, selecting the frame format and number of channel pairs, selecting whether the SAIF is BITCLK/LRCLK master or slave, clearing the CLKGATE bit, and setting the RUN bit. Once running, the SAIF either waits until the BITCLK and LRCLK pins begin to transition (slave mode) or begins to toggle BITCLK and LRCLK (master mode). In either case, once an LRCLK edge that corresponds to the start of a left sample is detected, the SAIF frame-control logic begins to assemble the sample in its serial shift register. Each time the LRCLK pin toggles, a new sample is pushed to the FIFO(s). In 16-bit operation, sample pairs are packed with the right samples occupying the upper halfword and left samples the lower halfword of the FIFO entries. For 17-bit to 24-bit operation, samples are placed in individual FIFO entries, are right justified (LSB in bit 0), and the unused MSBs are zero-filled. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31-7 Serial Audio Interface (SAIF) (BGA169 Only) The first sample pushed to the FIFO at the start of operation is always a left sample, followed by a right, and so on. If 4 or 6 channel pairs are enabled, sample pairs are grouped when pushed to the FIFO with all left samples first, followed by all right samples (e.g., front left, surround left, then center, followed by front right, surround right then LFE, and so on). As long as the BITCLK and LRCLK pins continue to transition, data is collected within the FIFO. If the FIFO ever overflows or underflows, an interrupt occurs. At this point, the system software should shut down the SAIF, clear the FIFO(s), and then cleanly resume operation because there is not a way to determine left from right PCM channel data within the FIFO after this point. If the FIFO does overflow, any PCM value that is pushed to the full FIFO is discarded, not allowing the top entry to be overwritten. If the FIFO underflows, the read of the empty FIFO returns all zeros. When the run bit is cleared at the end of operation, all PCM data corresponding to one sample collection (either two, four, or six channel pairs) that are currently being serially received are allowed to complete and are stored to the FIFO before operation ceases. Software can be used to empty the FIFO if the DMA is not used, either by responding to an interrupt that is issued whenever an empty FIFO entry exists, or by polling a FIFO status bit. 31.2.4 DMA Interface Both SAIFs on the i.MX23 are assigned to APBX DMA channels. See Chapter 11, "AHB-to-APBX Bridge with DMA," for the DMA channel assignments. Once the DMA channel and SAIF are programmed (except for the RUN bit), operation can be initiated either by setting the SAIF's RUN bit or by signaling a kick from the DMA channel. The HW_SAIF_CTRL_DMAWAIT_COUNT bit field can be programmed to wait 0 to 31 APBX clock cycles between each DMA request. This feature acts as a throttle on the bandwidth required by the SAIF to allow delays such that DMA requests from other modules can be serviced by the DMA controller. 31.2.5 PCM Data FIFO The SAIF contains three 4-entry by 32-bit wide FIFOs. These FIFOs serve as a buffer to ensure data is not corrupted if the DMA cannot service the SAIF before the next sample or sample pair is processed by the SAIF. Access to the FIFOs is achieved via read/writes of the 32-bit HW_SAIF_DATA register. Writes place PCM values at the top of the FIFOs, and reads take them from the bottom of the FIFOs. Each FIFO is used to store different sets of left/right channel pairs. FIFO1 stores the stereo or front channels, FIFO2 the surround or rear channels, and FIFO3 the center and low frequency effect (LFE) or subwoofer channels (see Figure 31-1). Read/write accesses are made to the FIFOs in round-robin fashion such that all left channel samples are transferred first including the center channel, followed by all right channel samples including the LFE channel. i.MX23 Applications Processor Reference Manual, Rev. 1 31-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Serial Audio Interface (SAIF) (BGA169 Only) In 16-bit operation, sample pairs are packed with the right samples occupying the upper halfword and left samples the lower halfword of the FIFO entries. For 17-bit to 24-bit operation, sample pairs are placed in individual FIFO entries, left channel first then followed by the right channel, and are right justified (LSB in bit 0) in each FIFO entry. The FIFO underflow, overflow, and service interrupt status bits reside within the HW_SAIF_STAT register. 31.2.6 Serial Frame Formats There are six types of serial PCM frames that can be transmitted or received. The three basic formats are I2S, left-justified, and right-justified. Because there are two variations of a frame based on whether or not the data consumes the entire frame width, these three formats have two frame types each that make up the six basic frame types. One variation exists for 16-bit and 24-bit serial PCM data that consumes the whole frame width, and the other for 17-bit to 24-bit serial PCM data that does not. Recall that for 16-bit operation, BITCLK is either 32xFs or 48xFs, while for 17-bit to 24-bit, it is either 48xFs or 64xFs. These six types of serial PCM frames are shown in Figure 31-2. * In left-justified (LJ) format, the serial PCM data is left-justified within the sample's start and end point indicated by the LRCLK. The first bit of PCM data is coincident with the first BITCLK period after LRCLK transitions. Conversely, in right-justified (RJ) format, the last bit of PCM data in a sample is coincident with the last BITCLK period before LRCLK transitions, indicating the start of the next sample. I2S format is simply a variant of LJ format, in that the first BITCLK period after the LRCLK transitions, is a null wait state, followed by the first serial PCM bit during the next BITCLK period. * * For both LJ and RJ formats, LRCLK is high for left samples and low for right samples. For I2S, it is the opposite: LRCLK is low for left samples and high for right samples. When the programmed data size is smaller than the frame size or number of BITCLKs per LRCLK, there are BITCLK periods within the sample frame in which no data is being transmitted or received. This occurs in 48xFs mode when that data is less than 24 bits, and for all data sizes allowed in 64xFs mode. For LJ and I2S modes, this occurs after the sample has been transmitted or received, while for RJ mode, this occurs prior to the sample being transmitted or received. For 16-bit (32xFs mode) operation and 24-bit (48xFs mode) operation, data is always being transmitted, so that LJ and RJ modes are identical. I2S is a special case for these modes. At the start of transmit or receive, the first BITCLK period after LRCLK transitions is a null or wait state cycle in which no PCM data is present. However, this means one too few BITCLK periods remain to transmit or receive data before LRCLK transitions. As a result, the protocol dictates that the last serial PCM bit of each sample be transmitted or received during the BITCLK wait state at the start of the next sample. Additionally data can be programmed to be transmitted or received MSB or LSB first. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31-9 Serial Audio Interface (SAIF) (BGA169 Only) The bits to program frame format reside within the HW_SAIF_CTRL register. 31.2.7 Pin Timing Figure 31-2 shows the six basic frame formats supported by the SAIF. Keep in mind that for 16-bit operation, BITCLK runs at either 32x or 48x the sample rate, and for 17-bit through 24-bit operation, it runs at either 48x or 64x the sample rate (i.e., clock frequency relationship of differing data sizes is not shown here). LRCLK BITCLK SDATA I2S w/ nulls SDATA I2S w/o nulls SDATA LJ w/ nulls SDATA RJ w/ nulls SDATA LJ/RJ w/o nulls WAIT MSB MSB-1 LSB 0 WAIT MSB WAIT MSB MSB-1 LSB+1 LSB MSB MSB MSB-1 MSB-2 LSB 0 MSB MSB-1 0 MSB LSB 0 MSB MSB-1 MSB-2 LSB MSB MSB-1 Note: LRCLK_POLARITY=1 and BITCLK_EDGE=0 for this example. Figure 31-2. Frame Formats Supported by SAIF 31.3 Programmable Registers The following registers are available for CPU programmer access and control of the serial audio interface. 31.3.1 SAIF Control Register Description HW_SAIF_CTRL HW_SAIF_CTRL_SET HW_SAIF_CTRL_CLR HW_SAIF_CTRL_TOG 0x000 0x004 0x008 0x00C The SAIF Control Register controls the frame format and operation of the three-wire serial audio interface. i.MX23 Applications Processor Reference Manual, Rev. 1 31-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Serial Audio Interface (SAIF) (BGA169 Only) Table 31-3. HW_SAIF_CTRL 3 1 3 0 2 9 2 8 BITCLK_MULT_RATE 2 7 2 6 BITCLK_BASE_RATE 2 5 FIFO_ERROR_IRQ_EN 2 4 FIFO_SERVICE_IRQ_EN 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 CHANNEL_NUM_SELECT 1 4 1 3 1 2 1 1 1 0 0 9 LRCLK_POLARITY 0 8 0 7 0 6 0 5 0 4 0 3 BITCLK_48XFS_ENABLE 0 2 0 1 0 0 DMAWAIT_COUNT WORD_LENGTH BITCLK_EDGE SLAVE_MODE READ_MODE BIT_ORDER CLKGATE JUSTIFY RSRVD2 RSRVD1 SFTRST DELAY Table 31-4. HW_SAIF_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION Setting this bit to 1 forces a reset to the entire block. SFTRST has no effect on CLKGATE. Also, the SFTRST bit may be written when CLKGATE=1. This bit must be cleared to 0 for normal operation. This bit gates the clocks to the SAIF to save power when the clocks are not in use. When set to 1, this bit gates off the clocks to the block. When this bit is cleared to 0, the block receives its clocks for normal operation. BITCLK Mutiplier Rate. This bit field selects the multiple of the base frequency rate of BITCLK for transmit mode and receive master clock mode (READ_MODE=1, SLAVE_MODE=0), or if the alternate BITCLK pin is used, it selects the multiple of the base frequency rate of MCLK (any mode). When BITCLK_BASE_RATE = 0 (32x base rate): 000=512 x Fs, 001=256 x Fs, 010=128 x Fs, 011=64 x Fs, 100=32 x Fs, 101-111=reserved. When BITCLK_BASE_RATE = 1 (48x base rate): 000=384 x Fs, 001=192 x Fs, 010=96 x Fs, 011=48 x Fs, 100-111=reserved. When the SAIF_BITCLK_MCLK pin is used as BITCLK, this field should be programmed to 32x for 16-bit data, 48x for 16-bit to 24-bit data (BITCLK_48XFS_ENABLE=1), and 64x for 17-bit to 24-bit data, depending on the modes supported by the off-chip codec. When the SAIF_BITCLK_MCLK pin is used as MCLK (and the alternate BITCLK pin mux function is enabled), any oversample rate can be selected as dictated by the codec's required MCLK frequency. Note that the clock controller block should be programmed with the correct DIV value to produce the correct oversample clock base frequency (either 512x or 384x the sample rate) to the SAIF. 30 CLKGATE RW 0x1 29:27 BITCLK_MULT_RATE RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RUN 31-11 Serial Audio Interface (SAIF) (BGA169 Only) Table 31-4. HW_SAIF_CTRL Bit Field Descriptions BITS LABEL BITCLK_BASE_RATE 26 RW RESET RW 0x0 DEFINITION BITCLK Base Rate. This bit selects the base frequency rate at which the BITCLK pin toggles when configured as an output (either in transmit mode or in receive master clock mode), or if the alternate BITCLK pin is used, it selects the base frequency rate at which both the MCLK and alternate BITCLK pin toggles. 0 = BITCLK/MCLK base frequency rate is in multiples of 32x the sample rate. 1 = BITCLK/MCLK base frequency rate in in multiples of 48x the sample rate. This bit field is used in conjunction with the BITCLK_MULT_RATE field to program the BITCLK/MCLK output frequency. Set this bit to one to enable a SAIF interrupt request on FIFO overflow or underflow status condition. Set this bit to one to enable a SAIF interrupt request to service the FIFO when it contains an empty entry (for transmit) or a full entry (for receive). Reserved. DMA Request Delay Count. This bit field specifies the number of APBX clock cycles (0 to 31) to delay after a DMA request has been serviced and before the next request is granted. This field acts as a throttle on the bandwidth consumed by the SAIF block. This field can be loaded by the DMA. Channel Number Select. This bit field selects the number of channel pairs (left and right) that are transmitted and/or received by the SAIF. 00 = One channel pair (stereo) 01 = Two channel pairs (front, surround) 10 = Three channel pairs (front, surround, center/lfe) 11 = Reserved Reserved. SAIF PCM Data Serial Bit Order. This bit selects whether PCM data is serially transmitted or received LSB or MSB first. 0 = MSB first 1 = LSB first Note that the two's complement audio data written to and read from the FIFO is always ordered MSB to LSB (LSB located in bit 0 for 17-bit through 24-bit operation, and in bits 15 and 0 for 16-bit operation). SAIF Data Delay. In left-justified mode, this bit selects whether or not serial PCM data transmission/reception is delayed by one BITCLK period each LRCLK frame (to generate I2S serial operation). 0 = Data is not delayed. MSB of serial sample is output/input coincident with LRCLK transition (left-justified mode) 1 = Data is delayed one BITCLK period. MSB of serial serial sample is output/input one BITCLK period after LRCLK transitions (I2S mode). Note that this bit is ignored in right-justified mode (JUSTIFY=1). 25 24 FIFO_ERROR_IRQ_EN FIFO_SERVICE_IRQ_EN RW 0x0 RW 0x0 23:21 RSRVD2 20:16 DMAWAIT_COUNT RO 0x0 RW 0x00 15:14 CHANNEL_NUM_SELECT RW 0x0 13 12 RSRVD1 BIT_ORDER RO 0x0 RW 0x0 11 DELAY RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 31-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Serial Audio Interface (SAIF) (BGA169 Only) Table 31-4. HW_SAIF_CTRL Bit Field Descriptions BITS JUSTIFY 10 LABEL RW RESET RW 0x0 DEFINITION SAIF Data Justification. This bit selects whether serial PCM data is left- or right-justified within each sample's LRCLK frame. 0 = Data is left-justified (start or MSB of serial sample transmission/reception coincides with LRCLK transition) 1 = Data is right-justified (end or LSB of serial sample transmission/reception coincides with LRCLK transition). SAIF LRCLK Polarity Select. This bit selects which LRCLK levels (high/low) correspond to left and right PCM samples. 0 = Left low/right high 1 = Left high/right low. SAIF BITCLK Edge Select. For both transmit and receive, this bit selects the BITCLK edge upon which serial PCM data changes. For receive, data is sampled and stored to the receive FIFO on the opposite edge as selected by BITCLK_EDGE that corresponds to the midpoint of the data. 0 = TX: data is driven (changes) on falling-edges of BITCLK; RX: data is sampled on rising-edges of BITCLK 1 = TX: data is driven (changes) on rising-edges of BITCLK; RX: data is sampled on falling-edges of BITCLK. SAIF data size. Selects one of nine PCM data widths from 16-bit to 24-bit to serially input or output from/to a codec. 17-bit to 24-bit PCM data should be right-justified (LSB in bit 0) when it is DMAed or written to the HW_SAIF_DATA register. These samples should be interleaved starting with a left sample first, followed by a right, then left and so on. For 16-bit PCM data, stereo pairs should be constructed with the right sample in the upper half-word (bits 31-16) and the left sample in the lower half word (bits 15-0). 0000 = 16-bit 0001 = 17-bit 0010 = 18-bit 0011 = 19-bit 0100 = 20-bit 0101 = 21-bit 0110 = 22-bit 0111 = 23-bit 1000 = 24-bit 1001-1111 = Reserved but defaults to 24-bit. BITCLK 48x Sample Rate Enable. For 384x base frequency multiples, this bit enables generation of 48 BITCLKs per sample pair (24 BITCLKs per channel or LRCLK transition) when the SAIF is BITCLK master. This bit is ignored for the following cases: BITCLK_BASE_RATE=0, or READ_MODE=1, or READ_MODE=0 and SLAVE_MODE=1. 9 LRCLK_POLARITY RW 0x0 8 BITCLK_EDGE RW 0x0 7:4 WORD_LENGTH RW 0x0 3 BITCLK_48XFS_ENABLE RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31-13 Serial Audio Interface (SAIF) (BGA169 Only) Table 31-4. HW_SAIF_CTRL Bit Field Descriptions BITS LABEL 2 SLAVE_MODE RW RESET RW 0x0 DEFINITION SAIF Receive Master/Slave Clock Mode Select. For receive operation, this bit selects whether BITCLK and LRCLK are driven to the off-chip codec or uses the two clock pins as inputs to determine when to receive data from the codec. In receive master mode (SLAVE_MODE=0), BITCLK and LRCLK are output to the codec. When SLAVE_MODE=0, both BITCLK and LRCLK start to transition immediately after the RUN bit is set. Note that when in transmit mode or receive master mode, the user must configure the SAIF's clock controls within the clock controller to the correct oversample rate (see BITCLK_BASE_RATE/BITCLK_MULT_RATE above). 0 = Master mode. SAIF drives BITCLK and LRCLK 1 = Slave mode. SAIF uses BITCLK and LRCLK as inputs to determine when to sample input PCM data. Note that is bit is ignored in transmit operation (READ_MODE=0). SAIF Transmit/Receive Select. This bit selects whether the SAIF block transmits to an off-chip DAC (write mode) or receives from an off-chip ADC (read mode). The selected mode (TX or RX) starts operation once the RUN bit is set. 0 = TX or write mode 1 = RX or read mode Setting this bit to one causes the SAIF to begin transmitting or receiving serial PCM data, depending on the programming of the READ_MODE bit. For transmit, when this bit is cleared, operation ends after transmission of the current active channel set (pairs from all enabled channels) from the FIFO. If the FIFO is already empty and the RUN bit is cleared, operation halts immediately and the LRCLK and BITCLK pins stop transitioning. For receive, when the RUN bit is cleared, reception ends after the current active channel set (pairs from all enabled channels) are pushed to the FIFO. Note for 4- and 6-channel operation, clearing the RUN bit means that the SAIF does not stop until the corresponding audio samples for all 4 or 6 channels have been transmitted or received. 1 READ_MODE RW 0x0 0 RUN RW 0x0 DESCRIPTION: The SAIF Control Register is used to configure the SAIF's input/output frame format, MCLK, BITCLK and LRCLK, and interrupt enables. EXAMPLE: HW_SAIF_CTRL.RUN = 1; // start SAIF operation i.MX23 Applications Processor Reference Manual, Rev. 1 31-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Serial Audio Interface (SAIF) (BGA169 Only) 31.3.2 SAIF Status Register Description The SAIF Status Register provides status of key hardware components required by software of the SAIF module. HW_SAIF_STAT HW_SAIF_STAT_SET HW_SAIF_STAT_CLR HW_SAIF_STAT_TOG Table 31-5. HW_SAIF_STAT 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 FIFO_UNDERFLOW_IRQ 0x010 0x014 0x018 0x01C 0 5 FIFO_OVERFLOW_IRQ 0 4 FIFO_SERVICE_IRQ 0 3 0 2 0 1 0 0 DMA_PREQ PRESENT RSRVD2 RSRVD1 RSRVD0 Table 31-6. HW_SAIF_STAT Bit Field Descriptions BITS LABEL 31 PRESENT 30:17 RSRVD2 16 DMA_PREQ RW RESET RO 0x1 RO 0x0 RO 0x0 DEFINITION This bit is set to 1 in products in which SAIF is present. Reserved. DMA Request Status. This read-only bit reflects the current state of the SAIF's DMA request signal. DMA requests are issued any time the request signal toggles. Reserved. This bit is set by hardware if the FIFO underflows during SAIF operation. Underflow occurs whenever a read or pop is attempted on an empty FIFO. This occurs in transmit mode when the FIFO is not filled in time and the hardware tries to pop a sample from the bottom of the FIFO. It also occurs in receive mode when the DMA or software attempts to read data from an empty FIFO. Reset this bit by writing a one to the SCT clear address space and not by a general write. This bit is set by hardware if the FIFO overflows during SAIF operation. Overflow occurs whenever a write or push is attempted to a full FIFO. This occurs in transmit mode if the FIFO is full and software or the DMA attempts to write additional data to the top of the FIFO. It also occurs in receive mode when the DMA or software does not respond in time to a service request, and the hardware attempts to push data to a full FIFO. Reset this bit by writing a one to the SCT clear address space and not by a general write. 15:7 6 RSRVD1 FIFO_UNDERFLOW_IRQ RO 0x0 RW 0x0 5 FIFO_OVERFLOW_IRQ RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice BUSY 31-15 Serial Audio Interface (SAIF) (BGA169 Only) Table 31-6. HW_SAIF_STAT Bit Field Descriptions BITS LABEL 4 FIFO_SERVICE_IRQ RW RESET RO 0x0 DEFINITION This bit is set by hardware when the FIFO requires service. FIFO service requests are made when an empty entry exists during transmit or a full entry exists during receive. A DMA request is generated (DMA_PREQ toggles) each time this bit is set. Once the DMA or software has serviced the request and the FIFO is filled (TX) or emptied (RX), this bit is automatically cleared. This interrupt can be used by software to trigger the manual movement of samples from/to the SAIF's FIFO to/from a memory buffer when the SAIF's DMA channel is not used. Reserved. This bit indicates when the SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s). For transmit, it is automatically set when the first sample from the FIFO begins to be output by the serial shifter. For receive, it is set coincident with the RUN bit beging set as serial receive begins immediately. After the RUN bit is cleared and the serial shifter becomes inactive (end of the current sample set), this bit is automatically cleared. 3:1 0 RSRVD0 BUSY RO 0x0 RO 0x0 DESCRIPTION: The SAIF Status Register provides the status of interrupt requests and active operation of the SAIF. EXAMPLE: unsigned TestBit = HW_SAIF_STAT.PRESENT; 31.3.3 SAIF Data Register Description The SAIF Data Register is used to either write PCM data samples to the top of the SAIF FIFOs for transmit, or read PCM samples from the bottom of the FIFOs during receive. 32-bit values written/read to/from this register contain either one 17-bit to 24-bit sample or two 16-bit samples. HW_SAIF_DATA HW_SAIF_DATA_SET HW_SAIF_DATA_CLR HW_SAIF_DATA_TOG Table 31-7. HW_SAIF_DATA 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 PCM_RIGHT 0x020 0x024 0x028 0x02C 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 PCM_LEFT 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 31-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Serial Audio Interface (SAIF) (BGA169 Only) Table 31-8. HW_SAIF_DATA Bit Field Descriptions BITS LABEL 31:16 PCM_RIGHT RW RESET RW 0x0000 DEFINITION For 16-bit mode, this field contains the entire right channel sample. For 17-bit through 24-bit modes, this field contains 1 through 8 of the MSBs of the sample (either left or right). For 16-bit mode, this field contains the entire left channel sample. For 17-bit through 24-bit modes, this field contains the 16 LSBs of the sample (either left or right). 15:0 PCM_LEFT RW 0x0000 DESCRIPTION: In transmit mode, writing a value to this register causes it to push the value to the top of the FIFO. In receive mode, reads cause values to be popped from the bottom of the FIFO. Writing to a full FIFO does not change the contents of the FIFO's top entry, and reading from an empty FIFO returns all zeros. For 16-bit operation, the left sample should be written to the register's lower half word, and the right to the upper half word. For all other data sizes, PCM audio values should be right-justified within the 32-bit word. Three FIFOs exist, one for each channel pair. If two-channel operation is enabled, only the stereo or front FIFO is accessed. Four-channel opearation causes both the front and surround FIFOs to be accessed. Six-channel operation uses all three FIFOs: front, surround, and center/LFE FIFOs. For both transmit and receive FIFO accesses, left and right samples should be interleaved, starting with all left samples for a given sample time, followed by all right samples (e.g., left front, left surround, center, right front, right surround, LFE (subwoofer), and so on). Operation should always start with the left samples. All left or all right channels for a given sample collection in time are received/transmitted simultaneously (e.g., for 6-channel mode, three PCM audio samples are popped from the FIFO prior to serialization and transmission). For mono operation, use the left channel to transmit/receive PCM audio, while the right channel should be zero-filled (TX) or discarded (RX). For transmit, if the FIFO is empty when operation begins, null (zero) data is output until the FIFO contains valid PCM data. Once a complete set of left samples resides within the bottom of the active FIFOs, the SAIF waits for the current collection of null samples (all left and right samples for a given time) to complete before transmitting the left sample collection from the FIFOs. EXAMPLE: HW_SAIF_DATA = 0x12345678; // write 0x1234 to the right channel and 0x5678 to the left channel in 16 bit mode HW_SAIF_DATA = 0x12345678; // write 0x12345678 to either the left or right channel in 32 bit per sample mode. 31.3.4 SAIF Version Register Description The SAIF Version Register is read-only and is used for debug to determine the implementation version number for the block. HW_SAIF_VERSION 0x030 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31-17 Serial Audio Interface (SAIF) (BGA169 Only) Table 31-9. HW_SAIF_VERSION 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 31-10. HW_SAIF_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x01 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x01 RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_SAIF_VERSION.B.MAJOR != 1) Error(); SAIF Block v1.1, Revision 2.1 i.MX23 Applications Processor Reference Manual, Rev. 1 31-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 32 Power Supply This chapter describes the power supply subsystem provided on the i.MX23. It includes sections on the DC-DC converter, linear regulators, PSWITCH pin functions, battery monitor and charger, and silicon speed sensor. Programmable registers are described in Section 32.11, "Programmable Registers." 32.1 * * * * * * * * * * * Overview One integrated DC-DC converter that supports Li-Ion batteries. Four linear regulators directly power the supply rails from 5 V. Linear battery charger for Li-Ion cells. Battery voltage and brownout detection monitoring for VDDD, VDDA, VDDIO, VDD4P2 and 5V supplies. Integrated current limiter from 5 V power source. Reset controller. System monitors for temperature and speed. Generates USB-Host 5V from Li-Ion battery (using PWM). Support for on-the-fly transitioning between 5V and battery power. VDD4P2, a nominal 4.2 V supply, is available when the i.MX23 is connected to a 5 V source and allows the DCDC to run from a 5 V source with a depleted battery. The 4.2 V regulated output also allows for programmable current limits: -- Battery Charge current + DCDC input current < the 5 V current limit -- DCDC input current (which ultimately provides current to the on-chip and off-chip loads) as the priority and battery charge current will be automatically reduced if the 5V current limit is reached The i.MX23 integrates a comprehensive power supply subsystem, including the following features: The i.MX23 power supply is designed to offer maximum flexibility and performance, while minimizing external component requirements. Figure 32-1 shows a functional block diagram of the power supply components including switching converters, five linear regulators, battery charge support, as well as battery monitoring, supply brownout detection, and silicon process/temperature sensors. This figure can be used to understand which register and status bits relate to which subsystems, but it is not intended to be a complete architecture description. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-1 Power Supply X VDD5V Current Limiter VDDIO HW_POWER_STS_VDDIO_BO VDD4P2 VBG HW_POWER_STS_VDD4P2_BO IOFB Battery Charge X VBG VDDIO VDDM X VDD4P2 VBG Battery VDDA X HW_POWER_STS_VDDA_BO VDDM X VBG AFB X VDDA DCDC VDDD IOFB, AFB, DFB HW_POWER_STS_VDDD_BO VBG HW_POWER_CTRL_DC_OK_IRQ DFB X VDDD Notes: Status Bits are in Italic Figure 32-1. Power Supply Block Diagram 32.2 DC-DC Converters The DC-DC converters efficiently scale battery voltage (or a regulated 4.2 V derived from a 5 V source) to the required supply voltages. The DC-DC converters include several advanced features: * * * * Single inductor architecture Programmable output voltages Programmable brownout detection thresholds Pulse frequency modulation (PFM) mode for low-current load operation 32.2.1 DC-DC Operation The i.MX23 DC-DC converter enables a low-power system and features programmable output voltages and control modes. Most products adjust VDDD dynamically to provide the minimum voltage required i.MX23 Applications Processor Reference Manual, Rev. 1 32-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply for proper system operation. VDDIO and VDDA are typically set once during system initialization and not changed during operation. 32.2.1.1 Brownout/Error Detection The power subsystem has several mechanisms active by default that safely return the device to the off state if any one of the following errors or brownouts occur: * The crystal oscillator frequency is detected below a certain threshold--This threshold is processand voltage-sensitive, but will always be between 100 kHz and 2 MHz. This feature can be disabled in the DISABLE_XTALOK field in the HW_RTC_PERSISTENT0 register. The battery voltage falls below the battery brownout level (field BRWNOUT_LVL in HW_POWER_BATTMONITOR)--This feature is disabled by clearing PWDN_BATTBRNOUT in the same register. 5 V is detected, then removed--This feature is disabled by clearing HW_POWER_5VCTRL_PWDN_5VBRNOUT. * * All three mechanisms are active by default to ensure that the device always has a valid transition to a known state in case the power source is unexpectedly removed before software has completed system configuration. Software will typically disable the functionality of PWDN_5VBRNOUT and PWDN_BATTBRNOUT after system configuration is complete, as shown in Figure 32-2. System configuration generally includes setting up brownout detection thresholds on the supply voltages, battery, etc. to obtain the desired system operation as the battery or power source is depleted or removed. Typically, each output target voltage is set to some voltage margin above the minimum operating level via the TRG field in the HW_POWER_VDDDCTRL, HW_POWER_VDDACTRL, and HW_POWER_VDDIOCTRL registers. The brownout detection threshold is also set via the BO_OFFSET field in the same three registers. The BO_OFFSET field determines how far the brownout voltage is below the output target voltage for each supply and might typically be set 75-100 mV below the target voltage. If the voltage drops to the brownout detector's level, then it optionally triggers a CPU Fast Interrupt (FIQ). The CPU can then alleviate the problem and/or shut down the system elegantly. To eliminate false detection, the brownout circuit filters transient noise above 1 MHz. Any system with an i.MX23 should include at least 33F of decoupling capacitance on the VDDIO, VDDA, and VDDD power rails. The capacitors should be arranged to filter supply noise in the 1-MHz and higher frequencies. See Figure 32-2. 32.2.1.2 DC-DC Extended Battery Life Features The DC-DC converter has several other power-reducing programmable modes that are useful for maximizing battery life: * Li-Ion Buck/Boost--The Li-Ion battery configuration supports buck/boost operation, which means that a VDDIO voltage can be supported that is higher than the input Li-Ion battery voltage. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-3 Power Supply * * * * This is important to maximize battery life in all applications, but is crucial in hard drives that have large transient current requirements. Transient Loading Optimizations--Several new incremental improvements have been made to the control architecture of the switching converters. At this time, Freescale recommends setting the following bits via software in HW_POWER_LOOPCTRL to obtain maximum efficiency and minimum supply ripple: TOGGLE_DIF, EN_CM_HYST, and EN_RCSCALE=0x1. Also, set HW_POWER_BATTMONITOR_EN_BATADJ. The complete settings to optimize transient loading will be dependent on the application, component selection, and board layout. Pulse Frequency Modulation (PFM)--PFM, also known as pulse-skipping mode, is used to reduce power consumed by the DC-DC converter when the voltage outputs are lightly-loaded at a cost of higher transient noise. The DC-DC converter can be separately placed in PFM mode via the EN_DC_PFM bit in HW_POWER_MINPWR. DC-DC Switching Frequency--The standard DC-DC switching frequency is 1.5 MHz, which provides a good mix of efficiency and power output. The frequency can be reduced to 750 kHz to reduce operating current in some light load situations via DC_HALFCLK in HW_POWER_MINPWR. The DC-DC converter can also be programmed to a frequency that is based on the PLL using the SEL_PLLCLK and FREQSEL fields in the HW_POWER_MISC register. DC-DC Converter Power Down--If the system is to operate from linear regulators or an external power supply, then the internal DC-DC converters can be powered down via DC_STOPCLK in HW_POWER_MINPWR. This bit is not intended to power down the whole system. Use the HW_POWER_RESET bits to power the system off. The DC-DC converter can be programmed to run off of the battery or the 4.2 V regulated voltage supply. It can be set up to oppportunistically draw power from either source. This allows the system to draw up to the USB current limit from the 5 V supply and take the balance of the required power from the battery. i.MX23 Applications Processor Reference Manual, Rev. 1 32-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply Base State Defaults: HW_POWER_5VCTRL_PWDN_5VBRNOUT=1 HW_POWER_BATTMONITOR_PWDN_BATTBRNOUT=1 Brownout = (HW_POWER_STS_VDD5V_GT_VDDIO=0) & (HW_POWER_BATTMONITOR_PWDN _BATTBRNOUT=1) & (HW_POWER_STS_BATT_BO=1) Unplug = (On falling edge of HW_POWER_STS_VDD5V_GT_VDDIO) & (HW_POWER_5VCTRL_PWDN_5VBRNOUT=1) Unplug=1 Brownout=1 Off (PSWITCH or RTC wakeup or HW_POWER_STS_VDD5V_GT_VDDIO=1) ROM Bist HW_POWER_STS_VDD5V_GT_VDDIO=0 Enable LRADC to measure battery and put value into HW_POWER_BATTMONITOR_BATT_VAL. Set up battery brownout code. HW_POWER_BATTMONITOR_EN _BATADJ=1 HW_POWER_STS_VDD5V_GT_VDDIO=1 Reset Do you want to reset or continue on a future plugin? HW_POWER_STS_ VDD5V_GT_VDDIO=1 (any instance) 5V Device Plugin (interrupt-driven event) Continue Do you want to reset or continue on a future unplug? Reset Set up IRQ for VDDIO5V plug in. HW_POWER_CTRL_POLARITY _VDD5V_GT_VDDIO=1 HW_POWER_CTRL_ENIRQ _VDD5V_GT_VDDIO=1 HW_POWER_5VCTRL_PWDN _5VBRNOUT=1 HW_POWER_5VCTRL _ENABLE_DCDC=1 HW_POWER_5VCTRL _PWDN_5VBRNOUT=0 Continue Configure* 5V unplug detection. HW_POWER_5VCTRL_DCDC_XFER=1 HW_POWER_5VCTRL_PWDN_5VBRNOUT=0 HW_POWER_BATTMONITOR_PWDN _BATTBRNOUT=1 HW_POWER_CTRL_ENIRQBATT_BO=1 HW_POWER_BATTMONITOR_PWDN _BATTBRNOUT=0 HW_POWER_5VCTRL _PWDN_5VBRNOUT=1 Application Note: See Section 32.3.2.1, "Battery Power to 5-V Power". Figure 32-2. Brownout Detection Flowchart i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-5 Power Supply 32.3 Linear Regulators The i.MX23 integrates four linear regulators that can be used to directly power the supply rails when 5 V is present. All of these regulators have an output impedance of approximately one-quarter ohm. This means that the measured output voltage will be slightly dependent on the current consumed on each supply. Architecturally, one regulator generates VDDIO from the VDD5V pin, one generates VDDA from VDDIO, one generates VDDM from VDDIO, and the other generates VDDD from the VDDA supply. Therefore, all of the current is supplied by the VDD5V->VDDIO regulator. In addition, the i.MX23 integrates a 4.2 V regulator enables the DCDC converter to run off the power supplied by 5 V. This allows DCDC converter operation when 5 V is present and the battery is exhausted. In addition, the path can provide better power consumption as compared to the other linear regulator generated supplies. a current limiter is implemented in series with the 4.2 V regulator and the battery supply. The intent is to limit the Ibattery plus I4P2 to be less than Ilimit. The 4.2 V regulator has priority on the current and will dynamically reduce the battery charge current in order to preserve the Ilimit and the regulated 4.2 V. It should also be noted that the VDD5V voltage can dynamically change as the product is plugged into a USB port or other 5-V supply. The i.MX23 is programmable to provide a variety of behaviors when the VDD5V supply becomes valid or invalid, as well as to support operation via USB or external power. 32.3.1 USB Compliance Features Upon connection of 5 V to the powered-down device, the linear regulators will automatically power up the device. To meet USB inrush specifications, linear regulators have a current limit which is <100 mA, nominally 50 mA, and is active by default. This current limit is disabled in hardware after power-up, but can be re-enabled via the HW_POWER_5VCTRL_ENABLE_ILIMIT by software. System designers must understand that the current inrush limit during 5-V power-up places restrictions on application current consumption until it is disabled. Specifically, after connection to 5V, if the system draws more current than the current limit allows, the startup sequence does not complete and the ROM code does not execute. Further, USB Host implies that B-devices must draw very little current from 5V. This requirement can be met by setting HW_POWER_5VCTRL_ILIMIT_EQ_ZERO when the Host application is active. The comparators required for Host capability can be enabled by HW_POWER_5VCTRL_PWRUP_VBUS_CMPS. It is also possible to change the threshold of the Vbus valid comparator using HW_POWER_5VCTRL_VBUSVALID_TRSH. If very low power operation is required, as in USB suspend, then the circuits required to elegantly switch to the DC-DC converter may have to be powered off. In those cases, the system must fully power down after VDD5V becomes invalid. It can auto restart with the DC-DC converter if HW_RTC_PERSISTENT0_AUTO_RESTART is set. i.MX23 Applications Processor Reference Manual, Rev. 1 32-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply 32.3.2 5V to Battery Power Interaction The i.MX23 supports several different options related to the interaction of the switching converters with the linear regulators. The two primary options are a reset on 5V insertion/removal or a handoff to the DC-DC converters that is invisible to the end-user of the application. Figure 32-3 includes these two options as the two system architecture decision boxes. 32.3.2.1 Battery Power to 5-V Power By default, the DC-DC converter turns off when VDD5V becomes valid and the system does not reset. If the system is operating from the DC-DC converter and using more current than the linear regulators can supply, then the VDDD, VDDA, and VDDIO rails will droop when 5V is attached and the system may brownout and shut down. To avoid this issue, set the ENABLE_DCDC bit and set the LINREG_OFFSET fields to 0b2 in anticipation of VDD5V becoming present. The ENABLE_DCDC bit will cause the DC-DC converter to remain on even after 5V is connected and, thus, guarantee a stable supply voltage until the system is configured for removal of 5V. The LINREG_OFFSET fields = 0b2 cause the linear regulators to regulate to a lower target voltage than the switching converter and prevent unwanted interaction between the two power supplies. After the system is configured for removal of 5V, ENABLE_DCDC can be set low and ENABLE_ILIMIT set low in register HW_POWER_5VCTRL to allow the linear regulators to supply the system power, if desired. 32.3.2.2 5-V Power to Battery Power Configuring the system for a 5-V-to-battery power handoff requires setup code to monitor the battery voltage as well as detect the removal of 5V. Monitoring the battery voltage is performed by the LRADC. Typically, this involves programming the LRADC registers to periodically monitor the battery voltage as described in Chapter 33, "Low-Resolution ADC and Touch-Screen Interface." The measured battery voltage should be written into the HW_POWER_BATTMONITOR register field BATT_VAL using the AUTOMATIC field in the HW_LRADC_CONVERSION register. Also, configuring battery brownout should be performed so that the system behaves as desired when 5V is no longer present and the battery is low. The recommended method to detect removal of 5V requires setting VBUSVALID_5VDETECT and programming the detection threshold VBUSVALID_TRSH to 0x1 in HW_POWER_5VCTRL. Next, in order to minimize linear regulator and DC-DC converter interaction, it is necessary to set the LINREG_OFFSET = 0b2 in the HW_POWER_VDDIOCTRL, HW_POWER_VDDACTRL, and HW_POWER_VDDDCTRL registers. Finally, set DCDC_XFER and clear PWDN_5VBRNOUT in the HW_POWER_5VCTRL register. This sequence is important because it is safe to disable the powerdown-on-unplug functionality of the device only after the system is completely ready for a transition to battery power. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-7 Power Supply 32.3.2.3 5-V Power and Battery Power Battery charge can also be enabled to provide additional power efficiency when connected to 5V. If the DCDC switching converter is also enabled, the buck switching converters will efficiently convert the battery voltage to the desired VDDA, VDDD, and VDDIO voltages (instead of using the less efficient internal linear regulators). 32.3.3 Power-Up Sequence The DC-DC converter controls the power-up and reset of the i.MX23. The power-up sequence begins when the battery is connected to the BATT pin of the device (or a 5V source is connected to the VDD5V pin). Either the BATT pin or VDD5V provides power to the DC-DC startup circuitry, the crystal oscillator, and the real-time clock. This means that the crystal oscillator can be running, if desired, whenever a battery is connected to BATT pin. This feature allows the real-time clock to operate when the chip is in the off state. The crystal oscillator/RTC is the only power drain on the battery in this state and consumes only a very small amount of power. During this time, the VDDIO, VDDD and VDDA supplies are held at ground. This is the off state that continues until the system power up begins. Power-up can be started with one of several events: * * * PSWITCH pin >= minimum MID level PSWITCH for 100 ms (see "Characteristics & Specifications" chapter) VDD5V power pin >= minimum VDD5V voltage for 100 ms (see "Characteristics & Specifications" chapter) Real-time clock alarm wakeup When a power-up event has occurred, if VDD5V is valid, then the on-chip linear regulators charge the VDDD, VDDA and VDDIO rails to their default voltages. If VDD5V is not valid, then the DC-DC supplies the VDDD, VDDA, and VDDIO rails. When the voltage rails have reached their target values, the digital logic reset is deasserted and the CPU begins executing code. If the power supplies do not reach the target values by the time PSWITCH is deasserted or 5V is removed, the system returns to the off state. The power-up time is dependent on the VDDD/VDDA/VDDIO load and battery or VDD5V voltage, but should be less than 100 ms. The VDDD//VDDAVDDIO load should be minimal during power up to ensure proper startup of the DC-DC converter. There is an integrated 5-K resistor that can be switched in between the VDDXTAL pin and PSWITCH. If enabled using HW_RTC_PERSISTENT0_AUTO_RESTART, then the device immediately begins the power-up sequence after power-down. i.MX23 Applications Processor Reference Manual, Rev. 1 32-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply 32.3.4 Power-Down Sequence Power-down is also controlled by the DC-DC converters. When the DC-DC converter detects a power-down event, it returns the player to the off state described above. The power-down sequence is started when one of these events occurs: * * * * HW_POWER_RESET_PWD bit set while the register is unlocked. Error condition occurs, as described in Section 32.2.1.1, "Brownout/Error Detection." The watchdog timer expires while enabled. Fast falling edge (<10 ns) on PSWITCH pin. The HW_POWER_RESET_PWD_OFF bit disables all power-down paths except for the watchdog timer when it is set. The lower 16 bits of the HW_POWER_RESET register can only be written if the value 0x3E77 is placed in the unlock field. An external capacitor on the PSWITCH can be used to prevent an unwanted power down due to falling edges. This can also be disabled in register HW_POWER_RESET_PWD_OFF. 32.3.4.1 Powered-Down State While the chip is powered down, the VDDIO, VDDD and VDDA rail are pulled down to ground. The crystal oscillator and the RTC can continue to operate by drawing power from the BATT pin. See Chapter 23, "Real-Time Clock, Alarm, Watchdog, Persistent Bits," for more information about operating a crystal and the RTC in the powered-down state. 32.3.5 Reset Sequence Figure 32-3 shows a flowchart for the power-up, power-down, and reset sequences. A reset event can be triggered by unlocking the HW_POWER_RESET register and setting the HW_CLKCTRL_RESET_DIG bit. This reset affects the digital logic only, although the digital logic also includes most of the registers that control the analog portions of the chip. The persistent bits within the RTC block and the power module control bits are not reset using this method. To reset the analog as well as the digital logic, set the HW_CLKCTRL_RESET_CHIP bit. The DC-DC converter and/or linear regulators continue to maintain the power supply rails during the reset. 32.4 PSWITCH Pin Functions The PSWITCH pin has several functions whose operation is determined by the i.MX23-based product's hardware and software design. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-9 Power Supply 32.4.1 Power On When the PSWITCH pin voltage is higher than the minimum MID level (as specified in Table 2-3., "Recommended Power Supply Operating Conditions") for >100 ms, the DC-DC converter begins its startup routine. This is the primary method of starting the system via PSWITCH. All products based on the i.MX23 must have a mechanism of bringing PSWITCH high to power up via an always-present supply (e.g, battery or VDDXTAL). 32.4.2 Power Down If the PSWITCH pin voltage has a falling edge faster than 15 ns, then this sends a power-down request to the DC-DC converter. The fast-falling-edge power-down may be blocked by the HW_POWER_RESET_PWD_OFF function. The fast-falling edge can also be prevented by placing an RC filter on the PSWITCH pin. Most i.MX23-based systems do not use the PSWITCH fast-falling-edge power-down and include the RC filter to prevent it from occurring accidentally. 32.4.3 Software Functions/Recovery Mode When the PSWITCH pin voltage is pulled up to the minimum MID level (as specified in Table 2-3., "Recommended Power Supply Operating Conditions") the lower HW_POWER_STS_PSWITCH bit is set. Software can poll this bit and perform a function as desired by the product designer. Example functions include a play/pause/power-down button, delay for startup, etc. When the PSWITCH pin is connected to VDDIO through a current limiting resistor, the upper HW_POWER_STS_PSWITCH bit is also set. If this bit is set for more than five seconds during ROM boot, the system executes the Freescale USB Firmware Recovery function, as described in Chapter 35, "Boot Modes." If the product designer does not wish to use Freescale USB Firmware Recovery, the product can be designed to not assert a voltage higher than the maximum MID level (as specified in Table 2-3., "Recommended Power Supply Operating Conditions") on the PSWITCH pin. Refer to the Freescale i.MX23 reference schematics for example configurations of the PSWITCH pin. i.MX23 Applications Processor Reference Manual, Rev. 1 32-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply Software-Controlled Resets Normal Power-Up Flow No Power No Battery, no 5V. Battery Insert or 5V_Detect=1 Power-On Reset (Clock and Persistent Bits Reset) To Power Down: Set HW_POWER_RESET_PW D State Zero (Persistent bits retain state, XTAL and clock active if enabled) For Cold Reboot: Set HW_RTC_PERSISTENT0_AUTO_RESTART then HW_POWER_RESET_PW D PSWITCH=1 or RTC Alarm or AUTO_RESTART=1 or 5V_DETECT=1 Power Up (Start XTAL if it's off, Start 5V Linear Regs if 5V Detect, else start DCDC converter) Power is Stable Start Digital Clocks (Digital Reset Asserted. Digital clocks all = 1 M Hz) To Reset DCDC and Digital: Set HW_CLKCTRL_RESET_CHIP To Reset Digital but not DCDC (warm boot): Set HW_CLKCTRL_RESET_DIG Reset DCDC PIO Registers (All non-persistent flop resets asserted, Note that the DCDC continues to operate even if the PIO registers are reset. Digital clocks all = 1 MHz) Reset Non-DCDC Digital Registers (Non persistent and non-POW ER flop resets asserted. Digital clocks all = 1 MHz) W ait 16 cycles for all resets to propogate Release Reset (Digital clock domains at default frequency and gating, boot CPU ) Figure 32-3. Power-Up, Power-Down, and Reset Flow Chart i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-11 Power Supply 32.5 Battery Monitor The power control system includes a battery monitor. The battery monitor has two functions: battery brownout detection and battery voltage feedback to the DC-DC converter. If the battery voltage drops below the programmable brownout, then a fast interrupt (FIQ) can be generated for the CPU. Software typically uses the LRADC to monitor the battery voltage and shut down elegantly while there is a minimal operating margin. But, if an unexpected event (such as a battery removal) occurs, then the system needs to be placed immediately in the off state to ensure that it can restart properly. The brownout is controlled in the HW_POWER_BATTMONITOR register. The IRQ must also be enabled in the interrupt collector. To enable optimum performance over the battery range, the DC-DC converter needs to be provided with the battery voltage, which is measured by the battery pin LRADC. Normally, LRADC channel 7 is dedicated to periodically measuring the battery voltage with a period in the millisecond range for most applications. The voltage is automatically placed into the BATT_VAL field of the HW_POWER_BATTMONITOR register via the HW_LRADC_CONVERSION register. If necessary, software can turn off the automatic battery voltage update and set the BATT_VAL field manually. 32.6 Battery Charger The battery charger is essentially a linear regulator that has current and voltage limits. Charge current is software-programmable within the HW_POWER_CHARGE register. The maximum Li-Ion battery charge current will be the lower of 1C, 785 mA, or the VDD5V current limit. USB charging is typically limited to 500 mA or less to meet compliance requirements. Also, battery charge current will be automatically reduced if the current demands from VDD4P2 and the battery charger exceed the CHARGE_4P2_ILIMIT. Full battery charge current will be restored once the VDD4P2 + battery charge current falls below the CHARGE_4P2_ILIMIT value. Typical charge times for a Li-Ion battery are 1.5 to 3 hours with >70% of the charge delivered in the first hour. The battery charge voltage limit is 4.2 V for the Li-Ion batteries. The Li-Ion charge is typically stopped after a certain time limit OR when the charging current drops below 10% of the charge current setting. The HW_POWER_CHARGE register includes controls for the maximum charge current and for the stop charge current. While the charger is delivering current greater than the stop charge limit, the HW_POWER_STS_CHRGSTS bit will be high. This bit should be polled (a low rate of 1 second or greater is fine) during charge. When the bit goes low, the charging is complete. It would be good practice to check that this bit is low for two consecutive checks, as the DC-DC switching might cause a spurious "low" result. Once this bit goes low, the charger can either be stopped immediately or stopped after a "top-off" time limit. Although the charger will avoid exceeding the charge i.MX23 Applications Processor Reference Manual, Rev. 1 32-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply voltage limit on the battery, it is NOT recommended to leave the charger active indefinitely. It should be turned off when the charge is complete. One can programatically monitor the battery voltage using the LRADC. The charger has its own (very robust) voltage limiting that operates independently of the LRADC. But monitoring the battery voltage during the charge might be helpful for reporting the charge progress. The battery charger is capable of generating a large amount of heat within the i.MX23, especially at currents above 400 mA. The dissipated power can be estimated as: (5V - battery_volt) * current. At max current (785 mA) and a 3-V battery, the charger can dissipate 1.57 W on chip, which can cause a dramatic increase in the die temperature. To ensure that the system operates correctly, the die temperature sensor should be monitored periodically (every 100 ms is recommended). If the die temperature exceeds (or closely approaches) the maximum junction temperature in the Characteristics and Specifications chapter, then the battery charge current should be reduced. The LRADC can also be used to monitor the battery temperature or chip temperature. There is an integrated current source for the external temperature sensor that can be configured and enabled via HW_LRADC_CTRL2 register. 32.7 Silicon Speed Sensor The i.MX23 integrates a silicon speed sensor to measure the performance characteristics of an individual die at its ambient temperature and process parametrics. It consists of a ring oscillator and a frequency counter. The ring oscillator runs on the VDDD power rail. Therefore, its frequency tracks the silicon performance as it changes in response to changes in operating voltage and temperature. The crystal oscillator is directly used as the precision time base for measuring the frequency of a ring oscillator. The ring oscillator is normally disabled. There is a 8-bit counter connected to the ring oscillator that performs the frequency measurement. See the HW_POWER_SPEED register. Thus, the counter holds the number of cycles the ring oscillator was able to generate during one crystal clock period. The natural frequency of the ring oscillator strongly tracks the silicon process parametrics, i.e., faster silicon processes yield ring oscillators that run faster and thereby yield larger count values. The natural frequency tracks junction temperature effects on silicon speed as well. The information given by the speed sensor can be used with the silicon temperature and process parameters, which can also be monitored by system software. Freescale can provide a power management application note and firmware that takes full advantage of the on-chip monitoring functions to enable minimum-voltage operation. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-13 Power Supply 32.8 Interrupts The power system supports nine CPU interrupt events that are programmable within the HW_POWER_CTRL register. The interrupts are listed in Table 32-1. Table 32-1. Power System Interrupts HW_POWER_CTRL Interrupt Bit Description VDDA_BO_IRQ VDDD_BO_IRQ VDDIO_BO_IRQ BATT_BO_IRQ VDD5V_GT_VDDIO_IRQ DC_OK_IRQ VBUSVALID_IRQ LINREG_OK_IRQ PSWITCH_IRQ VDDA Brownout VDDD Brownout VDDIO Brownout Battery Brownout VDD5V > (VDDIO + 0.6) Voltage Supplies Ok after target voltage change VDD5V > Vbusvalid Threshold Debug use only PSWITCH Status The VDDA_BO_IRQ, VDDD_BO_IRQ, VDDIO_BO_IRQ, and BATT_BO_IRQ each have their own interrupt line back to the interrupt collector. However, the remaining five interrupts--VDD5V_GT_VDDIO_IRQ, DC_OK_IRQ, VBUSVALID_IRQ, LINREG_OK_IRQ, and PSWITCH_IRQ--all share a single interrupt line. In this case, software must read the interrupt status bits to discover which event caused the interrupt. 32.9 Proper Power Supply Protection To fully comprehend this section, first read the above power supply sections which discuss the basic operation of the power supply and Chapter 3 "Characteristics and Specifications" which provides the operational limits of the integrated DC-DC converter and power supply. Great care must be taken when programming of the internal PMU to ensure proper protection and operation. The integrated power supply provides undervoltage-protection mechanisms on the input and output voltage rails. The power supply does not provide overcurrent protection with the exception of the VDD4P2 rail. The LRADC peripheral can be used to take die temperature measurements and external thermistor measurements which software can monitor for further system protection against overheating. The RTC peripheral's watchdog functionality can be used to monitor the health of the processor to guarantee software reliability. 32.9.1 Power Supply Protection Goal The primary goal of the power supply system protection should be to keep both the supply input voltages and the regulated output voltages within their proper operational limits. Voltages outside these limits could result in undefined behavior. When voltages outside the limits are detected, the device should be i.MX23 Applications Processor Reference Manual, Rev. 1 32-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply completely shut down. Proper protection of the power supply input voltage requires at least one supply source to be within its valid operating voltage range. 32.9.2 Power Supply Input Voltage Protection On boot up, the PWDN_BATTBRNOUT and the PWDN_5VBRNOUT functions are enabled by default to allow hardware the ability to shutdown the device in the case of a battery or 5V supply brownout, respectively. After the system is booted and initialized, these hardware protection functionalities are commonly replaced by software protection mechanisms and then disabled. For example, PWDN_5VBRNOUT is disabled once sufficient battery voltage is available and the 5V-to-Battery transfer has been properly configured. PWDN_BATTBRNOUT is disabled and replaced by a battery brownout FIQ handler. To ensure proper power supply operation, the developer must take great care to ensure proper protection of the system by using software interrupts to handle supply and output rail brownouts. Detailed knowledge of the power supply behavior is necessary to achieve proper coordination of the protection functionalities of the supply. 32.9.3 PWDN_BATTBRNOUT and PWDN_5VBRNOUT Details The hardware battery brownout shutdown functionality is only enabled when PWDN_BATTBRNOUT is set and when the chip's 5V status is false. This allows the hardware to keep this register bit enabled by default and still allow 5V to boot up the device when the battery is completely discharged. Then the application can start and charge the battery. Note the PWDN_BATTBRNOUT only uses the VDD5V_GT_VDDIO 5V detection method to determine 5V status. The hardware 5V brownout shutdown functionality is only enabled after the VDD5V voltage has reached the 5V connection voltage threshold. The threshold is established by the 5V detection method and in the case of VBUSVALID, can be configured by firmware. This allows the PWDN_5VBRNOUT bit to be enabled by default in hardware while still booting a device from battery when 5V is not present. It is necessary to keep the PWDN_5VBRNOUT and PWD_BATTBRNOUT behavior details in mind to understand how these functionalities can affect the system protection implementation. 32.9.4 VDD5V Input Protection The integrated power supply has two methods for determining the 5V connection status of the chip: VBUSVALID and VDD5V_GT_VDDIO. Software can poll status bits to determine 5V connection status for either or both of these methods. The hardware can only use one of the 5V detection methods and the choice is programmed via the VBUSVALID_5VDETECT bit. Note the PWDN_BATTBRNOUT functionality always uses VDD5V_GT_VDDIO to determine 5V status regardless of the VBUSVALID_5VDETECT setting. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-15 Power Supply On boot up, the hardware defaults to the VDD5V_GT_VDDIO 5V detection method. Even though it is the default, VDD5V_GT_VDDIO is only intended as the chip startup 5V detection method. Firmware should immediately switch to the VBUSVALID detection method to avoid some potential issues. First, the VDD5V_GT_VDDIO method depends on a fixed offset between VDDIO and the VDD5V voltage. So the VDD5V_GT_VDDIO status will change as the VDDIO level changes. Second, as with any linear regulator, the VDDIO linear regulator supply strength is based upon its supply voltage which is VDD5V. As the VDD5V level decreases, the VDDIO supply strength decreases. So if the VDDIO rail has too much load and the VDD5V level decreases, the VDDIO output voltage can decrease as well. If the VDDIO voltage drops with VDD5V, then a scenario arises where VDD5V_GT_VDDIO never becomes false. One method for countering this scenario is to enable and properly handle VDDIO brownouts. But this brings other complications such as causing the device to shutdown on a 5V disconnect when it could have performed a 5V-to-battery transfer, or having to add functionality to the VDDIO interrupt handler to determine whether a brownout was caused by a 5V disconnect. To avoid these issues with the VDD5V_GT_VDDIO functionality, the hardware should be programmed to use the VBUSVALID functionality for detecting 5V by setting VBUSVALID_5VDETECT. But, great care must be taken to coordinate this change properly. Remember the PWD_BATTBRNOUT functionality always uses VDD5V_GT_VDDIO as an internal enable/disable mechanism. A problem can occur when the 5V detection is changed from VDD5V_GT_VDDIO to VBUSVALID if the VDD5V_GT_VDDIO status is true but VBUSVALID status is false due to the VBUSVALID_TRSH level selected. In this case, VDD5V level is higher than the set threshold. A false VBUSVALID will register as a 5V disconnection. A hardware 5V disconnection event causes the DCDC to automatically turn on regardless of the battery voltage level. This could result in the DCDC operating from a voltage lower than the minimum operating voltage specified in the Characteristics and Specifications section and physical damage to the DCDC converter itself. To avoid this situation, follow these rules. * * Before switching to VBUSVALID detection method, ensure the VDD5V voltage level is higher than the VBUSVALID_TRSH level. When raising the VBUSVALID_TRSH from one level to another, be sure that the VDD5V is higher than the target threshold level being programmed. In addition to the power supply 5V detection methods, VDD5V voltage measurements can be taken by the LRADC peripheral. 32.9.5 DCDC Input Protection The DCDC converter must only be allowed to operate within the valid operational range provided in the "Characteristics and Specifications" section of the datasheet. Failure to do so could result in damage to the DCDC converter. i.MX23 Applications Processor Reference Manual, Rev. 1 32-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply As mentioned above, PWD_BATTBRNOUT is the hardware protection mechanism for shutting down the device if the VBATT rail voltage falls too low during DCDC activity. This hardware mechanism can be disabled and replaced with a software FIQ mechanism. The FIQ handler can then take the appropriate action such as shutting down the device. The VDD4P2 rail must also be protected so that the DCDC gets a valid input voltage. To do this, configure the system to shutdown on a VDD4P2 brownout FIQ if battery voltage is insufficient. 32.9.6 DCDC Output Protection The output rails voltage brownout functionality provides both software FIQ handling and automatic hardware shutdown to protect against undervoltage events. The software FIQ handling provides flexibility on what actions are taken when a brownout is detected, but it is vulnerable to software problems that could lead to it not functioning as intended. Also, the time needed to handle the brownout will be greater than if the automatic hardware brownouts are used. 32.9.7 PWD_OFF Bit Usage Some applications set the PWD_OFF bit in an attempt to raise the ESD tolerance level, but the PWD_OFF bit disables all automatic hardware shutdown functions. Before setting the PWD_OFF bit, all hardware power supply protections for input and output power rails must be replaced by a software FIQ mechanism. 32.9.8 Power Supply Protection Summary Given the above information, here are some basic rules to follow: 1. Never allow the power supply to operate from an input source that is not at a sufficient voltage level * When a 5V disconnection event is detected, the DCDC automatically attempts to operate from the battery source. To avoid the possibility of causing the DCDC to start sourcing from a voltage that is below its specified minimum operating voltage, the PWDN_5VBRNOUT (or similar software FIQ functionality) must remain active until the battery has sufficient charge and the 5V-to-battery transfer has been enabled. * The switch from VDD5V_GT_VDDIO to VBUSVALID 5V detection method can cause a 5V disconnected hardware status event if not handled properly. * Never manually enable the DCDC in software while the battery voltage or VDD4P2 voltage is too low. Also ensure battery voltage and VDD4P2 protection mechanisms are enabled prior to enabling the DCDC. 2. Shutdown the device if the regulated output voltage rails fall below the brownout level. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-17 Power Supply 3. Proper power supply protection and operation can depend on immediate FIQ handling of power supply events. * When depending on FIQ handlers for proper system protection and operation, never disable FIQ handling. * FIQ handling code and the context the FIQ runs in should be located in OCRAM for fastest and most reliable operation. When enabling virtual memory, take care to not require a page table walk that would cause an external memory access. In many applications, it is sometimes necessary to disable the external memory access or vastly reduce its performance. Special fixed TLB cache entries exist in the ARM926ej-s core to allow the lockdown of particular page entries which can be used to avoid a page table access. 32.10 DC-DC Converter Efficiency Graphs showing estimates of typical efficiencies of the DC-DC converter under nominal conditions will be provided after silicon is validated and characterized. 32.11 Programmable Registers 32.11.1 Power Control Register Description The Power Control Register contains control bits specific to the digital section. HW_POWER_CTRL HW_POWER_CTRL_SET HW_POWER_CTRL_CLR HW_POWER_CTRL_TOG Table 32-2. HW_POWER_CTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 ENIRQ_VDD5V_DROOP 0x000 0x004 0x008 0x00C 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 POLARITY_VBUSVALID 0 4 0 3 0 2 POLARITY_VDD5V_GT_VDDIO 0 1 VDD5V_GT_VDDIO_IRQ 0 0 ENIRQ_VDD5V_GT_VDDIO ENIRQ_DCDC4P2_BO PSWITCH_MID_TRAN POLARITY_PSWITCH i.MX23 Applications Processor Reference Manual, Rev. 1 32-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor ENIRQ_VBUS_VALID VDD5V_DROOP_IRQ PSWITCH_IRQ_SRC POLARITY_DC_OK DCDC4P2_BO_IRQ ENIRQ_VDDIO_BO ENIRQ_VDDA_BO ENIRQ_VDDD_BO ENIRQ_PSWITCH VBUSVALID_IRQ ENIRQBATT_BO VDDIO_BO_IRQ VDDA_BO_IRQ VDDD_BO_IRQ ENIRQ_DC_OK BATT_BO_IRQ PSWITCH_IRQ DC_OK_IRQ CLKGATE RSRVD3 RSRVD2 RSRVD1 Power Supply Table 32-3. HW_POWER_CTRL Bit Field Descriptions BITS LABEL 31 RSRVD3 30 CLKGATE RW RESET RO 0x0 RW 0x1 DEFINITION 29:28 RSRVD2 27 PSWITCH_MID_TRAN RO 0x0 RW 0x0 26:25 RSRVD1 24 DCDC4P2_BO_IRQ RO 0x0 RW 0x0 23 22 ENIRQ_DCDC4P2_BO VDD5V_DROOP_IRQ RW 0x0 RW 0x0 21 20 ENIRQ_VDD5V_DROOP PSWITCH_IRQ RW 0x0 RW 0x0 19 18 17 PSWITCH_IRQ_SRC POLARITY_PSWITCH ENIRQ_PSWITCH RW 0x0 RW 0x0 RW 0x0 16 15 POLARITY_DC_OK DC_OK_IRQ RW 0x1 RW 0x0 14 13 ENIRQ_DC_OK BATT_BO_IRQ RW 0x0 RW 0x0 12 11 ENIRQBATT_BO VDDIO_BO_IRQ RW 0x0 RW 0x0 Empty Description. This bit must be set to zero for normal operation. When set to one, it gates off the clocks to the block. This bit has no effect on the RTC analog section. Empty Description. When this bit is set, it selects the from-mid-transition interrupt functionality for PSWITCH. When set, in conjuction with ENIRQ_PSWITCH, it will set PSWITCH_IRQ when either a 01 to 11 or 01 to 00 transition is detected on the PSWITCH comparators. When this bit is set, PSWITCH_IRQ_SRC and POLARITY_PSWITCH have no effect. Empty Description. Interrupt Status for 4P2_BO. Reset this bit by writing a one to the SCT clear address space and not by a general write. Enable interrupt for 4P2_BO. Interrupt Status for VDD5V_DROOP. Reset this bit by writing a one to the SCT clear address space and not by a general write. Enable interrupt for VDD5V_DROOP. Interrupt status for PSWITCH signals. Interrupt polarity is set using POLARITY_PSWITCH. Comparator bit is selected via PSWITCH_IRQ_SRC. Reset this bit by writing a one to the SCT clear address space and not by a general write. Set to 1 to use HW_POWER_STS_PSWITCH bit 1 as source, 0 for HW_POWER_STS_PSWITCH bit 0 Set to 1 to interupt when the interrupt source is high, 0 for low Interrupt status for PSWITCH signal. Interrupt polarity is set using POLARITY_PWITCH and source selected by PSWITCH_SRC. Debug use only. Set to 1 to check for linear regulators ok. Set to 0 to check for 5V disconnected. Interrupt Status for DC_OK. Reset this bit by writing a one to the SCT clear address space and not by a general write. The IRQ will be asserted when switching DC-DC converter control loop has stabilized after a voltage target change. When linear regulators are active, interrupt will get asserted when the actual voltage is above the target voltage. Therefore, DC_OK_IRQ will assert when changing a linear regulator output to a lower value before the actual voltage decreases to the new target value. Enable interrupt for DC_OK. Interrupt Status for BATT_BO. Reset this bit by writing a one to the SCT clear address space and not by a general write. Enable interrupt for battery brownout. Interrupt Status for VDDIO_BO. Reset this bit by writing a one to the SCT clear address space and not by a general write. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-19 Power Supply Table 32-3. HW_POWER_CTRL Bit Field Descriptions BITS LABEL 10 ENIRQ_VDDIO_BO 9 VDDA_BO_IRQ RW RESET RW 0x0 RW 0x0 DEFINITION Enable interrupt for VDDIO brownout. Interrupt Status for VDDA_BO. Reset this bit by writing a one to the SCT clear address space and not by a general write. Enable interrupt for VDDA brownout. Interrupt Status for VDDD_BO. Reset this bit by writing a one to the SCT clear address space and not by a general write. Enable interrupt for VDDD brownout. Set to 1 to check for 5V connected using VBUSVALID status bit. Set to 0 to check for 5V disconnected. Interrupt status for VBUSVALID signal. Interrupt polarity is set using POLARITY_VBUSVALID. Reset this bit by writing a one to the SCT clear address space and not by a general write. Enable interrupt for 5V detect using VBUSVALID. Set to 1 to check for 5V connected. Set to 0 to check for 5V disconnected. Interrupt status for VDD5V_GT_VDDIO signal. Interrupt polarity is set using POLARITY_VDD5V_GT_VDDIO. Reset this bit by writing a one to the SCT clear address space and not by a general write. Enable interrupt for 5V detect. 8 7 ENIRQ_VDDA_BO VDDD_BO_IRQ RW 0x0 RW 0x0 6 5 4 ENIRQ_VDDD_BO POLARITY_VBUSVALID VBUSVALID_IRQ RW 0x0 RW 0x1 RW 0x0 3 2 1 ENIRQ_VBUS_VALID RW 0x0 POLARITY_VDD5V_GT_VDDI RW 0x1 O VDD5V_GT_VDDIO_IRQ RW 0x0 0 ENIRQ_VDD5V_GT_VDDIO RW 0x0 DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.2 DC-DC 5V Control Register Description This register contains the configuration options of the power management subsystem that are available when external 5V is applied. HW_POWER_5VCTRL HW_POWER_5VCTRL_SET HW_POWER_5VCTRL_CLR HW_POWER_5VCTRL_TOG 0x010 0x014 0x018 0x01C i.MX23 Applications Processor Reference Manual, Rev. 1 32-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply Table 32-4. HW_POWER_5VCTRL 3 1 3 0 2 9 VBUSDROOP_TRSH 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 PWD_CHARGE_4P2 1 9 1 8 1 7 1 6 1 5 CHARGE_4P2_ILIMIT 1 4 1 3 1 2 1 1 1 0 0 9 VBUSVALID_TRSH 0 8 0 7 PWDN_5VBRNOUT 0 6 ENABLE_LINREG_ILIMIT 0 5 0 4 VBUSVALID_5VDETECT 0 3 VBUSVALID_TO_B 0 2 0 1 PWRUP_VBUS_CMPS 0 0 HEADROOM_ADJ ILIMIT_EQ_ZERO Table 32-5. HW_POWER_5VCTRL Bit Field Descriptions BITS LABEL 31:30 RSRVD6 29:28 VBUSDROOP_TRSH RW RESET RO 0x0 RW 0x0 DEFINITION Empty Description. Set the threshold for the VBUSDROOP comparator. This comparator should typically be programmed at least 200mV above VVBUSVALID, and can be used to terminate battery charge when the voltage on VDD5V falls below the programmed threshold. This comparator has ~50mV of hystersis to prevent chattering at the comparator trip point. 00: 4.3V 01: 4.4V 10: 4.5V 11: 4.7V Empty Description. Adjustment to optimize the performance of the battery charge and 4.2V regulation circuit at low 5v voltages. Empty Description. Controls the power down of both the battery charger and 4.2V regulation circuit. Default is powered down. Empty Description. Limits the combined current from 5V that the battery charger and DCDC_4P2 circuit consume. Current represented by each bits is as follows: (400 mA, 200 mA, 100 mA, 50 mA, 20 mA, 10 mA) = (bit 5,bit 4, bit 3, bit 2, bit 1, bit 0). The DCDC_4P2 circuit is given priority as the sum of the currents exceeds the limit. Empty Description. RSRVD5 27 26:24 HEADROOM_ADJ RO 0x0 RW 0x0 RO 0x0 RW 0x1 RO 0x0 RW 0x00 23:21 RSRVD4 20 PWD_CHARGE_4P2 19:18 RSRVD3 17:12 CHARGE_4P2_ILIMIT 11 RSRVD2 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice ENABLE_DCDC DCDC_XFER RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 32-21 Power Supply Table 32-5. HW_POWER_5VCTRL Bit Field Descriptions BITS LABEL 10:8 VBUSVALID_TRSH RW RESET RW 0x0 DEFINITION Set the threshold for the VBUSVALID comparator. This comparator is the most accurate method to determine the presence of 5v, and includes hystersis to minimize the need for software debounce of the detection. This comparator has ~50mV of hystersis to prevent chattering at the comparator trip point. 000: 2.9V 001: 4.0V 010: 4.1V 011: 4.2V 100= 4.3V 101: 4.4V 110: 4.5V 111: 4.6V The purpose of this bit is to power down the device if 5V is removed before the system is completely initialized. Clear this bit to disable automatic hardware powerdown AFTER the system is configured for 5v removal. This bit should not be set if DCDC_XFER is set. Enable the current limit in the linear regulators. The current limit is active during powerup from 5v and automatically disables before the ROM executes. This limit is needed to meet the USB in rush current specification of 100mA + 50uC. Note this linear regulator current limit is not related to the CHARGE_4P2_ILIMIT. Enable automatic transition to switching DC-DC converter when VDD5V is removed. The LRADC must be operational and the BATT_VAL field must be written with the battery voltage using 8-mV step-size. It is also important to set the EN_BATADJ field. Power up and use VBUSVALID comparator as detection circuit for 5V in the switching converter. Default is for the switching converter to use the VDD5V_GT_VDDIO status bit to determine the presence of 5V in the system. The VBUSVALID comparator provides a more accurate and adjustable threshold to determine the presence of 5V in the system, and is the recommended method of detecting 5V. This bit muxes the Bvalid comparator to the VBUSVALID comparator and is used for test purposes only. The amount of current the device will consume from the 5V rail is minimized. The VDDIO linear regulator current limit is set to zero mA. Also, the source of current for the crystal oscillator and RTC is switched to the battery. Note that this functionality does not affect battery charge. 7 PWDN_5VBRNOUT RW 0x1 6 ENABLE_LINREG_ILIMIT RW 0x0 5 DCDC_XFER RW 0x0 4 VBUSVALID_5VDETECT RW 0x0 3 VBUSVALID_TO_B RW 0x0 2 ILIMIT_EQ_ZERO RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 32-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply Table 32-5. HW_POWER_5VCTRL Bit Field Descriptions BITS LABEL 1 PWRUP_VBUS_CMPS 0 ENABLE_DCDC RW RESET RW 0x0 RW 0x0 DEFINITION Powers up comparators for 5v Enables the switching DC-DC converter when 5V is present. It is recommended to set ILIMIT_EQ_ZERO, ENABLE_ILIMIT, and all LINREG_OFFSET bits when enabling this functionality. DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.3 DC-DC Minimum Power and Miscellaneous Control Register Description This register controls options to drop the power used by the switching DC-DC converter. These bits should only be modified with guidance from Freescale. HW_POWER_MINPWR HW_POWER_MINPWR_SET HW_POWER_MINPWR_CLR HW_POWER_MINPWR_TOG Table 32-6. HW_POWER_MINPWR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 LOWPWR_4P2 0x020 0x024 0x028 0x02C 1 3 VDAC_DUMP_CTRL 1 2 1 1 USE_VDDXTAL_VBG 1 0 PWD_ANA_CMPS 0 9 ENABLE_OSC 0 8 0 7 0 6 DOUBLE_FETS 0 5 0 4 0 3 0 2 DC_STOPCLK 0 1 0 0 DC_HALFCLK SELECT_OSC PWD_XTAL24 Table 32-7. HW_POWER_MINPWR Bit Field Descriptions BITS LABEL 31:15 RSRVD1 14 LOWPWR_4P2 RW RESET RO 0x0 RW 0x0 DEFINITION 13 VDAC_DUMP_CTRL RW 0x0 12 PWD_BO RW 0x0 Empty Description. Enable low power regulation of DCDC_4P2 limited to 2.5mA. This bit should always be set to 0. Dumps extra Video DAC current into the VDDD supply rail only when the VDDD supply voltage is below it's target value and XX bit is set. Default is to always dump the current to VDDD when XX bit is set. Powers down supply brownout comparators. This should only be used when monitoring supply brownouts is not needed. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice EN_DC_PFM HALF_FETS LESSANA_I VBG_OFF PWD_BO RSRVD1 32-23 Power Supply Table 32-7. HW_POWER_MINPWR Bit Field Descriptions BITS LABEL USE_VDDXTAL_VBG 11 RW RESET RW 0x0 DEFINITION Change the reference used in the dcdc converter to a low power, less accurate reference. This should only be used when achieving minimum system power is more important than supply voltage accuracy. Powers down analog comparators used in the power module, including the VDD and VDDA brownout comparators, low power reference. This bit should only be set to reach absolute minimum system power when running from the linear regulators and supply accuracy and VDDD/VDDA brownout detection is not important. Enables the internal oscillator. This oscillator is less accurate , but lower power than the 24mhz xtal. Switch internal 24mhz clock reference to the less accurate internal oscillator. This bit should be set only when accuracy of the 24mhz clock is not important. The value of this bit should only be changed when ENABLE_OSC=1 and PWD_XTAL24=0. Powers down the bandgap reference. This should only be used in 5v-powered applications when absolute minimum power is more important than supply voltage accuracy. USB_I_SUSPEND must be set before this bit is set. Approximately doubles the size of power transistors in DC-DC converter. This maybe be useful in high power conditions. Disable half the power transistors in DC-DC converter. This maybe be useful in low-power conditions when the increased resistance of the power FETs is acceptable. Reduce DC-DC analog bias current 20%. This bit is intended to reduce power in low-performance operating modes, such as USB suspend. Powers down the 24mhz oscillator, even when the system is still operating. This can be used with ENABLE_OSC and SELECT_OSC to reduce current in usb suspend and other low power modes where the accuracy of the clock is not important. Stop the clock to internal logic of switching DC-DC converter. This bit will take effect only after the switching FETs are off, due to battery configuration, PFM mode, or internal linear regulator operation. Forces DC-DC to operate in a Pulse Frequency Modulation mode. Intended to allow minimum system power in very low-power configurations when increased ripple on the supplies is acceptable. Also, HYST_SIGN in HW_POWER_LOOPCTRL should be set high when using PFM mode. Slow down DC-DC clock from 1.5 MHz to 750 kHz. This maybe be useful to improve efficiency at light loads or improve EMI radiation, although peak-to-peak voltage on the supplies will increase. 10 PWD_ANA_CMPS RW 0x0 9 8 ENABLE_OSC SELECT_OSC RW 0x0 RW 0x0 7 VBG_OFF RW 0x0 6 DOUBLE_FETS RW 0x0 5 HALF_FETS RW 0x0 4 LESSANA_I RW 0x0 3 PWD_XTAL24 RW 0x0 2 DC_STOPCLK RW 0x0 1 EN_DC_PFM RW 0x0 0 DC_HALFCLK RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 32-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.4 Battery Charge Control Register Description This register cotrols the battery charge features for both NiMH slow charge and Li-Ion charge. HW_POWER_CHARGE HW_POWER_CHARGE_SET HW_POWER_CHARGE_CLR HW_POWER_CHARGE_TOG Table 32-8. HW_POWER_CHARGE 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 ENABLE_CHARGER_RESISTORS 0x030 0x034 0x038 0x03C 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ENABLE_FAULT_DETECT PWD_BATTCHRG CHRG_STS_OFF ENABLE_LOAD Table 32-9. HW_POWER_CHARGE Bit Field Descriptions BITS LABEL 31:27 RSVD5 26:24 ADJ_VOLT RW RESET RO 0x0 RW 0x0 DEFINITION Empty Description. Adjustments to the final LiIon final voltage. These bits shouldn't be set unless recommended by Freescale. 0b000: no change 0b001: -0.25% 0b010: +0.50% 0b011: -0.75% 0b100: +0.25% 0b101: -0.50% 0b110: +0.75% 0b111: -1.00% Empty Description. Enable 100ohm load on the regulated 4.2V output. This bit shouldn't be set unless recommended by Freescale. 23 22 RSRVD3 ENABLE_LOAD RW 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice BATTCHRG_I STOP_ILIMIT ADJ_VOLT RSRVD3 RSVD4 RSVD3 RSVD2 RSVD5 RSVD1 32-25 Power Supply Table 32-9. HW_POWER_CHARGE Bit Field Descriptions BITS LABEL RW RESET 21 ENABLE_CHARGER_RESIST RW 0x0 ORS DEFINITION Enable 125k pullup on USB_DP and 375k on USB_DN to provice USB_CHARGER functionality. This functionality is a new USB spec and should not be enabled unless recommended by Freescale. Enable fault detection in the battery charger. When enabled, this bit will power down the battery charger when the VDD5V voltage falls below the battery voltage. The fault can be cleared by cycling PWD_CHARGE_4P2. The fault detection is visible via HW_POWER_STS_VDD5V_FAULT. Setting this bit disables the CHRGSTS status bit. Disabling CHRGSTS should only be done when the switching converter is enabled during battery charge if noise from the switching converter causes CHRGSTS to toggle excessively. Program this field to 0x0. Empty Description. Power-down the battery charge circuitry. This should only be set low when 5V is present Empty Description. Current threshold at which the Li-Ion battery charger signals to stop charging. The current represented by each bits is as follows: (100 mA, 50 mA, 20 mA, 10 mA) = (bit 3, bit 2, bit 1, bit 0) It is recommended to set this value to 10% of the charge current. Empty Description. Magnitude of the battery charge current, the current represented by each bits is as follows: (400 mA, 200 mA, 100 mA, 50 mA, 20 mA, 10 mA) = (bit 5,bit 4, bit 3, bit 2, bit 1, bit 0) 20 ENABLE_FAULT_DETECT RW 0x0 19 CHRG_STS_OFF RW 0x0 18 17 16 RSVD4 RSVD3 PWD_BATTCHRG RW 0x0 RO 0x0 RW 0x1 RO 0x0 RW 0x0 15:12 RSVD2 11:8 STOP_ILIMIT 7:6 5:0 RSVD1 BATTCHRG_I RO 0x0 RW 0x00 DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.5 VDDD Supply Targets and Brownouts Control Register Description This register controls the voltage targets and brownout targets for the VDDD supply generated from the switching DC-DC converter and integrated linear regulators. The brownout comparators default enabled. HW_POWER_VDDDCTRL 0x040 i.MX23 Applications Processor Reference Manual, Rev. 1 32-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply Table 32-10. HW_POWER_VDDDCTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 PWDN_BRNOUT 2 2 DISABLE_STEPPING 2 1 ENABLE_LINREG 2 0 DISABLE_FET 1 9 1 8 1 7 LINREG_OFFSET 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BO_OFFSET RSRVD4 RSRVD3 RSRVD2 RSRVD1 ADJTN Table 32-11. HW_POWER_VDDDCTRL Bit Field Descriptions BITS 31:28 ADJTN LABEL RW RESET RW 0x0 DEFINITION Two's complement number that can be used to adjust the duty cycle of VDDD. This is intended for test purposes only Empty Description. Powers down the device after the DC-DC converter completes startup if a VDDD brownout occurs. This function is only active when 5V is not present. Additionally, software should clear this bit and disable this function after the system is configured for a VDDD brownout and the VDDD brownout interrupt is enabled. Disables the default behavior of the voltage stepping algorithm when the TRG field is updated. By default, the control loop steps sequentially through 25mV steps on both target and brownout voltage to minimize transients during TRG adjustments. When this bit is set, the entire target voltage and brownout adjustment takes place at one time, which will speed transitions, but will result in increased supply transients as well as possible brownouts when the new (TRG - BO_OFFSET) >= old TRG. Thus, it is recommended to change TRG by less than the (BO_OFFSET-2) value when using DISABLE_STEPPING. This bit should be set high when powering VDDD from the integrated linear regulators. Enables the VDDD linear regulator converter when the switching converter is active. By default, the linear regulator is not active when the switching converter is active. Disable the VDDD switching converter output. Empty Description. 27:24 RSRVD4 23 PWDN_BRNOUT RO 0x0 RW 0x0 22 DISABLE_STEPPING RW 0x0 21 ENABLE_LINREG RW 0x1 DISABLE_FET 20 19:18 RSRVD3 RW 0x1 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice TRG 32-27 Power Supply Table 32-11. HW_POWER_VDDDCTRL Bit Field Descriptions BITS LABEL 17:16 LINREG_OFFSET RW RESET RW 0x1 DEFINITION Number of 25mV steps between linear regulator output voltage and switching converter target. 00b = 0 steps, recommended when powering VDDD only from linear regulator and ENABLE_DCDC=DCDC_XFER=0. It is also recommended to set DISABLE_STEPPING when powering VDDD from the linear regulators. 01b = 1 step above, default. 1Xb = 1 step below, important when powering VDDD from DC-DC converter and linear regulator simultaneously. Empty Description. Brownout voltage offset in 25mV steps below the TRG value. Note that the hardware only supports brownout voltages between 0.8V and 1.475V, and values outside this range should not be programmed. The brownout trip voltage will adjust as the target voltage changes. Empty Description. Voltage level of the VDDD supply. The step size of this field is 25 mV. 0x00 = 0.8 V, 0x1F = 1.575 V, and the reset value = 1.2 V. This field should not be set above the operating maximum as specified in the Recommended Operating Conditions table. It is also recommended to set DISABLE_STEPPING when powering VDDD from the integrated linear regulators. Setting DISABLE_STEPPING does set additional restrictions on TRG adjusments. 15:11 RSRVD2 10:8 BO_OFFSET RO 0x0 RW 0x7 7:5 4:0 RSRVD1 TRG RO 0x0 RW 0x10 DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.6 VDDA Supply Targets and Brownouts Control Register Description This register controls the voltage targets and brownout targets for the VDDA supply generated from the switching DC-DC converter and integrated linear regulators. The brownout comparators default enabled. HW_POWER_VDDACTRL 0x050 i.MX23 Applications Processor Reference Manual, Rev. 1 32-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply Table 32-12. HW_POWER_VDDACTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 PWDN_BRNOUT 1 8 DISABLE_STEPPING 1 7 ENABLE_LINREG 1 6 DISABLE_FET 1 5 1 4 1 3 LINREG_OFFSET 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BO_OFFSET RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 32-13. HW_POWER_VDDACTRL Bit Field Descriptions BITS LABEL 31:20 RSRVD4 19 PWDN_BRNOUT RW RESET RO 0x0 RW 0x0 DEFINITION Empty Description. Powers down the device after the DC-DC converter completes startup if a VDDA brownout occurs. This function is only active when 5V is not present. Additionally, software should clear this bit and disable this function after the system is configured for a VDDA brownout and the VDDA brownout interrupt is enabled. Disables the default behavior of the voltage stepping algorithm when the TRG field is updated. By default, the control loop steps sequentially through 25mV steps on both target and brownout voltage to minimize transients during TRG adjustments. When this bit is set, the entire target voltage and brownout adjustment takes place at one time, which will speed transitions, but will result in increased supply transients as well as possible brownouts when the new (TRG - BO_OFFSET) >= old TRG. Thus, it is recommended to change TRG by less than the (BO_OFFSET-2) value when using DISABLE_STEPPING. This bit should be set high when powering VDDA from the integrated linear regulators. Enables the VDDA linear regulator converter when the switching converter is active. By default, the linear regulator is not active when the switching converter is active. Disable the VDDA switching converter output. The switching converter is enabled by default when the battery is not present or the ENABLE_DCDC is set. Empty Description. 18 DISABLE_STEPPING RW 0x0 17 ENABLE_LINREG RW 0x0 16 DISABLE_FET RW 0x0 15:14 RSRVD3 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice TRG 32-29 Power Supply Table 32-13. HW_POWER_VDDACTRL Bit Field Descriptions BITS LABEL 13:12 LINREG_OFFSET RW RESET RW 0x1 DEFINITION Number of 25mV steps between linear regulator output voltage and switching converter target. 00b = 0 steps, recommended when powering VDDA from linear regulator and ENABLE_DCDC=DCDC_XFER=0. It is also recommended to set DISABLE_STEPPING when powering VDDA from the linear regulators. 01b = 1 step above, default. 1Xb = 1 step below, important when powering VDDA from DC-DC converter and linear regulator simultaneously. Empty Description. Brownout voltage offset in 25mV steps below the TRG value. Note that the hardware only supports brownout voltages between 1.4V and 2.175V, and values outside this range should not be programmed. The brownout trip voltage will adjust as the target voltage changes. Empty Description. Voltage level of the VDDA supply. The step size of this field is 25 mV. 0x00 = 1.5 V, 0x1F = 2.275 V, and the reset value = 1.75 V. This field should not be set above 1.95V as this may cause damage to the device. It is also recommended to set DISABLE_STEPPING when powering VDDA from the integrated linear regulators. Setting DISABLE_STEPPING does set additional restrictions on TRG adjusments. 11 10:8 RSRVD2 BO_OFFSET RO 0x0 RW 0x7 7:5 4:0 RSRVD1 TRG RO 0x0 RW 0xA DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.7 VDDIO Supply Targets and Brownouts Control Register Description This register controls the voltage targets and brownout targets for the VDDIO supply generated from the switching DC-DC converter and integrated linear regulators. The brownout comparators default enabled. HW_POWER_VDDIOCTRL 0x060 i.MX23 Applications Processor Reference Manual, Rev. 1 32-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply Table 32-14. HW_POWER_VDDIOCTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 PWDN_BRNOUT 1 7 DISABLE_STEPPING 1 6 DISABLE_FET 1 5 1 4 1 3 LINREG_OFFSET 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BO_OFFSET RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 ADJTN Table 32-15. HW_POWER_VDDIOCTRL Bit Field Descriptions BITS 31:24 RSRVD5 23:20 ADJTN LABEL RW RESET RO 0x0 RW 0x0 DEFINITION Empty Description. Two's complement number that can be used to adjust the duty cycle of VDDIO. This is intended for test purposes only Empty Description. Powers down the device after the DC-DC converter completes startup if a VDDIO brownout occurs. This function is only active when 5V is not present. Additionally, software should clear this bit and disable this function after the system is configured for a VDDIO brownout and the VDDIO brownout interrupt is enabled. Disables the default behavior of the voltage stepping algorithm when the TRG field is updated. By default, the control loop steps sequentially through 25mV steps on both target and brownout voltage to minimize transients during TRG adjustments. When this bit is set, the entire target voltage and brownout adjustment takes place at one time, which will speed transitions, but will result in increased supply transients as well as possible brownouts when the new (TRG - BO_OFFSET) >= old TRG. Thus, it is recommended to change TRG by less than the (BO_OFFSET-2) value when using DISABLE_STEPPING. This bit should be set high when powering VDDIO from the integrated linear regulators. Disable the VDDIO switching converter output. The switching converter is enabled by default when the battery is not present or the ENABLE_DCDC is set. Empty Description. 19 18 RSRVD4 PWDN_BRNOUT RO 0x0 RW 0x0 17 DISABLE_STEPPING RW 0x0 16 DISABLE_FET RW 0x0 15:14 RSRVD3 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice TRG 32-31 Power Supply Table 32-15. HW_POWER_VDDIOCTRL Bit Field Descriptions BITS LABEL 13:12 LINREG_OFFSET RW RESET RW 0x1 DEFINITION Number of 25mV steps between linear regulator output voltage and switching converter target. 00b = 0 steps, recommended when powering VDDIO from linear regulator and ENABLE_DCDC=DCDC_XFER=0. It is also recommended to set DISABLE_STEPPING when powering VDDIO from the linear regulators. 01b = 1 step above, default. 1Xb = 1 step below, important when powering VDDIO from DC-DC converter and linear regulator simultaneously. Empty Description. Brownout voltage offset in 25mV steps below the TRG value. Note that the hardware only supports brownout voltages between 2.7V and 3.475V, and values outside this range should not be programmed. The brownout trip voltage will adjust as the target voltage changes. Empty Description. Voltage level of the VDDIO supply. The step size of this field is 25 mV. 0x00 = 2.8 V, 0x1F = 3.575 V, and the reset value = 3.1 V. It is also recommended to set DISABLE_STEPPING when powering VDDIO from the integrated linear regulators. Setting DISABLE_STEPPING does set additional restrictions on TRG adjusments. 11 10:8 RSRVD2 BO_OFFSET RO 0x0 RW 0x7 7:5 4:0 RSRVD1 TRG RO 0x0 RW 0x0C DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.8 VDDMEM Supply Targets Control Register Description This register controls the voltage target for a supply generated from the VDDIO. This supply is intended for use with external memories such as DDR that have unique voltage requirements not compatible with VDDIO, VDDA , or VDDD. HW_POWER_VDDMEMCTRL 0x070 i.MX23 Applications Processor Reference Manual, Rev. 1 32-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply Table 32-16. HW_POWER_VDDMEMCTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 PULLDOWN_ACTIVE 0 9 ENABLE_ILIMIT 0 8 ENABLE_LINREG 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD2 RSRVD1 Table 32-17. HW_POWER_VDDMEMCTRL Bit Field Descriptions BITS LABEL 31:11 RSRVD2 10 PULLDOWN_ACTIVE RW RESET RO 0x0 RW 0x0 DEFINITION Empty Description. Activates pulldown on external memory supply. This bit should be set before the regulator is enabled to be sure the supply voltage powers up from ground. Default is pulldown inactive. Controls the inrush limit (~10mA) for the memory supply voltage. Default is active. This should remain active until the supply settles after enabling the linreg. This should be disabled before accessing the memory. Enables the regulator that creates the external memory supply voltage. After enabling the linreg need to wait until the VDDMEM rail is up before disabling the linreg current limit and accessing the memories. 500uS is usually an adequate delay, but it can be longer if VDDMEM cap is >1uF. Empty Description. Voltage level of the External memory supply. The step size of this field is 50 mV. 0x00 = 1.7 V, 0x1F = 3.25 V, and the reset value = 1.7 V. 9 ENABLE_ILIMIT RW 0x1 8 ENABLE_LINREG RW 0x0 7:5 4:0 RSRVD1 TRG RO 0x0 RW 0x0C DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.9 DC-DC Converter 4.2V Control Register Description This register contains controls that need to be adjusted to select the 4.2V source as the input for the dcdc converter HW_POWER_DCDC4P2 0x080 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice TRG 32-33 Power Supply Table 32-18. HW_POWER_DCDC4P2 3 1 3 0 DROPOUT_CTRL 2 9 2 8 2 7 2 6 2 5 ISTEAL_THRESH 2 4 2 3 ENABLE_4P2 2 2 ENABLE_DCDC 2 1 HYST_DIR 2 0 HYST_THRESH 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 32-19. HW_POWER_DCDC4P2 Bit Field Descriptions BITS LABEL 31:28 DROPOUT_CTRL RW RESET RW 0x0 DEFINITION Adjusts the behavior of the dcdc converter and 4.2V regulation circuit. The two msbs control the VDD4P2 brownout below the target set by DCDC4p2_trg before the regulation circuit steals battery charge current to support the voltage on VDD4P2. The two lsbs control which power source is selected by the dcdc converter after ENABLE_DCDC is set. 0b11XX: 200mV 0b10XX: 100mV 0b01XX: 50mV 0b00XX: 25mV 0bXX00: DcDc Converter power source is DCDC_4P2 regardless of BATTERY voltage 0bXX01: DcDc converter uses DCDC_4P2 always, and only enables DCDC_BATT when VDD4P2 is less than BATTERY. 0bXX1X: DcDc converter selects either VDD4P2 or BATTERY, which ever is higher. Empty Description. Has no effect. Enables the DCDC_4P2 regulation circuitry. The 4p2V load current has priority over the battery charge current when the sum of the two tries to exceed the limit set with CHARGE_4P2_ILIMIT. Enable the dcdc converter to use the DCDC_4P2 pin as a power source based on a voltage comparison between the BATTERY pin voltage and the VDD4P2 pin voltage. The trip point of this comparator is controlled by the CMPTRIP bitfield. Enable hysteresis in analog comparator. Increase the threshold detection for DCDC_4P2/BATTERY analog comparator. Empty Description. Regulation voltage of the DCDC_4P2 pin. 0b000 : 4.2V 0b001 : 4.1V 0b010 : 4.0V 0b011 : 3.9V 0b1XX : BATTERY Empty Description. 27:26 RSRVD5 25:24 ISTEAL_THRESH 23 ENABLE_4P2 RO 0x0 RW 0x0 RW 0x0 22 ENABLE_DCDC RW 0x0 21 20 HYST_DIR HYST_THRESH RW 0x0 RW 0x0 RO 0x0 RW 0x0 RSRVD3 19 18:16 TRG 15:13 RSRVD2 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 32-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor CMPTRIP RSRVD5 RSRVD3 RSRVD2 RSRVD1 TRG BO Power Supply Table 32-19. HW_POWER_DCDC4P2 Bit Field Descriptions BITS 12:8 BO LABEL RW RESET RW 0x0 DEFINITION Brownout voltage in 25mV steps for the DCDC_4P2 pin. 0b00000 : 3.6V .. 0b11111 : 4.375V Empty Description. Sets the trip point for the comparison between the DCDC_4P2 and BATTERY pin. When the comparator output is high then, the switching converter may use the DCDC_4P2 pin as the source for the switching converter, otherwise it will use the DCDC_BATT pin. 0b00000 DCDC_4P2 pin >= 0.85 * BATTERY pin 0b00001 DCDC_4P2 pin >= 0.86 * BATTERY pin 0b11000 DCDC_4P2 pin >= BATTERY pin (default) 0b11111 DCDC_4P2 pin >= 1.05 * BATTERY pin 7:5 4:0 RSRVD1 CMPTRIP RO 0x0 RW 0x18 DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.10 DC-DC Miscellaneous Register Description This register contains controls that may need to be adjusted to optimize DC-DC converter performance using the battery voltage information HW_POWER_MISC Table 32-20. HW_POWER_MISC 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 FREQSEL 0x090 0 4 0 3 0 2 DELAY_TIMING 0 1 0 0 SEL_PLLCLK RSRVD2 RSRVD1 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice TEST 32-35 Power Supply Table 32-21. HW_POWER_MISC Bit Field Descriptions BITS LABEL 31:7 RSRVD2 6:4 FREQSEL RW RESET RO 0x0 RW 0x0 DEFINITION 3 2 RSRVD1 DELAY_TIMING RW 0x0 RW 0x0 1 0 TEST SEL_PLLCLK RW 0x0 RW 0x0 Empty Description. This register will select the PLL-based frequency that the dcdc uses when SEL_PLLCLK is set high. The decode is as follows: 0x0=Reserved 0x1=20MHz 0x2=24MHz 0x3=19.2MHz 0x4=14.4MHz 0x5=18MHz 0x6=21.6MHz 0x7=17.28Mhz . Empty Description. This bit delays the timing of the output fets in the switching dcdc converter. This may provide improved ground noise performance in high power applications. Reserved. Do not set. This bit selects the source of the clock used for the DC-DC converter. The default is to use the 24-MHz clock. Setting this bit selects the PLL clock as a clock source for the DC-DC converter. It is required to program FREQSEL before setting this bit. DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.11 DC-DC Duty Cycle Limits Control Register Description This register defines the upper and lower duty cycle limits of DC-DC. These values depend on details of switching converter implementation and should not be changed without guidance from Freescale. HW_POWER_DCLIMITS Table 32-22. HW_POWER_DCLIMITS 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 POSLIMIT_BUCK 0x0A0 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 32-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor NEGLIMIT RSRVD3 RSRVD2 RSRVD1 Power Supply Table 32-23. HW_POWER_DCLIMITS Bit Field Descriptions BITS LABEL 31:16 RSRVD3 15 RSRVD2 14:8 POSLIMIT_BUCK RW RESET RO 0x0 RO 0x0 RW 0xC DEFINITION 7 6:0 RSRVD1 NEGLIMIT RO 0x0 RW 0x5F Empty Description. Empty Description. Upper limit duty cycle limit in DC-DC converter. This field will limit the maximum VDDIO acheivable for a given battery voltage, and it's value may be increased if very low battery operation is desired. Empty Description. Negative duty cycle limit of DC-DC converter. DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.12 Converter Loop Behavior Control Register Description This register defines the control loop parameters available for the DC-DC converter. HW_POWER_LOOPCTRL HW_POWER_LOOPCTRL_SET HW_POWER_LOOPCTRL_CLR HW_POWER_LOOPCTRL_TOG Table 32-24. HW_POWER_LOOPCTRL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 TOGGLE_DIF 0x0B0 0x0B4 0x0B8 0x0BC 1 9 1 8 EN_CM_HYST 1 7 EN_DF_HYST 1 6 CM_HYST_THRESH 1 5 DF_HYST_THRESH 1 4 RCSCALE_THRESH 1 3 EN_RCSCALE 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 HYST_SIGN RSRVD3 RSRVD2 RSRVD1 DC_FF DC_R Table 32-25. HW_POWER_LOOPCTRL Bit Field Descriptions BITS LABEL 31:21 RSRVD3 20 TOGGLE_DIF RW RESET RO 0x0 RW 0x0 DEFINITION Empty Description. Set high to enable supply stepping to change only after the differential control loop has toggled as well. This should eliminate any chance of large transients when supply voltage changes are made. Invert the sign of the hysteresis in DC-DC analog comparators. This bit should set when using PFM mode. 19 HYST_SIGN RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice DC_C 32-37 Power Supply Table 32-25. HW_POWER_LOOPCTRL Bit Field Descriptions BITS LABEL 18 EN_CM_HYST RW RESET RW 0x0 DEFINITION Enable hysteresis in switching converter common mode analog comparator. This feature will improve transient supply ripple and efficiency. Enable hysteresis in switching converter differential mode analog comparators. This feature will improve transient supply ripple and efficiency. Increase the threshold detection for common mode analog comparator. Increase the threshold detection for common mode analog comparator. Increase the threshold detection for RC scale circuit. Enable analog circuit of DC-DC converter to respond faster under transient load conditions. 00: disabled 01: 2X increase 10: 4X increase 11: 8X increase Empty Description. Two's complement feed forward step in duty cycle in the switching DC-DC converter. Each time this field makes a transition from 0x0, the loop filter of the DC-DC converter is stepped once by a value proportional to the change. This can be used to force a certain control loop behavior, such as improving response under known heavy load transients. Magnitude of proportional control parameter in the switching DC-DC converter control loop. Empty Description. Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response. 00: Maximum 01: Decrease ratio 2X 10: Decrease ratio 4X 11: Lowest ratio. 17 EN_DF_HYST RW 0x0 16 15 CM_HYST_THRESH DF_HYST_THRESH RW 0x0 RW 0x0 RW 0x0 RW 0x0 RCSCALE_THRESH 14 13:12 EN_RCSCALE 11 10:8 RSRVD2 DC_FF RO 0x0 RW 0x0 7:4 3:2 1:0 DC_R RSRVD1 DC_C RW 0x2 RO 0x0 RW 0x1 DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.13 Power Subsystem Status Register Description This register contains status information for the battery charger, DCDC converter and USB/OTG connections. HW_POWER_STS 0x0C0 i.MX23 Applications Processor Reference Manual, Rev. 1 32-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply Table 32-26. HW_POWER_STS 3 1 3 0 2 9 2 8 2 7 PWRUP_SOURCE 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 AVALID_STATUS 1 6 BVALID_STATUS 1 5 VBUSVALID_STATUS 1 4 SESSEND_STATUS 1 3 1 2 VDD5V_FAULT 1 1 1 0 DCDC_4P2_BO 0 9 0 8 0 7 0 6 0 5 VDD5V_GT_VDDIO 0 4 VDD5V_DROOP 0 3 0 2 0 1 0 0 VBUSVALID VDDIO_BO VDDA_BO CHRGSTS VDDD_BO Table 32-27. HW_POWER_STS Bit Field Descriptions BITS LABEL 31:30 RSVD4 29:24 PWRUP_SOURCE RW RESET RO 0x0 RO 0x0 DEFINITION Empty Description. These read-only bits determine which source was active when the dcdc converter powerup sequence was complete. This can be used to determine what event caused the device to powerup. bit5 : five volts bit4 : rtc wakeup bit3 : reserved bit2 : reserved bit1 : high level pswitch voltage bit0 : midlevel pswitch voltage Empty Description. These read-only bits reflect the current state of the pswitch comparators. The lsb is high when voltage on the PSWITCH pin is above 0.8V, and the msb is high when the voltage on the PSWITCH pin is above 1.75V Empty Description. Indicates VBus is valid for a A-peripheral. This bit is a read only version of the state of the analog signal. It can not be overritten by software like the AVALID bit below. Indicates VBus is valid for a B-peripheral. This bit is a read only version of the state of the analog signal. It can not be overwritten by software like the BVALID bit below. VBus valid for USB OTG. This bit is a read only version of the state of the analog signal. It can not be overwritten by software like the VBUSVALID bit below. Session End for USB OTG. This bit is a read only version of the state of the analog signal. It can not be overwritten by software like the SESSEND bit below. Output of battery brownout comparator. 23:22 RSVD3 21:20 PSWITCH RO 0x0 RO 0x0 19:18 RSVD2 17 AVALID_STATUS RO 0x0 RO 0x0 16 BVALID_STATUS RO 0x0 15 VBUSVALID_STATUS RO 0x0 14 SESSEND_STATUS RO 0x0 13 BATT_BO RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice SESSEND BATT_BO PSWITCH BVALID AVALID RSVD4 RSVD3 RSVD2 RSVD1 32-39 Power Supply Table 32-27. HW_POWER_STS Bit Field Descriptions BITS LABEL 12 VDD5V_FAULT RW RESET RO 0x0 DEFINITION Battery charging fault status. If the battery charger is not powered down, the bit is high when the 5V supply falls below the battery voltage. If the charger is powered down, the bit asserts high when 5V falls to below roughly VDDIO/2. If the charger is not powered down, the bit is sticky and remains set until the PWD_CHARGE_4P2 bit is cycled. Otherwise, the bit is cleared when 5V is restored. Battery charging status. High during Li-Ion battery charge until the charging current falls below the STOP_ILIMIT threshold. Output of the brownout comparator on the DCDC_4P2 pin Program this field to 0x0. Output of VDDIO brownout comparator. High when a brownout is detected. This comparator defaults powered up, but can be powered down via the POWER_MINPWR register. Output of VDDA brownout comparator. High when a brownout is detected. It is not possible to power-down this comparator. Output of VDDD brownout comparator. High when a brownout is detected. It is not possible to power-down this comparator. Indicates the voltage on the VDD5V pin is higher than VDDIO by a Vt voltage, nominally 500 mV. Indicates the voltage on the VDD5V pin is below the VBUSDROOP_TRSH defined in the 5VCTRL register. Indicates VBus is above the VA_SESS_VLD threshold, i.e. high if VBus greater than 2.0, low if VBus less than 0.8, otherwise unknown. Indicates VBus is above the VB_SESS_VLD threshold, high if VBus greater than 4.0, low if VBus less than 0.8, otherwise unknown. Accurate detection of the presence of 5v power. This can be used for detection of 5v in all modes of operation including USB OTG. See POWER_5VCTRL to enable and set threshold for comparison. Indicates VBus is below the VB_SESS_END threshold, i.e. 0 if VBus is greater than 0.8 V, 1 if VBus is less than 0.2 V, otherwise unknown. See POWER_5VCTRL to enable comparators. 11 CHRGSTS RO 0x0 10 9 8 DCDC_4P2_BO RSVD1 VDDIO_BO RO 0x0 RO 0x0 RO 0x0 7 VDDA_BO RO 0x0 6 VDDD_BO RO 0x0 5 4 3 VDD5V_GT_VDDIO VDD5V_DROOP AVALID RO 0x0 RO 0x0 RW 0x0 2 BVALID RW 0x0 1 VBUSVALID RW 0x0 0 SESSEND RW 0x0 DESCRIPTION: Empty Description. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 32-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply 32.11.14 Transistor Speed Control and Status Register Description This register contains the setup and controls needed to measure silicon speed. HW_POWER_SPEED HW_POWER_SPEED_SET HW_POWER_SPEED_CLR HW_POWER_SPEED_TOG Table 32-28. HW_POWER_SPEED 3 1 3 0 2 9 2 8 RSRVD1 0x0D0 0x0D4 0x0D8 0x0DC 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 STATUS 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 RSRVD0 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 CTRL 0 0 Table 32-29. HW_POWER_SPEED Bit Field Descriptions BITS 31:24 RSRVD1 23:16 STATUS LABEL RW RESET RO 0x0 RO 0x0 DEFINITION Empty Description. Result from the speed sensor. This result is only valid when SPEEDCTRL=0b11; otherwise this field contains debug information from the switching DC-DC converter. Empty Description. Speed Control bits. 00: Speed sensor off, 0b01: Speed sensor enabled, 11: Enable speed sensor measurement. Every time a measurement is taken, the sequence of 0x00 ; 01 ; 11 must be repeated. This sequence should proceed no faster than 1.5 MHz to ensure proper operation. 15:2 1:0 RSRVD0 CTRL RO 0x0 RW 0x0 DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.15 Battery Level Monitor Register Description This register provides brownout controls and monitors the battery voltage. HW_POWER_BATTMONITOR 0x0E0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-41 Power Supply Table 32-30. HW_POWER_BATTMONITOR 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 PWDN_BATTBRNOUT 0 8 BRWNOUT_PWD 0 7 0 6 0 5 0 4 0 3 0 2 BRWNOUT_LVL 0 1 0 0 EN_BATADJ BATT_VAL RSRVD3 RSRVD2 Table 32-31. HW_POWER_BATTMONITOR Bit Field Descriptions BITS LABEL 31:26 RSRVD3 25:16 BATT_VAL RW RESET RO 0x0 RW 0x0 DEFINITION Empty Description. Software should be configured to place the battery voltage in this register measured with an 8-mV LSB resolution via the LRADC. This value is used by the DC-DC converter and must be correct before setting EN_BATADJ. Empty Description. This bit enables the DC-DC to improve efficiency and minimize ripple using the information from the BATT_VAL field. It is very important that BATT_VAL contain accurate information before setting EN_BATADJ. Powers down the device after the DC-DC converter completeS startup if a battery brownout occurs. This function is only active when 5V is not present. Additionally, software should clear this bit and disable this function after the system is configured for a battery brownout and the battery brownout interrupt is enabled. Power-down circuitry for battery brownout detection. This bit should only be set when it is not important to montior battery brownouts and minimum system power consumption is required. Empty Description. The default setting of the brownout settings decode to a voltage as follows: Li-Ion = 2.4 V The voltage level can be calculated for other values by the following equation: Li-Ion brownout voltage = 2.4 V + 0.04 * BRWNOUT_LVL 15:11 RSRVD2 10 EN_BATADJ RO 0x0 RW 0x0 9 PWDN_BATTBRNOUT RW 0x1 8 BRWNOUT_PWD RW 0x0 7:5 4:0 RSRVD1 BRWNOUT_LVL RO 0x0 RW 0x0 DESCRIPTION: Empty Description. i.MX23 Applications Processor Reference Manual, Rev. 1 32-42 Preliminary--Subject to Change Without Notice RSRVD1 Freescale Semiconductor Power Supply EXAMPLE: Empty Example. 32.11.16 Power Module Reset Register Description This register allows software to put the chip into the off state. HW_POWER_RESET HW_POWER_RESET_SET HW_POWER_RESET_CLR HW_POWER_RESET_TOG Table 32-32. HW_POWER_RESET 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 UNLOCK 0x100 0x104 0x108 0x10C 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 RSRVD1 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 PWD_OFF 0 0 PWD Table 32-33. HW_POWER_RESET Bit Field Descriptions BITS 31:16 UNLOCK LABEL RW RESET RW 0x0 DEFINITION Write 0x3E77 to unlock this register and allow other bits to be changed. NOTE: This register must be unlocked on a write-by-write basis, so the UNLOCK bitfield must contain the correct key value during all writes to this register in order to update any other bitfield values in the register. KEY = 0x3E77 Key needed to unlock HW_POWER_RESET register. 15:2 1 RSRVD1 PWD_OFF RO 0x0000 RW 0x0 0 PWD RW 0x0 Empty Description. Optional bit to disable all paths to power off the chip except the watchdog timer. Setting this bit will be useful for preventing fast falling edges on the PSWITCH pin from resetting the chip. It may also be useful increasing system tolerance of noisy EMI environments. Note that setting this bit disables most automatic hardware shutdown protection mechanisms such as PWDN_BATTBRNOUT and the PWDN_5VBRNOUT. Before setting PWD_OFF, the application must configure the proper FIQ handled replacements for these protection mechanisms. Powers down the chip. DESCRIPTION: Empty Description. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-43 Power Supply 32.11.17 Power Module Debug Register Description Debug Register. HW_POWER_DEBUG HW_POWER_DEBUG_SET HW_POWER_DEBUG_CLR HW_POWER_DEBUG_TOG Table 32-34. HW_POWER_DEBUG 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 VBUSVALIDPIOLOCK 0x110 0x114 0x118 0x11C 0 2 AVALIDPIOLOCK 0 1 BVALIDPIOLOCK 0 0 SESSENDPIOLOCK Table 32-35. HW_POWER_DEBUG Bit Field Descriptions BITS 31:4 3 2 1 0 LABEL RSRVD0 VBUSVALIDPIOLOCK AVALIDPIOLOCK BVALIDPIOLOCK SESSENDPIOLOCK RW RO RW RW RW RW RESET 0x0 0x0 0x0 0x0 0x0 DEFINITION RSRVD0 Empty Description. Empty Description. Empty Description. Empty Description. Empty Description. DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.18 Power Module Special Register Description Special test functionality. HW_POWER_SPECIAL HW_POWER_SPECIAL_SET HW_POWER_SPECIAL_CLR HW_POWER_SPECIAL_TOG Table 32-36. HW_POWER_SPECIAL 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x120 0x124 0x128 0x12C TEST i.MX23 Applications Processor Reference Manual, Rev. 1 32-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor Power Supply Table 32-37. HW_POWER_SPECIAL Bit Field Descriptions BITS 31:0 TEST LABEL RW RESET RW 0x0 DEFINITION DESCRIPTION: Empty Description. EXAMPLE: Empty Example. 32.11.19 Power Module Version Register Description This register always returns a known read value for debug purposes it indicates the version of the block. HW_POWER_VERSION Table 32-38. HW_POWER_VERSION 3 1 3 0 2 9 2 8 MAJOR 0x130 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 32-39. HW_POWER_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x03 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x01 RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: Empty Example. POWER Block v3.1, Revision 1.0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 32-45 Power Supply i.MX23 Applications Processor Reference Manual, Rev. 1 32-46 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 33 Low-Resolution ADC and Touch-Screen Interface This chapter describes the low-resolution analog-to-digital converters and touch-screen interface included on the i.MX23. It includes sections on scheduling conversions and delay channels. Programmable registers are described in Section 33.4, "Programmable Registers." 33.1 Overview The sixteen-channel low-resolution ADC (LRADC) block is used for voltage measurement Figure 33-1 shows a block diagram of the LRADC. Eight "virtual" channels can be used at one time. Each of the eight virtual channels can be mapped to any of the 16 physical channels using HW_LRADC_CTRL4. Six physical channels are available for general use. * * Channel 15 is dedicated to measuring the voltage on the VDD5V pin and can be used to detect possible issues with 5V rail drooping. Channel 14 is dedicated to measuring the bandgap reference voltage and can be used to calibrate out a portion of the LRADC measurement error (comparator offset, buffer amp offset, and DAC offset). In most cases, the bandgap reference error (specified to 1%) will dominate the total LRADC error, and this calibration will not be helpful. But if the bandgap reference is calibrated using the fuses, then it is possible that LRADC accuracy will be limited by these other sources and that using the VBG input for calibration of the LRADC can improve accuracy further. Channel 12 and 13 are dedicated to measuring the voltage on the USB_DP and USB_DN pins. This is to be used only in non-USB mode and can be used for special peripheral circuitry detection. HW_USBPHY_CTRL_DATA_ON_LRADC must be set to measure these inputs. Channel 10 and 11 are reserved inputs for analog testing. Channel 8 and 9 are dedicated to measuring the internal die temperature. HW_LRADC_CTRL2_TEMPSENSE_PWD must be cleared for these inputs to function. See Section 33.2.2, "Internal Die Temperature Sensing." Channel 7 is dedicated to measuring the voltage on the BATT pin and can be used to sense the amount of battery life remaining. Channel 6 is dedicated to measuring the voltage on the VDDIO Rail and is used to calibrate the voltage levels measured on the auxiliary channels when those inputs are resistor divided from the VDDIO rail. On the 128 -pin LQFP package, LRADC4 is bonded to the VDDM 2.5 V regulator output. To use this pin as an LRADC input, the VDDM 2.5 V LDO must be disabled. * * * * * * The LRADC has 12 bits of resolution and an absolute accuracy of 1.3% limited primarily by the bandgap voltage reference accuracy. If the bandgap voltage reference is calibrated with the fuses, the LRADC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-1 Low-Resolution ADC and Touch-Screen Interface absolute accuracy might be improved to better than 0.5%. All channels sample on the same divided clock rate from the 24.0-MHz crystal clock. The LRADC controller includes an integrated touch-screen controller with drive voltage generation for touch-screen coordinate measurement, as well as a touch-detection interrupt circuit. The LRADC controller also contains four delay-control channels that can be used to automatically time and schedule control events within the LRADC. ARM Core SRAM AHB AHB Slave AHB Master Shared DMA APBX Master AHB-to-APBX Bridge APBX LRADC Programmable Registers APBX Clock Domain State Machines and Logic XTAL/4 Clock Domain State Machines and Logic LRADC5-0 Pins 16-Channel LRADC Touch-Screen Controller Temp-Sensor Controller LRADC Figure 33-1. Low-Resolution ADC and Touch-Screen Interface Block Diagram 33.2 Operation All channels of the LRADC share a common successive approximation style analog-to-digital converter through a common analog mux front end (see Figure 33-1). * * * The BATT pin has a built-in 4:1 voltage divider on its analog multiplexer input that is activated only in Li-Ion battery mode. The Channel 15 5V input also has a built-in 4:1 divider on its input. The Channel 6 VDDIO input has a built-in 2:1 divider on its input. The maximum analog input voltage into the LRADC is 1.85 V. i.MX23 Applications Processor Reference Manual, Rev. 1 33-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface * For input channels (other than BATT, 5V, or VDDIO) with signals larger than 1.85 V, the divide-by-two option should be set (HW_LRADC_CTRL2_DIVIDE_BY_TWO). With the DIVIDE_BY_TWO option set, the maximum input voltage is VDDIO - 50mv. The touch-screen driver works for typical touch-screen impedances of 200-900 ohm and for high impedance touch-panels with impedances in the 50-Kohm range. The LRADC channels 0 and 1 have optional current source outputs to allow these channels to be used with an external themistor (or an external diode) for temperature sensing. The controls for these current sources are in HW_LRADC_CTRL2. The current source values can be changed to allow significant temperature sensing range using a thermistor or to use a diode for temperature sensing. The currents are derived using the on-chip 1% accurate bandgap voltage reference and an optionally tuned on-chip poly resistor. The accuracy of the current source is limited by the on-chip resistor, which should be 5% accurate and optionally tuned for higher accuracy (with efuses). Most thermistors are no more than 5% accurate, so this level of current source accuracy is acceptable for most applications. For temperature sensing with higher accuracy, customers can use a 1% resistor divider from VDDIO with the thermistor. In this case, the thermistor will be the dominant source of error. 33.2.1 External Temperature Sensing with a Diode Using a diode instead of a thermistor for external temperature sensing can be cheaper and provide greater temperature range for a given accuracy level. A cheap diode like a 1N4148 is connected between ground and either LRADC 0 or 1. Two voltage measurements are taken--first with the HW_LRADC_CTRL2_TEMP_ISRC current source set at 300 A, then another voltage measurement with the current source set at 20 A. The temperature will be roughly: degrees Kelvin = (Vmax - Vmin) / 0.409 mV or, from the LRADC conversion (LSB=0.45mV): degrees Kelvin = (Codemax - Codemin) * 1.104 Freescale recommends taking 5-10 samples for the min and max and then averaging them to get a good reading. The temperature reading error will likely be dominated by part-to-part matching of the diodes. Some manufacturers' diodes show substantially less variation than others. Freescale has shown 3sigma accuracy of +/-7.5C using Fairchild MMBD914 (from multiple batches of diodes). If better accuracy is required, Freescale recommends using a thermistor for external temperature sensing. The thermistor will be more accurate, but over a smaller temperature range than the diode method. Any routing impedance to the diode will cause a shift in the temperature reading. This can be measured and corrected in software for each design. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-3 Low-Resolution ADC and Touch-Screen Interface Two ohms of routing impedance would cause (2 * (300A - 20A) error of 0.56 mV or 1.25 degrees C error. 33.2.2 Internal Die Temperature Sensing The i.MX23 has a new internal die temperature sensor that uses two of the sixteen physical LRADC channels. To use the internal die temperature sensor, HW_LRADC_CTRL2_TEMPSENSE_PWD should be cleared. (This bit can be left cleared after power up. There is no need to toggle it on and off.) Two of the eight virtual LRADC channels need to be mapped to the temperature sensing channels 8 and 9 using HW_LRADC_CTRL4. Then, these virtual LRADC channels should BOTH be converted using the LRADC conversion scheduler described below. The temperature in degrees Kelvin will be equal to: T = (Channel9 - Channel8) * Gain_correction/4 The Gain_correction corrects a mean gain error in the temperature conversion and should be 1.012. After this correction factor, the three-sigma error of the temperature sensor should be within 1.5% in degrees Kelvin. Additionally, the temperature sampling has a three-sigma sample-to-sample variation of 2 degrees Kelvin. If desired, this error can be removed by oversampling and averaging the temperature result. Prior to starting a battery charge cycle, the internal die temperature sensing could be used for an approximate ambient temperature. During high-current battery charging, the temperature sensor can be used as extra protection to avoid excessive die temperatures (to throttle the charging current). 33.2.3 Scheduling Conversions The APBX clock domain logic schedules conversions on a per-channel basis and handles interrupt processing back to the CPU. Each of the eight virtual channels has its own interrupt request enable bit and its own interrupt request status bit. A schedule request bit, HW_LRADC_CTRL0_SCHEDULE, exists for each virtual channel. Setting this bit causes the LRADC to schedule a conversion for that virtual channel. Each virtual channel schedule bit is sequentially checked and, if scheduled, causes a conversion. The schedule bit is cleared upon completion of a successive approximation conversion, and its corresponding interrupt request status bit is set. Thus, software controls how often a conversion is requested. As each scheduled channel is converted, its interrupt status bit is set and its schedule bit is reset. There is a mechanism to continuously reschedule a conversion for a particular virtual channel. With set/clear/toggle addressing modes, independent threads can request conversions without needing any information from unrelated threads using other channels. Setting a schedule bit can be performed in an atomic way. Setting a "gang" of four channel-schedule bits can also be performed atomically. The LRADC scheduler is round-robin. It snapshots all schedule bits at once, and then processes them in sequence until all are converted. It then monitors the schedule bits. If any schedule bits are set, it snapi.MX23 Applications Processor Reference Manual, Rev. 1 33-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface shots them and starts a new conversion operation for all scheduled channels. Thus, one can set the schedule bits for four channels on the same clock edge. The channel with the largest channel number is converted last and has its interrupt status bit set last. If that channel is the only one of the four with an interrupt enable bit set, then it interrupts the ARM after all four channels have been converted, effectively ganging four channels together. 33.2.4 Delay Channels To minimize the interrupt load on the ARM processor, four delay channels are provided. Each has an 11-bit counter that increments at 2 kHz. A delay channel can be kicked off either by an ARM store instruction or at the completion of a delay channel time-out. At time-out, each channel has the option of kicking off any combination of LRADC conversions, as well as any combination of delay channels. NOTE: The DELAY fields in HW_LRADC_DELAY0, HW_LRADC_DELAY1, HW_LRADC_DELAY2, and HW_LRADC_DELAY3 must be non-zero; otherwise, the LRADC will not trigger the delay group. The ACCUMULATE bit in the appropriate channel register HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0; otherwise, the IRQs will not fire. Consider the case of a touch-screen that requires 4x oversampling of its coordinate values. Further, suppose you wish to receive an oversampled X or Y coordinate approximately every 5 ms and that the oversampling should be spaced at 1-ms intervals. * * * In the touch-screen, first select either X or Y drive, then set up the appropriate LRADC. In setting up the LRADC, clear the accumulator associated with it by setting the ACCUMULATE bit and set the NUM_SAMPLES field to 3 (4 samples before interrupt request). Next, set up two delay channels. -- Delay Channel 1 is set to delay 1 ms (DELAY = 1, two ticks) and then kick the schedule bit for LRADC 4. Its LOOP_COUNT bit field is also set to 3, so that four kicks of LRADC 4 occur, each spaced by 1 ms. -- Delay Channel 0 is set to delay 1 ms with LOOP_COUNT = 0, i.e., one time. Its TRIGER_DELAYS field is set to trigger Delay Channel 1 when it times out. The ISR routine kicks off Delay Channel 0 immediately before it does its return from interrupt. Another interrupt (LRADC4_IRQ) is asserted once the entire 4x oversample data capture is complete. A sample timeline for such a sequence is shown in Figure 33-3. NOTE: If a delay group schedules channels to be sampled and a manual write to the schedule field in CTRL0 occurs while the block is discarding samples, the LRADC will switch to the new schedule and will not sample the channels that were previously scheduled. The time window for this to happen is very small and lasts only while the LRADC is discarding samples. WARNING: The pad ESD protection limits the voltage on the LRADC0-LRADC6 inputs to VDDIO. The BATT and 5V inputs to the LRADC have built-in dividers to handle the higher voltages. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-5 Low-Resolution ADC and Touch-Screen Interface 33.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10, "Correct Way to Soft Reset a Block," for additional information on using the SFTRST and CLKGATE bit fields. i.MX23 Applications Processor Reference Manual, Rev. 1 33-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface Vts_PU ~ 1.85V drive_xplus VddIO softpu_xplus 200K + - touch_detect LRADC2 LRADC4 X+ Xdrive_xminus drive_yminus YY+ drive_yplus Vts_PU LRADC5 LRADC3 temp_isrc1[3:0] analog mux LRADC1 LRADC0 1/2 + - temp_isrc0[3:0] 50 K LRADC6 (VDDIO) 50 K Channel 6 Active 12-Bit DAC XTALSAR State Machine APBX CLK State Machine 75 K LRADC7 (BATT) 25 K Li-Ion Mode Channel 7 Active PwrDwn clkdiv (1:4,1:6,1:8,1:12) apbxclk = xtal_clk/n 24.0 MHz Freescale Internal Temperature Sensing Freescale Internal Test Points 8-9 10-11 LRADC12 (USB_DP) LRADC13 (USB_DN) 14 Bandgap Reference 375 K LRADC15 (VDD5V) 125 K Figure 33-2. Low-Resolution ADC Successive Approximation Unit i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-7 Low-Resolution ADC and Touch-Screen Interface DelayChannel_0 Kicks DelayChannel1 DelayChannel_1 Kicks LRADC4_X+ DelayChannel_1 Kicks LRADC4_X+ DelayChannel_1 Kicks LRADC4_X+ DelayChannel_1 Kicks LRADC4_X+ TouchScreenIRQ Kick DelayChannel_0 Delay Channel 1 oversample intervals: 1. Times out. 2. Kicks LRADC4 (X+ sample). 3. Repeats 3 more times. Delay Channel 0 (touch-screen settling time): 1. Times out. 2. Kicks Delay Channel 1. Touch-screen ISR: 1. Sets Y+,Y- drive and clears LRADC4 ACC. 2. Set Delay Channel 1 for LRADC4. 3. Kicks Delay Channel 0. 4. Return from interrupt. Final Conversion sets IRQ. Figure 33-3. Using Delay Channels to Oversample a Touch-Screen 33.4 Programmable Registers The following registers describe the programming interfaces for the Low-Resolution ADC and Touch-Screen Interface. 33.4.1 LRADC Control Register 0 Description The LRADC Control Register 0 provides overall control of the eight low resolution analog to digital converters. HW_LRADC_CTRL0 HW_LRADC_CTRL0_SET 0x000 0x004 i.MX23 Applications Processor Reference Manual, Rev. 1 33-8 Preliminary--Subject to Change Without Notice LRADC4IRQ Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface HW_LRADC_CTRL0_CLR HW_LRADC_CTRL0_TOG Table 33-1. HW_LRADC_CTRL0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 ONCHIP_GROUNDREF 0x008 0x00C 2 0 TOUCH_DETECT_ENABLE 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 YMINUS_ENABLE XMINUS_ENABLE YPLUS_ENABLE XPLUS_ENABLE Table 33-2. HW_LRADC_CTRL0 Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION When set to one, this bit causes a reset to the entire LRADC block. In addition, it turns off the converter clock and powers down the analog portion of the LRADC. Set this bit to zero for normal operation. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. Reserved Set this bit to one to use the on-chip ground as reference for conversions. OFF = 0x0 Turn it off. ON = 0x1 Turn it on. 30 CLKGATE RW 0x1 RO 0x0 RW 0x0 29:22 RSRVD2 ONCHIP_GROUNDREF 21 20 19 TOUCH_DETECT_ENABLE YMINUS_ENABLE RW 0x0 RW 0x0 Set this bit to one to enable touch panel touch detector. OFF = 0x0 Turn it off. ON = 0x1 Turn it on. Set this bit to one to enable yminus pull down on the LRADC5 pin. OFF = 0x0 Turn it off. ON = 0x1 Turn it on. 18 XMINUS_ENABLE RW 0x0 Set this bit to one to enable xminus pull down on the LRADC4 pin. OFF = 0x0 Turn it off. ON = 0x1 Turn it on. 17 YPLUS_ENABLE RW 0x0 Set this bit to one to enable yplus pull up on the LRADC3 pin. . OFF = 0x0 Turn it off. ON = 0x1 Turn it on. 16 XPLUS_ENABLE RW 0x0 Set this bit to one to enable xplus pull up on the LRADC2 pin. OFF = 0x0 Turn it off. ON = 0x1 Turn it on. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice SCHEDULE CLKGATE RSRVD2 RSRVD1 SFTRST 33-9 Low-Resolution ADC and Touch-Screen Interface Table 33-2. HW_LRADC_CTRL0 Bit Field Descriptions BITS LABEL 15:8 RSRVD1 SCHEDULE 7:0 RW RESET RO 0x00 RW 0x00 DEFINITION Reserved Setting a bit to one schedules the corresponding LRADC channel to be converted. When the conversion of a scheduled channel is completed the corresponding schedule bit is reset by the hardware and the corresponding interrupt request is set to one. Thus any thread can request a conversion asynchronously from any other thread. DESCRIPTION: The LRADC control register provides control over the shared eight channel LRADC converter. It allows software to independently schedule conversion cycles on any number of any size subsets of the eight channels. In addition it allows software to manage the interrupt reporting for the channel conversion sets. EXAMPLE: BW_LRADC_CTRL0_YPLUS_ENABLE(BV_LRADC_CTRL0_YPLUS_ENABLE__ON); 33.4.2 LRADC Control Register 1 Description The LRADC Control Register 1 provides overall control of the eight low resolution analog to digital converters. HW_LRADC_CTRL1 HW_LRADC_CTRL1_SET HW_LRADC_CTRL1_CLR HW_LRADC_CTRL1_TOG Table 33-3. HW_LRADC_CTRL1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 TOUCH_DETECT_IRQ_EN 0x010 0x014 0x018 0x01C 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 TOUCH_DETECT_IRQ 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 LRADC7_IRQ_EN LRADC6_IRQ_EN LRADC5_IRQ_EN LRADC4_IRQ_EN LRADC3_IRQ_EN LRADC2_IRQ_EN LRADC1_IRQ_EN LRADC0_IRQ_EN LRADC7_IRQ LRADC6_IRQ LRADC5_IRQ LRADC4_IRQ LRADC3_IRQ LRADC2_IRQ LRADC1_IRQ Table 33-4. HW_LRADC_CTRL1 Bit Field Descriptions BITS LABEL 31:25 RSRVD2 TOUCH_DETECT_IRQ_EN 24 RW RESET RO 0x00 RW 0x0 DEFINITION Reserved Set to one to enable an interrupt for the touch detector comparator. DISABLE = 0x0 Disable Interrupt request. ENABLE = 0x1 Enable Interrupt request. i.MX23 Applications Processor Reference Manual, Rev. 1 33-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor LRADC0_IRQ RSRVD2 RSRVD1 Low-Resolution ADC and Touch-Screen Interface Table 33-4. HW_LRADC_CTRL1 Bit Field Descriptions BITS LABEL 23 LRADC7_IRQ_EN RW RESET RW 0x0 DEFINITION Set to one to enable an interrupt for channel 7 (BATT) conversions. DISABLE = 0x0 Disable Interrupt request. ENABLE = 0x1 Enable Interrupt request. 22 LRADC6_IRQ_EN RW 0x0 Set to one to enable an interrupt for channel 6 (VddIO) conversions. DISABLE = 0x0 Disable Interrupt request. ENABLE = 0x1 Enable Interrupt request. 21 LRADC5_IRQ_EN RW 0x0 Set to one to enable an interrupt for channel 5 conversions. DISABLE = 0x0 Disable Interrupt request. ENABLE = 0x1 Enable Interrupt request. 20 LRADC4_IRQ_EN RW 0x0 Set to one to enable an interrupt for channel 4 conversions. DISABLE = 0x0 Disable Interrupt request. ENABLE = 0x1 Enable Interrupt request. 19 LRADC3_IRQ_EN RW 0x0 Set to one to enable an interrupt for channel 3 conversions. DISABLE = 0x0 Disable Interrupt request. ENABLE = 0x1 Enable Interrupt request. 18 LRADC2_IRQ_EN RW 0x0 Set to one to enable an interrupt for channel 2 conversions. DISABLE = 0x0 Disable Interrupt request. ENABLE = 0x1 Enable Interrupt request. 17 LRADC1_IRQ_EN RW 0x0 Set to one to enable an interrupt for channel 1 conversions. DISABLE = 0x0 Disable Interrupt request. ENABLE = 0x1 Enable Interrupt request. 16 LRADC0_IRQ_EN RW 0x0 Set to one to enable an interrupt for channel 0 conversions. DISABLE = 0x0 Disable Interrupt request. ENABLE = 0x1 Enable Interrupt request. 15:9 8 RSRVD1 TOUCH_DETECT_IRQ RO 0x00 RW 0x0 Reserved This bit is set to one upon detection of a touch condition in the touch panel attached to LRADC2-LRADC5. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. CLEAR = 0x0 Interrupt request cleared. PENDING = 0x1 Interrupt request pending. 7 LRADC7_IRQ RW 0x0 This bit is set to one upon completion of a scheduled conversion for channel 7(BATT). It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. CLEAR = 0x0 Interrupt request cleared. PENDING = 0x1 Interrupt request pending. 6 LRADC6_IRQ RW 0x0 This bit is set to one upon completion of a scheduled conversion for channel 6(VDDIO). It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. CLEAR = 0x0 Interrupt request cleared. PENDING = 0x1 Interrupt request pending. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-11 Low-Resolution ADC and Touch-Screen Interface Table 33-4. HW_LRADC_CTRL1 Bit Field Descriptions BITS LABEL 5 LRADC5_IRQ RW RESET RW 0x0 DEFINITION This bit is set to one upon completion of a scheduled conversion for channel 5. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. CLEAR = 0x0 Interrupt request cleared. PENDING = 0x1 Interrupt request pending. 4 LRADC4_IRQ RW 0x0 This bit is set to one upon completion of a scheduled conversion for channel 4. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. CLEAR = 0x0 Interrupt request cleared. PENDING = 0x1 Interrupt request pending. 3 LRADC3_IRQ RW 0x0 This bit is set to one upon completion of a scheduled conversion for channel 3. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. CLEAR = 0x0 Interrupt request cleared. PENDING = 0x1 Interrupt request pending. 2 LRADC2_IRQ RW 0x0 This bit is set to one upon completion of a scheduled conversion for channel 2. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. CLEAR = 0x0 Interrupt request cleared. PENDING = 0x1 Interrupt request pending. 1 LRADC1_IRQ RW 0x0 This bit is set to one upon completion of a scheduled conversion for channel 1. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. CLEAR = 0x0 Interrupt request cleared. PENDING = 0x1 Interrupt request pending. 0 LRADC0_IRQ RW 0x0 This bit is set to one upon completion of a scheduled conversion for channel 0. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. CLEAR = 0x0 Interrupt request cleared. PENDING = 0x1 Interrupt request pending. DESCRIPTION: The LRADC control register 1 provides control over the shared eight channel LRADC converter. It allows software to independently schedule conversion cycles on any number of any size subsets of the eight channels. In addition it allows software to manage the interrupt reporting for the channel conversion sets. EXAMPLE: if(HW_LRADC_CTRL1.TOUCH_DETECT_IRQ == BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING){ // Then handle the interrupt. HW_LRADC_CTRL1.TOUCH_DETECT_IRQ_EN = BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE; } i.MX23 Applications Processor Reference Manual, Rev. 1 33-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface 33.4.3 LRADC Control Register 2 Description The LRADC Control Register 2 provides overall control of the eight low resolution analog to digital converters. HW_LRADC_CTRL2 HW_LRADC_CTRL2_SET HW_LRADC_CTRL2_CLR HW_LRADC_CTRL2_TOG Table 33-5. HW_LRADC_CTRL2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 TEMP_SENSOR_IENABLE1 0x020 0x024 0x028 0x02C 0 8 TEMP_SENSOR_IENABLE0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TEMPSENSE_PWD BL_AMP_BYPASS BL_MUX_SELECT BL_BRIGHTNESS DIVIDE_BY_TWO TEMP_ISRC1 Table 33-6. HW_LRADC_CTRL2 Bit Field Descriptions BITS LABEL 31:24 DIVIDE_BY_TWO RW RESET RW 0x0 DEFINITION Each bit of this eight bit field corresponds to a channel of an LRADC. Setting the bit to one caused the A/D converter to use its analog divide by two circuit for the conversion of the corresponding channel. The analog feedback control signal is normally gained up by 4X. When this bit is one, the feedback control signal bypasses the gain of 4 stage. DISABLE = 0x0 . ENABLE = 0x1 . 23 BL_AMP_BYPASS RW 0x0 22 21 BL_ENABLE BL_MUX_SELECT RW 0x0 RW 0x0 RW 0x0 20:16 BL_BRIGHTNESS 15 TEMPSENSE_PWD RW 0x1 Enables the back light. 0 - Use pin LRADC4 for feedback control. 1 - Use pin LRADC1 for feedback control. Sets the voltage comparison level for the analog feedback control. Each step is -1.293dB with the max voltage of 1.212V. BL_AMP_BYPASS 10 11111 = 1.213V 0.303 11110 = 1.046V 0.262 ..... 00001 = 0.0136V 0.0034 00000 = 0.0117V 0.0029 PWD the tempsense block. ENABLE = 0x0 When this is low the tempsense gain block muxes to LRADC channel 8 and 9. DISABLE = 0x1 . 14 RSRVD1 RO 0x00 Reserved i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice TEMP_ISRC0 BL_ENABLE EXT_EN1 EXT_EN0 RSRVD1 RSRVD2 33-13 Low-Resolution ADC and Touch-Screen Interface Table 33-6. HW_LRADC_CTRL2 Bit Field Descriptions BITS LABEL 13 EXT_EN1 RW RESET RW 0x0 DEFINITION These bits are not supported. DISABLE = 0x0 . ENABLE = 0x1 . 12 EXT_EN0 RW 0x0 11:10 RSRVD2 TEMP_SENSOR_IENABLE1 9 RO 0x00 RW 0x0 When set to zero(default) the mux amp is bypassed when the LRADC input channel is not using the divide-by-two. When set to one the mux amp is never bypassed (old behavior). Reserved Set this bit to one to enable the current source onto LRADC1. DISABLE = 0x0 Disable Temperature Sensor Current Source. ENABLE = 0x1 Enable Temperature Sensor Current Source. 8 TEMP_SENSOR_IENABLE0 RW 0x0 Set this bit to one to enable the current source onto LRADC0. DISABLE = 0x0 Disable Temperature Sensor Current Source. ENABLE = 0x1 Enable Temperature Sensor Current Source. 7:4 TEMP_ISRC1 RW 0x0 When the output voltage is lower than 1V the output current is 1uA higher than the decode shown above. This extra current drops to zero as the output voltage raises above 1.5V. This four bit field encodes the current magnitude to inject into an external temperature sensor attached to LRADC1. 300 = 0xF 300uA. 280 = 0xE 280uA. 260 = 0xD 260uA. 240 = 0xC 240uA. 220 = 0xB 220uA. 200 = 0xA 200uA. 180 = 0x9 180uA. 160 = 0x8 160uA. 140 = 0x7 140uA. 120 = 0x6 120uA. 100 = 0x5 100uA. 80 = 0x4 80uA. 60 = 0x3 60uA. 40 = 0x2 40uA. 20 = 0x1 20uA. ZERO = 0x0 0uA. 3:0 TEMP_ISRC0 RW 0x0 When the output voltage is lower than 1V the output current is 1uA higher than the decode shown above. This extra current drops to zero as the output voltage raises above 1.5V. This four bit field encodes the current magnitude to inject into an external temperature sensor attached to LRADC0. 300 = 0xF 300uA. 280 = 0xE 280uA. 260 = 0xD 260uA. 240 = 0xC 240uA. 220 = 0xB 220uA. 200 = 0xA 200uA. 180 = 0x9 180uA. 160 = 0x8 160uA. 140 = 0x7 140uA. 120 = 0x6 120uA. 100 = 0x5 100uA. 80 = 0x4 80uA. 60 = 0x3 60uA. 40 = 0x2 40uA. 20 = 0x1 20uA. ZERO = 0x0 0uA. i.MX23 Applications Processor Reference Manual, Rev. 1 33-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface DESCRIPTION: The LRADC control register 2 provides control over the shared eight channel LRADC converter. It allows software to independently schedule conversion cycles on any number of any size subsets of the eight channels. In addition it allows software to manage the interrupt reporting for the channel conversion sets. EXAMPLE: BW_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE); 33.4.4 LRADC Control Register 3 Description The LRADC touch panel control register specifies the voltages at which a touch detect interrupt is generated. HW_LRADC_CTRL3 HW_LRADC_CTRL3_SET HW_LRADC_CTRL3_CLR HW_LRADC_CTRL3_TOG Table 33-7. HW_LRADC_CTRL3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 FORCE_ANALOG_PWUP 0x030 0x034 0x038 0x03C 2 2 FORCE_ANALOG_PWDN 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 33-8. HW_LRADC_CTRL3 Bit Field Descriptions BITS LABEL 31:26 RSRVD5 25:24 DISCARD RW RESET RO 0x0 RW 0x0 DEFINITION Reserved This bit field specifies the number of samples to discard whenever the LRADC analog is first powered up. 00= discard first 3 samples 01= discard first sample 10= discard first 2 samples 11= discard first 3 samples 1_SAMPLE = 0x1 discard first sample before first capture. 2_SAMPLES = 0x2 discard 2 samples before first capture. 3_SAMPLES = 0x3 discard 3 samples before first capture. 23 FORCE_ANALOG_PWUP RW 0x0 Set this bit to zero for normal operation. Setting it to one forces an analog power up, regardless of where the digital state machine may be. OFF = 0x0 Turn it off. ON = 0x1 Turn it on. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice INVERT_CLOCK DELAY_CLOCK CYCLE_TIME HIGH_TIME DISCARD RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 33-15 Low-Resolution ADC and Touch-Screen Interface Table 33-8. HW_LRADC_CTRL3 Bit Field Descriptions BITS LABEL 22 FORCE_ANALOG_PWDN RW RESET RW 0x0 DEFINITION Set this bit to zero for normal operation. Setting it to one forces an analog power down, regardless of where the digital state machine may be. ON = 0x0 Turn it on. OFF = 0x1 Turn it off. 21:14 RSRVD4 13:10 RSRVD3 CYCLE_TIME 9:8 RO 0x0 RO 0x0 RW 0x0 Reserved Reserved Changes the LRADC clock frequency. Note: the sample rate is one thirteenth of the frequency selected here. 00= 6MHz 01= 4MHz 10= 3MHz 11= 2MHz 6MHZ = 0x0 6MHz clock. 4MHZ = 0x1 4MHz clock. 3MHZ = 0x2 3MHz clock. 2MHZ = 0x3 2MHz clock. 7:6 5:4 RSRVD2 HIGH_TIME RO 0x0 RW 0x0 Reserved When CYCLE_TIME=00 only 00 and 01 are valid for HIGH_TIME. When CYCLE_TIME=01 only 00,01,and 10 are valid Changes the duty cycle (time high) for the LRADC clock. 00= 41.66ns 01= 83.33ns 10= 125ns 11= 250ns 42NS = 0x0 Duty cycle high time to 41.66ns. 83NS = 0x1 Duty cycle high time to 83.33ns. 125NS = 0x2 Duty cycle high time to 125ns. 250NS = 0x3 Duty cycle high time to 250ns. 3:2 1 RSRVD1 DELAY_CLOCK RO 0x0 RW 0x0 Reserved Set this bit to one to delay the 24MHz clock used in the LRADC even further away from the predominant rising edge used within the digital section. The delay inserted is approximately 400pS. NORMAL = 0x0 Normal operation, that is no delay. DELAYED = 0x1 Delay the clock. 0 INVERT_CLOCK RW 0x0 Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section. This moves it away from the predominant digital rising edge. Setting this bit to one causes the A/D converter to run from the negative edge of the divided clock, effectively shifting the conversion point away from the edge used by the DCDC converter. NORMAL = 0x0 Run the clock in normal that is not inverted mode. INVERT = 0x1 Inver the clock. DESCRIPTION: The LRADC touch detect control and status register controls the voltage at which a touch detection interrupt is generated. This register also contains the interrupt request status bit and enable bit for the touch detection interrupt request to the CPU's IRQ interrupt input. i.MX23 Applications Processor Reference Manual, Rev. 1 33-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface EXAMPLE: BW_LRADC_CTRL3_HIGH_TIME(BV_LRADC_CTRL3_HIGH_TIME__83NS); BW_LRADC_CTRL3_INVERT_CLOCK(BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL); 33.4.5 LRADC Status Register Description HW_LRADC_STATUS HW_LRADC_STATUS_SET HW_LRADC_STATUS_CLR HW_LRADC_STATUS_TOG Table 33-9. HW_LRADC_STATUS The LRADC status register returns various read-only status bit field values. 0x040 0x044 0x048 0x04C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 TOUCH_PANEL_PRESENT 2 3 CHANNEL7_PRESENT 2 2 CHANNEL6_PRESENT 2 1 CHANNEL5_PRESENT 2 0 CHANNEL4_PRESENT 1 9 CHANNEL3_PRESENT 1 8 CHANNEL2_PRESENT 1 7 CHANNEL1_PRESENT 1 6 CHANNEL0_PRESENT 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TOUCH_DETECT_RAW TEMP1_PRESENT TEMP0_PRESENT RSRVD3 Table 33-10. HW_LRADC_STATUS Bit Field Descriptions BITS LABEL 31:27 RSRVD3 TEMP1_PRESENT 26 RW RESET RO 0x0 RO 0x1 DEFINITION Reserved This read-only bit returns a one when the temperature sensor 1 current source is present on the chip. This read-only bit returns a one when the temperature sensor 0 current source is present on the chip. This read-only bit returns a one when the touch panel controller function is present on the chip. This read-only bit returns a one when the LRADC channel 7 converter function is present on the chip. This read-only bit returns a one when the LRADC channel 6 converter function is present on the chip. This read-only bit returns a one when the LRADC channel 5 converter function is present on the chip. This read-only bit returns a one when the LRADC channel 4 converter function is present on the chip. This read-only bit returns a one when the LRADC channel 3 converter function is present on the chip. This read-only bit returns a one when the LRADC channel 2 converter function is present on the chip. This read-only bit returns a one when the LRADC channel 1 converter function is present on the chip. This read-only bit returns a one when the LRADC channel 0 converter function is present on the chip. 25 24 23 22 21 20 19 18 17 16 TEMP0_PRESENT TOUCH_PANEL_PRESENT CHANNEL7_PRESENT CHANNEL6_PRESENT CHANNEL5_PRESENT CHANNEL4_PRESENT CHANNEL3_PRESENT CHANNEL2_PRESENT CHANNEL1_PRESENT CHANNEL0_PRESENT RO 0x1 RO 0x1 RO 0x1 RO 0x1 RO 0x1 RO 0x1 RO 0x1 RO 0x1 RO 0x1 RO 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD2 33-17 Low-Resolution ADC and Touch-Screen Interface Table 33-10. HW_LRADC_STATUS Bit Field Descriptions BITS LABEL 15:1 RSRVD2 TOUCH_DETECT_RAW 0 RW RESET RO 0x0 RO 0x0 DEFINITION Reserved This read-only bit shows the status of the Touch Detect Comparator in the analog section. OPEN = 0x0 No contact, i.e. open connection. HIT = 0x1 Someone is touching the panel. DESCRIPTION: The status register returns the value of a number of status bit fields. EXAMPLE: if(HW_LRADC_STATUS.TOUCH_DETECT_RAW == BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT){ // Then something is touching the screen. } 33.4.6 LRADC 0 Result Register Description The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel zero. HW_LRADC_CH0 HW_LRADC_CH0_SET HW_LRADC_CH0_CLR HW_LRADC_CH0_TOG Table 33-11. HW_LRADC_CH0 3 1 3 0 2 9 ACCUMULATE 0x050 0x054 0x058 0x05C 2 8 2 7 2 6 NUM_SAMPLES 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TOGGLE RSRVD2 RSRVD1 Table 33-12. HW_LRADC_CH0 Bit Field Descriptions BITS 31 TOGGLE LABEL RW RESET RW 0x0 DEFINITION This bit toggles at every completed conversion so software can detect a missed or duplicated sample. Reserved Set this bit to one to add successive samples to the 18 bit accumulator. This bit field contains the number of conversion cycles to sum together before reporting operation complete interrupt status. Set this field to zero for a single conversion per interrupt. 30 29 RSRVD2 ACCUMULATE RO 0x0 RW 0x0 RW 0x0 28:24 NUM_SAMPLES i.MX23 Applications Processor Reference Manual, Rev. 1 33-18 Preliminary--Subject to Change Without Notice VALUE Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface Table 33-12. HW_LRADC_CH0 Bit Field Descriptions BITS 23:18 RSRVD1 17:0 VALUE LABEL RW RESET RO 0x000 RW 0x0000 DEFINITION Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. DESCRIPTION: The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE: if (HW_LRADC_CHn(0).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(0, (BF_LRADC_CHn_ACCUMULATE(1) | // Enable accumulation mode. BF_LRADC_CHn_NUM_SAMPLES(5) | // Set samples to five. BF_LRADC_CHn_VALUE(0) ) ); // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC0_IRQ != BV_LRADC_CTRL1_LRADC0_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(0).VALUE / 5; 33.4.7 LRADC 1 Result Register Description The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel one. HW_LRADC_CH1 HW_LRADC_CH1_SET HW_LRADC_CH1_CLR HW_LRADC_CH1_TOG 0x060 0x064 0x068 0x06C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-19 Low-Resolution ADC and Touch-Screen Interface Table 33-13. HW_LRADC_CH1 3 1 3 0 2 9 ACCUMULATE 2 8 2 7 2 6 NUM_SAMPLES 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TOGGLE RSRVD2 RSRVD1 Table 33-14. HW_LRADC_CH1 Bit Field Descriptions BITS 31 TOGGLE LABEL RW RESET RW 0x0 DEFINITION This toggles at every completed conversion so software can detect a missed or duplicated sample. Reserved Set this bit to one to add successive samples to the 18 bit accumulator. This bit field contains the number of conversion cycles to sum together before reporting operation complete interrupt status. Set this field to zero for a single conversion per interrupt. Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. 30 29 RSRVD2 ACCUMULATE RO 0x0 RW 0x0 RW 0x0 28:24 NUM_SAMPLES 23:18 RSRVD1 17:0 VALUE RO 0x000 RW 0x0000 DESCRIPTION: The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE: if (HW_LRADC_CHn(1).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(1, (BF_LRADC_CHn_ACCUMULATE(1) | // Enable accumulation mode. BF_LRADC_CHn_NUM_SAMPLES(5) | // Set samples to five. BF_LRADC_CHn_VALUE(0) ) ); // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC1_IRQ != BV_LRADC_CTRL1_LRADC1_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(1).VALUE / 5; i.MX23 Applications Processor Reference Manual, Rev. 1 33-20 Preliminary--Subject to Change Without Notice VALUE Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface 33.4.8 LRADC 2 Result Register Description The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel two. HW_LRADC_CH2 HW_LRADC_CH2_SET HW_LRADC_CH2_CLR HW_LRADC_CH2_TOG Table 33-15. HW_LRADC_CH2 3 1 3 0 2 9 ACCUMULATE 0x070 0x074 0x078 0x07C 2 8 2 7 2 6 NUM_SAMPLES 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TOGGLE RSRVD2 RSRVD1 Table 33-16. HW_LRADC_CH2 Bit Field Descriptions BITS 31 TOGGLE LABEL RW RESET RW 0x0 DEFINITION This bit toggles at every completed conversion so software can detect a missed or duplicated sample. Reserved Set this bit to one to add successive samples to the 18 bit accumulator. This bit field contains the number of conversion cycles to sum together before reporting operation complete interrupt status. Set this field to zero for a single conversion per interrupt. Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. 30 29 RSRVD2 ACCUMULATE RO 0x0 RW 0x0 RW 0x0 28:24 NUM_SAMPLES 23:18 RSRVD1 17:0 VALUE RO 0x000 RW 0x0000 DESCRIPTION: The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice VALUE 33-21 Low-Resolution ADC and Touch-Screen Interface EXAMPLE: if (HW_LRADC_CHn(2).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(2, (BF_LRADC_CHn_ACCUMULATE(1) | // Enable accumulation mode. BF_LRADC_CHn_NUM_SAMPLES(5) | // Set samples to five. BF_LRADC_CHn_VALUE(0) ) ); // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC2_IRQ != BV_LRADC_CTRL1_LRADC2_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(2).VALUE / 5; 33.4.9 LRADC 3 Result Register Description The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel three. HW_LRADC_CH3 HW_LRADC_CH3_SET HW_LRADC_CH3_CLR HW_LRADC_CH3_TOG Table 33-17. HW_LRADC_CH3 3 1 3 0 2 9 ACCUMULATE 0x080 0x084 0x088 0x08C 2 8 2 7 2 6 NUM_SAMPLES 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TOGGLE RSRVD2 RSRVD1 Table 33-18. HW_LRADC_CH3 Bit Field Descriptions BITS 31 TOGGLE LABEL RW RESET RW 0x0 DEFINITION This bit toggles at every completed conversion so software can detect a missed or duplicated sample. Reserved Set this bit to one to add successive samples to the 18 bit accumulator. This bit field contains the number of conversion cycles to sum together before reporting operation complete interrupt status. Set this field to zero for a single conversion per interrupt. 30 29 RSRVD2 ACCUMULATE RO 0x0 RW 0x0 RW 0x0 28:24 NUM_SAMPLES i.MX23 Applications Processor Reference Manual, Rev. 1 33-22 Preliminary--Subject to Change Without Notice VALUE Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface Table 33-18. HW_LRADC_CH3 Bit Field Descriptions BITS 23:18 RSRVD1 17:0 VALUE LABEL RW RESET RO 0x000 RW 0x0000 DEFINITION Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. DESCRIPTION: The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE: if (HW_LRADC_CHn(3).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(3, (BF_LRADC_CHn_ACCUMULATE(1) | // Enable accumulation mode. BF_LRADC_CHn_NUM_SAMPLES(5) | // Set samples to five. BF_LRADC_CHn_VALUE(0) ) ); // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC3_IRQ != BV_LRADC_CTRL1_LRADC3_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(3).VALUE / 5; 33.4.10 LRADC 4 Result Register Description The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel four. HW_LRADC_CH4 HW_LRADC_CH4_SET HW_LRADC_CH4_CLR HW_LRADC_CH4_TOG 0x090 0x094 0x098 0x09C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-23 Low-Resolution ADC and Touch-Screen Interface Table 33-19. HW_LRADC_CH4 3 1 3 0 2 9 ACCUMULATE 2 8 2 7 2 6 NUM_SAMPLES 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TOGGLE RSRVD2 RSRVD1 Table 33-20. HW_LRADC_CH4 Bit Field Descriptions BITS 31 TOGGLE LABEL RW RESET RW 0x0 DEFINITION This bit toggles at every completed conversion so software can detect a missed or duplicated sample. Reserved Set this bit to one to add successive samples to the 18 bit accumulator. This bit field contains the number of conversion cycles to sum together before reporting operation complete interrupt status. Set this field to zero for a single conversion per interrupt. Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. 30 29 RSRVD2 ACCUMULATE RO 0x0 RW 0x0 RW 0x0 28:24 NUM_SAMPLES 23:18 RSRVD1 17:0 VALUE RO 0x000 RW 0x0000 DESCRIPTION: The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE: if (HW_LRADC_CHn(4).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(4, (BF_LRADC_CHn_ACCUMULATE(1) | // Enable accumulation mode. BF_LRADC_CHn_NUM_SAMPLES(5) | // Set samples to five. BF_LRADC_CHn_VALUE(0) ) ); // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC4_IRQ != BV_LRADC_CTRL1_LRADC4_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(4).VALUE / 5; i.MX23 Applications Processor Reference Manual, Rev. 1 33-24 Preliminary--Subject to Change Without Notice VALUE Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface 33.4.11 LRADC 5 Result Register Description The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel five. HW_LRADC_CH5 HW_LRADC_CH5_SET HW_LRADC_CH5_CLR HW_LRADC_CH5_TOG Table 33-21. HW_LRADC_CH5 3 1 3 0 2 9 ACCUMULATE 0x0A0 0x0A4 0x0A8 0x0AC 2 8 2 7 2 6 NUM_SAMPLES 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TOGGLE RSRVD2 RSRVD1 Table 33-22. HW_LRADC_CH5 Bit Field Descriptions BITS 31 TOGGLE LABEL RW RESET RW 0x0 DEFINITION This bit toggles at every completed conversion so software can detect a missed or duplicated sample. Reserved Set this bit to one to add successive samples to the 18 bit accumulator. This bit field contains the number of conversion cycles to sum together before reporting operation complete interrupt status. Set this field to zero for a single conversion per interrupt. Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. 30 29 RSRVD2 ACCUMULATE RO 0x0 RW 0x0 RW 0x0 28:24 NUM_SAMPLES 23:18 RSRVD1 17:0 VALUE RO 0x000 RW 0x0000 DESCRIPTION: The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice VALUE 33-25 Low-Resolution ADC and Touch-Screen Interface EXAMPLE: if (HW_LRADC_CHn(5).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(5, (BF_LRADC_CHn_ACCUMULATE(1) | // Enable accumulation mode. BF_LRADC_CHn_NUM_SAMPLES(5) | // Set samples to five. BF_LRADC_CHn_VALUE(0) ) ); // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC5_IRQ != BV_LRADC_CTRL1_LRADC5_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(5).VALUE / 5; 33.4.12 LRADC 6 (VddIO) Result Register Description The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel six (VddIO). HW_LRADC_CH6 HW_LRADC_CH6_SET HW_LRADC_CH6_CLR HW_LRADC_CH6_TOG Table 33-23. HW_LRADC_CH6 3 1 3 0 2 9 ACCUMULATE 0x0B0 0x0B4 0x0B8 0x0BC 2 8 2 7 2 6 NUM_SAMPLES 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TOGGLE RSRVD2 RSRVD1 Table 33-24. HW_LRADC_CH6 Bit Field Descriptions BITS 31 TOGGLE LABEL RW RESET RW 0x0 DEFINITION This bit toggles at every completed conversion so software can detect a missed or duplicated sample. Reserved Set this bit to one to add successive samples to the 18 bit accumulator. This bit field contains the number of conversion cycles to sum together before reporting operation complete interrupt status. Set this field to zero for a single conversion per interrupt. 30 29 RSRVD2 ACCUMULATE RO 0x0 RW 0x0 RW 0x0 28:24 NUM_SAMPLES i.MX23 Applications Processor Reference Manual, Rev. 1 33-26 Preliminary--Subject to Change Without Notice VALUE Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface Table 33-24. HW_LRADC_CH6 Bit Field Descriptions BITS 23:18 RSRVD1 17:0 VALUE LABEL RW RESET RO 0x000 RW 0x0000 DEFINITION Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. DESCRIPTION: The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE: if (HW_LRADC_CHn(6).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(6, (BF_LRADC_CHn_ACCUMULATE(1) | // Enable accumulation mode. BF_LRADC_CHn_NUM_SAMPLES(5) | // Set samples to five. BF_LRADC_CHn_VALUE(0) ) ); // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC6_IRQ != BV_LRADC_CTRL1_LRADC6_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(6).VALUE / 5; 33.4.13 LRADC 7 (BATT) Result Register Description The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel seven (BATT). HW_LRADC_CH7 HW_LRADC_CH7_SET HW_LRADC_CH7_CLR HW_LRADC_CH7_TOG 0x0C0 0x0C4 0x0C8 0x0CC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-27 Low-Resolution ADC and Touch-Screen Interface Table 33-25. HW_LRADC_CH7 3 1 3 0 TESTMODE_TOGGLE 2 9 2 8 2 7 2 6 NUM_SAMPLES 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ACCUMULATE TOGGLE RSRVD1 Table 33-26. HW_LRADC_CH7 Bit Field Descriptions BITS 31 TOGGLE LABEL RW RESET RW 0x0 DEFINITION This bit toggles at every completed conversion so software can detect a missed or duplicated sample. This read-only bit toggles at every completed conversion of interest in test mode so software can synchornize to the desired sample. When the test mode count is loaded with a value of 7, this will toggle every eighth conversion on channel 7. If testmode operation for channel 5 and or 6 are set then the sample rate will be lower for channel 7. Set this bit to one to add successive samples to the 18 bit accumulator. This bit field contains the number of conversion cycles to sum together before reporting operation complete interrupt status. Set this field to zero for a single conversion per interrupt. Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. 30 TESTMODE_TOGGLE RO 0x0 29 ACCUMULATE RW 0x0 RW 0x0 28:24 NUM_SAMPLES 23:18 RSRVD1 17:0 VALUE RO 0x000 RW 0x0000 DESCRIPTION: The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. i.MX23 Applications Processor Reference Manual, Rev. 1 33-28 Preliminary--Subject to Change Without Notice VALUE Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface EXAMPLE: if (HW_LRADC_CHn(7).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(7, (BF_LRADC_CHn_ACCUMULATE(1) | // Enable accumulation mode. BF_LRADC_CHn_NUM_SAMPLES(5) | // Set samples to five. BF_LRADC_CHn_VALUE(0) ) ); // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC7_IRQ != BV_LRADC_CTRL1_LRADC7_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(7).VALUE / 5; 33.4.14 LRADC Scheduling Delay 0 Description The LRADC scheduling delay 0 register controls one delay operation. At the end of this delay, this channel can trigger one or more LRADC channels or one or more Scheduling delay channels . HW_LRADC_DELAY0 HW_LRADC_DELAY0_SET HW_LRADC_DELAY0_CLR HW_LRADC_DELAY0_TOG Table 33-27. HW_LRADC_DELAY0 3 1 3 0 2 9 2 8 TRIGGER_LRADCS 0x0D0 0x0D4 0x0D8 0x0DC 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 TRIGGER_DELAYS 1 7 1 6 1 5 1 4 1 3 LOOP_COUNT 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD2 Table 33-28. HW_LRADC_DELAY0 Bit Field Descriptions BITS LABEL 31:24 TRIGGER_LRADCS RW RESET RW 0x00 DEFINITION Setting a bit in this bit field to one causes the delay controller to trigger the corresponding LRADC channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all eight LRADC channels can be triggered at the same time. Any channel with its corresponding bit set in this field is triggered. The HW accomplishes this by setting the corresponding bit(s) in HW_LRADC_CTRL0_SCHEDULE. Reserved Setting this bit to one initiates a delay cycle. At the end of that cycle, any TRIGGER_LRADCS or TRIGGER_DELAYS will start. 23:21 RSRVD2 KICK 20 RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice DELAY KICK 33-29 Low-Resolution ADC and Touch-Screen Interface Table 33-28. HW_LRADC_DELAY0 Bit Field Descriptions BITS LABEL 19:16 TRIGGER_DELAYS RW RESET RW 0x0 DEFINITION Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all four delay channels can be triggered at the same time, including the one that issues the trigger. This can have the effect of automatically retriggering a delay channel. This bit field specifies the number of times this delay counter will count down and then trigger its designated targets. This is particularly useful for scheduling multiple samples of an LRADC channel set. If this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target LRADC and/or delay channels. Note setting the loop count to 0x01 will yield two conversions. This 11-bit field counts down to zero. At zero it triggers either a set of LRADC channel conversions or another delay channel, or both. It can trigger up to all eight LRADCs and all four delay channels in a single even. This counter operates on a 2KHz clock derived from crystal clock. 15:11 LOOP_COUNT RW 0x00 10:0 DELAY RW 0x000 DESCRIPTION: The LRADC Delay Channel provides control by which LRADC channels and delay channels (including itself) may be triggered. The triggering of the selected delay and LRADC channel(s) is delayed by the DELAY field value which counts down on a 2 kHz clock. It is possible to use delay channels chained together to configure dependent timing of channel conversions as in the example provided in introduction to this block. A delay channel may also be configured to trigger itself. In this case, it could be used to simultaneously trigger an LRADC channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the DELAY field. The delay channel is started by setting the KICK bit to one. EXAMPLE: HW_LRADC_DELAYn_WR(0, (BF_LRADC_DELAYn_TRIGGER_LRADCS(0x05) | // LRADC channel 0 and 2 BF_LRADC_DELAYn_KICK(1) | // Start the Delay channel BF_LRADC_DELAYn_TRIGGER_DELAYS(0x1) | // restart delay channel 0 each time BF_LRADC_DELAYn_DELAY(0x0E45) ) ); // delay 3653 periods of 2 kHz clock // ... do other things until the triggered LRADC channels report an interrupt. 33.4.15 LRADC Scheduling Delay 1 Description The LRADC scheduling delay 1 register controls one delay operation. At the end of this delay, this channel can trigger one or more LRADC channels or one or more Scheduling delay channels . HW_LRADC_DELAY1 HW_LRADC_DELAY1_SET HW_LRADC_DELAY1_CLR HW_LRADC_DELAY1_TOG 0x0E0 0x0E4 0x0E8 0x0EC i.MX23 Applications Processor Reference Manual, Rev. 1 33-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface Table 33-29. HW_LRADC_DELAY1 3 1 3 0 2 9 2 8 TRIGGER_LRADCS 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 TRIGGER_DELAYS 1 7 1 6 1 5 1 4 1 3 LOOP_COUNT 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD2 Table 33-30. HW_LRADC_DELAY1 Bit Field Descriptions BITS LABEL 31:24 TRIGGER_LRADCS RW RESET RW 0x00 DEFINITION Setting a bit in this bit field to one causes the delay controller to trigger the corresponding LRADC channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all eight LRADC channels can be triggered at the same time. Any channel with its corresponding bit set in this field is triggered. The HW accomplishes this by setting the corresponding bit(s) in HW_LRADC_CTRL0_SCHEDULE. Reserved Setting this bit to one initiates a delay cycle. At the end of that cycle, any TRIGGER_LRADCS or TRIGGER_DELAYS will start. Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all four delay channels can be triggered at the same time, including the one that issues the trigger. This can have the effect of automatically retriggering a delay channel. This bit field specifies the number of times this delay counter will count down and then trigger its designated targets. This is particularly useful for scheduling multiple samples of an LRADC channel set. If this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target LRADC and/or delay channels. This 11-bit field counts down to zero. At zero it triggers either a set of LRADC channel conversions or another delay channel, or both. It can trigger up to all eight LRADCs and all four delay channels in a single even. This counter operates on a 2KHz clock derived from crystal clock. 23:21 RSRVD2 KICK 20 RO 0x0 RW 0x0 19:16 TRIGGER_DELAYS RW 0x0 15:11 LOOP_COUNT RW 0x00 10:0 DELAY RW 0x000 DESCRIPTION: The LRADC Delay Channel provides control by which LRADC channels and delay channels (including itself) may be triggered. The triggering of the selected delay and LRADC channel(s) is delayed by the DELAY field value which counts down on a 2 kHz clock. It is possible to use delay channels chained i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice DELAY KICK 33-31 Low-Resolution ADC and Touch-Screen Interface together to configure dependent timing of channel conversions as in the example provided in introduction to this block. A delay channel may also be configured to trigger itself. In this case, it could be used to simultaneously trigger an LRADC channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the DELAY field. The delay channel is started by setting the KICK bit to one. EXAMPLE: HW_LRADC_DELAYn_WR(1, (BF_LRADC_DELAYn_TRIGGER_LRADCS(0x05) | // LRADC channel 0 and 2 BF_LRADC_DELAYn_KICK(1) | // Start the Delay channel BF_LRADC_DELAYn_TRIGGER_DELAYS(0x2) | // restart delay channel 1 each time BF_LRADC_DELAYn_DELAY(0x0E45) ) ); // delay 3653 periods of 2 kHz clock // ... do other things until the triggered LRADC channels report an interrupt. 33.4.16 LRADC Scheduling Delay 2 Description The LRADC scheduling delay 2 register controls one delay operation. At the end of this delay, this channel can trigger one or more LRADC channels or one or more Scheduling delay channels . HW_LRADC_DELAY2 HW_LRADC_DELAY2_SET HW_LRADC_DELAY2_CLR HW_LRADC_DELAY2_TOG Table 33-31. HW_LRADC_DELAY2 3 1 3 0 2 9 2 8 TRIGGER_LRADCS 0x0F0 0x0F4 0x0F8 0x0FC 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 TRIGGER_DELAYS 1 7 1 6 1 5 1 4 1 3 LOOP_COUNT 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD2 Table 33-32. HW_LRADC_DELAY2 Bit Field Descriptions BITS LABEL 31:24 TRIGGER_LRADCS RW RESET RW 0x00 DEFINITION Setting a bit in this bit field to one causes the delay controller to trigger the corresponding LRADC channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all eight LRADC channels can be triggered at the same time. Any channel with its corresponding bit set in this field is triggered. The HW accomplishes this by setting the corresponding bit(s) in HW_LRADC_CTRL0_SCHEDULE. Reserved Setting this bit to one initiates a delay cycle. At the end of that cycle, any TRIGGER_LRADCS or TRIGGER_DELAYS will start. 23:21 RSRVD2 KICK 20 RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 33-32 Preliminary--Subject to Change Without Notice DELAY KICK Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface Table 33-32. HW_LRADC_DELAY2 Bit Field Descriptions BITS LABEL 19:16 TRIGGER_DELAYS RW RESET RW 0x0 DEFINITION Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all four delay channels can be triggered at the same time, including the one that issues the trigger. This can have the effect of automatically retriggering a delay channel. This bit field specifies the number of times this delay counter will count down and then trigger its designated targets. This is particularly useful for scheduling multiple samples of an LRADC channel set. If this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target LRADC and/or delay channels. ERRATA: TA1 and TA2 silicon revisions do not correctly support the LOOP_COUNT field, do not use. This 11-bit field counts down to zero. At zero it triggers either a set of LRADC channel conversions or another delay channel, or both. It can trigger up to all eight LRADCs and all four delay channels in a single even. This counter operates on a 2KHz clock derived from crystal clock. 15:11 LOOP_COUNT RW 0x00 10:0 DELAY RW 0x000 DESCRIPTION: The LRADC Delay Channel provides control by which LRADC channels and delay channels (including itself) may be triggered. The triggering of the selected delay and LRADC channel(s) is delayed by the DELAY field value which counts down on a 2 kHz clock. It is possible to use delay channels chained together to configure dependent timing of channel conversions as in the example provided in introduction to this block. A delay channel may also be configured to trigger itself. In this case, it could be used to simultaneously trigger an LRADC channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the DELAY field. The delay channel is started by setting the KICK bit to one. EXAMPLE: HW_LRADC_DELAYn_WR(2, (BF_LRADC_DELAYn_TRIGGER_LRADCS(0x05) | // LRADC channel 0 and 2 BF_LRADC_DELAYn_KICK(1) | // Start the Delay channel BF_LRADC_DELAYn_TRIGGER_DELAYS(0x4) | // restart delay channel 2 each time BF_LRADC_DELAYn_DELAY(0x0E45) ) ); // delay 3653 periods of 2 kHz clock // ... do other things until the triggered LRADC channels report an interrupt. 33.4.17 LRADC Scheduling Delay 3 Description The LRADC scheduling delay 3 register controls one delay operation. At the end of this delay, this channel can trigger one or more LRADC channels or one or more Scheduling delay channels . HW_LRADC_DELAY3 HW_LRADC_DELAY3_SET HW_LRADC_DELAY3_CLR HW_LRADC_DELAY3_TOG 0x100 0x104 0x108 0x10C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-33 Low-Resolution ADC and Touch-Screen Interface Table 33-33. HW_LRADC_DELAY3 3 1 3 0 2 9 2 8 TRIGGER_LRADCS 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 TRIGGER_DELAYS 1 7 1 6 1 5 1 4 1 3 LOOP_COUNT 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RSRVD2 Table 33-34. HW_LRADC_DELAY3 Bit Field Descriptions BITS LABEL 31:24 TRIGGER_LRADCS RW RESET RW 0x00 DEFINITION Setting a bit in this bit field to one causes the delay controller to trigger the corresponding LRADC channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all eight LRADC channels can be triggered at the same time. Any channel with its corresponding bit set in this field is triggered. The HW accomplishes this by setting the corresponding bit(s) in HW_LRADC_CTRL0_SCHEDULE. Reserved Setting this bit to one initiates a delay cycle. At the end of that cycle, any TRIGGER_LRADCS or TRIGGER_DELAYS will start. Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all four delay channels can be triggered at the same time, including the one that issues the trigger. This can have the effect of automatically retriggering a delay channel. This bit field specifies the number of times this delay counter will count down and then trigger its designated targets. This is particularly useful for scheduling multiple samples of an LRADC channel set. If this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target LRADC and/or delay channels. ERRATA: TA1 and TA2 silicon revisions do not correctly support the LOOP_COUNT field, do not use. This 11-bit field counts down to zero. At zero it triggers either a set of LRADC channel conversions or another delay channel, or both. It can trigger up to all eight LRADCs and all four delay channels in a single even. This counter operates on a 2KHz clock derived from crystal clock. 23:21 RSRVD2 KICK 20 RO 0x0 RW 0x0 19:16 TRIGGER_DELAYS RW 0x0 15:11 LOOP_COUNT RW 0x00 10:0 DELAY RW 0x000 i.MX23 Applications Processor Reference Manual, Rev. 1 33-34 Preliminary--Subject to Change Without Notice DELAY KICK Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface DESCRIPTION: The LRADC Delay Channel provides control by which LRADC channels and delay channels (including itself) may be triggered. The triggering of the selected delay and LRADC channel(s) is delayed by the DELAY field value which counts down on a 2 kHz clock. It is possible to use delay channels chained together to configure dependent timing of channel conversions as in the example provided in introduction to this block. A delay channel may also be configured to trigger itself. In this case, it could be used to simultaneously trigger an LRADC channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the DELAY field. The delay channel is started by setting the KICK bit to one. EXAMPLE: HW_LRADC_DELAYn_WR(3, (BF_LRADC_DELAYn_TRIGGER_LRADCS(0x05) | // LRADC channel 0 and 2 BF_LRADC_DELAYn_KICK(1) | // Start the Delay channel BF_LRADC_DELAYn_TRIGGER_DELAYS(0x8) | // restart delay channel 3 each time BF_LRADC_DELAYn_DELAY(0x0E45) ) ); // delay 3653 periods of 2 kHz clock // ... do other things until the triggered LRADC channels report an interrupt. 33.4.18 LRADC Debug Register 0 Description The LRADC debug register provides read-only access to various internal states and other debug information. HW_LRADC_DEBUG0 HW_LRADC_DEBUG0_SET HW_LRADC_DEBUG0_CLR HW_LRADC_DEBUG0_TOG Table 33-35. HW_LRADC_DEBUG0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 READONLY 0x110 0x114 0x118 0x11C 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 RSRVD1 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 STATE 0 5 0 4 0 3 0 2 0 1 0 0 Table 33-36. HW_LRADC_DEBUG0 Bit Field Descriptions BITS LABEL 31:16 READONLY 15:12 RSRVD1 11:0 STATE RW RESET RO 0x4321 RO 0x0 RO 0x0 DEFINITION LRADC internal state machine current state. Reserved LRADC internal state machine current state. DESCRIPTION: The LRADC debug register contains read-only diagnostic information regarding the internal state machine. This only used in debugging. EXAMPLE: if (HW_LRADC_DEBUG0.STATE == 0X33) {} // some action based on this state. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-35 Low-Resolution ADC and Touch-Screen Interface 33.4.19 LRADC Debug Register 1 Description The LRADC debug register provides read-only access to various internal states and other debug information. HW_LRADC_DEBUG1 HW_LRADC_DEBUG1_SET HW_LRADC_DEBUG1_CLR HW_LRADC_DEBUG1_TOG Table 33-37. HW_LRADC_DEBUG1 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 TESTMODE_COUNT 0x120 0x124 0x128 0x12C 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 TESTMODE6 TESTMODE5 Table 33-38. HW_LRADC_DEBUG1 Bit Field Descriptions BITS 31:24 23:16 15:13 12:8 LABEL RSRVD3 REQUEST RSRVD2 TESTMODE_COUNT RW RO RO RO RW RESET 0x0 0x0 0x0 0x0 DEFINITION Reserved LRADC internal request register. Reserved When in test mode, the value in this register will be loaded in to a counter which is decremented upon each Channel 7 conversion. When that counter decrements to zero, the HW_LRADC_CH7.TESTMODE_TOGGLE field will be toggled, indicating that the conversion value of interest is available in the HW_LRADC_CH7.VALUE bit field. Reserved Force dummy conversion cycles on channel 6 during test mode. NORMAL = 0x0 Normal operation. TEST = 0x1 Put it in test mode, i.e. continuously sample channel 6. 7:3 2 RSRVD1 TESTMODE6 RO 0x0 RW 0x0 1 TESTMODE5 RW 0x0 Force dummy conversion cycles on channel 5 during test mode. NORMAL = 0x0 Normal operation. TEST = 0x1 Put it in test mode, i.e. continuously sample channel 5. 0 TESTMODE RW 0x0 Place the LRADC in a special test mode in which the analog section is free-running at its clock rate. LRADC_CH7 result is continuously updated every N conversions from the analog source selected in CTRL2, where N is determined by TESTMODE_COUNT. NORMAL = 0x0 Normal operation. TEST = 0x1 Put it in test mode, i.e. continuously sample channel 7. i.MX23 Applications Processor Reference Manual, Rev. 1 33-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor TESTMODE REQUEST RSRVD3 RSRVD2 RSRVD1 Low-Resolution ADC and Touch-Screen Interface DESCRIPTION: The LRADC DEBUG1 register provides, read-only diagnostic information and control over the test modes of LRADC channels 5, 6 and 7. This is only used in debugging the LRADC. EXAMPLE: BW_LRADC_DEBUG1_TESTMODE(BV_LRADC_DEBUG1_TESTMODE__TEST); 33.4.20 LRADC Battery Conversion Register Description The LRADC battery conversion register provides access to the battery voltage scale multiplier. HW_LRADC_CONVERSION HW_LRADC_CONVERSION_SET HW_LRADC_CONVERSION_CLR HW_LRADC_CONVERSION_TOG 0x130 0x134 0x138 0x13C Table 33-39. HW_LRADC_CONVERSION 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 SCALED_BATT_VOLTAGE 0 4 0 3 0 2 0 1 0 0 SCALE_FACTOR AUTOMATIC RSRVD3 RSRVD2 Table 33-40. HW_LRADC_CONVERSION Bit Field Descriptions BITS LABEL 31:21 RSRVD3 AUTOMATIC 20 RW RESET RO 0x0 RW 0x0 DEFINITION Reserved Control the automatic update mode of the BATT_VAL bit field in the HW_POWER_BATTMONITOR register. DISABLE = 0x0 No automatic update of the scaled value. ENABLE = 0x1 Automatically compute the scaled battery voltage each time an LRADC Channel 7 (BATT) conversion takes place. 19:18 RSRVD2 17:16 SCALE_FACTOR RO 0x0 RW 0x0 Reserved Scale factors of 29/512, 29/256 or 29/128 are selected here. NIMH = 0x0 Single NiMH Battery operation, 29/512. DUAL_NIMH = 0x1 Two NiMH Battery operation, 29/256. LI_ION = 0x2 Lithium Ion Battery operation, 29/128. ALT_LI_ION = 0x3 Lithium Ion Battery operation, 29/128. 15:10 RSRVD1 SCALED_BATT_VOLTAGE 9:0 RO 0x0 RW 0x80 Reserved LRADC Battery Voltage Divided by approximately 17.708. The actual scale factor is (battery voltage) times 29 divided by 512, 256 or 128. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD1 33-37 Low-Resolution ADC and Touch-Screen Interface DESCRIPTION: This register controls the voltage scaling multiplier which is used to multiply the LRADC battery voltage by 29 divided by 512 for NiMH, battery voltage times 29 divided by 256 for dual NiMH and battery voltage times 29 divided by 128 for Lithium Ion batteries. EXAMPLE: HW_LRADC_CONVERSION.AUTOMATIC = 1; 33.4.21 LRADC Control Register 4 Description LRADC control register 4 specifies the analog mux selector values used for channels 0 through channel 7. HW_LRADC_CTRL4 HW_LRADC_CTRL4_SET HW_LRADC_CTRL4_CLR HW_LRADC_CTRL4_TOG Table 33-41. HW_LRADC_CTRL4 3 1 3 0 LRADC7SELECT 0x140 0x144 0x148 0x14C 2 9 2 8 2 7 2 6 LRADC6SELECT 2 5 2 4 2 3 2 2 LRADC5SELECT 2 1 2 0 1 9 1 8 LRADC4SELECT 1 7 1 6 1 5 1 4 LRADC3SELECT 1 3 1 2 1 1 1 0 LRADC2SELECT 0 9 0 8 0 7 0 6 LRADC1SELECT 0 5 0 4 0 3 0 2 LRADC0SELECT 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 33-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface Table 33-42. HW_LRADC_CTRL4 Bit Field Descriptions BITS LABEL 31:28 LRADC7SELECT RW RESET RW 0x7 DEFINITION This bit field selects which analog mux input is used for conversion on LRADC channel 7. CHANNEL0 = 0x0 CHANNEL1 = 0x1 CHANNEL2 = 0x2 CHANNEL3 = 0x3 CHANNEL4 = 0x4 CHANNEL5 = 0x5 CHANNEL6 = 0x6 VDDIO CHANNEL7 = 0x7 BATTERY CHANNEL8 = 0x8 PMOS THIN CHANNEL9 = 0x9 NMOS THIN CHANNEL10 = 0xA NMOS THICK CHANNEL11 = 0xB PMOS THICK CHANNEL12 = 0xC USB_DP (must also set usb_data_on_lradc to use this) CHANNEL13 = 0xD USB_DN (must also set usb_data_on_lradc to use this) CHANNEL14 = 0xE VBG (Can be used to calibrate the LRADC) CHANNEL15 = 0xF 5V input 27:24 LRADC6SELECT RW 0x6 This bit field selects which analog mux input is used for conversion on LRADC channel 6. CHANNEL0 = 0x0 CHANNEL1 = 0x1 CHANNEL2 = 0x2 CHANNEL3 = 0x3 CHANNEL4 = 0x4 CHANNEL5 = 0x5 CHANNEL6 = 0x6 VDDIO CHANNEL7 = 0x7 BATTERY CHANNEL8 = 0x8 PMOS THIN CHANNEL9 = 0x9 NMOS THIN CHANNEL10 = 0xA NMOS THICK CHANNEL11 = 0xB PMOS THICK CHANNEL12 = 0xC USB_DP (must also set usb_data_on_lradc to use this) CHANNEL13 = 0xD USB_DN (must also set usb_data_on_lradc to use this) CHANNEL14 = 0xE VBG (Can be used to calibrate the LRADC) CHANNEL15 = 0xF 5V input 23:20 LRADC5SELECT RW 0x5 This bit field selects which analog mux input is used for conversion on LRADC channel 5. CHANNEL0 = 0x0 CHANNEL1 = 0x1 CHANNEL2 = 0x2 CHANNEL3 = 0x3 CHANNEL4 = 0x4 CHANNEL5 = 0x5 CHANNEL6 = 0x6 VDDIO CHANNEL7 = 0x7 BATTERY CHANNEL8 = 0x8 PMOS THIN CHANNEL9 = 0x9 NMOS THIN CHANNEL10 = 0xA NMOS THICK CHANNEL11 = 0xB PMOS THICK CHANNEL12 = 0xC USB_DP (must also set usb_data_on_lradc to use this) CHANNEL13 = 0xD USB_DN (must also set usb_data_on_lradc to use this) CHANNEL14 = 0xE VBG (Can be used to calibrate the LRADC) CHANNEL15 = 0xF 5V input i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-39 Low-Resolution ADC and Touch-Screen Interface Table 33-42. HW_LRADC_CTRL4 Bit Field Descriptions BITS LABEL 19:16 LRADC4SELECT RW RESET RW 0x4 DEFINITION This bit field selects which analog mux input is used for conversion on LRADC channel 4. CHANNEL0 = 0x0 CHANNEL1 = 0x1 CHANNEL2 = 0x2 CHANNEL3 = 0x3 CHANNEL4 = 0x4 CHANNEL5 = 0x5 CHANNEL6 = 0x6 VDDIO CHANNEL7 = 0x7 BATTERY CHANNEL8 = 0x8 PMOS THIN CHANNEL9 = 0x9 NMOS THIN CHANNEL10 = 0xA NMOS THICK CHANNEL11 = 0xB PMOS THICK CHANNEL12 = 0xC USB_DP (must also set usb_data_on_lradc to use this) CHANNEL13 = 0xD USB_DN (must also set usb_data_on_lradc to use this) CHANNEL14 = 0xE VBG (Can be used to calibrate the LRADC) CHANNEL15 = 0xF 5V input 15:12 LRADC3SELECT RW 0x3 This bit field selects which analog mux input is used for conversion on LRADC channel 3. CHANNEL0 = 0x0 CHANNEL1 = 0x1 CHANNEL2 = 0x2 CHANNEL3 = 0x3 CHANNEL4 = 0x4 CHANNEL5 = 0x5 CHANNEL6 = 0x6 VDDIO CHANNEL7 = 0x7 BATTERY CHANNEL8 = 0x8 PMOS THIN CHANNEL9 = 0x9 NMOS THIN CHANNEL10 = 0xA NMOS THICK CHANNEL11 = 0xB PMOS THICK CHANNEL12 = 0xC USB_DP (must also set usb_data_on_lradc to use this) CHANNEL13 = 0xD USB_DN (must also set usb_data_on_lradc to use this) CHANNEL14 = 0xE VBG (Can be used to calibrate the LRADC) CHANNEL15 = 0xF 5V input 11:8 LRADC2SELECT RW 0x2 This bit field selects which analog mux input is used for conversion on LRADC channel 2. CHANNEL0 = 0x0 CHANNEL1 = 0x1 CHANNEL2 = 0x2 CHANNEL3 = 0x3 CHANNEL4 = 0x4 CHANNEL5 = 0x5 CHANNEL6 = 0x6 VDDIO CHANNEL7 = 0x7 BATTERY CHANNEL8 = 0x8 PMOS THIN CHANNEL9 = 0x9 NMOS THIN CHANNEL10 = 0xA NMOS THICK CHANNEL11 = 0xB PMOS THICK CHANNEL12 = 0xC USB_DP (must also set usb_data_on_lradc to use this) CHANNEL13 = 0xD USB_DN (must also set usb_data_on_lradc to use this) CHANNEL14 = 0xE VBG (Can be used to calibrate the LRADC) CHANNEL15 = 0xF 5V input i.MX23 Applications Processor Reference Manual, Rev. 1 33-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor Low-Resolution ADC and Touch-Screen Interface Table 33-42. HW_LRADC_CTRL4 Bit Field Descriptions BITS LABEL 7:4 LRADC1SELECT RW RESET RW 0x1 DEFINITION This bit field selects which analog mux input is used for conversion on LRADC channel 1. CHANNEL0 = 0x0 CHANNEL1 = 0x1 CHANNEL2 = 0x2 CHANNEL3 = 0x3 CHANNEL4 = 0x4 CHANNEL5 = 0x5 CHANNEL6 = 0x6 VDDIO CHANNEL7 = 0x7 BATTERY CHANNEL8 = 0x8 PMOS THIN CHANNEL9 = 0x9 NMOS THIN CHANNEL10 = 0xA NMOS THICK CHANNEL11 = 0xB PMOS THICK CHANNEL12 = 0xC USB_DP (must also set usb_data_on_lradc to use this) CHANNEL13 = 0xD USB_DN (must also set usb_data_on_lradc to use this) CHANNEL14 = 0xE VBG (Can be used to calibrate the LRADC) CHANNEL15 = 0xF 5V input 3:0 LRADC0SELECT RW 0x0 This bit field selects which analog mux input is used for conversion on LRADC channel 0. CHANNEL0 = 0x0 CHANNEL1 = 0x1 CHANNEL2 = 0x2 CHANNEL3 = 0x3 CHANNEL4 = 0x4 CHANNEL5 = 0x5 CHANNEL6 = 0x6 VDDIO CHANNEL7 = 0x7 BATTERY CHANNEL8 = 0x8 PMOS THIN CHANNEL9 = 0x9 NMOS THIN CHANNEL10 = 0xA NMOS THICK CHANNEL11 = 0xB PMOS THICK CHANNEL12 = 0xC USB_DP (must also set usb_data_on_lradc to use this) CHANNEL13 = 0xD USB_DN (must also set usb_data_on_lradc to use this) CHANNEL14 = 0xE VBG (Can be used to calibrate the LRADC) CHANNEL15 = 0xF 5V input DESCRIPTION: Each virtual channel of the LRADC can be directed to use any of the 16 analog mux input sources for it conversion. This register specifies the analog mux to channels to be used for LRADC virtual channels 0 through 7. EXAMPLE: BW_LRADC_CTRL4_LRADC3SELECT(BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11); 33.4.22 LRADC Version Register Description This register always returns a known read value for debug purposes it indicates the version of the block. HW_LRADC_VERSION 0x150 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33-41 Low-Resolution ADC and Touch-Screen Interface Table 33-43. HW_LRADC_VERSION 3 1 3 0 2 9 2 8 MAJOR 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 MINOR 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 STEP 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 33-44. HW_LRADC_VERSION Bit Field Descriptions BITS 31:24 MAJOR LABEL RW RESET RO 0x01 DEFINITION Fixed read-only value reflecting the MAJOR field of the RTL version. Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. 23:16 MINOR 15:0 STEP RO 0x01 RO 0x0000 DESCRIPTION: This register indicates the RTL version in use. EXAMPLE: if (HW_ICOLL_VERSION.B.MAJOR != 1) Error(); LRADC Block v1.1, Revision 1.48 i.MX23 Applications Processor Reference Manual, Rev. 1 33-42 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 34 Serial JTAG (SJTAG) This chapter describes the one-wire serial JTAG (SJTAG) function included on the i.MX23 and how to use it. There are no registers in this module. 34.1 Overview The i.MX23 provides a one-wire serial JTAG (SJTAG) interface to connect to various external JTAG debugger dongles through a Freescale-defined FPGA/CPLD. SJTAG supports the Green Hills Slingshot and ETM probe debugger dongles, as well as those made by ARM, Abatron, and Lauterbach. The SJTAG block provides the following functions. * * * * Maps one-wire protocol to six-wire JTAG interface on the ARM926 core. Detects presence of external debugger when it is connected to the one-wire SJTAG pin (DEBUG) and it issues clock or JTAG reset commands. Signals JTAG presence to external FPGA/CPLD translator. Detects glitches and false JTAG clocks to improve noise immunity. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 34-1 Serial JTAG (SJTAG) The one-wire SJTAG interface is illustrated in Figure 34-1. SJTAG-to-PJTAG Converter Clock Multiplier 24-MHz Xtal osc Xtal osc 24 MHz Serial JTAG SJTAG FPGA/CPLD ($10) DEBUG CPUCLK ARM JTAG ARM Core Instruction Master AHB Layer 0 AHB Layer 1 Parallel JTAG (PJTAG) Slingshot or similar Data Master SoC Figure 34-1. Serial JTAG (SJTAG) Block Diagram 34.2 Operation The architecture of the one-wire serial JTAG interface depends on the FPGA/CPLD to always be present and for it to do all of the "heavy lifting" associated with synchronizing data back and forth across the interface. To that end, the FPGA/CPLD is programmed to use its digital clock modules to generate an 8x oversample clock to interface with the 24-MHz on-chip crystal oscillator circuits. Figure 34-2 defines the clock relationships. 24 MHz > 12 x jtag_clk jtag_clk 24 MHz 192 MHz 192 MHz = 8 x 24 MHz Figure 34-2. SJTAG Clock Relationships i.MX23 Applications Processor Reference Manual, Rev. 1 34-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Serial JTAG (SJTAG) The following high-level steps describe using the FPGA/CPLD and the debugger with the i.MX23 SJTAG interface: * * * * * * The FPGA/CPLD synchronizes the debugger's JTAG clock into its 192-MHz domain and edge-detects it. The rising edge of the debugger's clock triggers an asynchronous start phase in which the FPGA/CPLD drives the DEBUG pin high for one FPGA/CPLD clock period. The DEBUG pin is pulled lightly high until the SJTAG block on the chip recognizes the start condition on the wire. The timing mark phase is entered at that point, and the chip pulls the DEBUG line back low. This falling edge is detected by the oversample clock in the FPGA/CPLD, and it uses this timing mark to drive all subsequent transfers to the chip. The 8x oversample clock then works on pseudo-synchronous timing points derived by counting out the 8x clocks. The following sections describe these phases illustrated in Figure 34-3 in more detail. debugger_jtag_clk arm_jtag_clk Debugger Async Start SoC Timing Mark Debugger SoC Send TDI, Mode Wait for RTCK SoC Send TDO SoC . . . Debugger Terminate Async Start Figure 34-3. SJTAG Phases of Operation for One JTAG Clock 34.2.1 * * Debugger Async Start Phase * * This phase begins when a rising edge is detected on the JTAG clock signal coming from the debugger. This phase lasts a fixed number of 192-MHz clock periods. That is, the DEBUG pin is driven high for a period corresponding to half a 24-MHz clock, i.e., 20.8 ns. This drive is completely asynchronous to the on-chip 24-MHz clock, i.e., the relationship is unknown at this point. The soft pullup is turned on by the FPGA/CPLD and left on as the phase ends. This phase ends when the strong driver is turned off and the timing mark phase is entered. 34.2.2 * * * i.MX23 Timing Mark Phase This phase is entered when the FPGA/CPLD releases its strong driver, i.e., when it three-states the driver. The SJTAG controller on the chip detects the rising edge on the DEBUG pin and synchronizes it. This action starts a shift register timing chain that runs through this and the next phase. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 34-3 Serial JTAG (SJTAG) * * When the synchronized edge is recognized by the on-chip SJTAG controller, it pulls the DEBUG line back down clock to Q to pad after the rising edge of its 24-MHz clock. This is the critical timing mark that is detected in the FPGA/CPLD and used to time data in next phase. The timing mark phase ends when the on-chip SJTAG stops driving the serial JTAG wire low for one cycle. 34.2.3 * Debugger Send TDI, Mode Phase * * * During the first 24-MHz clock period of this phase, the FPGA/CPLD sends a one clock-wide signal that either tells the on-chip SJTAG that it is present and a JTAG clock begins, or it tells the on-chip SJTAG to do a JTAG reset operation to the ARM JTAG TAP controller. If a noise glitch falsely triggered the ASYNC Start Phase, then the on-chip SJTAG will treat it as a TAP controller reset in most cases. If the debugger is performing a JTAG clock cycle operation then, it next sends the state of the debugger TDI and MODE pins sequentially on the wire, i.e., one in each of the following two 24-MHz clocks. Notice that for this phase, the FPGA/CPLD knows the correct timing to change these three data elements on the wire because of the timing information it learned from the Timing Mark Phase. This phase ends after the FPGA/CPLD drives the serial wire low on the fourth 24-MHz clock of this phase. To review, the first data element sent is the signal that distinguishes clock cycles from TAP reset cycles. The next two bits sent are the JTAG MODE and TDI bits from the debugger. Finally, the line is driven low and pulled down for half a 24-MHz clock and the driver is turned off and the pulldown left on. This phase ends when the half-clock pulldown is complete. The rising edge of the JTAG clock is sent to the ARM TAP controller during this phase. 34.2.4 * * * i.MX23 Wait For Return Clock Phase During this phase: The on-chip SJTAG controller waits for the ARM TAP controller to send back the return clock. This is an asynchronous event for both the on-chip TAP controller and the FPGA/CPLD controller. The on-chip controller drives the serial wire high for one 24-MHz clock period to tell the FPGA/CPLD that the variable length wait for return clock period is complete. This phase ends when the on-chip SJTAG detects the return clock going high and drives the serial high for one 24-MHz clock. 34.2.5 * * i.MX23 Sends TDO and Return Clock Timing Phase During this phase: The on-chip SJTAG controller sends the value of the ARM TAP controller's TDO signal on the wire for one full 24-MHz period that begins on the rising edge of the on-chip 24-MHz clock. This phase ends when the TDO value has been sent. i.MX23 Applications Processor Reference Manual, Rev. 1 34-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Serial JTAG (SJTAG) 34.2.6 * * * i.MX23 Terminate Phase The primary purpose of this phase to leave the SJTAG serial wire in the low state. The on-chip SJTAG controller accomplishes this by driving it low for half a 24-MHz clock, releasing it at the falling edge of its internal 24-MHz clock. This allows the next JTAG cycle to be started by the FPGA/CPLD around 3/4 of a 24-MHz clock after this phase is entered. When this phase ends, the on-chip SJTAG controller resets its "Active" flip-flop and returns to its idle state in both its timing chain and its state machine. The on-chip SJTAG always drives out the serial wire at the rising edge of the 24-MHz clock. It may drive for one 24-MHz clock cycle (return clock and TDO) or half cycle (terminate phase). SJTAG-toPJTAG Converter Xtal osc Xtal osc 24 MHz pad_1wire_in pad_1wire_data rcvr_1wire_in direct_drive 4.7K SJTAG pad_1wire_oe direct_oe pull_drive pull_oe FPGA SoC Figure 34-4. SJTAG Drivers 34.2.7 SJTAG External Pin The SJTAG interface uses a single bidirectional interface pin (DEBUG) running at VDDIO to communicate with external debuggers. The DEBUG pad itself is wired as a conventional 8-mA 3.3-V driver. The DEBUG pin is completely dedicated to this one function. The signal on this interface is actively pulled up or down by the SOC as well as by the external debugger. However, the SOC will never drive this interface until it is first driven high by the external debugger.. The external JTAG debugger interface circuit includes a switched 4.7 Kohm pulldown resistor on its board. The DEBUG pin has a Schmitt trigger. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 34-5 Serial JTAG (SJTAG) If the DEBUG pin is unused, Freescale recommends pulling the DEBUG pin to ground through a 100K resistor. It is also possible to short the DEBUG pin to ground directly, but doing this will prohibit debugging on a production player. 34.2.8 Selecting Serial JTAG or Six-Wire JTAG Mode The HW_DIGCTL_CTRL_USE_SERIAL_JTAG bit in the digital control block selects whether the serial JTAG interface or the alternative six-wire parallel JTAG interface is used. * * When this bit is cleared to 0, parallel six-wire JTAG is enabled and is mapped to a collection of module pins that must be enabled by programming their PINMUXSEL bits in the PINCTRL block. When this bit is set to 1, serial JTAG is enabled and uses the dedicated DEBUG pin. The ROM bootcode writes this field prior to enabling JTAG, selecting which type of JTAG pin signaling to use. i.MX23 Applications Processor Reference Manual, Rev. 1 34-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 35 Boot Modes This chapter describes the boot modes implemented on the i.MX23. 35.1 Boot Modes Table 35-1 lists all of the boot modes supported by the i.MX23 ROM. The boot mode can be selected either through external resistors or via OTP eFuse bit programming. Table 35-1. ROM Supported Boot Modes PORT USB I2C SPI1 SPI2 SSP1 SSP2 GPMI JTAG_WAIT Encrypted/unencrypted USB slave boot mode. Encrypted/unencrypted I2C master--Boots from 3.3-V EEPROM. Encrypted/unencrypted SPI master from SSP1--Boots from 3.3-V flash memory. Encrypted/unencrypted SPI master from SSP2--Boots from 3.3-V flash and EEPROM. Encrypted/unencrypted SD/MMC master from SSP1--Boots from 3.3-V 1-bit, 4-bit, and 8-bit SD/MMC cards. Encrypted/unencrypted SD/MMC master from SSP2--Boots from 3.3-V 1-bit, 4-bit, and 8-bit SD/MMC cards. Encrypted/unencrypted NAND, 3.3-V, 8-bit wide and ECC4 and ECC8. Unencrypted startup --Waits for JTAG debugger connection. BOOT MODE 35.1.1 Boot Pins Definition and Mode Selection Boot pins are located on LCD_RS, LCD_DATA[5] and LCD_DATA[3:0]. To enable boot mode selection from the LCD data pins, pull up LCD_RS. The ROM probes the LCD_RS pin and then, if valid, decodes the boot mode vector from the pins LCD_DATA[5] and LCD_DATA[3:0]. If LCD_RS is pulled down, then the boot mode is determined by OTP eFuse bits, as defined in Table 35-4. Table 35-2 shows the boot pins. Table 35-2. Boot Pins PIN NAME LCD_RS BOOT FUNCTION Determines if there is a need to examine the other boot pins. BIT NAME i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-1 Boot Modes Table 35-2. Boot Pins PIN NAME LCD_DATA[5] LCD_DATA[3] LCD_DATA[2] LCD_DATA[1] LCD_DATA[0] ETM Enable Boot Mode Bit 3 Boot Mode Bit 2 Boot Mode Bit 1 Boot Mode Bit 0 BOOT FUNCTION BIT NAME TBM1 BM3 BM2 BM1 BM0 These pads are powered during the initial startup sequence. The pads are enabled as GPIOs for sensing and then disabled. However, the pads remain powered. The TBMx pins are not powered or configured as GPIOs unless BM3:0=0xF. The ETM sets drive strength to 8mA on the ETM pins. 35.1.2 Boot Mode Selection Map Table 35-3. Boot Mode Selection Map ETM Enable/ LCD_ DATA[5] 0/1 0/1 0/1 0/1 0/1 0/1 0/1 x 0/1 0/1 0/1 x 0/1 0/1 x x BM3/ LCD_ DATA[3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BM2/ LCD_ DATA[2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BM1/ LCD_ DATA[1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BM0/ LCD_ DATA[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PORT USB I2C SPI SPI GPMI - JTAG_WAIT - SPI SSP1 SSP2 - - - - - BOOT MODE USB (unencrypted vs. encrypted is under OTP control) I2C master SPI master SSP1 boot from flash SPI master SSP2 boot from flash NAND Reserved Startup waits for JTAG debugger connection Reserved SPI master SSP2 boot from EEPROM SD/MMC master on SSP1 SD/MMC master on SSP2 Reserved Reserved Reserved Reserved Reserved i.MX23 Applications Processor Reference Manual, Rev. 1 35-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes 35.2 35.2.1 OTP eFuse and Persistent Bit Definitions OTP eFuse The i.MX23 contains a 1-Kbit array of OTP eFuse bits, some of which are used by the ROM. The bits listed in Table 35-4 through Table 35-6 can be configured by customers and are typically programmed on the customer's board assembly line. For more information about the OTP bits, see Chapter 7, "On-Chip OTP (OCOTP) Controller." Table 35-4. General ROM Bits eFuse Bank:Address:Bit HW_OCOTP_ROM0:0x8002C1A0:31:29 HW_OCOTP_ROM0:0x8002C1A0:28 HW_OCOTP_ROM0:0x8002C1A0:27 HW_OCOTP_ROM0:0x8002C1A0:26 HW_OCOTP_ROM0:0x8002C1A0:25 HW_OCOTP_ROM0:0x8002C1A0:24 HW_OCOTP_ROM0:0x8002C1A0:23 HW_OCOTP_ROM0:0x8002C1A0:22 HW_OCOTP_ROM0:0x8002C1A0:21:20 Undefined TBM0 BM3 BM2 BM1 BM0 ENABLE_PJTAG_12MA_DRIVE - This bit is used to drive pins for 6-wire parallel JTAG at 12ma. USE_PARALLEL_JTAG - The default is serial jtag, this bit can be used to enable 6-wire parallel JTAG. POWER_GATE_GPIO-SD/MMC card power gate GPIO pin select. 00 = PWM0 01 = LCD_DOTCK 10 = PWM3 11 = NO_GATE= POWER_UP_DELAY--SD/MMC card power up delay required after enabling GPIO power gate. 000000 = 20 ms (default) 000001 = 10 ms 000010 = 20 ms .... 111111 = 630 ms SD_BUS_WIDTH--SD/MMC card bus width. 00 = 4-bit 01 = 1-bit 10 = 8-bit 11 = Reserved Index to SSP clock speed. By default (0x0), the clock speed is set to 12 MHz. The value of the index will modify the SPI clock speed accordingly. DISABLE_SPI_NOR_FAST_READ--Blow to disable SPI NOR fast reads, which are used by default. Some SPI NORs do not support this functionality. eFuse Function HW_OCOTP_ROM0:0x8002C1A0:19:14 HW_OCOTP_ROM0:0x8002C1A0:13:12 HW_OCOTP_ROM0:0x8002C1A0:11:8 HW_OCOTP_ROM0:0x8002C1A0:6 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-3 Boot Modes Table 35-4. General ROM Bits (continued) eFuse Bank:Address:Bit HW_OCOTP_ROM0:0x8002C1A0:5 eFuse Function ENABLE_USB_BOOT_SERIAL_NUMBER--If set, the device serial number is reported to the host during USB boot mode initialization, else no serial number is reported. ENABLE_UNENCRYPTED_BOOT--If clear, allows only booting of encrypted images. If set, both encrypted/unencrypted images are valid. SD_MBR_BOOT--Set to enable SD Master Boot Record (MBR) mode. The SD/MMC card should have a valid MBR to boot successfully in this mode. If this bit is not set, ROM will try to boot in default mode, BCB (Boot Control Block). DISABLE_RECOVERY_MODE--If set, does not allow booting in recovery mode. HW_OCOTP_ROM0:0x8002C1A0:4 HW_OCOTP_ROM0:0x8002C1A0:3 HW_OCOTP_ROM0:0x8002C1A0:2 Table 35-5. NAND/SD-MMC Related Bits eFuse Bank:Address:Bit HW_OCOTP_ROM1:0x8002C1B0:29:28 eFuse Function USE_ALT_GPMI_RDY3 - These bits are used by ROM NAND driver to enable one of 3 alternate pins for GPMI_RDY3. 00-GPMI_RDY3 01-PWM2 10-LCD_DOTCK USE_ALT_GPMI_CE3 - These bits are used by ROM NAND driver to enable one of 4 alternate pins for GPMI_CE3. 00-GPMI_D15 01-LCD_RESET 10-SSP_DETECT 11-ROTARYB USE_ALT_GPMI_RDY2 - If the bit is blown then ROM NAND driver will enable alternate pins for GPMI_RDY2 USE_ALT_GPMI_CE2 If the bit is blown then ROM NAND driver will enable alternate pins for GPMI_CE2 ENABLE_NAND3_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE3 and GPMI_RDY3 pins. ENABLE_NAND2_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE2 and GPMI_RDY2 pins. ENABLE_NAND1_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE1 and GPMI_RDY1 pins. ENABLE_NAND0_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE0 and GPMI_RDY0 pins. UNTOUCH_INTERNAL_SSP_PULLUP - If this bit is blown then internal pull-ups for SSP are neither enabled nor disabled. This bit is used only if external pull-ups are implemented and ROM1:18 and/or ROM1:17 are blown. SSP2_EXT_PULLUP - Blow to indicate external pull-ups implemented for SSP2 HW_OCOTP_ROM1:0x8002C1B0:27:26 HW_OCOTP_ROM1:0x8002C1B0:25 HW_OCOTP_ROM1:0x8002C1B0:24 HW_OCOTP_ROM1:0x8002C1B0:23 HW_OCOTP_ROM1:0x8002C1B0:22 HW_OCOTP_ROM1:0x8002C1B0:21 HW_OCOTP_ROM1:0x8002C1B0:20 HW_OCOTP_ROM1:0x8002C1B0:19 HW_OCOTP_ROM1:0x8002C1B0:18 i.MX23 Applications Processor Reference Manual, Rev. 1 35-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes Table 35-5. NAND/SD-MMC Related Bits (continued) HW_OCOTP_ROM1:0x8002C1B0:17 HW_OCOTP_ROM1:0x8002C1B0:12 HW_OCOTP_ROM1:0x8002C1B0:11:8 SSP1_EXT_PULLUP - Blow to indicate external pull-ups implemented for SSP1 USE_ALT_SSP1_DATA4-7 - This bit is blown to enable alternate pin use for SSP1 data lines 4-7 BOOT_SEARCH_COUNT - Number of 64-page blocks skipped by the NAND driver when searching for information saved into the NAND (see Section 35.8, "NAND Boot Mode" for details). Default value of 0 means 4 blocks to skip. NUMBER_OF_NANDS - Indicates the number of external NANDs. A 0 value means that the NAND driver will scan the chip selects to dynamically find the correct number of NANDs. HW_OCOTP_ROM1:0x8002C1B0:2:0 Table 35-6. USB-Related Bits eFuse Bank:Address:Bit HW_OCOTP_ROM2:0x8002C1C0:31:16 HW_OCOTP_ROM2:0x8002C1C0:15:0 eFuse Function USB_VID--Vendor ID used in recovery mode. If the field is 0, Freescale vendor ID is used. USB_PID--Product ID used in recovery mode. 35.2.2 Persistent Bits Persistent bits are used to control certain features in the ROM, as shown in Table 35-7. For more information on the persistent bits, see Chapter 23, "Real-Time Clock, Alarm, Watchdog, Persistent Bits." Table 35-7. Persistent Bits PERSISTENT BIT HW_RTC_PERSISTENT1:0x8005C070:3 HW_RTC_PERSISTENT1:0x8005C070:2 FUNCTION SD_SPEED_ENABLE--If this bit is set, ROM will put the SD/MMC card in high-speed mode. NAND_SDK_BLOCK_REWRITE--The NAND driver sets this bit to indicate to the SDK that the boot image has ECC errors that reached the warning threshold. The SDK must regenerate the firmware by copying it from the backup image. The SDK will clear this bit. NAND_SECONDARY_BOOT--When this bit is set, the ROM attempts to boot from the secondary image if the boot driver supports it. This bit is set by the ROM boot driver and cleared by the SDK after repair. FORCE_RECOVERY--When this bit is set, the ROM code forces the system to boot in recovery mode, regardless of the selected mode. The ROM will clear the bit. HW_RTC_PERSISTENT1:0x8005C070:1 HW_RTC_PERSISTENT1:0x8005C070:0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-5 Boot Modes 35.3 Memory Map Figure 35-1 shows the memory map for the boot loader. ROM boot code resides in the top 64K address space. The boot code uses the top 16K of OCRAM for data, and the 4K just below it should be reserved for patching the ROM. This leaves 16K of OCRAM for loading application data. If a system uses external memory, then a boot image may be created that first loads a small SDRAM initialization program into OCRAM. The program will set up the SDRAM, and then the rest of the boot image may continue to load, overwriting the initialization program in OCRAM. 0xFFFFFFFF 0x00007FFF ROM Boot Code ROM Data 0xFFFF0000 0x00005000 64K ROM 0x00004FFF ROM Patch 0x00004000 0x00003FFF Application Load Area 0x00000000 32K OCRAM Figure 35-1. Boot Loader Memory Map 35.4 General Boot Procedure During ROM startup, the boot mode is determined, and then control is passed to the boot loader. The loader first calls an init function for the boot driver responsible for reading boot images from the target boot port. The driver initializes the hardware port and external device, and then finds the boot image on i.MX23 Applications Processor Reference Manual, Rev. 1 35-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes that device. The loader then requests boot image data from the driver. The boot image contains commands for loading code and data into memory, so the loader will interpret these commands and load the boot image into memory. At the end of a boot image, the loader passes control to the code that was loaded. Boot images are encrypted, and customers have full control over the encryption keys by setting the CRYPTO_KEY TOP bits. Boot images are created by the Freescale-supplied elftosb application. 35.4.1 * * Preparing Bootable Images Preparing a bootable image for all boot modes includes the following high-level steps: Prepare the ELF file for the firmware that is to be booted by the i.MX23 ROM. Run the ELF file through the elftosb program (available from Freescale), which generates an encrypted SB file that can be booted from ROM. Any additional requirements for individual boot modes are identified in the following sections. 35.4.2 Constructing Image to Be Loaded by Boot Loader The image is stored in an encrypted form that includes an authenticating hash. Freescale supplies a program called elftosb to convert a fully resolved executable binary image into a boot image usable by the boot loader. A key set must be input to the elftosb program to properly encrypt and authenticate the image. A default key set is supplied with elftosb. The process of creating a boot loader image is shown in Figure 35-2. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-7 Boot Modes C and ASM LIBs GHS Tools gnu Tools ELF elftosb Figure 35-2. Creating a Boot Loader Image 35.5 I2C Boot Mode EEPROMs must have the slave address 0xA0 (i.e., '1010000R', where R indicates a read if 1 and a write if 0). Also, the EEPROM must have exactly a two-byte "sub" address. Boot images must start at address 0x0 of the EEPROM and cannot exceed 64 Kbytes in size. Note that because of the boot image size limitation, I2C boot mode will likely not be useful for OS boot. The I2C port is set to run at 400 kHz. 35.6 SPI Boot Mode SPI memories are either EEPROMs or NORs. By default, the SPI serial clock is set to 0.9 MHz for EEPROMs and 12 MHz for NORs. The SSP_SCK_INDEX OTP bits are used to change the SPI serial clock from defaults. These bits serve as the index for the SSP HAL clock rate array (see Section 35.6.2, "SSP," for details on the clock rate array). The defaults may also be changed by using the ConfigBlock.Clocks field (see ,"). If ConfigBlock.Clocks.SspClockConfig is non-zero, then that struct will be used to change the SPI SCK rate and will override the SSP_SCK_INDEX OTP setting. i.MX23 Applications Processor Reference Manual, Rev. 1 35-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Load Image (SB) ELF LIBs Boot Modes This driver supports only 2-byte addresses for EEPROMs and 3-byte addresses for NORs. This boot mode supports SPI mode 0 only. 35.6.1 Media Format The media is arbitrarily partitioned into 128-byte "sectors". An optional configuration block may reside on the media at byte address 0. This block has the following format: //! \brief Spi media configuration block structs typedef struct _spi_ConfigBlockFlags { uint32_t DisableFastRead:1; // Ignored for Spis // 0 - Do not disable fast reads // 1 - Disable fast reads } spi_ConfigBlockFlags_t; typedef struct _spi_ConfigBlockClocks { uint32_t SizeOfSspClockConfig; // sizeof(ssp_ClockConfig_t) ssp_ClockConfig_t SspClockConfig; // SSP clock configuration structure. A null // structure indicates no clock change. } spi_ConfigBlockClocks_t; typedef struct _spi_ConfigBlock // Little Endian { uint32_t Signature; // 0x4D454D53, or "SMEM" uint32_t BootStartAddr; // Start address of boot image. Must be >= // sizeof(spi_ConfigBlock_t) uint32_t SectorSize; // Sector size in bytes. Overrides ROM default // of 128-bytes. Max is 1024-bytes. 0 is // default 128-bytes. spi_ConfigBlockFlags_t Flags; // Various flags. See spi_ConfigBlockFlags spi_ConfigBlockClocks_t Clocks; // SCK clock update structure. } spi_ConfigBlock_t; If the block is present, then the boot image is found at the address specified by BootStartAddr. If the block is not present, then it assumes that the boot image resides on the media starting at byte address 0. 35.6.2 SSP The SSP is used for the SPI boot mode. The following table is used to look up a requested speed. If the speed is not an exact match, the boot ROM picks the next lowest value. Speed values can range from 1 to 50 MHz. A speed value of 0 is not allowed. // { int int int int int } clkSel io_frac ssp_frac ssp_div ssp_rate :1; :6; :9; :8; :8; //!< //!< //!< //!< //!< Clock Select (0=io_ref 1=xtal_ref) IO FRAC 18-35 (io_frac+16) SSP FRAC (1=default) Divider: Must be an even value 2-254 Serial Clock Rate Lookup Table entry typedef struct _ssp_clockConfig ssp_clockConfig_t; i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-9 Boot Modes The table is loaded with the clock rates listed in Table 35-8. Table 35-8. SCK Clock Standard Values Lookup Table SCK INDEX CLK_SEL IOFRAC SSP_FRAC SSP_CLK SSP_DIV SSP_RATE X X N/A 0 X X X .9 1 1 X X 24 26 0 1 2 1 X X 24 24 0 2 3 1 X X 24 12 0 4 4 1 X X 24 6 0 6 5 1 X X 24 4 0 8 6 0 18 6 80 10 0 10 7 0 18 6 80 8 0 12 8 1 X X 24 2 0 16 9 0 18 5 96 6 0 20 10 0 18 6 80 4 0 24 11 0 18 10 48 2 0 40 12 0 18 6 80 2 0 48 13 0 18 5 96 2 0 X 14 X 15 X X X X X X 35.7 * * * * * SD/MMC Boot Mode iNand Product Manual, Version 2.1 SD Specifications, Part 1, Physical Layer Specification, Version 1.10 SD Specifications, Part 1, Physical Layer Specifications, Version 2.0 Draft MultiMediaCard System Specification, Version 4.1 MultiMediaCard System Specification, Version 4.2 SD/MMC boot mode supports booting from SD/MMC cards adhering to the following specifications: Note, however, that this mode does not support dynamic insertion removal, so systems will typically not include removable cards. The following modes are supported: * * SD/MMC on SSP1 SD/MMC on SSP2 The SD_POWER_GATE_GPIO eFuse bits indicate which GPIO pin to use for controlling an external power gate for the connected device. Table 35-9. GPIO Pin Selection SD_POWER_GATE_GPIO 00b 01b 10b 11b Gate GPIO PWM0 LCD_DOTCK PWM3 NONE i.MX23 Applications Processor Reference Manual, Rev. 1 35-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes If a gate GPIO is used, then the driver will use the SD_POWER_UP_DELAY eFuse to determine the amount of time, in 10-ms increments, to wait until starting the 1-ms initialization sequence. This eFuse field is 6-bits wide, providing from 10-600 ms of delay. If the field is 000000b, then the delay is a default 20 ms. If no gate GPIO is specified in SD_POWER_GATE_GPIO, then the delay is skipped. The SSP ports on the i.MX23 top out at 50 MHz with 20-40 pF loading. By default, the serial clock is set to 12 MHz. If the SD_SPEED_ENABLE persistent bit is set, then the driver will use a maximum speed based on the results of device identification and limited by choices available in the SSP clock index. This mode supports the 1-bit, 4-bit, and 8-bit data MMC/SD buses. The SD_BUS_WIDTH efuse bits selects how many bus pins are physically available for the SSP port. Bus width will be limited based on these bits, as well as the bus width capabilities indicated by the connected device. Table 35-10. Bus Pin Selection SD_BUS_WIDTH 00b 01b 10b 11b Width 4-bit 1-bit 8-bit Reserved The SD/MMC boot mode requires either a Boot Control Block (BCB) or Master Boot Record (MBR) on the device. The boot loader will first search for a MBR. If found, it will use the MBR data to find the boot image. If the MBR is not present, the boot loader will search for a BCB. If found, the BCB will provide the boot image located and size to the boot loader. If neither structure is fount, the boot loader will return an error to the ROM. 35.7.1 Boot Control Block (BCB) The last physical sector of the device contains a media configuration block. This block contains the sector address of the boot image. The config block has the following format: typedef struct { drive_type_t uint32_t uint32_t } media_regions_t; eDriveType; Tag; Reserved[5]; typedef struct { uint32_t Signature; uint32_t Version uint32_t Reserved[1]; uint32_t NumRegions; media_regions_t Regions[]; } media_config_block_t; The driver will first verify the Signature and Version, then search all NumRegions for the appropriate Tag. Table 35-11 shows the expected values for these parameters. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-11 Boot Modes Table 35-11. Media Config Block Parameters Field Signature Version Tag Value 0x4D454D53 0x00000001 0x00000050 35.7.2 Master Boot Record (MBR) The first block of the device contains the master boot record (MBR). The MBR is identified by its signature located at offset 0x1FE of the first sector. The partition table is stored at address 0x1BE. The Freescale partition is identified by MBR_SIGMATEL_ID at an offset 0x04 from partition table. The boot image address is stored at offset 0x08 of partition table and size of the image at offset 0x10 of partition table. Table 35-12. MBR Signature Bits Field MBR Signature MBR_SIGMATEL_ID Value 0x55AA `S' 35.7.3 Device Identification SD/MMC boot mode uses the identification processes specified in SD Specifications, Part 1, Physical Layer Specifications, Version 2.0 Draft and MultiMediaCard System Specification, Version 4.2. 35.8 35.8.1 NAND Boot Mode NAND Control Block (NCB) As part of the NAND media initialization, the ROM driver uses safe NAND timings to search for a NAND Control Block (NCB) that contains the optimum NAND timings and the Factory Marked Bad Block Table. A flowchart is shown in Figure 35-3. In the i.MX23, there are no separate boot modes for each type of ECC level. The hardware ECC level to use is embedded inside NCB block. The NCB data structure is itself protected using software ECC (SEC-DED Hamming Codes). Driver reads raw 2112 bytes of first sector and runs through software ECC engine that determines whether NCB data is valid or not. If the NCB is found, the optimum NAND timings are loaded for further reads. If the software ECC fails, or the fingerprints do not match, the Block Search state machine increments 64 pages and reads that page i.MX23 Applications Processor Reference Manual, Rev. 1 35-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes until 2n efNANDBootSearchLimit pages have been read. The 64-page stride value was picked as the smallest block size in many of the current NAND devices. If a NCB cannot be found, the driver sets the NAND_SDK_BLOCK_REWRITE persistent bit and retries the Block Search looking for NCB2. If the second search fails, the NAND driver responds with an error and the boot ROM enters recovery mode. Upon finding the NCB, the NAND parameters are read from the NCB, and the NAND driver updates the fail-safe parameters with the new parameters. These parameters include NAND timing, page size, and block size. The next step is to find the Logical Drive Layout Block (LDLB), which uses the same search method as the NCB but the starting address will be different. The LDLB contains the Media Table, a pointer to the Discovered Bad Block Table (DBBT), and the sector information for the initial boot image. After the LDLB is read, the DBBT is loaded, and the initial boot image is loaded using the initial boot image starting address pointer. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-13 Boot Modes rom_nand_FindBootControlBlocks() iReadSector = 0 CurrentNAND = NAND0 Load NCB Fingerprints NCB Search Using Secondary Boot Blocks? N FindNCB() Y Multi NAND? N Y CurrentNAND = NAND1 iReadSector = 0; iReadSector = 2nd search block (64 * efNANDBootSearchLImit) NCB N SUCCESS ? Y While !SUCCESS (runs 2 times max) SUCCESS LDLB fingerprints Using Secondary Boot Blocks? N Y Return ERROR_ROM_NAND_DRIVER_NO_NCB Set SDK_BLOCK_REWRITE persist. Bit Set Use Secondary Boot Block flag. LDLB Search Is UseSecondary Boot persist. Bit set? N Y Multi NAND? N Y CurrentNAND = NAND1 iReadSector = 2nd search block (64 * efNANDBootSearchLImit) iReadSector = 4th search block (3 * 64 * efNANDBootSearchLImit) Multi NAND? N iReadSector = 4 search block (3 * 64 * efNANDBootSearchLImit) th Y CurrentNAND = NAND1 iReadSector = 2nd search block; FindLDLB() LDLB SUCCESS? Y N Using Secondary Boot Blocks? N Y Return ERROR_ROM_NAND_DRIVER_NO_LDLB Set SDK_BLOCK_REWRITE persist. Bit Set Use Secondary Boot Block flag. While !SUCCESS (runs 2 times max) SUCCESS FindDBBT() Return result of last discovery Figure 35-3. FindBootControlBlocks Flowchart i.MX23 Applications Processor Reference Manual, Rev. 1 35-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes If the ECC fails or the fingerprints do not match, the Block Search state machine will increment 64 pages and read that page until 2n efNANDBootSearchLimit pages have been read. If a LDLB cannot be found, the driver sets the NAND_SDK_BLOCK_REWRITE persistent bit and retries the Block Search. If the second search fails, the NAND driver responds with an error, and the boot ROM enters recovery mode. The block search flowchart is shown in Figure 35-4. Block_Search Page Address = Expected Page Address efBootBlock Search times Do efBootBlockSearch # times Read Current Page While < efBootBlockSearch Page Address += 64 Did ECC pass and do fingerprints match? Y N Record failure for SDK rewrite Return ERROR Return SUCCESS Figure 35-4. Block Search Flowchart Once the LDLB is identified, more information about the boot image geometry is determined, including information required to calculate the appropriate boot image starting NAND, starting sector, stride, etc. The NCB and LDLB search and load function also monitors the ECC correction threshold and sets the NAND_SDK_BLOCK_REWRITE persistent bit if the threshold exceeds three corrections in the four-bit ECC case and seven corrections in the eight-bit ECC case. One bit is used for all boot block images. If the NAND_SDK_BLOCK_REWRITE bit is set, the ROM continues loading the image, but the SDK will need to "refresh" the boot blocks at a later time. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-15 Boot Modes 35.8.2 NAND Patch Boot using NCB A secondary mechanism to boot NAND patch image is implemented in the ROM. A flag is used in NCB data structure that would indicate to the ROM to boot the patch binary image present on the second page of first good block of NAND. If this flag is set, ROM will not try to locate LDLB and other boot blocks and would start loading the patch image. 35.8.3 Expected NAND Layout The ROM expects the layout described in this section and illustrated in Figure 35-5 when booting from a single NAND configuration. The first search area contains the NAND Configuration Block (NCB) followed by an alternate NCB in the second search area. The third search area contains the Logical Drive Layout Block (LDLB), which is followed by an alternate LDLB in the fourth search area. i.MX23 Applications Processor Reference Manual, Rev. 1 35-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes NAND Control Block (NCB1) NAND Physical Params with appropriate ECC 1. # of NANDs 2. Timing Parameters Factory Marked Bad Block Table Fingerprints for identification Alternate NCB (NCB2) NAND Physical Params with appropriate ECC 1. # of NANDs 2. Timing Parameters Factory Marked Bad Block Table Fingerprints for identification Logical Drive Layout Block (LDLB1) Infrequently written data with appropriate ECC (4 bit or 8 bit) Media Table (starting sectors of each drive and size of drive) Pointer to the Discovered Bad Block Table (BB discovered during operation) Initial Boot Applet pointer (Chip and sector) Alternate LDLB (LDLB2) Infrequently written data with appropriate ECC (4 bit or 8 bit) Media Table (starting sectors of each drive and size of drive) Pointer to the Discovered Bad Block Table (BB discovered during operation) Initial Boot Applet pointer (Chip and sector) Discovered Bad Block Table (DBBT1) Table of Bad Blocks discovered during SDK operation. Fingerprints. Discovered Bad Block Table (DBBT2) Table of Bad Blocks discovered during SDK operation. Fingerprints. Boot Applet 1 Small boot image loaded from ROM Alternate Boot Applet 1 Small boot image loaded from ROM And so on... Boot Applet y Small boot image loaded from ROM 1st Search Block 2nd Search Block 3rd Search Block 4th Search Block 5th Search Block Figure 35-5. Expected NAND Layout Search areas are defined as 64 pages * efSearchSize. They are defined in such a way that there is at least one extra block to hedge against a Boot Control Block (BCB) going bad during operation. If a Boot Control Block goes bad during operation, the data is copied from the original BCB to the extra BCB, and the original BCB is written with zeros. Since we rely upon both the ECC being correct and the fingerprints, overwriting the BCB with zeros should invalidate all the data. The search algorithm will search an entire search area before looking for the backup or secondary Boot Control Block. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-17 Boot Modes 35.8.3.1 NAND Config Block The primary NAND Config Block (NCB) resides on the NAND attached to GPMI_CE0. The NCB is the first sector in the first good block. In the single NAND configuration, a copy of the NCB also resides on the NAND--its location is immediately after NCB1 - 2nd search area. In the case of multiple NAND devices, copies of the NCB, LDLB, and DBBT are located on the first two NANDs. This case is shown in more detail in Section 35.8.3.4, "Firmware Layout on the NAND." The layout of first good page containing NCB is described in Figure 35-6. 2111 Spare 1036 Parity Bits for NCB Data 524 NCB Data 12 Bytes Left 0 Figure 35-6. Layout of Boot Page Containing NCB The NCB is located on the first good page of the NAND; minimum size of a page is 2112 bytes. The first 12 bytes of NCB page are reserved and left blank (all 0s), next 512 bytes are reserved for NCB data. The remaining 512 bytes are available for software ECC and the rest are all 0s. NCB is protected using SEC-DED Hamming codes. 35.8.3.2 Single Error Correct and Double Error Detect (SEC-DED) Hamming For each 8 bits of data in 512 byte NCB, 5-bit parity is used. Each byte of parity area contains 5 parity bits (LSB) and 3 unused bits (MSB). For each 8 bits of NCB data, parity is calculated and compared with corresponding parity bits read from the parity area of NCB page to detect errors and correct single error. If errors are more than one then flag shall be raised against the block. To determine a good NCB, all three fingerprints must match and the ECC must not fail. i.MX23 Applications Processor Reference Manual, Rev. 1 35-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes The data held in the NCB includes: * * * * * * * NAND Timing parameters. Which NANDs are in the system (GPMI_CE0, GPMI_CE1, GPMI_CE2, GPMI_CE3)--this is also in the eFuse. Geometry information (sectors per block, sectors per page, etc.). Additionally, the NCB is marked with three fingerprints in the sector. Factory Marked Bad Block Table. Pointer to physical sector of LDLB (on this chip) and, in a single NAND configuration, a pointer to the physical sector of LDLB2. A flag to boot NAND patch image located at sector 2 of first block. 35.8.3.3 Logical Drive Layout Block A copy of the Logical Drive Layout Block (LDLB) resides on each NAND. A copy of the LDLB also resides on the NAND if it is a single NAND configuration, or on the first two NANDs if it is a multi-NAND configuration (See Figure 35-7). Its location is determined using the search area described above. The starting page will be the beginning of the 3rd search area. The LDLB has the same ECC as the rest of the system drives. The data held in the LDLB includes: * * * * * * Start Sector and stride of boot region. Start Sector and stride of alternate boot region. Tag of boot region. The LDLB is marked with three fingerprints in the sector. Media Table (Layout of drives on the NAND--used for SDK only). Pointer to the Discovered Bad Block Table and Alternate Discovered Bad Block Table (if a single NAND). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-19 Boot Modes 35.8.3.4 Firmware Layout on the NAND The boot image firmware is stored in the NAND as shown in Figure 35-7. Page n Boot Image Spare Block DBBT Spare Block LDLB NCB Boot Image Spare Block DBBT Spare Block LDLB NCB Page 0 Bad Block Figure 35-7. NAND Layout--Multiple NANDs A pointer in the LDLB contains the physical sector address (on that NAND) of the boot image. The boot image is typically located on the first good block after the NCB, LDLB, and DBBT blocks and the additional blocks reserved for Boot Control Blocks that become Bad Blocks. The next sector will be drawn from the same block, until all sectors are drawn from the block. Then, the first sector of the subsequent block on NAND0 will be read. All boot blocks are located on the first NAND. If a block is determined to be bad (from the Discovered Bad Block Table or fails the ECC), then the algorithm will skip to the next block on NAND0, etc. In a multiple NAND configuration, the first two NANDs will have the NCB, LDLB, DBBT, and boot images. The DBBT will be duplicated across all the NANDs. 35.8.3.5 Recovery From a Failed Boot Firmware Image Read The mechanism for recovering from a failed NCB or LDLB read is covered in Section 35.8.1, "NAND Control Block (NCB)." The SDK is warned about impending errors with the i.MX23 Applications Processor Reference Manual, Rev. 1 35-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes NAND_SDK_BLOCK_REWRITE persistent bit and is notified of firmware boot errors with the NAND_SECONDARY_BOOT persistent bit. In the case of a warning, the read routine will monitor the ECC threshold and set the NAND_SDK_BLOCK_REWRITE bit if the threshold is within one symbol of the maximum correctable number of symbols. The ROM continues to load from the primary boot image. At a later time, the SDK will refresh the primary boot images by copying and rewriting the primary boot image blocks. If an error is discovered while reading the boot firmware image, the NAND driver sets the NAND_SECONDARY_BOOT persistent bit and resets the device. Booting will proceed the second time from the secondary boot images. If booting continues uninterrupted, no "unwinding" needs to take place at the loader level. Boot Image Load Do ReadSector() until image is loaded Boot Image Loaded Did error occur during read ? Boot Complete Exit Y Set NAND_SECONDARY_BOOT persistent bit N Reset Device Figure 35-8. Boot Image Recovery 35.8.3.6 Bad Block Handling in the ROM Bad blocks are not an issue for the Boot Control Blocks of the NAND because the NCB and LDLB Boot Control Blocks are found from a search as described in Section 35.8.1, "NAND Control Block (NCB)." The search for the Discovered Bad Block Table Header Control Block works with a similar mechanism. The search starts where the LDLB indicates the DBBT should be and progresses for 2n efNANDBootSearchLimit times in the same fashion as the search described in Figure 35-4. If the DBBT is not found, the ROM will search for the DBBT2. It will not change to boot from the secondary boot blocks even if the DBBT2 is found. Because the DBBT2 must be duplicated across all the NANDs, this is a safe assumption. If no DBBTs are found, the ROM will assume there are no Bad Blocks and will continue to boot with no Bad Blocks. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-21 Boot Modes During firmware boot, at the block boundary, the Bad Block table is searched for a match to the next block. If no match is found, the next block can be loaded. If a match is found, the block must be skipped and the next block checked. i.MX23 Applications Processor Reference Manual, Rev. 1 35-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes Bad Block_Search Use secondary boot? N StartSector = LDLB.DBBTSector Y StartSector = LDLB.DBBT2Sector BootBlockSearch() N Was DBBT found? Y UseSecondary BootBlock flag set? Y N Set UseSecondaryBootBlock flag N Booting from NAND0 ? Y Set # of BB to 0 BBTableSector = StartSector + 4 + NAND0_Num2KPages; BBTableSector = StartSector + 4 ReadPage() Return DBBT_NOT_FOUND Grab # of BB. Truncate to MAX_BB_TABLE_SIZE Copy # BB into NandContext BB array. Return SUCCESS Figure 35-9. Bad Block Search i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-23 Boot Modes The DBBT structure is contained within a block and is discussed in more detail below. Figure 35-10 depicts the layout of the Discovered Bad Block Table block. The first 8K are reserved for the DBBT Header. The following pages are used by the DBBT for each NAND. The Bad Block table for each NAND begins on a 2KB boundary that coincides with current NAND page sizes and is a subset of future NAND page sizes. The BBT can extend beyond 2K, which is the purpose of the #2K_num, and translates to the number of 2K pages that NAND0 through NAND3 require. In this way, the ROM can quickly index to the appropriate NAND table. Only the Bad Blocks for the current NAND are loaded. In other words, in a dual NAND configuration, if the primary boot blocks are being used, then NAND0's BBTable will be loaded. Conversely, if the secondary boot blocks are being used, then NAND1's BB table will be loaded into the ROM's NandContext Bad Block array in NAND. FGR1 #2K_1 8K FGR2 #BB_0 #2K_2 #BB_1 #2K_3 FGR3 #BB_2 #BB_3 #2K_0 Discovered Bad Block Table Header # of 2K pages NAND0 # of 2K pages NAND1 # of 2K pages NAND2 # of 2K pages NAND3 NAND0 BB5 BB511 NAND1 BB5 BB511 NAND2 BB5 BB511 NAND3 BB5 BB511 #BB BB1 BB2 BB3 BB4 NAND0 Bad Block Table BB512 #BB BB513 BB1 BB2 BB3 BB4 NAND1 Bad Block Table BB512 #BB BB513 BB1 BB2 BB3 BB4 NAND2 Bad Block Table BB512 #BB BB513 BB1 BB2 BB3 BB4 NAND3 Bad Block Table BB512 BB513 Figure 35-10. DBBT Layout 35.8.3.7 NAND Control Block Structure and Definitions The NCB structure is as follows: typedef struct _NAND_Control_Block { uint32_t m_u32Fingerprint1; struct { uint8_t m_u8DataSetup; uint8_t m_u8DataHold; uint8_t m_u8AddressSetup; uint8_t m_u8DSAMPLE_TIME; } NAND_Timing; i.MX23 Applications Processor Reference Manual, Rev. 1 35-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t m_u32DataPageSize; m_u32TotalPageSize; m_u32SectorsPerBlock; m_u32SectorInPageMask; m_u32SectorToPageShift; m_u32NumberOfNANDs; //!< //!< //!< //!< //!< //!< 2048 for 2K pages, 4096 for 4K pages. 2112 for 2K pages, 4314 for 4K pages. Number of 2K sections per block. Mask for handling pages > 2K. Address shift for handling pages > 2K. Total Number of NANDs - not used by ROM. uint32_t m_u32Fingerprint2; uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t // @ word offset 10 m_u32NumRowBytes; //!< Number of row bytes in read/write transactions. m_u32NumColumnBytes; //!< Number of row bytes in read/write transactions. m_u32TotalInternalDie; //!< Number of separate chips in this NAND. m_u32InternalPlanesPerDie; //! Where: m_u32Fingerprint1--32 bit word consisting of STMP (stored as 0x504d5453) m_u32Fingerprint2--32 bit word consisting of NCB (stored as 0x2042434E) m_u32Fingerprint3--32 bit word consisting of RBIN (stored as 0x4E494252) m_u32_NumberOfNANDs--32 bit word detailing the number and configuration of NANDs that are in the system. NAND_Timing structure m_u8DataSetup--Number of nanoseconds required for NAND Data Setup. m_u8DataHold--Number of nanoseconds required for NAND Data Hold. m_u8AddressSetup--Number of nanoseconds required for NAND Data Setup. m_u8DSAMPLE_TIME--Number of 1/2 GPMI cycles to wait before latching Read. m_u32DataPageSize--Number of bytes in Data section of a page. m_u32TotalPageSize--Number of bytes in a page - total. m_ u32SectorsPerBlock--Number of 2K sections per block. (4K pages = 2 x #pages) m_ u32SectorInPageMask--Mask for handling pages > 2K. m_ u32SectorToPageShift--Address shift for handling pages > 2K. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-25 Boot Modes m_ u32NumRowBytes--Number of row bytes in read/write transactions. m_ u32NumColumnBytes--Number of column bytes in read/write transactions. m_u32TotalInternalDie--Number of die in this chip. m_u32InternalPlanesPerDie--Number of planes or districts per die. m_u32CellType--Type of NAND Cell--SLC, MLC. m_u32ECCType--Type of ECC for this NAND-- 0 - RS-4 bit ECC per 512 bytes 1 - RS-8 bit ECC per 512 bytes 2 - BCH-0 bit ECC per 512 bytes 3 - BCH-2 bit ECC per 512 bytes 4 - BCH-4 bit ECC per 512 bytes 5 - BCH-6 bit ECC per 512 bytes 6 - BCH-8 bit ECC per 512 bytes 7 - BCH-10 bit ECC per 512 bytes 8 - BCH-12 bit ECC per 512 bytes 9 - BCH-14 bit ECC per 512 bytes 10 - BCH-16 bit ECC per 512 bytes 11 - BCH-18 bit ECC per 512 bytes 12 - BCH-20 bit ECC per 512 bytes m_32EccBlock0Size--Number of bytes for BCH block 0 of a page. m_32EccBlockNSize--Number of bytes for BCH blocks N of a page; N=BCH blocks in a page except block 0. m_u32EccBlock0EccLevel--ECC for BCH Block 0, Please refer to m_u32ECCType description for ECC values applicable to this field. m_u32NumEccBlocksPerPage--Number of BCH blocks per page. m_u32MetadataBytes--Metadata size - BCH only m_u32EraseThreshold--This goes into BCH_MODE register. m_ u32Read1stCode--Read command code--1st byte. m_ u32Read2ndCode--Read command code--2nd byte. m_u32BootPatch--To load patch image data located on 2nd page of NCB block. i.MX23 Applications Processor Reference Manual, Rev. 1 35-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes m_u32PatchSectors--size of patch image data in sectors. m_u32Firmware_startingNAND2--required for patch image boot for location of duplicate copy of firmware. 35.8.3.8 Logical Drive Layout Block Structure and Definitions typedef struct _LogicalDriveLayoutBlock { uint32_t m_u32Fingerprint1; struct { uint16_t m_u16Major; uint16_t m_u16Minor; uint16_t m_u16Sub; } LDLB_Version; uint32_t m_u32Fingerprint2; uint32_t m_u32Firmware_startingNAND; uint32_t m_u32Firmware_startingSector; uint32_t m_u32Firmware_sectorStride; uint32_t m_u32SectorsInFirmware; uint32_t m_u32Firmware_StartingNAND2; uint32_t m_u32Firmware_StartingSector2; uint32_t m_u32Firmware_SectorStride2; uint32_t m_uSectorsInFirmware2; struct { uint16_t m_u16Major; uint16_t m_u16Minor; uint16_t m_u16Sub; } FirmwareVersion; uint32_t Rsvd[10]; uint32_t m_u32DiscoveredBBTableSector; uint32_t m_u32DiscoveredBBTableSector2; uint32_t m_u32Fingerprint3; uint32_t RSVD[100]; // Region configuration used by SDK only. } LogicalDriveLayoutBlock_t;; The first 512 bytes of the LDLB structure are as follows: Where: m_u32Fingerprint1--32 bit word consisting of STMP (stored as 0x504d5453) m_u32Fingerprint2--32 bit word consisting of LDLB (stored as 0x424C444C) m_u32Fingerprint3--32 bit word consisting of RBIL (stored as 0x4C494252) LDLBVersion structure--must be set to Major = 1, Minor = 0; Sub = anything. m_u32Firmware_startingNAND/m_u32Firmware_startingNAND2--Which NAND holds the firmware that will get loaded. This is zero-based, so NAND0 will be 0, NAND1 will be 1, etc. m_u32Firmware_startingSector/m_u32Firmware_StartingSector2--Which sector on the NAND to start with. Remember that sectors from the ROM's perspective are 512 bytes. Since the supported NANDs store data in 2K pages, this conversion will need a <<2 (or * 4). This is zero-based on the specific NAND (i.e., Sector0 of NAND3 will be 0 which may be physical sector 2048 (assuming NANDs are 1024 sectors per NAND) of the entire group of NANDs. Use 0 instead of 2048.) i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-27 Boot Modes m_u32Firmware_sectorStride/m_u32Firmware_SectorStride2--This 32 bit word describes how consecutive pages are read. Are the pages concatenated (read sequentially from the same block, then the next block on the same NAND), striped across NANDs on a sector basis (in NAND2 case -> sector 0 on NAND0, sector 0 on NAND1, sector 1 on NAND0, sector 1 on NAND1, etc.), striped across NANDs on a Block basis (sector 0-63 on NAND0, then sector 0-63 on NAND1, etc.)? Not used on current ROM. m_u32SectorsInFirmware--Number of sectors (2K byte chunks) that will be read by the ROM. m_ u32DiscoveredBBTableSector--Physical sector of Discovered Bad Block Table. m_ u32DiscoveredBBTableSector--Physical sector of secondary Discovered Bad Block Table. 35.8.3.9 Discovered Bad Block Table Header Layout Block Structure and Definitions typedef struct _LogicalDriveLayoutBlock { uint32_t m_u32Fingerprint1; uint32_t m_u32NumberBB_NAND0; uint32_t m_u32NumberBB_NAND1; uint32_t m_u32NumberBB_NAND2; uint32_t m_u32NumberBB_NAND3; uint32_t m_u32Number2KPagesBB_NAND0; uint32_t m_u32Number2KPagesBB_NAND1; uint32_t m_u32Number2KPagesBB_NAND2; uint32_t m_u32Number2KPagesBB_NAND3; uint32_t m_u32Fingerprint2; uint32_t RSVD[20]; // uint32_t m_u32Fingerprint3; } LogicalDriveLayoutBlock_t; The first 512 bytes of the DBBT header structure are as follows: Where: m_u32Fingerprint1--32 bit word consisting of STMP (stored as 0x504d5453) m_u32Fingerprint2--32 bit word consisting of DBBT (stored as 0x54424244) m_u32Fingerprint3--32 bit word consisting of RBId (stored as 0x44494252) m_u32NumberBB_NAND0--The number of Bad Blocks stored in this table for NAND0. m_u32NumberBB_NAND1--The number of Bad Blocks stored in this table for NAND1. m_u32NumberBB_NAND2--The number of Bad Blocks stored in this table for NAND2. m_u32NumberBB_NAND3--The number of Bad Blocks stored in this table for NAND3. m_u32Number2KPagesBB_NAND0--The number of 2K pages that the Bad Block table for NAND0 consumes. m_u32Number2KPagesBB_NAND1--The number of 2K pages that the Bad Block table for NAND1 consumes. i.MX23 Applications Processor Reference Manual, Rev. 1 35-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes m_u32Number2KPagesBB_NAND2--The number of 2K pages that the Bad Block table for NAND2 consumes. m_u32Number2KPagesBB_NAND3--The number of 2Kpages that the Bad Block table for NAND3 consumes. 35.8.3.10 Discovered Bad Block Table Layout Block Structure and Definitions The DBBT structure is as follows: typedef struct _BadBlockTableNand_t { uint32_t uNAND; uint32_t uNumberBB; int16_t u16BadBlock[]; } BadBlockTableNand_t; Where: uNAND- 32 bit word denoting which NAND the table describes. uNumberBB--32 bit word holding the number of Bad Blocks. u16BadBlock--Array of 16 bit words holding the Bad Blocks for this particular NAND. 35.8.4 35.8.4.1 Typical NAND Page Organization BCH ECC Page Organization. For NAND boot, ROM restricts the size of a BCH data block to 512 bytes. The first data block is called block 0 and the rest of the blocks are called block N. Separate ECC levels can be used for block 0 and block N. The metadata bytes should be located at the beginning of a page, starting at byte 0, followed by data block 0, followed by ECC bytes for data block 0, followed by block 1 and its ECC bytes, and so on until N data blocks. The ECC level for block 0 can be different from the ECC level of rest of the blocks. Metadata bytes can be 0. For NAND boot, with page size restrictions and data block size restricted to 512 bytes, only few combinations of ECC for block 0 and block N are possible. M Block0 512 bytes EccB0 Block1 512 bytes EccBN Block2 512 bytes EccBN Block3 512 bytes EccBN Figure 35-11. Valid layout for 2112 bytes sized page The number of ECC bits required for a data block is calculated using (ECC_Correction_Level * 13) bits. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-29 Boot Modes In the above layout the ECC size for EccB0 and EccBN should be selected to not exceed a total page size of 2112 bytes. EccB0 and EccBN can be one of 2, 4, 6, 8, 10, 12, 14, 16, 18, 20 bits ECC correction level. The total bytes would then be: [M + (data_block_size * 4) + ([EccB0 + (EccBN * 3)] * 13) / 8] <= 2112; M = metadata bytes and data_block_size is 512. There are 4 data blocks of 512 bytes each in a page of 2k page sized NAND. The values of EccB0 and EccBN should be such that the above calculation would not result in a value greater than 2112 bytes. c M Block0 512 bytes EccB0 Block1 512 bytes EccBN Block2 512 bytes EccBN Block3 512 bytes EccBN Block4 512 bytes EccBN Block5 512 bytes EccBN Block6 512 bytes EccBN Block7 512 bytes EccBN Figure 35-12. Valid layout for 4K bytes sized page Different NAND manufacturers have different sizes for a 4K page, 4314 bytes is typical. [M + (data_block_size * 8) + ([EccB0 + (EccBN * 7)] * 13) / 8] <= 4314; M = metadata bytes and data_block_size is 512. There are 8 data blocks of 512 bytes each in a page of a 4k page sized NAND. The values of EccB0 and EccBN should be such that above calculation should not result in a value greater than the size of a page in a 4k page NAND. 35.8.4.2 2K Page Organization on the NAND for RS-4 Bit ECC The ECC engine expects the following layout of data in a 2K page. Note that this configuration conflicts with the factory-marked bad block byte. Each 512 byte group has an ECC and the metadata has its own ECC. DATA - 512 E 1 DATA - 512 E 2 DATA - 512 E 3 DATA - 512 E 4 metadata E M EM E1 E2 Data = 512 byte ECC = 9 bytes Metadata = 19 bytes ECC = 9 bytes E3 E4 Figure 35-13. 2K Page Layout in NAND i.MX23 Applications Processor Reference Manual, Rev. 1 35-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes 35.8.4.3 In-Memory Organization for RS-4 Bit ECC A data read or data write does not have the ECC interspersed in the data as shown in Figure 35-13. Instead, on a read, the data is stored as follows in the i.MX23 on-chip RAM memory. Data Buffer DATA - 512 DATA - 512 DATA - 512 DATA - 512 Auxiliary Buffer metadata EM E1 E2 E3 E4 EM = Metadata ECC E1 = 1st 512 block ECC E2 = 2nd 512 block ECC E3 = 3rd 512 block ECC E4 = 4th 512 block ECC Figure 35-14. 2K Page Layout in On-Chip Memory The ECC is stripped off and placed in the Auxiliary buffer. This Auxiliary buffer is 188 bytes for a 2K page NAND. In the write case, the 2048 byte buffer is sent to the GPMI, but the Auxiliary buffer must be allocated for scratch pad space. 35.8.4.4 Metadata The Metadata consists of 19 bytes of the 2112 bytes in a page. Currently unused bytes are set to 0, but they can be any value as long as they are included in the ECC calculation. Currently, the ROM does not care about the metadata. Only the ECC bytes are important. The ROM expects the boot image sectors to have metadata as described in Figure 35-15. The EM shown in Figure 35-14 is the ECC for the metadata. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-31 Boot Modes 512 513 514 515 516 517 518 519 520 RS_1_ECC1 RS_1_ECC2 RS_1_ECC3 RS_1_ECC4 RS_1_ECC5 RS_1_ECC6 RS_1_ECC7 RS_1_ECC8 RS_1_ECC9 1554 1555 1556 1557 1558 1559 1560 1561 1562 RS_3_ECC1 RS_3_ECC2 RS_3_ECC3 RS_3_ECC4 RS_3_ECC5 RS_3_ECC6 RS_3_ECC7 RS_3_ECC8 RS_3_ECC9 1033 1034 1035 1036 1037 1038 1039 1040 1041 RS_2_ECC1 RS_2_ECC2 RS_2_ECC3 RS_2_ECC4 RS_2_ECC5 RS_2_ECC6 RS_2_ECC7 RS_2_ECC8 RS_2_ECC9 2075 2076 2078 2079 2080 2081 2082 2083 2084 RS_4_ECC1 RS_4_ECC2 RS_4_ECC3 RS_4_ECC4 RS_4_ECC5 RS_4_ECC6 RS_4_ECC7 RS_4_ECC8 RS_4_ECC9 Figure 35-15. Redundant Area--2K 35.8.4.5 4K Page Organization on the NAND for RS-8 Bit ECC The ECC engine expects the following layout of data in a 4K page. Note that this configuration conflicts with the factory marked bad block byte. Each 512 byte group has an ECC and the metadata has its own ECC. DATA - 512 E 1 DATA - 512 E 2 DATA - 512 E 3 DATA - 512 E 4 DATA - 512 E 5 DATA - 512 E 6 DATA - 512 E 7 DATA - 512 E 8 metadata E M E1 E2 E3 E4 E5 Data = 512 byte ECC = 18 bytes Metadata = 65 bytes ECC = 9 bytes E6 E7 E8 EM Figure 35-16. 4K Page in NAND 35.8.4.6 In-Memory Organization for RS-8 Bit ECC A data read or data write does not have the ECC interspersed in the data as shown in Figure 35-16. Instead, on a read, the data is stored as follows in the i.MX23 on-chip RAM memory. i.MX23 Applications Processor Reference Manual, Rev. 1 35-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Boot Modes Data Buffer DATA - 512 DATA - 512 DATA - 512 DATA - 512 DATA - 512 DATA - 512 DATA - 512 DATA - 512 EM = Metadata ECC E1 = 1st 512 block ECC E2 = 2nd 512 block ECC rd E3 = 3 512 block ECC th E4 = 4 512 block ECC E5 = 5th 512 block ECC E6 = 6th 512 block ECC E7 = 7th 512 block ECC th E8 = 8 512 block ECC Auxiliary Buffer metadata EM E1 E2 E3 E4 E5 E6 E7 E8 Figure 35-17. 4K Page Layout in On-Chip Memory The ECC is stripped off and placed in the Auxiliary buffer. This Auxiliary buffer is 412 bytes in the 4K page case. In the write case, the 4096 byte buffer is sent to the GPMI, but the Auxiliary buffer must be allocated for scratch pad space. 35.9 USB Boot Driver The USB Boot Driver is implemented as a USB HID class and is referred to as the Recovery HID, or RHID. The RHID serves as a fail-safe mechanism for downloading and communicating with application-specific code. The system is based on two HID Application collections: the Boot Loader Transfer Controller (BLTC) and the Plug-in Transfer Controller (PITC). Each collection has its own set of HID reports. 35.9.1 Boot Loader Transfer Controller (BLTC) The BLTC provides a tunnel to download application-specific PITCs to local system memory. The BLTC runs completely from ROM and interfaces directly to the ROM Loader. Typically, a PITC will be packaged on the host and downloaded through the BLTC and ROM Loader straight to OCRAM (or SDRAM). Four HID reports are provided for communication with the BLTC: * * * * BLTC Command Out (BLCO) BLTC Data Out (BLDO) BLTC Data In (BLDI) BLTC Status In (BLSI) The BLTC provides a command/data protocol for downloading code to the ROM Loader. The BLTC has no knowledge of the contents of the data passing through so it is really possible to download anything (not just PITCs). A list of USB bootloader commands is available upon request. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35-33 Boot Modes 35.9.2 Plug-in Transfer Controller (PITC) The PITC is a generic command/data/status tunnel that may be used for any type of application. The implementation only specifies the HID report structure and ROM HID-stack installation for a PITC--the protocol implementation is specific to a given PITC. Typically, a PITC will be downloaded to memory via the BLTC. Four HID reports are provided for communication with a PITC: * * * * PITC Command Out (PICO) PITC Data Out (PIDO) PITC Data In (PIDI) PITC Status In (PISI) The command/data protocol is specific to any given PITC. Only one PITC may be installed at any given time. 35.9.3 * * * USB IDs and Serial Number By default the USB Device Descriptor Vendor ID, Product ID, and serial number are reported as follows: Vendor ID--0x066F Product ID--0x3700 Serial Number String--none If any of the HW_OCOTP_ROM2 bits are blown, then the full contents of that OTP register are used to report the Vendor ID and Product ID. If the ENABLE_USB_BOOT_SERIAL_NUMBER OTP is blown, then a unique serial number will be generated from the factory-programmed SGTL_OPS3 OTP registers. 35.9.4 USB Recovery Mode USB boot mode is provided as a fail-safe mechanism for writing system firmware to the boot media. The boot mode is not usually entered by the normal methods of setting the boot pins or OTP: the other methods of entering USB boot mode are referred to generally as recovery mode. An end user can manually start recovery mode by holding the recovery switch for several seconds while plugging in USB. Holding the recovery switch is defined as reading the i.MX23 PSWITCH input as a 0x3. There are several switch circuits that will produce this input. The loader also automatically starts recovery mode if a non-recoverable error is detected from any boot mode other than USB. If the DISABLE_RECOVERY_MODE OTP bit is blown, then USB boot mode is disabled completely. Attempts to enter USB boot mode via boot pins, OTP, or recovery methods will result in a chip power-down. i.MX23 Applications Processor Reference Manual, Rev. 1 35-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 36 Pin Descriptions This chapter provides various views of the pinout for the i.MX23. * * Pin definitions for the 128-Pin LQFP are in Section 36.1, "Pin Definitions for 128-Pin LQFP." Pin definitions for the 169-Pin BGA are in Section 36.2, "Pin Definitions for 169-Pin BGA." The pin tables in this chapter include columns with the headings "Description 1", "Description 2", and "Description 3". These columns refer to the different functions that can be enabled for each individual pin by programming the pin control registers (HW_PINCTRL_MUXSELx). For example: * * * Enable the function listed in the "Description 1" column by programming the BANKx_PINx bit field to 00. Enable the function listed in the "Description 2" column by programming the BANKx_PINx bit field to 01. Enable the function listed in the "Description 3" column by programming the BANKx_PINx bit field to 10. See Chapter 37, "Pin Control and GPIO." for more information. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 36-1 Pin Descriptions Table 36-1 lists the abbreviations used in the pin tables in this chapter. Table 36-1. Nomenclature for Pin Tables TYPE DESCRIPTION MODULE DESCRIPTION A I I/O O P Analog pin Input pin Input/output pin Output pin Power pin ADC CLOCK DCDC EMI ETM GPIO GPMI HP I2C LCDIF LineOut LRADC POWER PWM RTC SSP SYSTEM TIMER UART USB ADC analog pins Clock pins DC-DC Converter pins External Memory Interface pins Embedded Trace Macrocell General-Purpose Input/Output pins General-Purpose Media Interface (NAND) pins Headphone pins I2C pins LCD Interface pins Line Out pins Low-Resolution ADC/Touch-Screen pins Power pins Pulse Width Modulator pins Real-Time Clock pins Synchronous Serial Port pins System pins Timer/Rotary Encoder pins Either debug or application UART pins USB pins Note: Almost all digital pins are powered down (i.e., high-impedance) at reset, until reprogrammed. The only exceptions are DEBUG. This pin is always active. 36.1 * * * Pin Definitions for 128-Pin LQFP Table 36-2, "128-Pin LQFP Pin Definitions by Pin Name," on page 2 Table 36-3, "128-Pin LQFP Pin Definitions by Pin Number," on page 5 Table 36-4, "128-Pin LQFP Connection Diagram--Top View," on page 9 Table 36-2. 128-Pin LQFP Pin Definitions by Pin Name This section includes the following pin information for the 128-pin LQFP package: Number Pin Name Group Type Description 1 Description 2 Description 3 103 100 98 97 99 96 BATT DCDC_BATTERY DCDC_GND DCDC_LN1 DCDC_LP DCDC_VDDA DCDC DCDC DCDC DCDC DCDC DCDC A A A A A A Battery Input DCDC Battery DCDC Ground DCDC Inductor N 1 DCDC Inductor P DCDC Analog Power i.MX23 Applications Processor Reference Manual, Rev. 1 36-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Descriptions Table 36-2. 128-Pin LQFP Pin Definitions by Pin Name (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 94 95 76 75 74 73 72 71 70 69 68 67 66 65 64 79 80 61 63 78 36 37 41 43 42 44 47 48 49 50 51 52 54 55 57 58 60 59 46 56 39 40 62 77 20 82 DCDC_VDDD DCDC_VDDIO EMI_A00 EMI_A01 EMI_A02 EMI_A03 EMI_A04 EMI_A05 EMI_A06 EMI_A07 EMI_A08 EMI_A09 EMI_A10 EMI_A11 EMI_A12 EMI_BA0 EMI_BA1 EMI_CASN EMI_CE0N EMI_CKE EMI_CLK EMI_CLKN EMI_D00 EMI_D01 EMI_D02 EMI_D03 EMI_D04 EMI_D05 EMI_D06 EMI_D07 EMI_D08 EMI_D09 EMI_D10 EMI_D11 EMI_D12 EMI_D13 EMI_D14 EMI_D15 EMI_DQM0 EMI_DQM1 EMI_DQS0 EMI_DQS1 EMI_RASN EMI_WEN GPMI_ALE GPMI_CE0N DCDC DCDC EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI GPMI GPMI A A DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DCDC Digital Core Power DCDC I/O Power EMI Address 0 EMI Address 1 EMI Address 2 EMI Address 3 EMI Address 4 EMI Address 5 EMI Address 6 EMI Address 7 EMI Address 8 EMI Address 9 EMI Address 10 EMI Address 11 EMI Address 12 DRAM Bank Address 0 DRAM Bank Address 1 EMI Column Address Strobe# EMI Chip Enable 0# EMI Clock Enable EMI Clock EMI Clock# EMI Data 0 EMI Data 1 EMI Data 2 EMI Data 3 EMI Data 4 EMI Data 5 EMI Data 6 EMI Data 7 EMI Data 8 EMI Data 9 EMI Data 10 EMI Data 11 EMI Data 12 EMI Data 13 EMI Data 14 EMI Data 15 EMI Data Mask 0 EMI Data Mask1 EMI mDDR-DDR Data Strobe 0 (Low Byte) EMI mDDR-DDR Data Strobe 1 (High Byte) EMI Row Address Strobe# EMI Write Enable# NAND ALE GPMI Chip Enable 0# LCD_D17 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 36-3 Pin Descriptions Table 36-2. 128-Pin LQFP Pin Definitions by Pin Name (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 81 19 22 23 24 25 27 26 29 28 31 32 21 34 33 113 109 111 127 128 10 2 3 4 5 6 7 8 9 17 11 15 12 14 16 13 115 114 108 107 116 119 125 126 91 83 GPMI_CE1N GPMI_CLE GPMI_D00 GPMI_D01 GPMI_D02 GPMI_D03 GPMI_D04 GPMI_D05 GPMI_D06 GPMI_D07 GPMI_RDN GPMI_RDY0 GPMI_RDY1 GPMI_WPN GPMI_WRN HPL HPR HP_VGND I2C_SCL I2C_SDA LCD_CS LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 LCD_D06 LCD_D07 LCD_DOTCK LCD_ENABLE LCD_HSYNC LCD_RESET LCD_RS LCD_VSYNC LCD_WR LINE1_INL LINE1_INR LRADC0 LRADC1 MIC PSWITCH PWM0 PWM1 PWM2 SSP1_CMD GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI HP HP HP I2C I2C LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF ADC ADC LRADC LRADC ADC DCDC PWM PWM PWM SSP DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO A A A DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO A A A A A A DIO DIO DIO DIO GPMI Chip Enable 1# NAND CLE NAND Data 0 NAND Data 1 NAND Data 2 NAND Data 3 NAND Data 4 NAND Data 5 NAND Data 6 NAND Data 7 NAND Read Strobe NAND0 Ready-Busy# NAND1 Ready-Busy# NAND Write Protect NAND Write Strobe Headphone Left Headphone Right Direct Coupled Headphone Virtual Ground I2C Serial Clock I2C Serial Data LCD Interface Chip Select LCD Interface Data 0 LCD Interface Data 1 LCD Interface Data 2 LCD Interface Data 3 LCD Interface Data 4 LCD Interface Data 5 LCD Interface Data 6 LCD Interface Data 7 LCD Interface DOT clock LCD Interface Enable LCD Interface horizontal sync LCD Interface Reset Out LCD Interface Register Select / LCD CCIR clock LCD Interface Vertical Sync LCD Interface 6800 E / 8800 WR Line-in 1 Left Line-in 1 Right LRADC0 (Button 1 or Temp or MicBias) LRADC1 (Button 2 or Temp or MicBias) Microphone Input Power On / Recovery PWM 0 PWM 1 PWM 2 SD-MMC CMD / SPI MOSI ROTARYA ROTARYB GPMI_RDY3 JTAG_TDO DUART RX DUART TX LCD_BUSY GPMI_RDY3 I2C_SCL I2C_SDA GPMI_CE3N GPMI_RDY2 GPMI_CE2N AUART1_TX AUART1_RX SSP2_SCK SSP2_DETECT SSP2_CMD LCD_D16 LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 SSP2_DATA0 SSP2_DATA1 SSP2_DATA2 SSP2_DATA3 SSP2_DATA4 SSP2_DATA5 SSP2_DATA6 SSP2_DATA7 i.MX23 Applications Processor Reference Manual, Rev. 1 36-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Descriptions Table 36-2. 128-Pin LQFP Pin Definitions by Pin Name (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 84 85 86 87 88 90 123 124 117 104 101 102 110 1 93 106 45 53 38 18 92 120 112 118 105 89 30 35 122 121 SSP1_DATA0 SSP1_DATA1 SSP1_DATA2 SSP1_DATA3 SSP1_DETECT SSP1_SCK USB_DM USB_DP VAG VDAC1 VDD4P2 VDD5V VDDA1 VDDD1 VDDD3 VDDM VDDIO_EMI1 VDDIO_EMI2 VDDIO_EMIQ VDDIO33_1 VDDIO33_3 VDDXTAL VSSA1 VSSA2 VSSA4 DEBUG VSSD1 VSSD2 XTALI XTALO SSP SSP SSP SSP SSP SSP USB USB HP VDAC DCDC DCDC POWER POWER POWER DCDC POWER POWER POWER POWER POWER CLOCK POWER POWER POWER SYSTEM DIO DIO DIO DIO DIO DIO A A A A A A A P P A P P P P P A A A A I/O D D A A SD-MMC Data0 / SPI MISO SD-MMC Data1 SD-MMC Data2 SD-MMC Data3 / SPI Slave Select 0 Removable Card Detect SSP Serial Clock USB Negative Data Line USB Positive Data Line Analog Reference Capacitor VDAC composite out DCDC 4.2V Regulated Output 5V Power Input Analog Power 1 Digital Core Power 1 Digital Core Power 3 2.5V Supply for external DDR DRAM Digital I/O Power 1 - EMI Digital I/O Power 2 - EMI EMI quiet supply Digital I/O 3.3v Power 1 Digital I/O 3.3v Power 3 Crystal Power Filter Cap - Cross bond to side 4 Analog Ground 1 Analog Ground 2 (quiet) Shared Analog Ground 1c Serial JTAG Debug Port Ground Ground Crystal In - 24MHz Crystal Out - 24MHz LRADC4 GPMI_CE3N I2C_SCL I2C_SDA JTAG_TDI JTAG_TCLK JTAG_RTCK JTAG_TMS USB_ID JTAG_TRST POWER POWER CLOCK CLOCK Table 36-3. 128-Pin LQFP Pin Definitions by Pin Number Number Pin Name Group Type Description 1 Description 2 Description 3 1 2 3 4 5 6 7 8 9 10 11 12 VDDD1 LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 LCD_D06 LCD_D07 LCD_CS LCD_ENABLE LCD_RESET POWER LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF P DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO Digital Core Power 1 LCD Interface Data 0 LCD Interface Data 1 LCD Interface Data 2 LCD Interface Data 3 LCD Interface Data 4 LCD Interface Data 5 LCD Interface Data 6 LCD Interface Data 7 LCD Interface Chip Select LCD Interface Enable LCD Interface Reset Out I2C_SCL GPMI_CE3N i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 36-5 Pin Descriptions Table 36-3. 128-Pin LQFP Pin Definitions by Pin Number (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 LCD_WR LCD_RS LCD_HSYNC LCD_VSYNC LCD_DOTCK VDDIO33_1 GPMI_CLE GPMI_ALE GPMI_RDY1 GPMI_D00 GPMI_D01 GPMI_D02 GPMI_D03 GPMI_D05 GPMI_D04 GPMI_D07 GPMI_D06 VSSD1 GPMI_RDN GPMI_RDY0 GPMI_WRN GPMI_WPN VSSD2 EMI_CLK EMI_CLKN VDDIO_EMIQ EMI_DQS0 EMI_DQS1 EMI_D00 EMI_D02 EMI_D01 EMI_D03 VDDIO_EMI1 EMI_DQM0 EMI_D04 EMI_D05 EMI_D06 EMI_D07 EMI_D08 EMI_D09 VDDIO_EMI2 EMI_D10 EMI_D11 EMI_DQM1 EMI_D12 EMI_D13 LCDIF LCDIF LCDIF LCDIF LCDIF POWER GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI POWER GPMI GPMI GPMI GPMI POWER EMI EMI POWER EMI EMI EMI EMI EMI EMI POWER EMI EMI EMI EMI EMI EMI EMI POWER EMI EMI EMI EMI EMI DIO DIO DIO DIO DIO P DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO P DIO DIO DIO DIO P DIO DIO P DIO DIO DIO DIO DIO DIO P DIO DIO DIO DIO DIO DIO DIO P DIO DIO DIO DIO DIO LCD Interface 6800 E / 8800 WR LCD Interface Register Select / LCD CCIR clock LCD Interface horizontal sync LCD Interface Vertical Sync LCD Interface DOT clock Digital I/O 3.3v Power 1 NAND CLE NAND ALE NAND1 Ready-Busy# NAND Data 0 NAND Data 1 NAND Data 2 NAND Data 3 NAND Data 5 NAND Data 4 NAND Data 7 NAND Data 6 Ground NAND Read Strobe NAND0 Ready-Busy# NAND Write Strobe NAND Write Protect Ground EMI Clock EMI Clock# EMI quiet supply EMI mDDR-DDR Data Strobe 0 (Low Byte) EMI mDDR-DDR Data Strobe 1 (High Byte) EMI Data 0 EMI Data 2 EMI Data 1 EMI Data 3 Digital I/O Power 1 - EMI EMI Data Mask 0 EMI Data 4 EMI Data 5 EMI Data 6 EMI Data 7 EMI Data 8 EMI Data 9 Digital I/O Power 2 - EMI EMI Data 10 EMI Data 11 EMI Data Mask1 EMI Data 12 EMI Data 13 SSP2_DETECT SSP2_SCK LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D13 LCD_D12 LCD_D15 LCD_D14 LCD_D16 LCD_D17 SSP2_CMD SSP2_DATA0 SSP2_DATA1 SSP2_DATA2 SSP2_DATA3 SSP2_DATA5 SSP2_DATA4 SSP2_DATA7 SSP2_DATA6 I2C_SDA LCD_BUSY GPMI_RDY3 i.MX23 Applications Processor Reference Manual, Rev. 1 36-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Descriptions Table 36-3. 128-Pin LQFP Pin Definitions by Pin Number (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 EMI_D15 EMI_D14 EMI_CASN EMI_RASN EMI_CE0N EMI_A12 EMI_A11 EMI_A10 EMI_A09 EMI_A08 EMI_A07 EMI_A06 EMI_A05 EMI_A04 EMI_A03 EMI_A02 EMI_A01 EMI_A00 EMI_WEN EMI_CKE EMI_BA0 EMI_BA1 GPMI_CE1N GPMI_CE0N SSP1_CMD SSP1_DATA0 SSP1_DATA1 SSP1_DATA2 SSP1_DATA3 SSP1_DETECT DEBUG SSP1_SCK PWM2 VDDIO33_3 VDDD3 DCDC_VDDD DCDC_VDDIO DCDC_VDDA DCDC_LN1 DCDC_GND DCDC_LP DCDC_BATTERY VDD4P2 VDD5V BATT VDAC1 EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI GPMI GPMI SSP SSP SSP SSP SSP SSP SYSTEM DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO I/O DIO DIO P P A A A A A A A A A A A EMI Data 15 EMI Data 14 EMI Column Address Strobe# EMI Row Address Strobe# EMI Chip Enable 0# EMI Address 12 EMI Address 11 EMI Address 10 EMI Address 9 EMI Address 8 EMI Address 7 EMI Address 6 EMI Address 5 EMI Address 4 EMI Address 3 EMI Address 2 EMI Address 1 EMI Address 0 EMI Write Enable# EMI Clock Enable DRAM Bank Address 0 DRAM Bank Address 1 GPMI Chip Enable 1# GPMI Chip Enable 0# SD-MMC CMD / SPI MOSI SD-MMC Data0 / SPI MISO SD-MMC Data1 SD-MMC Data2 SD-MMC Data3 / SPI Slave Select 0 Removable Card Detect Serial JTAG Debug Port SSP Serial Clock PWM 2 Digital I/O 3.3v Power 3 Digital Core Power 3 DCDC Digital Core Power DCDC I/O Power DCDC Analog Power DCDC Inductor N 1 DCDC Ground DCDC Inductor P DCDC Battery DCDC 4.2V Regulated Output 5V Power Input Battery Input VDAC composite out GPMI_RDY3 JTAG_TRST GPMI_CE3N I2C_SCL I2C_SDA JTAG_TDO JTAG_TDI JTAG_TCLK JTAG_RTCK JTAG_TMS USB_ID SSP PWM POWER POWER DCDC DCDC DCDC DCDC DCDC DCDC DCDC DCDC DCDC DCDC VDAC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 36-7 Pin Descriptions Table 36-3. 128-Pin LQFP Pin Definitions by Pin Number (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VSSA4 VDDM LRADC1 LRADC0 HPR VDDA1 HP_VGND VSSA1 HPL LINE1_INR LINE1_INL MIC VAG VSSA2 PSWITCH VDDXTAL XTALO XTALI USB_DM USB_DP PWM0 PWM1 I2C_SCL I2C_SDA POWER DCDC LRADC LRADC HP POWER HP POWER HP ADC ADC ADC HP POWER DCDC CLOCK CLOCK CLOCK USB USB PWM PWM I2C I2C A A A A A A A A A A A A A A A A A A A A DIO DIO DIO DIO Shared Analog Ground 1c 2.5V Supply for external DDR DRAM LRADC1 (Button 2 or Temp or MicBias) LRADC0 (Button 1 or Temp or MicBias) Headphone Right Analog Power 1 Direct Coupled Headphone Virtual Ground Analog Ground 1 Headphone Left Line-in 1 Right Line-in 1 Left Microphone Input Analog Reference Capacitor Analog Ground 2 (quiet) Power On / Recovery Crystal Power Filter Cap - Cross bond to side 4 Crystal Out - 24MHz Crystal In - 24MHz USB Negative Data Line USB Positive Data Line PWM 0 PWM 1 I2C Serial Clock I2C Serial Data ROTARYA ROTARYB GPMI_RDY2 GPMI_CE2N DUART RX DUART TX AUART1_TX AUART1_RX LRADC4 i.MX23 Applications Processor Reference Manual, Rev. 1 36-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Descriptions Table 36-4. 128-Pin LQFP Connection Diagram--Top View DCDC_BATTERY DCDC_GND DCDC_LN1 96 DCDC_VDDA 95 DCDC_VDDIO 94 DCDC_VDDD 93 VDDD3 92 VDDIO33_3 91 PWM2 90 SSP1_SCK 89 DEBUG 88 SSP1_DETECT 87 SSP1_DATA3 86 SSP1_DATA2 85 SSP1_DATA1 84 SSP1_DATA0 83 SSP1_CMD 82 GPMI_CE0N 81 GPMI_CE1N 80 EMI_BA1 79 EMI_BA0 78 EMI_CKE 77 EMI_WEN 76 EMI_A00 75 EMI_A01 74 EMI_A02 73 EMI_A03 72 EMI_A04 71 EMI_A05 70 EMI_A06 69 EMI_A07 68 EMI_A08 67 EMI_A09 66 EMI_A10 65 EMI_A11 33 GPMI_WRN 34 GPMI_WPN 35 VSSD2 36 EMI_CLK 37 EMI_CLKN 38 VDDIO_EMIQ 39 EMI_DQS0 40 EMI_DQS1 41 EMI_D00 42 EMI_D02 43 EMI_D01 44 EMI_D03 45 VDDIO_EMI1 46 EMI_DQM0 47 EMI_D04 48 EMI_D05 49 EMI_D06 50 EMI_D07 51 EMI_D08 52 EMI_D09 53 VDDIO_EMI2 54 EMI_D10 55 EMI_D11 56 EMI_DQM1 57 EMI_D12 58 EMI_D13 59 EMI_D15 60 EMI_D14 61 EMI_CASN 62 63 64 EMI_RASN EMI_CE0N EMI_A12 LINE1_INR LINE1_INL HP_VGND 128 127 VDDD1 LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 LCD_D06 LCD_D07 1 2 3 4 5 6 7 8 9 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 LCD_CS 10 LCD_ENABLE 11 LCD_RESET 12 LCD_WR 13 LCD_RS 14 LCD_HSYNC 15 LCD_VSYNC 16 LCD_DOTCK 17 VDDIO33_1 18 GPMI_CLE 19 GPMI_ALE 20 GPMI_RDY1 21 GPMI_D00 22 GPMI_D01 23 GPMI_D02 24 GPMI_D03 25 GPMI_D05 26 GPMI_D04 27 GPMI_D07 28 GPMI_D06 29 VSSD1 30 GPMI_RDN 31 GPMI_RDY0 32 36.2 * * * Pin Definitions for 169-Pin BGA Table 36-5, "169-Pin BGA Pin Definitions by Pin Name," on page 9 Table 36-6, "169-Pin BGA Pin Definitions by Pin Number," on page 13 Table 36-7, "169-Pin BGA Ball Map," on page 18 Table 36-5. 169-Pin BGA Pin Definitions by Pin Name This section includes the following pin information for the 169-pin BGA package: Number Pin Name Group Type Description 1 Description 2 Description 3 G7 H7 H8 J8 AUART1_CTS AUART1_RTS AUART1_RX AUART1_TX UART UART UART UART DIO Application UART 1 Clear To Send Flow Control DIO Application UART 1 Ready To Send Flow Control DIO Application UART 1 Receive DIO Application UART 1 Transmit SSP1_DATA4 SSP1_DATA5 SSP1_DATA6 SSP1_DATA7 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice DCDC_LP PSWITCH VDDXTAL I2C_SDA USB_DM I2C_SCL USB_DP LRADC0 LRADC1 VDD4P2 VDDA1 VDAC1 VDD5V VSSA2 VSSA1 VSSA4 XTALO PWM1 PWM0 VDDM XTALI BATT HPR VAG HPL MIC 36-9 Pin Descriptions Table 36-5. 169-Pin BGA Pin Definitions by Pin Name (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 A11 B11 A13 B13 A12 B12 D13 C13 E12 K13 K12 J13 K11 G10 G12 F12 G11 G13 F13 J12 H10 H13 L13 L12 M13 J10 H12 F11 M6 N6 K10 M10 N11 N10 M11 K9 L11 L9 N9 N8 M8 K7 L7 K6 N7 M7 BATT DCDC_BATTERY DCDC_GND DCDC_LN1 DCDC_LP DCDC_VDDA DCDC_VDDD DCDC_VDDIO DEBUG EMI_A00 EMI_A01 EMI_A02 EMI_A03 EMI_A04 EMI_A05 EMI_A06 EMI_A07 EMI_A08 EMI_A09 EMI_A10 EMI_A11 EMI_A12 EMI_BA0 EMI_BA1 EMI_CASN EMI_CE0N EMI_CE1N EMI_CKE EMI_CLK EMI_CLKN EMI_D00 EMI_D01 EMI_D02 EMI_D03 EMI_D04 EMI_D05 EMI_D06 EMI_D07 EMI_D08 EMI_D09 EMI_D10 EMI_D11 EMI_D12 EMI_D13 EMI_D14 EMI_D15 DCDC DCDC DCDC DCDC DCDC DCDC DCDC DCDC SYSTEM EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI EMI A A A A A A A A Battery Input DCDC Battery DCDC Ground DCDC Inductor N 1 DCDC Inductor P DCDC Analog Power DCDC Digital Core Power DCDC I/O Power DIO 1-Wire Debug Port DIO EMI Address 0 DIO EMI Address 1 DIO EMI Address 2 DIO EMI Address 3 DIO EMI Address 4 DIO EMI Address 5 DIO EMI Address 6 DIO EMI Address 7 DIO EMI Address 8 DIO EMI Address 9 DIO EMI Address 10 DIO EMI Address 11 DIO EMI Address 12 DIO DRAM Bank Address 0 DIO DRAM Bank Address 1 DIO EMI Column Address Strobe# DIO EMI Chip Enable 0# DIO EMI Chip Enable 1# DIO EMI Clock Enable DIO EMI Clock DIO EMI Clock# DIO EMI Data 0 DIO EMI Data 1 DIO EMI Data 2 DIO EMI Data 3 DIO EMI Data 4 DIO EMI Data 5 DIO EMI Data 6 DIO EMI Data 7 DIO EMI Data 8 DIO EMI Data 9 DIO EMI Data 10 DIO EMI Data 11 DIO EMI Data 12 DIO EMI Data 13 DIO EMI Data 14 DIO EMI Data 15 i.MX23 Applications Processor Reference Manual, Rev. 1 36-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Descriptions Table 36-5. 169-Pin BGA Pin Definitions by Pin Name (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 M12 M9 N12 K8 N13 J11 K4 G8 F8 K5 K3 K2 L1 L2 L3 L5 L4 M2 M1 M3 M4 M5 N1 N2 N3 N4 N5 H6 G6 J6 F6 E6 F7 E7 A7 B7 B8 C5 C6 H4 D3 E2 E4 F1 F3 F5 EMI_DQM0 EMI_DQM1 EMI_DQS0 EMI_DQS1 EMI_RASN EMI_WEN GPMI_ALE GPMI_CE0N GPMI_CE1N GPMI_CE2N GPMI_CLE GPMI_D00 GPMI_D01 GPMI_D02 GPMI_D03 GPMI_D04 GPMI_D05 GPMI_D06 GPMI_D07 GPMI_D08 GPMI_D09 GPMI_D10 GPMI_D11 GPMI_D12 GPMI_D13 GPMI_D14 GPMI_D15 GPMI_RDN GPMI_RDY0 GPMI_RDY1 GPMI_RDY2 GPMI_RDY3 GPMI_WPN GPMI_WRN HP_VGND HPL HPR I2C_SCL I2C_SDA LCD_CS LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 EMI EMI EMI EMI EMI EMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI GPMI HP HP HP I2C I2C LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF DIO EMI Data Mask 0 DIO EMI Data Mask1 DIO EMI mDDR-DDR Data Strobe 0 (Low Byte) DIO EMI mDDR-DDR Data Strobe 1 (High Byte) DIO EMI Row Address Strobe# DIO EMI Write Enable# DIO NAND ALE DIO GPMI Chip Enable 0# DIO GPMI Chip Enable 1# DIO NAND2 Chip Enable# DIO NAND CLE DIO NAND Data 0 DIO NAND Data 1 DIO NAND Data 2 DIO NAND Data 3 DIO NAND Data 4 DIO NAND Data 5 DIO NAND Data 6 DIO NAND Data 7 DIO NAND Data 8 DIO NAND Data 9 DIO NAND Data 10 DIO NAND Data 11 DIO NAND Data 12 DIO NAND Data 13 DIO NAND Data 14 DIO NAND Data 15 DIO NAND Read Strobe DIO NAND0 Ready-Busy# DIO NAND1 Ready-Busy# DIO NAND2 Ready-Busy# DIO NAND3 Ready-Busy# DIO NAND Write Protect DIO NAND Write Strobe A A A Direct Coupled Headphone Virtual Ground Headphone Left Headphone Right GPMI_RDY2 GPMI_CE2N AUART1_TX AUART1_RX SSP2_SCK SSP2_DETECT SSP2_CMD LCD_D16 LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D18 LCD_D19 LCD_D20 LCD_D21 LCD_D22 LCD_D23 AUART2_RX AUART2_TX GPMI_CE3N SSP2_DATA0 SSP2_DATA1 SSP2_DATA2 SSP2_DATA3 SSP2_DATA4 SSP2_DATA5 SSP2_DATA6 SSP2_DATA7 SSP1_DATA4 SSP1_DATA5 SSP1_DATA6 SSP1_DATA7 LCD_D17 DIO I2C Serial Clock DIO I2C Serial Data DIO LCD Interface Chip Select DIO LCD Interface Data 0 DIO LCD Interface Data 1 DIO LCD Interface Data 2 DIO LCD Interface Data 3 DIO LCD Interface Data 4 DIO LCD Interface Data 5 ETM_DA8 ETM_DA9 ETM_DA10 ETM_DA11 ETM_DA12 ETM_DA13 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 36-11 Pin Descriptions Table 36-5. 169-Pin BGA Pin Definitions by Pin Name (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 G2 G5 H2 H3 H1 G4 G1 F4 F2 E5 E3 E1 K1 H5 J2 J5 J3 J1 J4 B5 A6 A8 B9 C9 D9 A10 B10 B6 B3 C3 D2 H11 D11 C12 D7 E8 B4 C4 C1 D1 H9 G9 F9 F10 E10 D10 LCD_D06 LCD_D07 LCD_D08 LCD_D09 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_DOTCK LCD_ENABLE LCD_HSYNC LCD_RESET LCD_RS LCD_VSYNC LCD_WR LINE1_INL LINE1_INR LRADC0 LRADC1 LRADC2 LRADC3 LRADC4 LRADC5 MIC PSWITCH PWM0 PWM1 PWM2 PWM3 PWM4 ROTARYA ROTARYB RTC_XTALI RTC_XTALO SPEAKERP SPEAKERN SSP1_CMD SSP1_DATA0 SSP1_DATA1 SSP1_DATA2 SSP1_DATA3 SSP1_DETECT LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF LCDIF ADC ADC LRADC LRADC LRADC LRADC LRADC LRADC ADC DCDC PWM PWM PWM PWM PWM TIMER TIMER CLOCK CLOCK SPKR SPKR SSP SSP SSP SSP SSP SSP DIO LCD Interface Data 6 DIO LCD Interface Data 7 DIO LCD Interface Data 8 DIO LCD Interface Data 9 DIO LCD Interface Data 10 DIO LCD Interface Data 11 DIO LCD Interface Data 12 DIO LCD Interface Data 13 DIO LCD Interface Data 14 DIO LCD Interface Data 15 DIO LCD Interface Data 16 DIO LCD Interface Data 17 DIO LCD Interface DOT clock DIO LCD Interface Enable DIO LCD Interface horizontal sync DIO LCD Interface Reset Out DIO LCD Interface Register Select / LCD CCIR clock DIO LCD Interface Vertical Sync DIO LCD Interface 6800 E / 8800 WR A A A A A A A A A A Line-in 1 Left Line-in 1 Right LRADC0 (Button 1 or Temp or MicBias) LRADC1 (Button 2 or Temp or MicBias) LRADC2 (Touchscreen 0) LRADC3 (Touchscreen 1) LRADC4 (Touchscreen 2) LRADC5 (Touchscreen 3) Microphone Input Power On / Recovery ETM_DA14 ETM_DA15 ETM_DA0 ETM_DA1 ETM_DA2 ETM_DA3 ETM_DA4 ETM_DA5 ETM_DA6 ETM_DA7 SAIF2_SDATA0 SAIF1_SDATA0 SAIF_MCLK_BITCLK SAIF_LRCLK SAIF2_SDATA1 SAIF2_SDATA2/SAIF_ALT_BITCLK SAIF1_SDATA2 SAIF1_SDATA1 SAIF_ALT_BITCLK GPMI_RDY3 I2C_SCL I2C_SDA ETM_TCTL ETM_TCLK LCD_BUSY GPMI_CE3N LINE2_INL LINE2_INR DIO PWM 0 DIO PWM 1 DIO PWM 2 DIO PWM 3 DIO PWM 4 DIO Rotary Encoder A DIO Rotary Encoder B A A A A 32.768 KHz Xtal In 32.768 KHz Xtal Out Speaker out P Speaker out N ROTARYA ROTARYB GPMI_RDY3 ETM_TCTL ETM_TCLK AUART2_RTS AUART2_CTS DUART RX DUART TX AUART1_CTS AUART1_RTS SPDIF GPMI_CE3N DIO SD-MMC CMD / SPI MOSI DIO SD-MMC Data0 / SPI MISO DIO SD-MMC Data1 DIO SD-MMC Data2 DIO SD-MMC Data3 / SPI Slave Select 0 DIO Removable Card Detect GPMI_CE3N I2C_SCL I2C_SDA JTAG_TDO JTAG_TDI JTAG_TCLK JTAG_RTCK JTAG_TMS USB_ID i.MX23 Applications Processor Reference Manual, Rev. 1 36-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Descriptions Table 36-5. 169-Pin BGA Pin Definitions by Pin Name (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 D12 A1 B2 A3 C11 A9 E13 C7 D5 D8 L8 L10 L6 G3 E11 C10 B1 C2 C8 A2 D4 D6 E9 J7 J9 A4 A5 SSP1_SCK USB_DP USB_DM VAG VDAC1 VDD4P2 VDD5V VDDA1 VDDD1/3 VDDD1/3 VDDIO_EMI1/2 VDDIO_EMI1/2 VDDIO_EMIQ VDDIO33_1/2/3 VDDIO33_1/2/3 VDDM VDDS VDDXTAL VSSA1 VSSA2 VSSA5 VSSD1/5 VSSD1/5 VSSIO_EMI1/2 VSSIO_EMI1/2 XTALI XTALO SSP USB USB HP VDAC DCDC DCDC POWER POWER POWER POWER POWER POWER POWER POWER DCDC SPKR CLOCK LCDIF LCDIF POWER POWER POWER POWER POWER CLOCK CLOCK DIO SSP Serial Clock A A A A A A A P P P P P P P A A A A A A P P P P A A USB Negative Data Line USB Positive Data Line Analog Reference Capacitor VDAC composite out DCDC 4.2V Regulated Output 5V Power Input Analog Power 1 Digital Core Power 1 Digital Core Power 3 Digital I/O Power 1 - EMI Digital I/O Power 2 - EMI EMI quiet supply Digital I/O 3.3v Power 1 Digital I/O 3.3v Power 3 2.5V Supply for external DDR DRAM Speaker out voltage source Crystal Power Filter Cap - Cross bond to side 4 Analog Ground 1 Analog Ground 2 (quiet) Shared Analog Ground 1d (speaker) Digital Ground 1 Digital Ground 2 EMI IO Ground 1 EMI IO Ground 2 Crystal In - 24MHz Crystal Out - 24MHz LRADC4 JTAG_TRST Table 36-6. 169-Pin BGA Pin Definitions by Pin Number Number Pin Name Group Type Description 1 Description 2 Description 3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 USB_DP VSSA2 VAG XTALI XTALO LINE1_INR HP_VGND LRADC0 VDD4P2 LRADC4 BATT DCDC_LP DCDC_GND VDDS USB_DM USB LCDIF HP CLOCK CLOCK ADC HP LRADC DCDC LRADC DCDC DCDC DCDC SPKR USB A A A A A A A A A A A A A A A USB Negative Data Line Analog Ground 2 (quiet) Analog Reference Capacitor Crystal In - 24MHz Crystal Out - 24MHz Line-in 1 Right Direct Coupled Headphone Virtual Ground LRADC0 (Button 1 or Temp or MicBias) DCDC 4.2V Regulated Output LRADC4 (Touchscreen 2) Battery Input DCDC Inductor P DCDC Ground Speaker out voltage source USB Positive Data Line i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 36-13 Pin Descriptions Table 36-6. 169-Pin BGA Pin Definitions by Pin Number (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 E1 E2 E3 E4 E5 E6 E7 E8 E9 PSWITCH RTC_XTALI LINE1_INL MIC HPL HPR LRADC1 LRADC5 DCDC_BATTERY DCDC_VDDA DCDC_LN1 SPEAKERP VDDXTAL PWM0 RTC_XTALO I2C_SCL I2C_SDA VDDA1 VSSA1 LRADC2 VDDM VDAC1 PWM4 DCDC_VDDIO SPEAKERN PWM1 LCD_D00 VSSA5 VDDD1/3 VSSD1/5 ROTARYA VDDD1/3 LRADC3 SSP1_DETECT PWM3 SSP1_SCK DCDC_VDDD LCD_D17 LCD_D01 LCD_D16 LCD_D02 LCD_D15 GPMI_RDY3 GPMI_WRN ROTARYB VSSD1/5 DCDC CLOCK ADC ADC HP HP LRADC LRADC DCDC DCDC DCDC SPKR CLOCK PWM CLOCK I2C I2C POWER LCDIF LRADC DCDC VDAC PWM DCDC SPKR PWM LCDIF POWER POWER POWER TIMER POWER LRADC SSP PWM SSP DCDC LCDIF LCDIF LCDIF LCDIF LCDIF GPMI GPMI TIMER POWER A A A A A A A A A A A A A Power On / Recovery 32.768 KHz Xtal In Line-in 1 Left Microphone Input Headphone Left Headphone Right LRADC1 (Button 2 or Temp or MicBias) LRADC5 (Touchscreen 3) DCDC Battery DCDC Analog Power DCDC Inductor N 1 Speaker out P Crystal Power Filter Cap - Cross bond to side 4 ROTARYA DUART RX DIO PWM 0 A 32.768 KHz Xtal Out DIO I2C Serial Clock DIO I2C Serial Data A A A A A Analog Power 1 Analog Ground 1 LRADC2 (Touchscreen 0) 2.5V Supply for external DDR DRAM VDAC composite out GPMI_RDY2 GPMI_CE2N AUART1_TX AUART1_RX LINE2_INL LRADC4 DIO PWM 4 A A DCDC I/O Power Speaker out N ETM_TCLK AUART1_RTS DIO PWM 1 DIO LCD Interface Data 0 A P P Shared Analog Ground 1d (speaker) Digital Core Power 1 Digital Ground 1 ROTARYB ETM_DA8 DUART TX DIO Rotary Encoder A P A Digital Core Power 3 LRADC3 (Touchscreen 1) AUART2_RTS SPDIF LINE2_INR GPMI_CE3N ETM_TCTL USB_ID AUART1_CTS JTAG_TRST DIO Removable Card Detect DIO PWM 3 DIO SSP Serial Clock A DCDC Digital Core Power DIO LCD Interface Data 17 DIO LCD Interface Data 1 DIO LCD Interface Data 16 DIO LCD Interface Data 2 DIO LCD Interface Data 15 DIO NAND3 Ready-Busy# DIO NAND Write Strobe DIO Rotary Encoder B P Digital Ground 2 AUART2_CTS SSP2_SCK GPMI_CE3N ETM_DA10 ETM_DA7 SAIF1_SDATA1 ETM_DA9 SAIF_ALT_BITCLK i.MX23 Applications Processor Reference Manual, Rev. 1 36-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Descriptions Table 36-6. 169-Pin BGA Pin Definitions by Pin Number (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 E10 E11 E12 E13 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 J1 J2 J3 SSP1_DATA3 VDDIO33_1/2/3 DEBUG VDD5V LCD_D03 LCD_D14 LCD_D04 LCD_D13 LCD_D05 GPMI_RDY2 GPMI_WPN GPMI_CE1N SSP1_DATA1 SSP1_DATA2 EMI_CKE EMI_A06 EMI_A09 LCD_D12 LCD_D06 VDDIO33_1/2/3 LCD_D11 LCD_D07 GPMI_RDY0 AUART1_CTS GPMI_CE0N SSP1_DATA0 EMI_A04 EMI_A07 EMI_A05 EMI_A08 LCD_D10 LCD_D08 LCD_D09 LCD_CS LCD_ENABLE GPMI_RDN AUART1_RTS AUART1_RX SSP1_CMD EMI_A11 PWM2 EMI_CE1N EMI_A12 LCD_VSYNC LCD_HSYNC LCD_RS SSP POWER SYSTEM DCDC LCDIF LCDIF LCDIF LCDIF LCDIF GPMI GPMI GPMI SSP SSP EMI EMI EMI LCDIF LCDIF POWER LCDIF LCDIF GPMI UART GPMI SSP EMI EMI EMI EMI LCDIF LCDIF LCDIF LCDIF LCDIF GPMI UART UART SSP EMI PWM EMI EMI LCDIF LCDIF LCDIF DIO SD-MMC Data3 / SPI Slave Select 0 P Digital I/O 3.3v Power 3 JTAG_TMS DIO 1-Wire Debug Port A 5V Power Input ETM_DA11 ETM_DA6 ETM_DA12 ETM_DA5 ETM_DA13 SAIF2_SDATA2/SAIF_ALT_BITCLK SAIF1_SDATA2 DIO LCD Interface Data 3 DIO LCD Interface Data 14 DIO LCD Interface Data 4 DIO LCD Interface Data 13 DIO LCD Interface Data 5 DIO NAND2 Ready-Busy# DIO NAND Write Protect DIO GPMI Chip Enable 1# DIO SD-MMC Data1 DIO SD-MMC Data2 DIO EMI Clock Enable DIO EMI Address 6 DIO EMI Address 9 DIO LCD Interface Data 12 DIO LCD Interface Data 6 P Digital I/O 3.3v Power 1 SSP2_SCK I2C_SCL I2C_SDA JTAG_TCLK JTAG_RTCK ETM_DA4 ETM_DA14 SAIF2_SDATA1 DIO LCD Interface Data 11 DIO LCD Interface Data 7 DIO NAND0 Ready-Busy# DIO Application UART 1 Clear To Send Flow Control DIO GPMI Chip Enable 0# DIO SD-MMC Data0 / SPI MISO DIO EMI Address 4 DIO EMI Address 7 DIO EMI Address 5 DIO EMI Address 8 DIO LCD Interface Data 10 DIO LCD Interface Data 8 DIO LCD Interface Data 9 DIO LCD Interface Chip Select DIO LCD Interface Enable DIO NAND Read Strobe DIO Application UART 1 Ready To Send Flow Control DIO Application UART 1 Receive DIO SD-MMC CMD / SPI MOSI DIO EMI Address 11 DIO PWM 2 DIO EMI Chip Enable 1# DIO EMI Address 12 DIO LCD Interface Vertical Sync DIO LCD Interface horizontal sync DIO LCD Interface Register Select / LCD CCIR clock ETM_DA3 ETM_DA15 SAIF_LRCLK SSP2_DETECT SSP1_DATA4 JTAG_TDI ETM_DA2 ETM_DA0 ETM_DA1 SAIF_MCLK_BITCLK SAIF2_SDATA0 SAIF1_SDATA0 I2C_SCL SSP2_DETECT SSP1_DATA5 SSP1_DATA6 JTAG_TDO GPMI_RDY3 LCD_BUSY I2C_SDA ETM_TCLK i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 36-15 Pin Descriptions Table 36-6. 169-Pin BGA Pin Definitions by Pin Number (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 LCD_WR LCD_RESET GPMI_RDY1 VSSIO_EMI1/2 AUART1_TX VSSIO_EMI1/2 EMI_CE0N EMI_WEN EMI_A10 EMI_A02 LCD_DOTCK GPMI_D00 GPMI_CLE GPMI_ALE GPMI_CE2N EMI_D13 EMI_D11 EMI_DQS1 EMI_D05 EMI_D00 EMI_A03 EMI_A01 EMI_A00 GPMI_D01 GPMI_D02 GPMI_D03 GPMI_D05 GPMI_D04 VDDIO_EMIQ EMI_D12 VDDIO_EMI1/2 EMI_D07 VDDIO_EMI1/2 EMI_D06 EMI_BA1 EMI_BA0 GPMI_D07 GPMI_D06 GPMI_D08 GPMI_D09 GPMI_D10 EMI_CLK EMI_D15 EMI_D10 EMI_DQM1 EMI_D01 LCDIF LCDIF GPMI POWER UART POWER EMI EMI EMI EMI LCDIF GPMI GPMI GPMI GPMI EMI EMI EMI EMI EMI EMI EMI EMI GPMI GPMI GPMI GPMI GPMI POWER EMI POWER EMI POWER EMI EMI EMI GPMI GPMI GPMI GPMI GPMI EMI EMI EMI EMI EMI DIO LCD Interface 6800 E / 8800 WR DIO LCD Interface Reset Out DIO NAND1 Ready-Busy# P EMI IO Ground 1 SSP1_DATA7 ETM_TCTL GPMI_CE3N SSP2_CMD DIO Application UART 1 Transmit P EMI IO Ground 2 DIO EMI Chip Enable 0# DIO EMI Write Enable# DIO EMI Address 10 DIO EMI Address 2 DIO LCD Interface DOT clock DIO NAND Data 0 DIO NAND CLE DIO NAND ALE DIO NAND2 Chip Enable# DIO EMI Data 13 DIO EMI Data 11 DIO EMI mDDR-DDR Data Strobe 1 (High Byte) DIO EMI Data 5 DIO EMI Data 0 DIO EMI Address 3 DIO EMI Address 1 DIO EMI Address 0 DIO NAND Data 1 DIO NAND Data 2 DIO NAND Data 3 DIO NAND Data 5 DIO NAND Data 4 P EMI quiet supply LCD_D9 LCD_D10 LCD_D11 LCD_D13 LCD_D12 SSP2_DATA1 SSP2_DATA2 SSP2_DATA3 SSP2_DATA5 SSP2_DATA4 GPMI_RDY3 LCD_D8 LCD_D16 LCD_D17 SSP2_DATA0 DIO EMI Data 12 P Digital I/O Power 1 - EMI DIO EMI Data 7 P Digital I/O Power 2 - EMI DIO EMI Data 6 DIO DRAM Bank Address 1 DIO DRAM Bank Address 0 DIO NAND Data 7 DIO NAND Data 6 DIO NAND Data 8 DIO NAND Data 9 DIO NAND Data 10 DIO EMI Clock DIO EMI Data 15 DIO EMI Data 10 DIO EMI Data Mask1 DIO EMI Data 1 LCD_D15 LCD_D14 LCD_D18 LCD_D19 LCD_D20 SSP2_DATA7 SSP2_DATA6 SSP1_DATA4 SSP1_DATA5 SSP1_DATA6 i.MX23 Applications Processor Reference Manual, Rev. 1 36-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Descriptions Table 36-6. 169-Pin BGA Pin Definitions by Pin Number (continued) Number Pin Name Group Type Description 1 Description 2 Description 3 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 EMI_D04 EMI_DQM0 EMI_CASN GPMI_D11 GPMI_D12 GPMI_D13 GPMI_D14 GPMI_D15 EMI_CLKN EMI_D14 EMI_D09 EMI_D08 EMI_D03 EMI_D02 EMI_DQS0 EMI_RASN EMI EMI EMI GPMI GPMI GPMI GPMI GPMI EMI EMI EMI EMI EMI EMI EMI EMI DIO EMI Data 4 DIO EMI Data Mask 0 DIO EMI Column Address Strobe# DIO NAND Data 11 DIO NAND Data 12 DIO NAND Data 13 DIO NAND Data 14 DIO NAND Data 15 DIO EMI Clock# DIO EMI Data 14 DIO EMI Data 9 DIO EMI Data 8 DIO EMI Data 3 DIO EMI Data 2 DIO EMI mDDR-DDR Data Strobe 0 (Low Byte) DIO EMI Row Address Strobe# LCD_D21 LCD_D22 LCD_D23 AUART2_RX AUART2_TX GPMI_CE3N SSP1_DATA7 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 36-17 Pin Descriptions Table 36-7. 169-Pin BGA Ball Map 1 A USB_DP 2 VSSA2 3 VAG 4 XTALI 5 XTALO 6 LINE1_INR 7 HP_VGND 8 LRADC0 9 VDD4P2 10 LRADC4 11 BATT 12 DCDC_LP 13 DCDC_GND A B VDDS USB_DM PSWITCH RTC_XTALI LINE1_INL MIC HPL HPR LRADC1 LRADC5 DCDC_BATTERY DCDC_VDDA DCDC_LN1 B C SPEAKERP VDDXTAL PWM0 RTC_XTALO I2C_SCL I2C_SDA VDDA1 VSSA1 LRADC2 VDDM VDAC1 PWM4 DCDC_VDDIO C D SPEAKERN PWM1 LCD_D00 VSSA5 VDDD1/3 VSSD1/5 ROTARYA VDDD1/3 LRADC3 SSP1_DETECT PWM3 SSP1_SCK DCDC_VDDD D E LCD_D17 LCD_D01 LCD_D16 LCD_D02 LCD_D15 GPMI_RDY3 GPMI_WRN ROTARYB VSSD1/5 SSP1_DATA3 VDDIO33_1/2/3 DEBUG VDD5V E F LCD_D03 LCD_D14 LCD_D04 LCD_D13 LCD_D05 GPMI_RDY2 GPMI_WPN GPMI_CE1N SSP1_DATA1 SSP1_DATA2 EMI_CKE EMI_A06 EMI_A09 F G LCD_D12 LCD_D06 VDDIO33_1/2/3 LCD_D11 LCD_D07 GPMI_RDY0 AUART1_CTS GPMI_CE0N SSP1_DATA0 EMI_A04 EMI_A07 EMI_A05 EMI_A08 G H LCD_D10 LCD_D08 LCD_D09 LCD_CS LCD_ENABLE GPMI_RDN AUART1_RTS AUART1_RX SSP1_CMD EMI_A11 PWM2 EMI_CE1N EMI_A12 H J LCD_VSYNC LCD_HSYNC LCD_RS LCD_WR LCD_RESET GPMI_RDY1 VSSIO_EMI1/2 AUART1_TX VSSIO_EMI1/2 EMI_CE0N EMI_WEN EMI_A10 EMI_A02 J K LCD_DOTCK GPMI_D00 GPMI_CLE GPMI_ALE GPMI_CE2N EMI_D13 EMI_D11 EMI_DQS1 EMI_D05 EMI_D00 EMI_A03 EMI_A01 EMI_A00 K L GPMI_D01 GPMI_D02 GPMI_D03 GPMI_D05 GPMI_D04 VDDIO_EMIQ EMI_D12 VDDIO_EMI1/2 EMI_D07 VDDIO_EMI1/2 EMI_D06 EMI_BA1 EMI_BA0 L M GPMI_D07 GPMI_D06 GPMI_D08 GPMI_D09 GPMI_D10 EMI_CLK EMI_D15 EMI_D10 EMI_DQM1 EMI_D01 EMI_D04 EMI_DQM0 EMI_CASN M N GPMI_D11 GPMI_D12 GPMI_D13 GPMI_D14 GPMI_D15 EMI_CLKN EMI_D14 EMI_D09 EMI_D08 EMI_D03 EMI_D02 EMI_DQS0 EMI_RASN N 1 2 3 4 5 6 7 8 9 10 11 12 13 i.MX23 Applications Processor Reference Manual, Rev. 1 36-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 37 Pin Control and GPIO This chapter describes the pin control and general-purpose input/output (GPIO) pin interface implemented on the i.MX23. It includes sections on pin multiplexing and configuration, including color-coded pin multiplexing tables (see Tables 37-1-37-3), followed by a description of the GPIO interface operation. Programmable registers are described in Section 37.4. 37.1 * Overview The i.MX23 has four banks of pins, three of which can serve as GPIOs. The last bank contains the EMI high speed pins which are not muxed with other functions due to tight timing requirements to memory and the need to skew match the timing of the pins. All digital pins have selectable output drive strengths as described in Section 37.2.2.1. All EMI pins have 1.8/2.5-V and 3.3-V selects as described in Section 37.2.2.1.1. All digital pins have weak internal keepers to minimize power loss due to undriven pins. The following pin interfaces have selectable pull up resistors: -- SSP data - 47 k -- SSP command - 10 k -- GPMI chip enable - 47 k -- GPMI ready/busy - 10 k All EMI data and DQM pins' internal keepers can be disabled to allow them to change to a high-impedance state (as required by some DRAM manufacturers). Slow transitioning pin interfaces contain internal Schmidt triggers for noise immunity. The pin control interface on the i.MX23 has the following features: * * * * * * NOTE In the context of this chapter, "digital pin" means the standard digital interface pins. This does not include the DEBUG pin. 37.2 Operation Each individual digital pin supporting GPIO operation may be dynamically programmed at any time to be in one of the following states: * * * High-impedance (for input, three-state, or open-drain applications) Low High i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-1 Pin Control and GPIO * Controlled by one to three selectable on-chip peripheral module interfaces, on a pin by pin basis, as described in Section 37.2.3. All non-EMI digital pins operate at a fixed nominal voltage of 3.3V. Whereas the EMI pins can be programmed for 1.8/2.5V operation. Selected pins have pullups that can be configured using register settings. When pullups are enabled, the pin's weak keeper devices are disabled. Additionally, the state of each pin may be read at any time (no matter how it is configured), and its drive strength may be configured as described in Section 37.2.2.1. Each GPIO pin may also be used as an interrupt input, and the interrupt trigger type may be configured to be low level-sensitive, high level-sensitive, rising edge-sensitive, or falling edge-sensitive. For programming purposes, these 120 digital interface pins are divided into four banks of up to 32 pins each. The following sections show how to use all the features of each pin. GPIO Output Enable HW_PINCTRL_DOEx OE# Drive Strength HARDWARE_FUNCTION_DOE HW_PINCTRL_DRIVEx HW_PINCTRL_MUXSELx OUTPUT GPIO Output HW_PINCTRL_DOUTx EN Pad Power 10K or 47K Integrated Pull-up (available only on certain pins). Enabling the internal pull-up disables the Gate Keeper. HW_PINCTRL_PULLx HARDWARE_FUNCTION_DO Pin Voltage Select VDDIO33 (3.3V) * Available only on EMI VDD18 (1.8V) pins. Non-EMI pins are fixed to 3.3V. * HW_PINCTRL_DRIVEx Pad Power Pad Power PAD GPIO Input HW_PINCTRL_DINx EN HARDWARE_FUNCTION_DI Gate Keeper. Consult Characteristics & Specifications chapter for pull-up and pulldown resistor values required to overdrive the gate keepers. INPUT HW_PINCTRL_MUXSELx Figure 37-1. Pad Diagram 37.2.1 Reset Configuration Out of reset, all non-EMI pins (with the exception of those required for boot) are configured as 3.3 V GPIO inputs with gate keepers enabled. i.MX23 Applications Processor Reference Manual, Rev. 1 37-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO 37.2.2 Pin Interface Multiplexing The i.MX23 is designed for cost sensitive applications. It contains a rich set of specialized hardware interfaces (mDDR, NAND flash, LCD panels, many types of insertable media, etc.), but does not have enough pins to allow use of all signals of all interfaces simultaneously. Consequently, a pin multiplexing scheme is used to allow customers to choose which specialized interfaces to enable for their application. In addition to these specialized hardware interfaces, the i.MX23 allows many digital pins to be used as GPIOs. This capability supports custom interfacing requirements, such as the ability to communicate with LEDs, digital buttons, and other devices that are not directly supported by any of the i.MX23 specialized hardware interfaces. Each pin is connected to one, two, or three specialized hardware interfaces, in addition to the GPIO function available on banks 0, 1, and 2. The description of each pin contains full details on which specialized hardware interfaces are attached to that pin. For example, the package pin named PWM0 is shared between the PWM, rotary, and debug UART hardware interfaces. Users define which of the available hardware interfaces controls each pin by writing a two-bit field for that pin into one of the HW_PINCTRL_MUXSELx registers. Tables 37-1-37-3 illustrate the pin multiplexing on the i.MX23. * * * Table 37-1 shows the color mapping used in the tables. Table 37-2 shows the multiplexing used in the 169-pin package. Table 37-3 shows the multiplexing used in both 128-pin packages. Table 37-1. Color Mapping for Pin Control Bank Tables EMI ETM GPIO GPMI I2C JTAG LCD PWM SAIF SPDIF SSP Timers and Rotary Debug UART Application UART USB i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-3 Pin Control and GPIO Table 37-2. Pin Multiplexing for 169-Pin BGA Package Bank 0 Mux Reg 0 select = 00 select = 01 select = 10 select = 11 3 1 15 3 0 2 9 14 2 8 2 7 13 2 6 2 5 12 2 4 2 3 11 2 2 2 1 10 2 0 1 9 9 1 8 1 7 8 1 6 1 5 7 1 4 1 3 6 1 2 1 1 5 1 0 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 gpmi_d 15 auart2_ tx gpmi_c e3n gpmi_d 14 auart2_ rx gpmi_d 13 lcd_d2 3 gpmi_d 12 lcd_d2 2 gpmi_d 11 lcd_d2 1 ssp1_d 7 gpmi_d 10 lcd_d2 0 ssp1_d 6 gpmi_d 9 lcd_d1 9 ssp1_d 5 gpmi_d 8 lcd_d1 8 ssp1_d 4 gpmi_d 7 lcd_d1 5 ssp2_d 7 gpmi_d 6 lcd_d1 4 ssp2_d 6 gpmi_d 5 lcd_d1 3 ssp2_d 5 gpmi_d 4 lcd_d1 2 ssp2_d 4 gpmi_d 3 gpmi_d 2 lcd_d1 0 ssp2_d 2 gpmi_d 1 gpmi_d0 lcd_d11 lcd_d9 lcd_d8 ssp2_d 3 ssp2_d 1 ssp2_d0 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Bank 0 Mux Reg 1 select = 00 select = 01 select = 10 select = 11 3 1 31 3 0 2 9 30 2 8 2 7 29 2 6 2 5 28 2 4 2 3 27 2 2 2 1 26 2 0 1 9 25 1 8 1 7 24 1 6 1 5 23 1 4 1 3 22 1 2 1 1 21 1 0 20 19 18 17 16 9 8 7 6 5 4 3 2 1 0 i2c_sd i2c_clk auart1_ tx auart1_ rx auart1_ rts auart1_ cts gpmi_r dn gpmi_w rn gpmi_w pn gpmi_r b3 gpmi_r b2 gpmi_r b1 gpmi_r b0 gpmi_c e2n gpmi_a le lcd_d1 7 gpmi_cle gpmi_c e2n auart1_ rx gpmi_r b2 auart1_ tx ssp1_d 7 ssp1_d 6 ssp1_d 5 ssp1_d 4 ssp2_s ck ssp2_c md ssp2_d et lcd_d16 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Bank 1 Mux Reg 2 select = 00 select = 01 select = 10 select = 11 3 1 15 3 0 2 9 14 2 8 2 7 13 2 6 2 5 12 2 4 2 3 11 2 2 2 1 10 2 0 1 9 9 1 8 1 7 8 1 6 1 5 7 1 4 1 3 6 1 2 1 1 5 1 0 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 lcd_d1 5 etm_da 7 saif1_d 1 lcd_d1 4 etm_da 5 saif1_d 2 lcd_d1 3 etm_da 6 saif2_d 2 lcd_d1 2 etm_da 4 saif2_d 1 lcd_d11 lcd_d1 0 etm_da 2 saif_bit clk lcd_d9 lcd_d8 lcd_d7 lcd_d6 lcd_d5 lcd_d4 lcd_d3 lcd_d2 lcd_d1 lcd_d0 etm_da 3 saif_lrcl k etm_da 1 saif1_d 0 etm_da 0 saif2_d 0 etm_da 15 etm_da 14 etm_da 13 etm_da 12 etm_da 11 etm_da 10 etm_da 9 etm_da8 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Bank 1 Mux Reg 3 select = 00 select = 01 select = 10 select = 11 3 1 31 3 0 2 9 30 2 8 2 7 29 2 6 2 5 28 2 4 2 3 27 2 2 2 1 26 2 0 1 9 25 1 8 1 7 24 1 6 1 5 23 1 4 1 3 22 1 2 1 1 21 1 0 20 19 18 17 16 9 8 7 6 5 4 3 2 1 0 pwm4 pwm3 pwm2 pwm1 pwm0 lcd_vsy nc lcd_bus y lcd_hsy nc lcd_en able lcd_dot clk gpmi_r b3 lcd_cs lcd_wr lcd_rs lcd_res et etm_tct l gpmi_c e3n lcd_d1 7 lcd_d16 etm_tcl k auart1_ rts etm_tct l auart1_ cts gpmi_r b3 timrot2 timrot1 i2c_sd i2c_clk etm_tcl k duart1_ tx duart1_ rx saif1_alt_b itclk GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO i.MX23 Applications Processor Reference Manual, Rev. 1 37-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-2. Pin Multiplexing for 169-Pin BGA Package Bank 2 Mux Reg 4 select = 00 select = 01 select = 10 select = 11 3 1 15 3 0 2 9 14 2 8 2 7 13 2 6 2 5 12 2 4 2 3 11 2 2 2 1 10 2 0 1 9 9 1 8 1 7 8 1 6 1 5 7 1 4 1 3 6 1 2 1 1 5 1 0 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 emi_a0 6 emi_a0 5 emi_a0 4 emi_a0 3 emi_a0 2 emi_a0 1 emi_a0 0 timrot2 timrot1 ssp1_s ck ssp1_d 3 ssp1_d 2 ssp1_d 1 ssp1_d 0 ssp1_d et gpmi_c e3n ssp1_cmd auart2_ cts gpmi_c e3n auart2_ rts jtag_trs t_n jtag_tm s i2c_sd i2c_clk spdif jtag_rtc k jtag_tck jtag_tdi usb_id jtag_tdo GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Bank 2 Mux Reg 5 select = 00 select = 01 select = 10 select = 11 3 1 31 3 0 2 9 30 2 8 2 7 29 2 6 2 5 28 2 4 2 3 27 2 2 2 1 26 2 0 1 9 25 1 8 1 7 24 1 6 1 5 23 1 4 1 3 22 1 2 1 1 21 1 0 20 19 18 17 16 9 8 7 6 5 4 3 2 1 0 emi_we n emi_ra sn emi_ck e gpmi_c e0n gpmi_c e1n emi_ce 1n emi_ce 0n emi_ca sn emi_ba 1 emi_ba 0 emi_a1 2 emi_a1 1 emi_a1 0 emi_a0 9 emi_a0 8 emi_a07 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Bank 3 Mux Reg 6 select = 00 select = 01 select = 10 select = 11 3 1 15 3 0 2 9 14 2 8 2 7 13 2 6 2 5 12 2 4 2 3 11 2 2 2 1 10 2 0 1 9 9 1 8 1 7 8 1 6 1 5 7 1 4 1 3 6 1 2 1 1 5 1 0 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 emi_d1 5 emi_d1 4 emi_d1 3 emi_d1 2 emi_d1 1 emi_d1 0 emi_d9 emi_d8 emi_d7 emi_d6 emi_d5 emi_d4 emi_d3 emi_d2 emi_d1 emi_d0 disable d disable d disable d disable d disable d disable d disable d disable d disable d disable d disable d disable d disable d disable d disable d disabled Bank 3 Mux Reg 7 select = 00 select = 01 select = 10 select = 11 3 1 31 3 0 2 9 30 2 8 2 7 29 2 6 2 5 28 2 4 2 3 27 2 2 2 1 26 2 0 1 9 25 1 8 1 7 24 1 6 1 5 23 1 4 1 3 22 1 2 1 1 21 1 0 20 19 18 17 16 9 8 7 6 5 4 3 2 1 0 emi_clk n emi_clk emi_dq s1 emi_dq s0 emi_dq m1 emi_dqm0 disable d disable d disable d disable d disable d disabled i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-5 Pin Control and GPIO Table 37-3. Pin Multiplexing for 128-Pin QFP Packages Bank 0 Mux Reg 0 select = 00 select = 01 select = 10 select = 11 3 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 gpmi_da ta07 gpmi_da ta06 gpmi_da ta05 gpmi_da ta04 gpmi_da ta03 gpmi_da ta02 gpmi_da ta01 gpmi_da ta00 lcd_d15 lcd_d14 lcd_d13 lcd_d12 lcd_d11 lcd_d10 lcd_d9 lcd_d8 ssp2_d7 ssp2_d6 ssp2_d5 ssp2_d4 ssp2_d3 ssp2_d2 ssp2_d1 ssp2_d0 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Bank 0 Mux Reg 1 select = 00 select = 01 select = 10 select = 11 3 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 i2c_sd i2c_clk gpmi_ rdn gpmi_ wrn gpmi_w pn gpmi_rb 1 gpmi_rb 0 gpmi_al e gpmi_cl e gpmi_c e2n auart1_ rx gpmi_rb 2 auart1_ tx ssp2_s ck ssp2_c md ssp2_de t lcd_d17 lcd_d16 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Bank 1 Mux Reg 2 select = 00 select = 01 select = 10 select = 11 3 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 lcd_d7 lcd_d6 lcd_d5 lcd_d4 lcd_d3 lcd_d2 lcd_d1 lcd_d0 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Bank 1 Mux Reg 3 select = 00 select = 01 select = 10 select = 11 3 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 pwm2 pwm1 pwm0 lcd_vs ync lcd_b usy lcd_hs ync lcd_ena ble lcd_dotcl k gpmi_rb 3 lcd_cs lcd_wr lcd_rs lcd_rese t gpmi_r b3 timrot2 timrot 1 duart 1_rx i2c_sd i2c_clk duart1 _tx gpmi_ce 3n GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO i.MX23 Applications Processor Reference Manual, Rev. 1 37-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-3. Pin Multiplexing for 128-Pin QFP Packages Bank 2 Mux Reg 4 select = 00 select = 01 select = 10 select = 11 jtag_trst _n 3 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 0 2 9 2 8 2 7 emi_ a04 2 6 2 5 2 4 2 3 2 2 2 1 emi_ a01 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 emi_a0 6 emi_a0 5 emi_a 03 emi_a 02 emi_a 00 ssp1_sc k ssp1_d3 ssp1_d2 ssp1_d1 ssp1_d0 ssp1_de t gpmi_ce 3n ssp1_c md i2c_sd i2c_clk jtag_tms jtag_rtck jtag_tck jtag_tdi usb_id jtag_tdo GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Bank 2 Mux Reg 5 select = 00 select = 01 select = 10 select = 11 3 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 emi_we n emi_ras n emi_c ke gpmi_ ce0n gpmi_ ce1n emi_c e0n emi_ca sn emi_ba1 emi_ba0 emi_a12 emi_a11 emi_a10 emi_a09 emi_a08 emi_a07 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Bank 3 Mux Reg 6 select = 00 select = 01 select = 10 select = 11 3 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 0 2 9 2 8 2 7 emi_ d13 2 6 2 5 2 4 2 3 2 2 2 1 emi_ d10 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 emi_d1 5 emi_d1 4 emi_d 12 emi_d 11 emi_d 9 emi_d 8 emi_d7 emi_d6 emi_d5 emi_d4 emi_d3 emi_d2 emi_d1 emi_d0 disable d disable d disabl ed disabl ed disabl ed disabl ed disabl ed disable d disabled disabled disabled disabled disabled disabled disabled disabled Bank 3 Mux Reg 7 select = 00 select = 01 select = 10 select = 11 3 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 emi_clkn emi_clk emi_dqs 1 emi_dqs 0 emi_dq m1 emi_dq m0 disabled disabled disabled disabled disabled disabled Readback registers are never affected by the operation of the HW_PINCTRL_MUXSELx registers and always sense the actual value on the data pin. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-7 Pin Control and GPIO For example, if a pin is programmed to be a GPIO output and then driven high, any specialized hardware interfaces that are actively monitoring that pin will read the high logic value. Conversely, if the pin mux is programmed to give a specialized hardware interface such as the EMI block control of a particular pin, the current state of that pin can be read through its GPIO read register at any time, even while active EMI cycles are in progress. Because the pin mux configuration is independent for each individual pin, many pins not required for a given active interface can be reused as GPIO pins. For example, the LCD_RESET pin can be configured and controlled as a GPIO pin, while the other LCD interface pins are controlled by the LCD block. 37.2.2.1 Pin Drive Strength Selection The drive strength for each digital pin can be programmed by setting the bit corresponding to that pin in one of the HW_PINCTRL_DRIVEx registers. All digital pins have selectable output drive strengths of 4, 8, and 12 mA, with the following exceptions: * * PWM4 has 8, 16, and 24 mA drive strengths. EMI_D[15:0], EMI_DQS[1:0], EMI_DQM[1:0], EMI_CLK/N have 4, 8, 12, and 16 mA drive strengths. Note: The HW_PINCTRL_DRIVEx registers must be configured prior to operation of the pins and cannot be changed mid-course during active operation. Drive-strength options are provided to optimize simultaneous switching output (SSO) noise. The majority of GPIO pins must be programmed in 4 mA mode. For EMI pins, the weakest mode should be used as long as timing is met. Note: It is recommended that the drive strength of GPMI_RDn and GPMI_WRn output pins be set to 8 mA. This will reduce the transition time under heavy loads. Low transition times will be important when NAND interface read and write cycle times are below 30 ns. The other GPMI pins may remain at 4 mA, since their frequency is only up to half that of GPMI_RDn and GPMI_WRn. 37.2.2.1.1 Pin Voltage Selection Each EMI pin can be programmed to operate at either 1.8/2.5 V or 3.3 V by setting the bit corresponding to that pin in one of the HW_PINCTRL_DRIVEx registers. Note: The I/O pad driver has two PMOS pullup drivers directly connected to a 1.8/2.5 V or 3.3 V power supply. Drive voltage selection for i.MX23 EMI pins is handled in the chip by switching N-well circuits. When the I/O driver is configured in 1.8/2.5 V mode, it is not 3.3 V signal-compatible and will cause a DC current flow if the input is driven by a 3.3 V signal. 37.2.2.2 Pullup/Pulldown Selection Several digital pins can be programmed to enable pullups by setting the appropriate bit in one of the HW_PINCTRL_PULLx registers. Note that enabling the pullup will also disable the internal gate keeper on that pin. i.MX23 Applications Processor Reference Manual, Rev. 1 37-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO The pullups are tied to the physical pin pad and not the function. So, for example, if the AUART1_TX pullup is enabled, that pullup will be present on the AUART1_TX pin regardless of what function (AUART1_TX, IR_TX, or SSP1_DATA7) is pin multiplexed out of that pin. The table below lists which function (not which pin name) that an internal pullup has implemented, to assist in the hardware interface operation. Table 37-4. i.MX23 Functions with Pullup Resistors FUNCTION TYPE VALUE PRESENT ON 169BGA PRESENT ON 128QFP SSP1_DATA0 SSP1_DATA1 SSP1_DATA2 SSP1_DATA3 SSP1_DATA4 SSP1_DATA5 SSP1_DATA6 SSP1_DATA7 SSP1_CMD SSP2_DATA0 SSP2_DATA1 SSP2_DATA2 SSP2_DATA3 SSP2_DATA4 SSP2_DATA5 SSP2_DATA6 SSP2_DATA7 SSP2_CMD GPMI_CE0N GPMI_CE1N GPMI_CE2N GPMI_CE3N GPMI_RDY0 GPMI_RDY1 GPMI_RDY2 GPMI_RDY3 Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup 47K 47K 47K 47K 47K 47K 47K 47K 10K 47K 47K 47K 47K 47K 47K 47K 47K 10K 47K 47K 47K 47K 10K 10K 10K 10K Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N N N N Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-9 Pin Control and GPIO 37.2.3 GPIO Interface The registers discussed in the following sections exist within each of the three GPIO banks to configure the chip's digital pins. Some pins exist in the 169-pin package only. The registers that control those pins exist but perform no useful function when in a 128-pin package. 37.2.3.1 Output Operation Programming and controlling a digital pin as a GPIO output is accomplished by programming the appropriate bits in four registers, as shown in Figure 37-2. * After setting the field in the HW_PINCTRL_MUXSELx to program for GPIO control, the HW_PINCTRL_DRIVEx register bit is set for the desired drive strength and pin voltage. Set bits in HW_PINCTRL_PULLx as required to enable pullups. The HW_PINCTRL_DOUTx register bit is then loaded with the level that will initially be driven on the pin. Finally, the HW_PINCTRL_DOEx register bit is set. Once set, the logic value the HW_PINCTRL_DOUTx bit will be driven on the pin and the value can be toggled with repeated writes. * * * i.MX23 Applications Processor Reference Manual, Rev. 1 37-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Begin Write to HW_PINCTRL_MUXSELx register bit to select pin as GPIO. Write to HW_PINCTRL_DRIVEx register bit to set current drive strength. Set bits in HW_PINCTRL_PULLx as required to enable pullups. Write to HW_PINCTRL_DOUTx register bit to set the output value to drive on the pin. Write to HW_PINCTRL_DOEx register bit to enable the data value to be driven on the pin. Re-write the HW_PINCTRL_DOUTx register bit to change the value driven on the pin. End Figure 37-2. GPIO Output Setup Flowchart 37.2.3.2 Input Operation Any (non-EMI high speed) digital pin may be used as a GPIO input by programming its HW_PINCTRL_MUXSELx field to 3 to enable GPIO mode, programming its HW_PINCTRL_DOEx field to 0 to disable output, and then reading from the HW_PINCTRL_DINx register, as shown in Figure 37-3. Note that because of clock synchronization issues, the logic levels read from the HW_PINCTRL_DINx registers are delayed from the pins by two APBX clock cycles. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-11 Pin Control and GPIO Begin Write to HW_PINCTRL_DRIVEx register bit to select desired pin voltage. Write to HW_PINCTRL_MUXSELx register bit to select pin as GPIO. Write zero to HW_PINCTRL_DOEx register bit to ensure pin is selected as an input. If applicable, set bits in HW_PINCTRL_PULLx to enable internal pull-up resistors. Read HW_PINCTRL_DINx register bit to get the value on the pin. End Figure 37-3. GPIO Input Setup Flowchart 37.2.3.3 Input Interrupt Operation Programming and controlling a digital pin as a GPIO interrupt input is accomplished by programming the appropriate bits in six registers, as shown in Figure 37-4. * After setting the HW_PINCTRL_MUXSELx register for GPIO, the HW_PINCTRL_IRQLEVELx and HW_PINCTRL_IRQPOLx registers set the interrupt trigger mode. A GPIO interrupt pin can be programmed in one of four trigger detect modes: positive edge, negative edge, positive level, and negative level triggered. i.MX23 Applications Processor Reference Manual, Rev. 1 37-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO * * * * The HW_PINCTRL_IRQSTATx register bit should then be cleared to ensure that there are no interrupts pending when enabled. Setting the HW_PINCTRL_PIN2IRQx register bit will then set up the pin to be an interrupt pin. At this point, if an interrupt event occurs on the pin, it will be sensed and recorded in the appropriate HW_PINCTRL_IRQSTATx bit. However, the interrupt will not be communicated back to the interrupt collector until the HW_PINCTRL_IRQENx register bit is enabled. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-13 Pin Control and GPIO Begin Write to HW_PINCTRL_DRIVEx register bit to select desired pin voltage. Write to HW_PINCTRL_MUXSELx register bit to select pin as GPIO. Write zero to HW_PINCTRL_DOEx register bit to ensure pin is selected as an input. If applicable, set bits in HW_PINCTRL_PULLx to enable internal pull-up resistors. Write to HW_PINCTRL_IRQLEVELx register bit to set level or edge assertion. Write to HW_PINCTRL_IRQPOLx register bit to set high or low logic assertion. Write zero to HW_PINCTRL_IRQSTATx register bit to clear interrupts. Write to HW_PINCTRL_PIN2IRQx register bit to enable as an interrupt pin. Write to HW_PINCTRL_IRQENx register bit to enable the interrupt signal back to the Interrupt collector. End Figure 37-4. GPIO Interrupt Flowchart i.MX23 Applications Processor Reference Manual, Rev. 1 37-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Figure 37-5 shows the logic diagram for the interrupt-generation circuit. SCT Clear write to GPIOx & (apb_wdata[b]== 1) sync pin GPxBb HIGH HW_PINCTRL_IRQLEVELxb HW_PINCTRL_DINxb LOW Internal Register RISE level edge 1 FALL HW_PINCTRL_PIN2IRQxb HW_PINCTRL_STATxb HW_PINCTRL_IRQPOLxb HW_PINCTRL_IRQENxb PINCTRL_IRQx to CPU HW_PINCTRL_CTRL [hw_pinctrl_ctrl_irqoutb] from other 31 bits Figure 37-5. GPIO Interrupt Generation 37.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Section 39.3.10 "Correct Way to Soft Reset a Block" on page 39-7, for additional information on using the SFTRST and CLKGATE bit fields. 37.4 Programmable Registers The following programmable registers are available for controlling the pin control and GPIO interface of the i.MX23. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-15 Pin Control and GPIO 37.4.1 PINCTRL Block Control Register Description The PINCTRL Block Control Register contains the block control bits and combined interrupt output status for each PINCTRL bank. HW_PINCTRL_CTRL HW_PINCTRL_CTRL_SET HW_PINCTRL_CTRL_CLR HW_PINCTRL_CTRL_TOG Table 37-5. HW_PINCTRL_CTRL 3 1 SFTRST 0x000 0x004 0x008 0x00C 3 0 CLKGATE 2 9 RSRVD2 2 8 2 7 PRESENT3 2 6 PRESENT2 2 5 PRESENT1 2 4 PRESENT0 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 RSRVD1 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 IRQOUT2 0 1 IRQOUT1 0 0 IRQOUT0 Table 37-6. HW_PINCTRL_CTRL Bit Field Descriptions BITS 31 SFTRST LABEL RW RESET RW 0x1 DEFINITION This bit must be set to zero to enable operation of any of the PINCTRL banks. When set to one, it forces a block-level reset. This bit must be set to zero for normal operation. When set to one, it disables the block clock. Always write zeroes to this field. GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 3 is not present in this product. 1: GPIO functionality for Bank 3 is present. GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 2 is not present in this product. 1: GPIO functionality for Bank 2 is present. GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 1 is not present in this product. 1: GPIO functionality for Bank 1 is present. GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 0 is not present in this product. 1: GPIO functionality for Bank 0 is present. Always write zeroes to this field. Read-only view of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 2. Read-only view of the interrupt collector GPIO1 signal, sourced from the combined IRQ outputs from bank 1. Read-only view of the interrupt collector GPIO0 signal, sourced from the combined IRQ outputs from bank 0. 30 CLKGATE RW 0x1 RO 0x0 RO 0x1 29:28 RSRVD2 27 PRESENT3 26 PRESENT2 RO 0x1 25 PRESENT1 RO 0x1 24 PRESENT0 RO 0x1 23:3 2 1 0 RSRVD1 IRQOUT2 IRQOUT1 IRQOUT0 RO 0x00000 RO 0x0 RO 0x0 RO 0x0 DESCRIPTION: This register contains block-wide control bits and combined bank interrupt status bits. For normal operation, write a 0x00000000 into this register. i.MX23 Applications Processor Reference Manual, Rev. 1 37-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO EXAMPLE: Empty Example. 37.4.2 PINCTRL Pin Mux Select Register 0 Description HW_PINCTRL_MUXSEL0 HW_PINCTRL_MUXSEL0_SET HW_PINCTRL_MUXSEL0_CLR HW_PINCTRL_MUXSEL0_TOG Table 37-7. HW_PINCTRL_MUXSEL0 The PINCTRL Pin Mux Select Register provides pin function selection for 16 pins in bank0. 0x100 0x104 0x108 0x10C 3 1 BANK0_PIN15 3 0 2 9 BANK0_PIN14 2 8 2 7 BANK0_PIN13 2 6 2 5 BANK0_PIN12 2 4 2 3 BANK0_PIN11 2 2 2 1 BANK0_PIN10 2 0 1 9 BANK0_PIN09 1 8 1 7 BANK0_PIN08 1 6 1 5 BANK0_PIN07 1 4 1 3 BANK0_PIN06 1 2 1 1 BANK0_PIN05 1 0 0 9 BANK0_PIN04 0 8 0 7 BANK0_PIN03 0 6 0 5 BANK0_PIN02 0 4 0 3 BANK0_PIN01 0 2 0 1 BANK0_PIN00 0 0 Table 37-8. HW_PINCTRL_MUXSEL0 Bit Field Descriptions BITS LABEL 31:30 BANK0_PIN15 RW RESET RW 0x3 DEFINITION Pin 59, GPMI_D15 pin function selection: 00= gpmi_data15; 01= auart2_tx; 10= gpmi_ce3n; 11= GPIO. Pin 58, GPMI_D14 pin function selection: 00= gpmi_data14; 01= auart2_rx; 10= reserved; 11= GPIO. Pin 57, GPMI_D13 pin function selection: 00= gpmi_data13; 01= lcd_d23; 10= reserved; 11= GPIO. Pin 56, GPMI_D12 pin function selection: 00= gpmi_data12; 01= lcd_d22; 10= reserved; 11= GPIO. Pin 55, GPMI_D11 pin function selection: 00= gpmi_data11; 01= lcd_d21; 10= ssp1_d7; 11= GPIO. 29:28 BANK0_PIN14 RW 0x3 27:26 BANK0_PIN13 RW 0x3 25:24 BANK0_PIN12 RW 0x3 23:22 BANK0_PIN11 RW 0x3 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-17 Pin Control and GPIO Table 37-8. HW_PINCTRL_MUXSEL0 Bit Field Descriptions BITS LABEL 21:20 BANK0_PIN10 RW RESET RW 0x3 DEFINITION Pin 54, GPMI_D10 pin function selection: 00= gpmi_data10; 01= lcd_d20; 10= ssp1_d6; 11= GPIO. Pin 53, GPMI_D09 pin function selection: 00= gpmi_data09; 01= lcd_d19; 10= ssp1_d5; 11= GPIO. Pin 52, GPMI_D08 pin function selection: 00= gpmi_data08; 01= lcd_d18; 10= ssp1_d4; 11= GPIO. Pin 50, GPMI_D07 pin function selection: 00= gpmi_data07; 01= lcd_d15; 10= ssp2_d7; 11= GPIO. Pin 51, GPMI_D06 pin function selection: 00= gpmi_data06; 01= lcd_d14; 10= ssp2_d6; 11= GPIO. Pin 48, GPMI_D05 pin function selection: 00= gpmi_data05; 01= lcd_d13; 10= ssp2_d5; 11= GPIO. Pin 49, GPMI_D04 pin function selection: 00= gpmi_data04; 01= lcd_d12; 10= ssp2_d4; 11= GPIO. Pin 47, GPMI_D03 pin function selection: 00= gpmi_data03; 01= lcd_d11; 10= ssp2_d3; 11= GPIO. Pin 46, GPMI_D02 pin function selection: 00= gpmi_data02; 01= lcd_d10; 10= ssp2_d2; 11= GPIO. 19:18 BANK0_PIN09 RW 0x3 17:16 BANK0_PIN08 RW 0x3 15:14 BANK0_PIN07 RW 0x3 13:12 BANK0_PIN06 RW 0x3 11:10 BANK0_PIN05 RW 0x3 9:8 BANK0_PIN04 RW 0x3 7:6 BANK0_PIN03 RW 0x3 5:4 BANK0_PIN02 RW 0x3 i.MX23 Applications Processor Reference Manual, Rev. 1 37-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-8. HW_PINCTRL_MUXSEL0 Bit Field Descriptions BITS LABEL 3:2 BANK0_PIN01 RW RESET RW 0x3 DEFINITION Pin 45, GPMI_D01 pin function selection: 00= gpmi_data01; 01= lcd_d9; 10= ssp2_d1; 11= GPIO. Pin 44, GPMI_D00 pin function selection: 00= gpmi_data00; 01= lcd_d8; 10= ssp2_d0; 11= GPIO. 1:0 BANK0_PIN00 RW 0x3 DESCRIPTION: This register allows the programmer to select which hardware interface blocks drive the 16 pins shown above. EXAMPLE: Empty Example. 37.4.3 PINCTRL Pin Mux Select Register 1 Description HW_PINCTRL_MUXSEL1 HW_PINCTRL_MUXSEL1_SET HW_PINCTRL_MUXSEL1_CLR HW_PINCTRL_MUXSEL1_TOG Table 37-9. HW_PINCTRL_MUXSEL1 The PINCTRL Pin Mux Select Register provides pin function selection for 16 pins in bank0. 0x110 0x114 0x118 0x11C 3 1 BANK0_PIN31 3 0 2 9 BANK0_PIN30 2 8 2 7 BANK0_PIN29 2 6 2 5 BANK0_PIN28 2 4 2 3 BANK0_PIN27 2 2 2 1 BANK0_PIN26 2 0 1 9 BANK0_PIN25 1 8 1 7 BANK0_PIN24 1 6 1 5 BANK0_PIN23 1 4 1 3 BANK0_PIN22 1 2 1 1 BANK0_PIN21 1 0 0 9 BANK0_PIN20 0 8 0 7 BANK0_PIN19 0 6 0 5 BANK0_PIN18 0 4 0 3 BANK0_PIN17 0 2 0 1 BANK0_PIN16 0 0 Table 37-10. HW_PINCTRL_MUXSEL1 Bit Field Descriptions BITS LABEL 31:30 BANK0_PIN31 RW RESET RW 0x3 DEFINITION Pin 4, I2C_SDA pin function selection: 00= i2c_sd; 01= gpmi_ce2n; 10= auart1_rx; 11= GPIO. Pin 2, I2C_SCL pin function selection: 00= i2c_clk; 01= gpmi_ready2; 10= auart1_tx; 11= GPIO. 29:28 BANK0_PIN30 RW 0x3 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-19 Pin Control and GPIO Table 37-10. HW_PINCTRL_MUXSEL1 Bit Field Descriptions BITS LABEL 27:26 BANK0_PIN29 RW RESET RW 0x3 DEFINITION Pin 69, AUART1_TX pin function selection: 00= auart1_tx; 01= reserved; 10= ssp1_d7; 11= GPIO. Pin 68, AUART1_RX pin function selection: 00= auart1_rx; 01= reserved; 10= ssp1_d6; 11= GPIO. Pin 67, AUART1_RTS pin function selection: 00= auart1_rts; 01= reserved; 10= ssp1_d5; 11= GPIO. Pin 66, AUART1_CTS pin function selection: 00= auart1_cts; 01= reserved; 10= ssp1_d4; 11= GPIO. Pin 60, GPMI_RDN pin function selection: 00= gpmi_rdn; 01= reserved; 10= reserved; 11= GPIO. Pin 65, GPMI_WRN pin function selection: 00= gpmi_wrn; 01= reserved; 10= ssp2_sck; 11= GPIO. Pin 64, GPMI_WPN pin function selection: 00= gpmi_wpn; 01= reserved; 10= reserved; 11= GPIO. Pin 63, GPMI_RDY3 pin function selection: 00= gpmi_ready3; 01= reserved; 10= reserved; 11= GPIO. Pin 62, GPMI_RDY2 pin function selection: 00= gpmi_ready2; 01= reserved; 10= reserved; 11= GPIO. Pin 43, GPMI_RDY1 pin function selection: 00= gpmi_ready1; 01= reserved; 10= ssp2_cmd; 11= GPIO. 25:24 BANK0_PIN28 RW 0x3 23:22 BANK0_PIN27 RW 0x3 21:20 BANK0_PIN26 RW 0x3 19:18 BANK0_PIN25 RW 0x3 17:16 BANK0_PIN24 RW 0x3 15:14 BANK0_PIN23 RW 0x3 13:12 BANK0_PIN22 RW 0x3 11:10 BANK0_PIN21 RW 0x3 9:8 BANK0_PIN20 RW 0x3 i.MX23 Applications Processor Reference Manual, Rev. 1 37-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-10. HW_PINCTRL_MUXSEL1 Bit Field Descriptions BITS LABEL 7:6 BANK0_PIN19 RW RESET RW 0x3 DEFINITION Pin 61, GPMI_RDY0 pin function selection: 00= gpmi_ready0; 01= reserved; 10= ssp2_detect; 11= GPIO. Pin 42, GPMI_CE2N pin function selection: 00= gpmi_ce2n; 01= reserved; 10= reserved; 11= GPIO. Pin 41, GPMI_ALE pin function selection: 00= gpmi_ale; 01= lcd_d17; 10= reserved; 11= GPIO. Pin 40, GPMI_CLE pin function selection: 00= gpmi_cle; 01= lcd_d16; 10= reserved; 11= GPIO. 5:4 BANK0_PIN18 RW 0x3 3:2 BANK0_PIN17 RW 0x3 1:0 BANK0_PIN16 RW 0x3 DESCRIPTION: This register allows the programmer to select which hardware interface blocks drive the 16 pins shown above. EXAMPLE: Empty Example. 37.4.4 PINCTRL Pin Mux Select Register 2 Description HW_PINCTRL_MUXSEL2 HW_PINCTRL_MUXSEL2_SET HW_PINCTRL_MUXSEL2_CLR HW_PINCTRL_MUXSEL2_TOG Table 37-11. HW_PINCTRL_MUXSEL2 The PINCTRL Pin Mux Select Register provides pin function selection for 16 pins in bank1. 0x120 0x124 0x128 0x12C 3 1 BANK1_PIN15 3 0 2 9 BANK1_PIN14 2 8 2 7 BANK1_PIN13 2 6 2 5 BANK1_PIN12 2 4 2 3 BANK1_PIN11 2 2 2 1 BANK1_PIN10 2 0 1 9 BANK1_PIN09 1 8 1 7 BANK1_PIN08 1 6 1 5 BANK1_PIN07 1 4 1 3 BANK1_PIN06 1 2 1 1 BANK1_PIN05 1 0 0 9 BANK1_PIN04 0 8 0 7 BANK1_PIN03 0 6 0 5 BANK1_PIN02 0 4 0 3 BANK1_PIN01 0 2 0 1 BANK1_PIN00 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-21 Pin Control and GPIO Table 37-12. HW_PINCTRL_MUXSEL2 Bit Field Descriptions BITS LABEL 31:30 BANK1_PIN15 RW RESET RW 0x3 DEFINITION Pin 15, LCD_D15 pin function selection: 00= lcd_d15; 01= etm_da7; 10= saif1_sdata1; 11= GPIO. Pin 17, LCD_D14 pin function selection: 00= lcd_d14; 01= etm_da6; 10= saif1_sdata2; 11= GPIO. Pin 19, LCD_D13 pin function selection: 00= lcd_d13; 01= etm_da5; 10= saif2_sdata2; 11= GPIO. Pin 22, LCD_D12 pin function selection: 00= lcd_d12; 01= etm_da4; 10= saif2_sdata1; 11= GPIO. Pin 24, LCD_D11 pin function selection: 00= lcd_d11; 01= etm_da3; 10= saif_lrclk; 11= GPIO. Pin 26, LCD_D10 pin function selection: 00= lcd_d10; 01= etm_da2; 10= saif_bitclk; 11= GPIO. Pin 28, LCD_D09 pin function selection: 00= lcd_d9; 01= etm_da1; 10= saif1_sdata0; 11= GPIO. Pin 27, LCD_D08 pin function selection: 00= lcd_d8; 01= etm_da0; 10= saif2_sdata0; 11= GPIO. Pin 25, LCD_D07 pin function selection: 00= lcd_d7; 01= etm_da15; 10= reserved; 11= GPIO. Pin 23, LCD_D06 pin function selection: 00= lcd_d6; 01= etm_da14; 10= reserved; 11= GPIO. 29:28 BANK1_PIN14 RW 0x3 27:26 BANK1_PIN13 RW 0x3 25:24 BANK1_PIN12 RW 0x3 23:22 BANK1_PIN11 RW 0x3 21:20 BANK1_PIN10 RW 0x3 19:18 BANK1_PIN09 RW 0x3 17:16 BANK1_PIN08 RW 0x3 15:14 BANK1_PIN07 RW 0x3 13:12 BANK1_PIN06 RW 0x3 i.MX23 Applications Processor Reference Manual, Rev. 1 37-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-12. HW_PINCTRL_MUXSEL2 Bit Field Descriptions BITS LABEL 11:10 BANK1_PIN05 RW RESET RW 0x3 DEFINITION Pin 21, LCD_D05 pin function selection: 00= lcd_d5; 01= etm_da13; 10= reserved; 11= GPIO. Pin 18, LCD_D04 pin function selection: 00= lcd_d4; 01= etm_da12; 10= reserved; 11= GPIO. Pin 16, LCD_D03 pin function selection: 00= lcd_d3; 01= etm_da11; 10= reserved; 11= GPIO. Pin 14, LCD_D02 pin function selection: 00= lcd_d2; 01= etm_da10; 10= reserved; 11= GPIO. Pin 12, LCD_D01 pin function selection: 00= lcd_d1; 01= etm_da9; 10= reserved; 11= GPIO. Pin 10, LCD_D00 pin function selection: 00= lcd_d0; 01= etm_da8; 10= reserved; 11= GPIO. 9:8 BANK1_PIN04 RW 0x3 7:6 BANK1_PIN03 RW 0x3 5:4 BANK1_PIN02 RW 0x3 3:2 BANK1_PIN01 RW 0x3 1:0 BANK1_PIN00 RW 0x3 DESCRIPTION: This register allows the programmer to select which hardware interface blocks drive the 16 pins shown above. EXAMPLE: Empty Example. 37.4.5 PINCTRL Pin Mux Select Register 3 Description HW_PINCTRL_MUXSEL3 HW_PINCTRL_MUXSEL3_SET HW_PINCTRL_MUXSEL3_CLR HW_PINCTRL_MUXSEL3_TOG 0x130 0x134 0x138 0x13C The PINCTRL Pin Mux Select Register provides pin function selection for 15 pins in bank1. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-23 Pin Control and GPIO Table 37-13. HW_PINCTRL_MUXSEL3 3 1 RSRVD0 3 0 2 9 BANK1_PIN30 2 8 2 7 BANK1_PIN29 2 6 2 5 BANK1_PIN28 2 4 2 3 BANK1_PIN27 2 2 2 1 BANK1_PIN26 2 0 1 9 BANK1_PIN25 1 8 1 7 BANK1_PIN24 1 6 1 5 BANK1_PIN23 1 4 1 3 BANK1_PIN22 1 2 1 1 BANK1_PIN21 1 0 0 9 BANK1_PIN20 0 8 0 7 BANK1_PIN19 0 6 0 5 BANK1_PIN18 0 4 0 3 BANK1_PIN17 0 2 0 1 BANK1_PIN16 0 0 Table 37-14. HW_PINCTRL_MUXSEL3 Bit Field Descriptions BITS LABEL 31:30 RSRVD0 29:28 BANK1_PIN30 RW RESET RO 0x0 RW 0x3 DEFINITION Always write zeroes to this field. Pin 131, PWM4 pin function selection: 00= pwm4; 01= etm_tclk; 10= auart1_rts; 11= GPIO. Pin 130, PWM3 pin function selection: 00= pwm3; 01= etm_tctl; 10= auart1_cts; 11= GPIO. Pin 129, PWM2 pin function selection: 00= pwm2; 01= gpmi_ready3; 10= reserved; 11= GPIO. Pin 3, PWM1 pin function selection: 00= pwm1; 01= timrot2; 10= duart_tx; 11= GPIO. Pin 1, PWM0 pin function selection: 00= pwm0; 01= timrot1; 10= duart_rx; 11= GPIO. Pin 35, LCD_VSYNC pin function selection: 00= lcd_vsync; 01= lcd_busy; 10= reserved; 11= GPIO. Pin 34, LCD_HSYNC pin function selection: 00= lcd_hsync; 01= i2c_sd; 10= reserved; 11= GPIO. Pin 30, LCD_ENABLE pin function selection: 00= lcd_enable; 01= i2c_clk; 10= reserved; 11= GPIO. 27:26 BANK1_PIN29 RW 0x3 25:24 BANK1_PIN28 RW 0x3 23:22 BANK1_PIN27 RW 0x3 21:20 BANK1_PIN26 RW 0x3 19:18 BANK1_PIN25 RW 0x3 17:16 BANK1_PIN24 RW 0x3 15:14 BANK1_PIN23 RW 0x3 i.MX23 Applications Processor Reference Manual, Rev. 1 37-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-14. HW_PINCTRL_MUXSEL3 Bit Field Descriptions BITS LABEL 13:12 BANK1_PIN22 RW RESET RW 0x3 DEFINITION Pin 36, LCD_DOTCK pin function selection: 00= lcd_dotck; 01= gpmi_ready3; 10= reserved; 11= GPIO. Pin 29, LCD_CS pin function selection: 00= lcd_cs; 01= reserved; 10= reserved; 11= GPIO. Pin 32, LCD_WR pin function selection: 00= lcd_wr; 01= reserved; 10= reserved; 11= GPIO. Pin 33, LCD_RS pin function selection: 00= lcd_rs; 01= etm_tclk; 10= reserved; 11= GPIO. Pin 31, LCD_RESET pin function selection: 00= lcd_reset; 01= etm_tctl; 10= gpmi_ce3n; 11= GPIO. Pin 11, LCD_D17 pin function selection: 00= lcd_d17; 01= reserved; 10= reserved; 11= GPIO. Pin 13, LCD_D16 pin function selection: 00= lcd_d16; 01= reserved; 10= saif_alt_bitclk; 11= GPIO. 11:10 BANK1_PIN21 RW 0x3 9:8 BANK1_PIN20 RW 0x3 7:6 BANK1_PIN19 RW 0x3 5:4 BANK1_PIN18 RW 0x3 3:2 BANK1_PIN17 RW 0x3 1:0 BANK1_PIN16 RW 0x3 DESCRIPTION: This register allows the programmer to select which hardware interface blocks drive the 15 pins shown above. EXAMPLE: Empty Example. 37.4.6 PINCTRL Pin Mux Select Register 4 Description HW_PINCTRL_MUXSEL4 HW_PINCTRL_MUXSEL4_SET HW_PINCTRL_MUXSEL4_CLR HW_PINCTRL_MUXSEL4_TOG 0x140 0x144 0x148 0x14C The PINCTRL Pin Mux Select Register provides pin function selection for 16 pins in bank2. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-25 Pin Control and GPIO Table 37-15. HW_PINCTRL_MUXSEL4 3 1 BANK2_PIN15 3 0 2 9 BANK2_PIN14 2 8 2 7 BANK2_PIN13 2 6 2 5 BANK2_PIN12 2 4 2 3 BANK2_PIN11 2 2 2 1 BANK2_PIN10 2 0 1 9 BANK2_PIN09 1 8 1 7 BANK2_PIN08 1 6 1 5 BANK2_PIN07 1 4 1 3 BANK2_PIN06 1 2 1 1 BANK2_PIN05 1 0 0 9 BANK2_PIN04 0 8 0 7 BANK2_PIN03 0 6 0 5 BANK2_PIN02 0 4 0 3 BANK2_PIN01 0 2 0 1 BANK2_PIN00 0 0 Table 37-16. HW_PINCTRL_MUXSEL4 Bit Field Descriptions BITS LABEL 31:30 BANK2_PIN15 RW RESET RW 0x3 DEFINITION Pin 108, EMI_A06 pin function selection: 00= emi_addr06; 01= reserved; 10= reserved; 11= GPIO. Pin 107, EMI_A05 pin function selection: 00= emi_addr05; 01= reserved; 10= reserved; 11= GPIO. Pin 109, EMI_A04 pin function selection: 00= emi_addr04; 01= reserved; 10= reserved; 11= GPIO. Pin 110, EMI_A03 pin function selection: 00= emi_addr03; 01= reserved; 10= reserved; 11= GPIO. Pin 111, EMI_A02 pin function selection: 00= emi_addr02; 01= reserved; 10= reserved; 11= GPIO. Pin 112, EMI_A01 pin function selection: 00= emi_addr01; 01= reserved; 10= reserved; 11= GPIO. Pin 113, EMI_A00 pin function selection: 00= emi_addr00; 01= reserved; 10= reserved; 11= GPIO. Pin 38, ROTARYB pin function selection: 00= timrot2; 01= auart2_cts; 10= gpmi_ce3n; 11= GPIO. 29:28 BANK2_PIN14 RW 0x3 27:26 BANK2_PIN13 RW 0x3 25:24 BANK2_PIN12 RW 0x3 23:22 BANK2_PIN11 RW 0x3 21:20 BANK2_PIN10 RW 0x3 19:18 BANK2_PIN09 RW 0x3 17:16 BANK2_PIN08 RW 0x3 i.MX23 Applications Processor Reference Manual, Rev. 1 37-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-16. HW_PINCTRL_MUXSEL4 Bit Field Descriptions BITS LABEL 15:14 BANK2_PIN07 RW RESET RW 0x3 DEFINITION Pin 37, ROTARYA pin function selection: 00= timrot1; 01= auart2_rts; 10= spdif; 11= GPIO. Pin 127, SSP1_SCK pin function selection: 00= ssp1_sck; 01= reserved; 10= alt_jtag_trst_n; 11= GPIO. Pin 125, SSP1_DATA3 pin function selection: 00= ssp1_d3; 01= reserved; 10= alt_jtag_tms; 11= GPIO. Pin 124, SSP1_DATA2 pin function selection: 00= ssp1_d2; 01= i2c_sd; 10= alt_jtag_rtck; 11= GPIO. Pin 123, SSP1_DATA1 pin function selection: 00= ssp1_d1; 01= i2c_clk; 10= alt_jtag_tck; 11= GPIO. Pin 122, SSP1_DATA0 pin function selection: 00= ssp1_d0; 01= reserved; 10= alt_jtag_tdi; 11= GPIO. Pin 126, SSP1_DETECT pin function selection: 00= ssp1_detect; 01= gpmi_ce3n; 10= usb_id; 11= GPIO. Pin 121, SSP1_CMD pin function selection: 00= ssp1_cmd; 01= reserved; 10= alt_jtag_tdo; 11= GPIO. 13:12 BANK2_PIN06 RW 0x3 11:10 BANK2_PIN05 RW 0x3 9:8 BANK2_PIN04 RW 0x3 7:6 BANK2_PIN03 RW 0x3 5:4 BANK2_PIN02 RW 0x3 3:2 BANK2_PIN01 RW 0x3 1:0 BANK2_PIN00 RW 0x3 DESCRIPTION: This register allows the programmer to select which hardware interface blocks drive the 16 pins shown above. EXAMPLE: Empty Example. 37.4.7 PINCTRL Pin Mux Select Register 5 Description The PINCTRL Pin Mux Select Register provides pin function selection for 16 pins in bank2. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-27 Pin Control and GPIO HW_PINCTRL_MUXSEL5 HW_PINCTRL_MUXSEL5_SET HW_PINCTRL_MUXSEL5_CLR HW_PINCTRL_MUXSEL5_TOG Table 37-17. HW_PINCTRL_MUXSEL5 3 1 BANK2_PIN31 0x150 0x154 0x158 0x15C 3 0 2 9 BANK2_PIN30 2 8 2 7 BANK2_PIN29 2 6 2 5 BANK2_PIN28 2 4 2 3 BANK2_PIN27 2 2 2 1 BANK2_PIN26 2 0 1 9 BANK2_PIN25 1 8 1 7 BANK2_PIN24 1 6 1 5 BANK2_PIN23 1 4 1 3 BANK2_PIN22 1 2 1 1 BANK2_PIN21 1 0 0 9 BANK2_PIN20 0 8 0 7 BANK2_PIN19 0 6 0 5 BANK2_PIN18 0 4 0 3 BANK2_PIN17 0 2 0 1 BANK2_PIN16 0 0 Table 37-18. HW_PINCTRL_MUXSEL5 Bit Field Descriptions BITS LABEL 31:30 BANK2_PIN31 RW RESET RW 0x3 DEFINITION Pin 114, EMI_WEN pin function selection: 00= emi_wen; 01= reserved; 10= reserved; 11= GPIO. Pin 98, EMI_RASN pin function selection: 00= emi_rasn; 01= reserved; 10= reserved; 11= GPIO. Pin 115, EMI_CKE pin function selection: 00= emi_cke; 01= reserved; 10= reserved; 11= GPIO. Pin 120, GPMI_CE0N pin function selection: 00= gpmi_ce0n; 01= reserved; 10= reserved; 11= GPIO. Pin 118, GPMI_CE1N pin function selection: 00= gpmi_ce1n; 01= reserved; 10= reserved; 11= GPIO. Pin 99, EMI_CE1N pin function selection: 00= emi_ce1n; 01= reserved; 10= reserved; 11= GPIO. Pin 100, EMI_CE0N pin function selection: 00= emi_ce0n; 01= reserved; 10= reserved; 11= GPIO. 29:28 BANK2_PIN30 RW 0x3 27:26 BANK2_PIN29 RW 0x3 25:24 BANK2_PIN28 RW 0x3 23:22 BANK2_PIN27 RW 0x3 21:20 BANK2_PIN26 RW 0x3 19:18 BANK2_PIN25 RW 0x3 i.MX23 Applications Processor Reference Manual, Rev. 1 37-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-18. HW_PINCTRL_MUXSEL5 Bit Field Descriptions BITS LABEL 17:16 BANK2_PIN24 RW RESET RW 0x3 DEFINITION Pin 97, EMI_CASN pin function selection: 00= emi_casn; 01= reserved; 10= reserved; 11= GPIO. Pin 117, EMI_BA1 pin function selection: 00= emi_ba1; 01= reserved; 10= reserved; 11= GPIO. Pin 116, EMI_BA0 pin function selection: 00= emi_ba0; 01= reserved; 10= reserved; 11= GPIO. Pin 101, EMI_A12 pin function selection: 00= emi_addr12; 01= reserved; 10= reserved; 11= GPIO. Pin 102, EMI_A11 pin function selection: 00= emi_addr11; 01= reserved; 10= reserved; 11= GPIO. Pin 104, EMI_A10 pin function selection: 00= emi_addr10; 01= reserved; 10= reserved; 11= GPIO. Pin 103, EMI_A09 pin function selection: 00= emi_addr09; 01= reserved; 10= reserved; 11= GPIO. Pin 106, EMI_A08 pin function selection: 00= emi_addr08; 01= reserved; 10= reserved; 11= GPIO. Pin 105, EMI_A07 pin function selection: 00= emi_addr07; 01= reserved; 10= reserved; 11= GPIO. 15:14 BANK2_PIN23 RW 0x3 13:12 BANK2_PIN22 RW 0x3 11:10 BANK2_PIN21 RW 0x3 9:8 BANK2_PIN20 RW 0x3 7:6 BANK2_PIN19 RW 0x3 5:4 BANK2_PIN18 RW 0x3 3:2 BANK2_PIN17 RW 0x3 1:0 BANK2_PIN16 RW 0x3 DESCRIPTION: This register allows the programmer to select which hardware interface blocks drive the 16 pins shown above. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-29 Pin Control and GPIO 37.4.8 PINCTRL Pin Mux Select Register 6 Description HW_PINCTRL_MUXSEL6 HW_PINCTRL_MUXSEL6_SET HW_PINCTRL_MUXSEL6_CLR HW_PINCTRL_MUXSEL6_TOG Table 37-19. HW_PINCTRL_MUXSEL6 The PINCTRL Pin Mux Select Register provides pin function selection for 16 pins in bank3. 0x160 0x164 0x168 0x16C 3 1 BANK3_PIN15 3 0 2 9 BANK3_PIN14 2 8 2 7 BANK3_PIN13 2 6 2 5 BANK3_PIN12 2 4 2 3 BANK3_PIN11 2 2 2 1 BANK3_PIN10 2 0 1 9 BANK3_PIN09 1 8 1 7 BANK3_PIN08 1 6 1 5 BANK3_PIN07 1 4 1 3 BANK3_PIN06 1 2 1 1 BANK3_PIN05 1 0 0 9 BANK3_PIN04 0 8 0 7 BANK3_PIN03 0 6 0 5 BANK3_PIN02 0 4 0 3 BANK3_PIN01 0 2 0 1 BANK3_PIN00 0 0 Table 37-20. HW_PINCTRL_MUXSEL6 Bit Field Descriptions BITS LABEL 31:30 BANK3_PIN15 RW RESET RW 0x3 DEFINITION Pin 95, EMI_D15 pin function selection: 00= emi_data15; 01= reserved; 10= reserved; 11= disabled. Pin 96, EMI_D14 pin function selection: 00= emi_data14; 01= reserved; 10= reserved; 11= disabled. Pin 94, EMI_D13 pin function selection: 00= emi_data13; 01= reserved; 10= reserved; 11= disabled. Pin 93, EMI_D12 pin function selection: 00= emi_data12; 01= reserved; 10= reserved; 11= disabled. Pin 91, EMI_D11 pin function selection: 00= emi_data11; 01= reserved; 10= reserved; 11= disabled. Pin 89, EMI_D10 pin function selection: 00= emi_data10; 01= reserved; 10= reserved; 11= disabled. 29:28 BANK3_PIN14 RW 0x3 27:26 BANK3_PIN13 RW 0x3 25:24 BANK3_PIN12 RW 0x3 23:22 BANK3_PIN11 RW 0x3 21:20 BANK3_PIN10 RW 0x3 i.MX23 Applications Processor Reference Manual, Rev. 1 37-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-20. HW_PINCTRL_MUXSEL6 Bit Field Descriptions BITS LABEL 19:18 BANK3_PIN09 RW RESET RW 0x3 DEFINITION Pin 87, EMI_D09 pin function selection: 00= emi_data09; 01= reserved; 10= reserved; 11= disabled. Pin 86, EMI_D08 pin function selection: 00= emi_data08; 01= reserved; 10= reserved; 11= disabled. Pin 85, EMI_D07 pin function selection: 00= emi_data07; 01= reserved; 10= reserved; 11= disabled. Pin 84, EMI_D06 pin function selection: 00= emi_data06; 01= reserved; 10= reserved; 11= disabled. Pin 83, EMI_D05 pin function selection: 00= emi_data05; 01= reserved; 10= reserved; 11= disabled. Pin 82, EMI_D04 pin function selection: 00= emi_data04; 01= reserved; 10= reserved; 11= disabled. Pin 79, EMI_D03 pin function selection: 00= emi_data03; 01= reserved; 10= reserved; 11= disabled. Pin 77, EMI_D02 pin function selection: 00= emi_data02; 01= reserved; 10= reserved; 11= disabled. Pin 76, EMI_D01 pin function selection: 00= emi_data01; 01= reserved; 10= reserved; 11= disabled. Pin 75, EMI_D00 pin function selection: 00= emi_data00; 01= reserved; 10= reserved; 11= disabled. 17:16 BANK3_PIN08 RW 0x3 15:14 BANK3_PIN07 RW 0x3 13:12 BANK3_PIN06 RW 0x3 11:10 BANK3_PIN05 RW 0x3 9:8 BANK3_PIN04 RW 0x3 7:6 BANK3_PIN03 RW 0x3 5:4 BANK3_PIN02 RW 0x3 3:2 BANK3_PIN01 RW 0x3 1:0 BANK3_PIN00 RW 0x3 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-31 Pin Control and GPIO DESCRIPTION: This register allows the programmer to select which hardware interface blocks drive the 16 pins shown above. EXAMPLE: Empty Example. 37.4.9 PINCTRL Pin Mux Select Register 7 Description HW_PINCTRL_MUXSEL7 HW_PINCTRL_MUXSEL7_SET HW_PINCTRL_MUXSEL7_CLR HW_PINCTRL_MUXSEL7_TOG Table 37-21. HW_PINCTRL_MUXSEL7 The PINCTRL Pin Mux Select Register provides pin function selection for 6 pins in bank3. 0x170 0x174 0x178 0x17C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 RSRVD0 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 BANK3_PIN21 1 0 0 9 BANK3_PIN20 0 8 0 7 BANK3_PIN19 0 6 0 5 BANK3_PIN18 0 4 0 3 BANK3_PIN17 0 2 0 1 BANK3_PIN16 0 0 Table 37-22. HW_PINCTRL_MUXSEL7 Bit Field Descriptions BITS LABEL 31:12 RSRVD0 11:10 BANK3_PIN21 RW RESET RO 0x0 RW 0x3 DEFINITION Always write zeroes to this field. Pin 72, EMI_CLKN pin function selection: 00= emi_clkn; 01= reserved; 10= reserved; 11= disabled. Pin 70, EMI_CLK pin function selection: 00= emi_clk; 01= reserved; 10= reserved; 11= disabled. Pin 74, EMI_DQS1 pin function selection: 00= emi_dqs1; 01= reserved; 10= reserved; 11= disabled. Pin 73, EMI_DQS0 pin function selection: 00= emi_dqs0; 01= reserved; 10= reserved; 11= disabled. 9:8 BANK3_PIN20 RW 0x3 7:6 BANK3_PIN19 RW 0x3 5:4 BANK3_PIN18 RW 0x3 i.MX23 Applications Processor Reference Manual, Rev. 1 37-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-22. HW_PINCTRL_MUXSEL7 Bit Field Descriptions BITS LABEL 3:2 BANK3_PIN17 RW RESET RW 0x3 DEFINITION Pin 92, EMI_DQM1 pin function selection: 00= emi_dqm1; 01= reserved; 10= reserved; 11= disabled. Pin 81, EMI_DQM0 pin function selection: 00= emi_dqm0; 01= reserved; 10= reserved; 11= disabled. 1:0 BANK3_PIN16 RW 0x3 DESCRIPTION: This register allows the programmer to select which hardware interface blocks drive the 6 pins shown above. EXAMPLE: Empty Example. 37.4.10 PINCTRL Drive Strength and Voltage Register 0 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 0. HW_PINCTRL_DRIVE0 HW_PINCTRL_DRIVE0_SET HW_PINCTRL_DRIVE0_CLR HW_PINCTRL_DRIVE0_TOG Table 37-23. HW_PINCTRL_DRIVE0 3 1 3 0 2 9 BANK0_PIN07_MA 0x200 0x204 0x208 0x20C 2 8 2 7 2 6 2 5 BANK0_PIN06_MA 2 4 2 3 2 2 2 1 BANK0_PIN05_MA 2 0 1 9 1 8 1 7 BANK0_PIN04_MA 1 6 1 5 1 4 1 3 BANK0_PIN03_MA 1 2 1 1 1 0 0 9 BANK0_PIN02_MA 0 8 0 7 0 6 0 5 BANK0_PIN01_MA 0 4 0 3 0 2 0 1 BANK0_PIN00_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-24. HW_PINCTRL_DRIVE0 Bit Field Descriptions BITS LABEL 31:30 RSRVD7 29:28 BANK0_PIN07_MA RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Pin 50, GPMI_D07 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. 27:26 RSRVD6 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD0 37-33 Pin Control and GPIO Table 37-24. HW_PINCTRL_DRIVE0 Bit Field Descriptions BITS LABEL 25:24 BANK0_PIN06_MA RW RESET RW 0x0 DEFINITION Pin 51, GPMI_D06 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 48, GPMI_D05 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 49, GPMI_D04 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 47, GPMI_D03 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 46, GPMI_D02 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 45, GPMI_D01 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 44, GPMI_D00 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. 23:22 RSRVD5 21:20 BANK0_PIN05_MA RO 0x0 RW 0x0 19:18 RSRVD4 17:16 BANK0_PIN04_MA RO 0x0 RW 0x0 15:14 RSRVD3 13:12 BANK0_PIN03_MA RO 0x0 RW 0x0 11:10 RSRVD2 9:8 BANK0_PIN02_MA RO 0x0 RW 0x0 7:6 5:4 RSRVD1 BANK0_PIN01_MA RO 0x0 RW 0x0 3:2 1:0 RSRVD0 BANK0_PIN00_MA RO 0x0 RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 37-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO 37.4.11 PINCTRL Drive Strength and Voltage Register 1 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 0. HW_PINCTRL_DRIVE1 HW_PINCTRL_DRIVE1_SET HW_PINCTRL_DRIVE1_CLR HW_PINCTRL_DRIVE1_TOG Table 37-25. HW_PINCTRL_DRIVE1 3 1 3 0 2 9 BANK0_PIN15_MA 0x210 0x214 0x218 0x21C 2 8 2 7 2 6 2 5 BANK0_PIN14_MA 2 4 2 3 2 2 2 1 BANK0_PIN13_MA 2 0 1 9 1 8 1 7 BANK0_PIN12_MA 1 6 1 5 1 4 1 3 BANK0_PIN11_MA 1 2 1 1 1 0 0 9 BANK0_PIN10_MA 0 8 0 7 0 6 0 5 BANK0_PIN09_MA 0 4 0 3 0 2 0 1 BANK0_PIN08_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-26. HW_PINCTRL_DRIVE1 Bit Field Descriptions BITS LABEL 31:30 RSRVD7 29:28 BANK0_PIN15_MA RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Pin 59, GPMI_D15 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 58, GPMI_D14 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 57, GPMI_D13 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 56, GPMI_D12 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 55, GPMI_D11 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. 27:26 RSRVD6 25:24 BANK0_PIN14_MA RO 0x0 RW 0x0 23:22 RSRVD5 21:20 BANK0_PIN13_MA RO 0x0 RW 0x0 19:18 RSRVD4 17:16 BANK0_PIN12_MA RO 0x0 RW 0x0 15:14 RSRVD3 13:12 BANK0_PIN11_MA RO 0x0 RW 0x0 11:10 RSRVD2 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD0 37-35 Pin Control and GPIO Table 37-26. HW_PINCTRL_DRIVE1 Bit Field Descriptions BITS LABEL 9:8 BANK0_PIN10_MA RW RESET RW 0x0 DEFINITION Pin 54, GPMI_D10 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 53, GPMI_D09 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 52, GPMI_D08 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. 7:6 5:4 RSRVD1 BANK0_PIN09_MA RO 0x0 RW 0x0 3:2 1:0 RSRVD0 BANK0_PIN08_MA RO 0x0 RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. 37.4.12 PINCTRL Drive Strength and Voltage Register 2 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 0. HW_PINCTRL_DRIVE2 HW_PINCTRL_DRIVE2_SET HW_PINCTRL_DRIVE2_CLR HW_PINCTRL_DRIVE2_TOG Table 37-27. HW_PINCTRL_DRIVE2 3 1 3 0 2 9 BANK0_PIN23_MA 0x220 0x224 0x228 0x22C 2 8 2 7 2 6 2 5 BANK0_PIN22_MA 2 4 2 3 2 2 2 1 BANK0_PIN21_MA 2 0 1 9 1 8 1 7 BANK0_PIN20_MA 1 6 1 5 1 4 1 3 BANK0_PIN19_MA 1 2 1 1 1 0 0 9 BANK0_PIN18_MA 0 8 0 7 0 6 0 5 BANK0_PIN17_MA 0 4 0 3 0 2 0 1 BANK0_PIN16_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 i.MX23 Applications Processor Reference Manual, Rev. 1 37-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD0 Pin Control and GPIO Table 37-28. HW_PINCTRL_DRIVE2 Bit Field Descriptions BITS LABEL 31:30 RSRVD7 29:28 BANK0_PIN23_MA RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Pin 64, GPMI_WPN pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 63, GPMI_RDY3 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 62, GPMI_RDY2 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 43, GPMI_RDY1 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 61, GPMI_RDY0 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 42, GPMI_CE2N pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 41, GPMI_ALE pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 40, GPMI_CLE pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. 27:26 RSRVD6 25:24 BANK0_PIN22_MA RO 0x0 RW 0x0 23:22 RSRVD5 21:20 BANK0_PIN21_MA RO 0x0 RW 0x0 19:18 RSRVD4 17:16 BANK0_PIN20_MA RO 0x0 RW 0x0 15:14 RSRVD3 13:12 BANK0_PIN19_MA RO 0x0 RW 0x0 11:10 RSRVD2 9:8 BANK0_PIN18_MA RO 0x0 RW 0x0 7:6 5:4 RSRVD1 BANK0_PIN17_MA RO 0x0 RW 0x0 3:2 1:0 RSRVD0 BANK0_PIN16_MA RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-37 Pin Control and GPIO DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. 37.4.13 PINCTRL Drive Strength and Voltage Register 3 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 0. HW_PINCTRL_DRIVE3 HW_PINCTRL_DRIVE3_SET HW_PINCTRL_DRIVE3_CLR HW_PINCTRL_DRIVE3_TOG Table 37-29. HW_PINCTRL_DRIVE3 3 1 3 0 2 9 BANK0_PIN31_MA 0x230 0x234 0x238 0x23C 2 8 2 7 2 6 2 5 BANK0_PIN30_MA 2 4 2 3 2 2 2 1 BANK0_PIN29_MA 2 0 1 9 1 8 1 7 BANK0_PIN28_MA 1 6 1 5 1 4 1 3 BANK0_PIN27_MA 1 2 1 1 1 0 0 9 BANK0_PIN26_MA 0 8 0 7 0 6 0 5 BANK0_PIN25_MA 0 4 0 3 0 2 0 1 BANK0_PIN24_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-30. HW_PINCTRL_DRIVE3 Bit Field Descriptions BITS LABEL 31:30 RSRVD7 29:28 BANK0_PIN31_MA RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Pin 4, I2C_SDA pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 2, I2C_SCL pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 69, AUART1_TX pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. 27:26 RSRVD6 25:24 BANK0_PIN30_MA RO 0x0 RW 0x0 23:22 RSRVD5 21:20 BANK0_PIN29_MA RO 0x0 RW 0x0 19:18 RSRVD4 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 37-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD0 Pin Control and GPIO Table 37-30. HW_PINCTRL_DRIVE3 Bit Field Descriptions BITS LABEL 17:16 BANK0_PIN28_MA RW RESET RW 0x0 DEFINITION Pin 68, AUART1_RX pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 67, AUART1_RTS pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 66, AUART1_CTS pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 60, GPMI_RDN pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 65, GPMI_WRN pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. 15:14 RSRVD3 13:12 BANK0_PIN27_MA RO 0x0 RW 0x0 11:10 RSRVD2 9:8 BANK0_PIN26_MA RO 0x0 RW 0x0 7:6 5:4 RSRVD1 BANK0_PIN25_MA RO 0x0 RW 0x0 3:2 1:0 RSRVD0 BANK0_PIN24_MA RO 0x0 RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. 37.4.14 PINCTRL Drive Strength and Voltage Register 4 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 1. HW_PINCTRL_DRIVE4 HW_PINCTRL_DRIVE4_SET HW_PINCTRL_DRIVE4_CLR HW_PINCTRL_DRIVE4_TOG 0x240 0x244 0x248 0x24C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-39 Pin Control and GPIO Table 37-31. HW_PINCTRL_DRIVE4 3 1 3 0 2 9 BANK1_PIN07_MA 2 8 2 7 2 6 2 5 BANK1_PIN06_MA 2 4 2 3 2 2 2 1 BANK1_PIN05_MA 2 0 1 9 1 8 1 7 BANK1_PIN04_MA 1 6 1 5 1 4 1 3 BANK1_PIN03_MA 1 2 1 1 1 0 0 9 BANK1_PIN02_MA 0 8 0 7 0 6 0 5 BANK1_PIN01_MA 0 4 0 3 0 2 0 1 BANK1_PIN00_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-32. HW_PINCTRL_DRIVE4 Bit Field Descriptions BITS LABEL 31:30 RSRVD7 29:28 BANK1_PIN07_MA RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Pin 25, LCD_D07 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 23, LCD_D06 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 21, LCD_D05 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 18, LCD_D04 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 16, LCD_D03 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 14, LCD_D02 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. 27:26 RSRVD6 25:24 BANK1_PIN06_MA RO 0x0 RW 0x0 23:22 RSRVD5 21:20 BANK1_PIN05_MA RO 0x0 RW 0x0 19:18 RSRVD4 17:16 BANK1_PIN04_MA RO 0x0 RW 0x0 15:14 RSRVD3 13:12 BANK1_PIN03_MA RO 0x0 RW 0x0 11:10 RSRVD2 9:8 BANK1_PIN02_MA RO 0x0 RW 0x0 7:6 RSRVD1 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 37-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD0 Pin Control and GPIO Table 37-32. HW_PINCTRL_DRIVE4 Bit Field Descriptions BITS LABEL 5:4 BANK1_PIN01_MA RW RESET RW 0x0 DEFINITION Pin 12, LCD_D01 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 10, LCD_D00 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. 3:2 1:0 RSRVD0 BANK1_PIN00_MA RO 0x0 RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. 37.4.15 PINCTRL Drive Strength and Voltage Register 5 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 1. HW_PINCTRL_DRIVE5 HW_PINCTRL_DRIVE5_SET HW_PINCTRL_DRIVE5_CLR HW_PINCTRL_DRIVE5_TOG Table 37-33. HW_PINCTRL_DRIVE5 3 1 3 0 2 9 BANK1_PIN15_MA 0x250 0x254 0x258 0x25C 2 8 2 7 2 6 2 5 BANK1_PIN14_MA 2 4 2 3 2 2 2 1 BANK1_PIN13_MA 2 0 1 9 1 8 1 7 BANK1_PIN12_MA 1 6 1 5 1 4 1 3 BANK1_PIN11_MA 1 2 1 1 1 0 0 9 BANK1_PIN10_MA 0 8 0 7 0 6 0 5 BANK1_PIN09_MA 0 4 0 3 0 2 0 1 BANK1_PIN08_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-34. HW_PINCTRL_DRIVE5 Bit Field Descriptions BITS LABEL 31:30 RSRVD7 29:28 BANK1_PIN15_MA RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Pin 15, LCD_D15 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. 27:26 RSRVD6 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD0 37-41 Pin Control and GPIO Table 37-34. HW_PINCTRL_DRIVE5 Bit Field Descriptions BITS LABEL 25:24 BANK1_PIN14_MA RW RESET RW 0x0 DEFINITION Pin 17, LCD_D14 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 19, LCD_D13 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 22, LCD_D12 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 24, LCD_D11 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 26, LCD_D10 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 28, LCD_D09 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 27, LCD_D08 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. 23:22 RSRVD5 21:20 BANK1_PIN13_MA RO 0x0 RW 0x0 19:18 RSRVD4 17:16 BANK1_PIN12_MA RO 0x0 RW 0x0 15:14 RSRVD3 13:12 BANK1_PIN11_MA RO 0x0 RW 0x0 11:10 RSRVD2 9:8 BANK1_PIN10_MA RO 0x0 RW 0x0 7:6 5:4 RSRVD1 BANK1_PIN09_MA RO 0x0 RW 0x0 3:2 1:0 RSRVD0 BANK1_PIN08_MA RO 0x0 RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 37-42 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO 37.4.16 PINCTRL Drive Strength and Voltage Register 6 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 1. HW_PINCTRL_DRIVE6 HW_PINCTRL_DRIVE6_SET HW_PINCTRL_DRIVE6_CLR HW_PINCTRL_DRIVE6_TOG Table 37-35. HW_PINCTRL_DRIVE6 3 1 3 0 2 9 BANK1_PIN23_MA 0x260 0x264 0x268 0x26C 2 8 2 7 2 6 2 5 BANK1_PIN22_MA 2 4 2 3 2 2 2 1 BANK1_PIN21_MA 2 0 1 9 1 8 1 7 BANK1_PIN20_MA 1 6 1 5 1 4 1 3 BANK1_PIN19_MA 1 2 1 1 1 0 0 9 BANK1_PIN18_MA 0 8 0 7 0 6 0 5 BANK1_PIN17_MA 0 4 0 3 0 2 0 1 BANK1_PIN16_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-36. HW_PINCTRL_DRIVE6 Bit Field Descriptions BITS LABEL 31:30 RSRVD7 29:28 BANK1_PIN23_MA RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Pin 30, LCD_ENABLE pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 36, LCD_DOTCK pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 29, LCD_CS pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 32, LCD_WR pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. 27:26 RSRVD6 25:24 BANK1_PIN22_MA RO 0x0 RW 0x0 23:22 RSRVD5 21:20 BANK1_PIN21_MA RO 0x0 RW 0x0 19:18 RSRVD4 17:16 BANK1_PIN20_MA RO 0x0 RW 0x0 15:14 RSRVD3 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD0 37-43 Pin Control and GPIO Table 37-36. HW_PINCTRL_DRIVE6 Bit Field Descriptions BITS LABEL 13:12 BANK1_PIN19_MA RW RESET RW 0x0 DEFINITION Pin 33, LCD_RS pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 31, LCD_RESET pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 11, LCD_D17 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 13, LCD_D16 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. 11:10 RSRVD2 9:8 BANK1_PIN18_MA RO 0x0 RW 0x0 7:6 5:4 RSRVD1 BANK1_PIN17_MA RO 0x0 RW 0x0 3:2 1:0 RSRVD0 BANK1_PIN16_MA RO 0x0 RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. 37.4.17 PINCTRL Drive Strength and Voltage Register 7 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 7 pins of bank 1. HW_PINCTRL_DRIVE7 HW_PINCTRL_DRIVE7_SET HW_PINCTRL_DRIVE7_CLR HW_PINCTRL_DRIVE7_TOG 0x270 0x274 0x278 0x27C i.MX23 Applications Processor Reference Manual, Rev. 1 37-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-37. HW_PINCTRL_DRIVE7 3 1 3 0 2 9 2 8 2 7 2 6 2 5 BANK1_PIN30_MA 2 4 2 3 2 2 2 1 BANK1_PIN29_MA 2 0 1 9 1 8 1 7 BANK1_PIN28_MA 1 6 1 5 1 4 1 3 BANK1_PIN27_MA 1 2 1 1 1 0 0 9 BANK1_PIN26_MA 0 8 0 7 0 6 0 5 BANK1_PIN25_MA 0 4 0 3 0 2 0 1 BANK1_PIN24_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-38. HW_PINCTRL_DRIVE7 Bit Field Descriptions BITS LABEL 31:28 RSRVD7 27:26 RSRVD6 25:24 BANK1_PIN30_MA RW RESET RO 0x0 RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Always write zeroes to this field. Pin 131, PWM4 pin output drive strength selection: 00= 8 mA; 01= 16 mA; 10= 24 mA; 11= reserved. Always write zeroes to this field. Pin 130, PWM3 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 129, PWM2 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 3, PWM1 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 1, PWM0 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 35, LCD_VSYNC pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. 23:22 RSRVD5 21:20 BANK1_PIN29_MA RO 0x0 RW 0x0 19:18 RSRVD4 17:16 BANK1_PIN28_MA RO 0x0 RW 0x0 15:14 RSRVD3 13:12 BANK1_PIN27_MA RO 0x0 RW 0x0 11:10 RSRVD2 9:8 BANK1_PIN26_MA RO 0x0 RW 0x0 7:6 5:4 RSRVD1 BANK1_PIN25_MA RO 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice RSRVD0 37-45 Pin Control and GPIO Table 37-38. HW_PINCTRL_DRIVE7 Bit Field Descriptions BITS LABEL 3:2 RSRVD0 1:0 BANK1_PIN24_MA RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Pin 34, LCD_HSYNC pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. 37.4.18 PINCTRL Drive Strength and Voltage Register 8 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 2. HW_PINCTRL_DRIVE8 HW_PINCTRL_DRIVE8_SET HW_PINCTRL_DRIVE8_CLR HW_PINCTRL_DRIVE8_TOG Table 37-39. HW_PINCTRL_DRIVE8 3 1 3 0 2 9 BANK2_PIN07_MA 0x280 0x284 0x288 0x28C 2 8 2 7 2 6 2 5 BANK2_PIN06_MA 2 4 2 3 2 2 2 1 BANK2_PIN05_MA 2 0 1 9 1 8 1 7 BANK2_PIN04_MA 1 6 1 5 1 4 1 3 BANK2_PIN03_MA 1 2 1 1 1 0 0 9 BANK2_PIN02_MA 0 8 0 7 0 6 0 5 BANK2_PIN01_MA 0 4 0 3 0 2 0 1 BANK2_PIN00_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-40. HW_PINCTRL_DRIVE8 Bit Field Descriptions BITS LABEL 31:30 RSRVD7 29:28 BANK2_PIN07_MA RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Pin 37, ROTARYA pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. 27:26 RSRVD6 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 37-46 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD0 Pin Control and GPIO Table 37-40. HW_PINCTRL_DRIVE8 Bit Field Descriptions BITS LABEL 25:24 BANK2_PIN06_MA RW RESET RW 0x0 DEFINITION Pin 127, SSP1_SCK pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 125, SSP1_DATA3 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 124, SSP1_DATA2 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 123, SSP1_DATA1 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 122, SSP1_DATA0 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 126, SSP1_DETECT pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 121, SSP1_CMD pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. 23:22 RSRVD5 21:20 BANK2_PIN05_MA RO 0x0 RW 0x0 19:18 RSRVD4 17:16 BANK2_PIN04_MA RO 0x0 RW 0x0 15:14 RSRVD3 13:12 BANK2_PIN03_MA RO 0x0 RW 0x0 11:10 RSRVD2 9:8 BANK2_PIN02_MA RO 0x0 RW 0x0 7:6 5:4 RSRVD1 BANK2_PIN01_MA RO 0x0 RW 0x0 3:2 1:0 RSRVD0 BANK2_PIN00_MA RO 0x0 RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-47 Pin Control and GPIO EXAMPLE: Empty Example. 37.4.19 PINCTRL Drive Strength and Voltage Register 9 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 2. HW_PINCTRL_DRIVE9 HW_PINCTRL_DRIVE9_SET HW_PINCTRL_DRIVE9_CLR HW_PINCTRL_DRIVE9_TOG Table 37-41. HW_PINCTRL_DRIVE9 3 1 3 0 BANK2_PIN15_V 0x290 0x294 0x298 0x29C 2 9 BANK2_PIN15_MA 2 8 2 7 2 6 BANK2_PIN14_V 2 5 BANK2_PIN14_MA 2 4 2 3 2 2 BANK2_PIN13_V 2 1 BANK2_PIN13_MA 2 0 1 9 1 8 BANK2_PIN12_V 1 7 BANK2_PIN12_MA 1 6 1 5 1 4 BANK2_PIN11_V 1 3 BANK2_PIN11_MA 1 2 1 1 1 0 BANK2_PIN10_V 0 9 BANK2_PIN10_MA 0 8 0 7 0 6 BANK2_PIN09_V 0 5 BANK2_PIN09_MA 0 4 0 3 0 2 0 1 BANK2_PIN08_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-42. HW_PINCTRL_DRIVE9 Bit Field Descriptions BITS LABEL 31 RSRVD7 30 BANK2_PIN15_V RW RESET RO 0x0 RW 0x1 DEFINITION Always write zeroes to this field. Pin 108, EMI_A06 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 108, EMI_A06 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 107, EMI_A05 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 107, EMI_A05 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 109, EMI_A04 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 109, EMI_A04 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. 29:28 BANK2_PIN15_MA RW 0x0 27 26 RSRVD6 BANK2_PIN14_V RO 0x0 RW 0x1 25:24 BANK2_PIN14_MA RW 0x0 23 22 RSRVD5 BANK2_PIN13_V RO 0x0 RW 0x1 21:20 BANK2_PIN13_MA RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 37-48 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD0 Pin Control and GPIO Table 37-42. HW_PINCTRL_DRIVE9 Bit Field Descriptions BITS LABEL 19 RSRVD4 18 BANK2_PIN12_V RW RESET RO 0x0 RW 0x1 DEFINITION Always write zeroes to this field. Pin 110, EMI_A03 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 110, EMI_A03 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 111, EMI_A02 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 111, EMI_A02 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 112, EMI_A01 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 112, EMI_A01 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 113, EMI_A00 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 113, EMI_A00 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 38, ROTARYB pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. 17:16 BANK2_PIN12_MA RW 0x0 15 14 RSRVD3 BANK2_PIN11_V RO 0x0 RW 0x1 13:12 BANK2_PIN11_MA RW 0x0 11 10 RSRVD2 BANK2_PIN10_V RO 0x0 RW 0x1 9:8 BANK2_PIN10_MA RW 0x0 7 6 RSRVD1 BANK2_PIN09_V RO 0x0 RW 0x1 5:4 BANK2_PIN09_MA RW 0x0 3:2 1:0 RSRVD0 BANK2_PIN08_MA RO 0x0 RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-49 Pin Control and GPIO 37.4.20 PINCTRL Drive Strength and Voltage Register 10 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 2. HW_PINCTRL_DRIVE10 HW_PINCTRL_DRIVE10_SET HW_PINCTRL_DRIVE10_CLR HW_PINCTRL_DRIVE10_TOG Table 37-43. HW_PINCTRL_DRIVE10 3 1 3 0 BANK2_PIN23_V 0x2a0 0x2a4 0x2a8 0x2aC 2 9 BANK2_PIN23_MA 2 8 2 7 2 6 BANK2_PIN22_V 2 5 BANK2_PIN22_MA 2 4 2 3 2 2 BANK2_PIN21_V 2 1 BANK2_PIN21_MA 2 0 1 9 1 8 BANK2_PIN20_V 1 7 BANK2_PIN20_MA 1 6 1 5 1 4 BANK2_PIN19_V 1 3 BANK2_PIN19_MA 1 2 1 1 1 0 BANK2_PIN18_V 0 9 BANK2_PIN18_MA 0 8 0 7 0 6 BANK2_PIN17_V 0 5 BANK2_PIN17_MA 0 4 0 3 0 2 BANK2_PIN16_V 0 1 BANK2_PIN16_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-44. HW_PINCTRL_DRIVE10 Bit Field Descriptions BITS LABEL 31 RSRVD7 30 BANK2_PIN23_V RW RESET RO 0x0 RW 0x1 DEFINITION Always write zeroes to this field. Pin 117, EMI_BA1 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 117, EMI_BA1 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 116, EMI_BA0 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 116, EMI_BA0 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 101, EMI_A12 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 101, EMI_A12 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 102, EMI_A11 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. 29:28 BANK2_PIN23_MA RW 0x0 27 26 RSRVD6 BANK2_PIN22_V RO 0x0 RW 0x1 25:24 BANK2_PIN22_MA RW 0x0 23 22 RSRVD5 BANK2_PIN21_V RO 0x0 RW 0x1 21:20 BANK2_PIN21_MA RW 0x0 19 18 RSRVD4 BANK2_PIN20_V RO 0x0 RW 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 37-50 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD0 Pin Control and GPIO Table 37-44. HW_PINCTRL_DRIVE10 Bit Field Descriptions BITS LABEL 17:16 BANK2_PIN20_MA RW RESET RW 0x0 DEFINITION Pin 102, EMI_A11 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 104, EMI_A10 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 104, EMI_A10 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 103, EMI_A09 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 103, EMI_A09 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 106, EMI_A08 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 106, EMI_A08 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 105, EMI_A07 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 105, EMI_A07 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. 15 14 RSRVD3 BANK2_PIN19_V RO 0x0 RW 0x1 13:12 BANK2_PIN19_MA RW 0x0 11 10 RSRVD2 BANK2_PIN18_V RO 0x0 RW 0x1 9:8 BANK2_PIN18_MA RW 0x0 7 6 RSRVD1 BANK2_PIN17_V RO 0x0 RW 0x1 5:4 BANK2_PIN17_MA RW 0x0 3 2 RSRVD0 BANK2_PIN16_V RO 0x0 RW 0x1 1:0 BANK2_PIN16_MA RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-51 Pin Control and GPIO 37.4.21 PINCTRL Drive Strength and Voltage Register 11 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 2. HW_PINCTRL_DRIVE11 HW_PINCTRL_DRIVE11_SET HW_PINCTRL_DRIVE11_CLR HW_PINCTRL_DRIVE11_TOG Table 37-45. HW_PINCTRL_DRIVE11 3 1 3 0 BANK2_PIN31_V 0x2b0 0x2b4 0x2b8 0x2bC 2 9 BANK2_PIN31_MA 2 8 2 7 2 6 BANK2_PIN30_V 2 5 BANK2_PIN30_MA 2 4 2 3 2 2 BANK2_PIN29_V 2 1 BANK2_PIN29_MA 2 0 1 9 1 8 1 7 BANK2_PIN28_MA 1 6 1 5 1 4 1 3 BANK2_PIN27_MA 1 2 1 1 1 0 BANK2_PIN26_V 0 9 BANK2_PIN26_MA 0 8 0 7 0 6 BANK2_PIN25_V 0 5 BANK2_PIN25_MA 0 4 0 3 0 2 BANK2_PIN24_V 0 1 BANK2_PIN24_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-46. HW_PINCTRL_DRIVE11 Bit Field Descriptions BITS LABEL 31 RSRVD7 30 BANK2_PIN31_V RW RESET RO 0x0 RW 0x1 DEFINITION Always write zeroes to this field. Pin 114, EMI_WEN pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 114, EMI_WEN pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 98, EMI_RASN pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 98, EMI_RASN pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 115, EMI_CKE pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 115, EMI_CKE pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. 29:28 BANK2_PIN31_MA RW 0x0 27 26 RSRVD6 BANK2_PIN30_V RO 0x0 RW 0x1 25:24 BANK2_PIN30_MA RW 0x0 23 22 RSRVD5 BANK2_PIN29_V RO 0x0 RW 0x1 21:20 BANK2_PIN29_MA RW 0x0 19:18 RSRVD4 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 37-52 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD0 Pin Control and GPIO Table 37-46. HW_PINCTRL_DRIVE11 Bit Field Descriptions BITS LABEL 17:16 BANK2_PIN28_MA RW RESET RW 0x0 DEFINITION Pin 120, GPMI_CE0N pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 118, GPMI_CE1N pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= reserved. Always write zeroes to this field. Pin 99, EMI_CE1N pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 99, EMI_CE1N pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 100, EMI_CE0N pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 100, EMI_CE0N pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 97, EMI_CASN pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 97, EMI_CASN pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. 15:14 RSRVD3 13:12 BANK2_PIN27_MA RO 0x0 RW 0x0 11 10 RSRVD2 BANK2_PIN26_V RO 0x0 RW 0x1 9:8 BANK2_PIN26_MA RW 0x0 7 6 RSRVD1 BANK2_PIN25_V RO 0x0 RW 0x1 5:4 BANK2_PIN25_MA RW 0x0 3 2 RSRVD0 BANK2_PIN24_V RO 0x0 RW 0x1 1:0 BANK2_PIN24_MA RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-53 Pin Control and GPIO 37.4.22 PINCTRL Drive Strength and Voltage Register 12 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 3. HW_PINCTRL_DRIVE12 HW_PINCTRL_DRIVE12_SET HW_PINCTRL_DRIVE12_CLR HW_PINCTRL_DRIVE12_TOG Table 37-47. HW_PINCTRL_DRIVE12 3 1 3 0 BANK3_PIN07_V 0x2c0 0x2c4 0x2c8 0x2cC 2 9 BANK3_PIN07_MA 2 8 2 7 2 6 BANK3_PIN06_V 2 5 BANK3_PIN06_MA 2 4 2 3 2 2 BANK3_PIN05_V 2 1 BANK3_PIN05_MA 2 0 1 9 1 8 BANK3_PIN04_V 1 7 BANK3_PIN04_MA 1 6 1 5 1 4 BANK3_PIN03_V 1 3 BANK3_PIN03_MA 1 2 1 1 1 0 BANK3_PIN02_V 0 9 BANK3_PIN02_MA 0 8 0 7 0 6 BANK3_PIN01_V 0 5 BANK3_PIN01_MA 0 4 0 3 0 2 BANK3_PIN00_V 0 1 BANK3_PIN00_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-48. HW_PINCTRL_DRIVE12 Bit Field Descriptions BITS LABEL 31 RSRVD7 30 BANK3_PIN07_V RW RESET RO 0x0 RW 0x1 DEFINITION Always write zeroes to this field. Pin 85, EMI_D07 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 85, EMI_D07 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 84, EMI_D06 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 84, EMI_D06 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 83, EMI_D05 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 83, EMI_D05 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 82, EMI_D04 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. 29:28 BANK3_PIN07_MA RW 0x0 27 26 RSRVD6 BANK3_PIN06_V RO 0x0 RW 0x1 25:24 BANK3_PIN06_MA RW 0x0 23 22 RSRVD5 BANK3_PIN05_V RO 0x0 RW 0x1 21:20 BANK3_PIN05_MA RW 0x0 19 18 RSRVD4 BANK3_PIN04_V RO 0x0 RW 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 37-54 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD0 Pin Control and GPIO Table 37-48. HW_PINCTRL_DRIVE12 Bit Field Descriptions BITS LABEL 17:16 BANK3_PIN04_MA RW RESET RW 0x0 DEFINITION Pin 82, EMI_D04 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 79, EMI_D03 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 79, EMI_D03 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 77, EMI_D02 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 77, EMI_D02 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 76, EMI_D01 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 76, EMI_D01 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 75, EMI_D00 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 75, EMI_D00 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. 15 14 RSRVD3 BANK3_PIN03_V RO 0x0 RW 0x1 13:12 BANK3_PIN03_MA RW 0x0 11 10 RSRVD2 BANK3_PIN02_V RO 0x0 RW 0x1 9:8 BANK3_PIN02_MA RW 0x0 7 6 RSRVD1 BANK3_PIN01_V RO 0x0 RW 0x1 5:4 BANK3_PIN01_MA RW 0x0 3 2 RSRVD0 BANK3_PIN00_V RO 0x0 RW 0x1 1:0 BANK3_PIN00_MA RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-55 Pin Control and GPIO 37.4.23 PINCTRL Drive Strength and Voltage Register 13 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 3. HW_PINCTRL_DRIVE13 HW_PINCTRL_DRIVE13_SET HW_PINCTRL_DRIVE13_CLR HW_PINCTRL_DRIVE13_TOG Table 37-49. HW_PINCTRL_DRIVE13 3 1 3 0 BANK3_PIN15_V 0x2d0 0x2d4 0x2d8 0x2dC 2 9 BANK3_PIN15_MA 2 8 2 7 2 6 BANK3_PIN14_V 2 5 BANK3_PIN14_MA 2 4 2 3 2 2 BANK3_PIN13_V 2 1 BANK3_PIN13_MA 2 0 1 9 1 8 BANK3_PIN12_V 1 7 BANK3_PIN12_MA 1 6 1 5 1 4 BANK3_PIN11_V 1 3 BANK3_PIN11_MA 1 2 1 1 1 0 BANK3_PIN10_V 0 9 BANK3_PIN10_MA 0 8 0 7 0 6 BANK3_PIN09_V 0 5 BANK3_PIN09_MA 0 4 0 3 0 2 BANK3_PIN08_V 0 1 BANK3_PIN08_MA 0 0 RSRVD7 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-50. HW_PINCTRL_DRIVE13 Bit Field Descriptions BITS LABEL 31 RSRVD7 30 BANK3_PIN15_V RW RESET RO 0x0 RW 0x1 DEFINITION Always write zeroes to this field. Pin 95, EMI_D15 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 95, EMI_D15 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 96, EMI_D14 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 96, EMI_D14 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 94, EMI_D13 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 94, EMI_D13 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 93, EMI_D12 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. 29:28 BANK3_PIN15_MA RW 0x0 27 26 RSRVD6 BANK3_PIN14_V RO 0x0 RW 0x1 25:24 BANK3_PIN14_MA RW 0x0 23 22 RSRVD5 BANK3_PIN13_V RO 0x0 RW 0x1 21:20 BANK3_PIN13_MA RW 0x0 19 18 RSRVD4 BANK3_PIN12_V RO 0x0 RW 0x1 i.MX23 Applications Processor Reference Manual, Rev. 1 37-56 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD0 Pin Control and GPIO Table 37-50. HW_PINCTRL_DRIVE13 Bit Field Descriptions BITS LABEL 17:16 BANK3_PIN12_MA RW RESET RW 0x0 DEFINITION Pin 93, EMI_D12 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 91, EMI_D11 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 91, EMI_D11 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 89, EMI_D10 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 89, EMI_D10 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 87, EMI_D09 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 87, EMI_D09 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 86, EMI_D08 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 86, EMI_D08 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. 15 14 RSRVD3 BANK3_PIN11_V RO 0x0 RW 0x1 13:12 BANK3_PIN11_MA RW 0x0 11 10 RSRVD2 BANK3_PIN10_V RO 0x0 RW 0x1 9:8 BANK3_PIN10_MA RW 0x0 7 6 RSRVD1 BANK3_PIN09_V RO 0x0 RW 0x1 5:4 BANK3_PIN09_MA RW 0x0 3 2 RSRVD0 BANK3_PIN08_V RO 0x0 RW 0x1 1:0 BANK3_PIN08_MA RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-57 Pin Control and GPIO 37.4.24 PINCTRL Drive Strength and Voltage Register 14 Description The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 6 pins of bank 3. HW_PINCTRL_DRIVE14 HW_PINCTRL_DRIVE14_SET HW_PINCTRL_DRIVE14_CLR HW_PINCTRL_DRIVE14_TOG Table 37-51. HW_PINCTRL_DRIVE14 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 BANK3_PIN21_V 0x2e0 0x2e4 0x2e8 0x2eC 2 1 BANK3_PIN21_MA 2 0 1 9 1 8 BANK3_PIN20_V 1 7 BANK3_PIN20_MA 1 6 1 5 1 4 BANK3_PIN19_V 1 3 BANK3_PIN19_MA 1 2 1 1 1 0 BANK3_PIN18_V 0 9 BANK3_PIN18_MA 0 8 0 7 0 6 BANK3_PIN17_V 0 5 BANK3_PIN17_MA 0 4 0 3 0 2 BANK3_PIN16_V 0 1 BANK3_PIN16_MA 0 0 RSRVD6 RSRVD5 RSRVD4 RSRVD3 RSRVD2 RSRVD1 Table 37-52. HW_PINCTRL_DRIVE14 Bit Field Descriptions BITS LABEL 31:24 RSRVD6 23 RSRVD5 22 BANK3_PIN21_V RW RESET RO 0x0 RO 0x0 RW 0x1 DEFINITION Always write zeroes to this field. Always write zeroes to this field. Pin 72, EMI_CLKN pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 72, EMI_CLKN pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 70, EMI_CLK pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 70, EMI_CLK pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 74, EMI_DQS1 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 74, EMI_DQS1 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. 21:20 BANK3_PIN21_MA RW 0x0 19 18 RSRVD4 BANK3_PIN20_V RO 0x0 RW 0x1 17:16 BANK3_PIN20_MA RW 0x0 15 14 RSRVD3 BANK3_PIN19_V RO 0x0 RW 0x1 13:12 BANK3_PIN19_MA RW 0x0 11 RSRVD2 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 37-58 Preliminary--Subject to Change Without Notice Freescale Semiconductor RSRVD0 Pin Control and GPIO Table 37-52. HW_PINCTRL_DRIVE14 Bit Field Descriptions BITS LABEL 10 BANK3_PIN18_V RW RESET RW 0x1 DEFINITION Pin 73, EMI_DQS0 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 73, EMI_DQS0 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 92, EMI_DQM1 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 92, EMI_DQM1 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. Always write zeroes to this field. Pin 81, EMI_DQM0 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Pin 81, EMI_DQM0 pin output drive strength selection: 00= 4 mA; 01= 8 mA; 10= 12 mA; 11= 16 mA. 9:8 BANK3_PIN18_MA RW 0x0 7 6 RSRVD1 BANK3_PIN17_V RO 0x0 RW 0x1 5:4 BANK3_PIN17_MA RW 0x0 3 2 RSRVD0 BANK3_PIN16_V RO 0x0 RW 0x1 1:0 BANK3_PIN16_MA RW 0x0 DESCRIPTION: The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. EXAMPLE: Empty Example. 37.4.25 PINCTRL Bank 0 Pull Up Resistor Enable Register Description The PINCTRL Bank 0 PULL Register enables/disables the internal pull up resistors for those pins in bank 0 which support this operation. HW_PINCTRL_PULL0 HW_PINCTRL_PULL0_SET HW_PINCTRL_PULL0_CLR HW_PINCTRL_PULL0_TOG 0x400 0x404 0x408 0x40C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-59 Pin Control and GPIO Table 37-53. HW_PINCTRL_PULL0 3 1 BANK0_PIN31 3 0 BANK0_PIN30 2 9 BANK0_PIN29 2 8 BANK0_PIN28 2 7 BANK0_PIN27 2 6 BANK0_PIN26 2 5 2 4 RSRVD2 2 3 2 2 BANK0_PIN22 2 1 BANK0_PIN21 2 0 BANK0_PIN20 1 9 BANK0_PIN19 1 8 BANK0_PIN18 1 7 RSRVD1 1 6 1 5 BANK0_PIN15 1 4 1 3 RSRVD0 1 2 1 1 BANK0_PIN11 1 0 BANK0_PIN10 0 9 BANK0_PIN09 0 8 BANK0_PIN08 0 7 BANK0_PIN07 0 6 BANK0_PIN06 0 5 BANK0_PIN05 0 4 BANK0_PIN04 0 3 BANK0_PIN03 0 2 BANK0_PIN02 0 1 BANK0_PIN01 0 0 BANK0_PIN00 Table 37-54. HW_PINCTRL_PULL0 Bit Field Descriptions BITS LABEL 31 BANK0_PIN31 RW RESET RW 0x0 DEFINITION Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 4, I2C_SDA. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 2, I2C_SCL. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 69, AUART1_TX. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 68, AUART1_RX. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 67, AUART1_RTS. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 66, AUART1_CTS. Always write zeroes to this field. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 63, GPMI_RDY3. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 62, GPMI_RDY2. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 43, GPMI_RDY1. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 61, GPMI_RDY0. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 42, GPMI_CE2N. Always write zeroes to this field. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 59, GPMI_D15. Always write zeroes to this field. 30 BANK0_PIN30 RW 0x0 29 BANK0_PIN29 RW 0x0 28 BANK0_PIN28 RW 0x0 27 BANK0_PIN27 RW 0x0 26 BANK0_PIN26 RW 0x0 25:23 RSRVD2 22 BANK0_PIN22 RO 0x0 RW 0x0 21 BANK0_PIN21 RW 0x0 20 BANK0_PIN20 RW 0x0 19 BANK0_PIN19 RW 0x0 18 BANK0_PIN18 RW 0x0 17:16 RSRVD1 15 BANK0_PIN15 RO 0x0 RW 0x0 14:12 RSRVD0 RO 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 37-60 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-54. HW_PINCTRL_PULL0 Bit Field Descriptions BITS LABEL 11 BANK0_PIN11 RW RESET RW 0x0 DEFINITION Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 55, GPMI_D11. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 54, GPMI_D10. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 53, GPMI_D09. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 52, GPMI_D08. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 50, GPMI_D07. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 51, GPMI_D06. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 48, GPMI_D05. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 49, GPMI_D04. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 47, GPMI_D03. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 46, GPMI_D02. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 45, GPMI_D01. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 44, GPMI_D00. 10 BANK0_PIN10 RW 0x0 9 BANK0_PIN09 RW 0x0 8 BANK0_PIN08 RW 0x0 7 BANK0_PIN07 RW 0x0 6 BANK0_PIN06 RW 0x0 5 BANK0_PIN05 RW 0x0 4 BANK0_PIN04 RW 0x0 3 BANK0_PIN03 RW 0x0 2 BANK0_PIN02 RW 0x0 1 BANK0_PIN01 RW 0x0 0 BANK0_PIN00 RW 0x0 DESCRIPTION: The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the pins. EXAMPLE: Empty Example. 37.4.26 PINCTRL Bank 1 Pull Up Resistor Enable Register Description The PINCTRL Bank 1 PULL Register enables/disables the internal pull up resistors for those pins in bank 1 which support this operation. HW_PINCTRL_PULL1 HW_PINCTRL_PULL1_SET HW_PINCTRL_PULL1_CLR 0x410 0x414 0x418 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-61 Pin Control and GPIO HW_PINCTRL_PULL1_TOG Table 37-55. HW_PINCTRL_PULL1 3 1 3 0 RSRVD3 0x41C 2 9 2 8 BANK1_PIN28 2 7 2 6 2 5 RSRVD2 2 4 2 3 2 2 BANK1_PIN22 2 1 2 0 RSRVD1 1 9 1 8 BANK1_PIN18 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 RSRVD0 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 37-56. HW_PINCTRL_PULL1 Bit Field Descriptions BITS LABEL 31:29 RSRVD3 28 BANK1_PIN28 RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 129, PWM2. Always write zeroes to this field. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 36, LCD_DOTCK. Always write zeroes to this field. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 31, LCD_RESET. Always write zeroes to this field. 27:23 RSRVD2 22 BANK1_PIN22 RO 0x0 RW 0x0 21:19 RSRVD1 18 BANK1_PIN18 RO 0x0 RW 0x0 17:0 RSRVD0 RO 0x0 DESCRIPTION: The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the pins. EXAMPLE: Empty Example. 37.4.27 PINCTRL Bank 2 Pull Up Resistor Enable Register Description The PINCTRL Bank 2 PULL Register enables/disables the internal pull up resistors for those pins in bank 2 which support this operation. HW_PINCTRL_PULL2 HW_PINCTRL_PULL2_SET HW_PINCTRL_PULL2_CLR HW_PINCTRL_PULL2_TOG 0x420 0x424 0x428 0x42C i.MX23 Applications Processor Reference Manual, Rev. 1 37-62 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-57. HW_PINCTRL_PULL2 3 1 3 0 RSRVD2 2 9 2 8 BANK2_PIN28 2 7 BANK2_PIN27 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 RSRVD1 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 BANK2_PIN08 0 7 RSRVD0 0 6 0 5 BANK2_PIN05 0 4 BANK2_PIN04 0 3 BANK2_PIN03 0 2 BANK2_PIN02 0 1 BANK2_PIN01 0 0 BANK2_PIN00 Table 37-58. HW_PINCTRL_PULL2 Bit Field Descriptions BITS LABEL 31:29 RSRVD2 28 BANK2_PIN28 RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 120, GPMI_CE0N. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 118, GPMI_CE1N. Always write zeroes to this field. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 38, ROTARYB. Always write zeroes to this field. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 125, SSP1_DATA3. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 124, SSP1_DATA2. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 123, SSP1_DATA1. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 122, SSP1_DATA0. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 126, SSP1_DETECT. Set this bit to one to disable the internal pad keeper and enable the internal pull up resistor on pin 121, SSP1_CMD. 27 BANK2_PIN27 RW 0x0 26:9 8 RSRVD1 BANK2_PIN08 RO 0x0 RW 0x0 7:6 5 RSRVD0 BANK2_PIN05 RO 0x0 RW 0x0 4 BANK2_PIN04 RW 0x0 3 BANK2_PIN03 RW 0x0 2 BANK2_PIN02 RW 0x0 1 BANK2_PIN01 RW 0x0 0 BANK2_PIN00 RW 0x0 DESCRIPTION: The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the pins. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-63 Pin Control and GPIO 37.4.28 PINCTRL Bank 3 Pad Keeper Disable Register Description The PINCTRL Bank 3 PULL Register enables/disables the pad keepers for those pins in bank 3 which support this operation. HW_PINCTRL_PULL3 HW_PINCTRL_PULL3_SET HW_PINCTRL_PULL3_CLR HW_PINCTRL_PULL3_TOG Table 37-59. HW_PINCTRL_PULL3 3 1 3 0 2 9 2 8 2 7 2 6 2 5 RSRVD0 0x430 0x434 0x438 0x43C 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 BANK3_PIN17 1 6 BANK3_PIN16 1 5 BANK3_PIN15 1 4 BANK3_PIN14 1 3 BANK3_PIN13 1 2 BANK3_PIN12 1 1 BANK3_PIN11 1 0 BANK3_PIN10 0 9 BANK3_PIN09 0 8 BANK3_PIN08 0 7 BANK3_PIN07 0 6 BANK3_PIN06 0 5 BANK3_PIN05 0 4 BANK3_PIN04 0 3 BANK3_PIN03 0 2 BANK3_PIN02 0 1 BANK3_PIN01 0 0 BANK3_PIN00 Table 37-60. HW_PINCTRL_PULL3 Bit Field Descriptions BITS LABEL 31:18 RSRVD0 17 BANK3_PIN17 RW RESET RO 0x0 RW 0x0 DEFINITION Always write zeroes to this field. Set this bit to one to disable the internal pad keeper on pin 92, EMI_DQM1. Set this bit to one to disable the internal pad keeper on pin 81, EMI_DQM0. Set this bit to one to disable the internal pad keeper on pin 95, EMI_D15. Set this bit to one to disable the internal pad keeper on pin 96, EMI_D14. Set this bit to one to disable the internal pad keeper on pin 94, EMI_D13. Set this bit to one to disable the internal pad keeper on pin 93, EMI_D12. Set this bit to one to disable the internal pad keeper on pin 91, EMI_D11. Set this bit to one to disable the internal pad keeper on pin 89, EMI_D10. Set this bit to one to disable the internal pad keeper on pin 87, EMI_D09. Set this bit to one to disable the internal pad keeper on pin 86, EMI_D08. Set this bit to one to disable the internal pad keeper on pin 85, EMI_D07. Set this bit to one to disable the internal pad keeper on pin 84, EMI_D06. Set this bit to one to disable the internal pad keeper on pin 83, EMI_D05. Set this bit to one to disable the internal pad keeper on pin 82, EMI_D04. Set this bit to one to disable the internal pad keeper on pin 79, EMI_D03. 16 15 14 13 12 11 10 9 8 7 6 5 4 3 BANK3_PIN16 BANK3_PIN15 BANK3_PIN14 BANK3_PIN13 BANK3_PIN12 BANK3_PIN11 BANK3_PIN10 BANK3_PIN09 BANK3_PIN08 BANK3_PIN07 BANK3_PIN06 BANK3_PIN05 BANK3_PIN04 BANK3_PIN03 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 i.MX23 Applications Processor Reference Manual, Rev. 1 37-64 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-60. HW_PINCTRL_PULL3 Bit Field Descriptions BITS LABEL 2 BANK3_PIN02 RW RESET RW 0x0 DEFINITION Set this bit to one to disable the internal pad keeper on pin 77, EMI_D02. Set this bit to one to disable the internal pad keeper on pin 76, EMI_D01. Set this bit to one to disable the internal pad keeper on pin 75, EMI_D00. 1 0 BANK3_PIN01 BANK3_PIN00 RW 0x0 RW 0x0 DESCRIPTION: The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the pins. EXAMPLE: Empty Example. 37.4.29 PINCTRL Bank 0 Data Output Register Description The Bank 0 Data Output register provides data for all pins in bank 0 that are configured for GPIO output mode. HW_PINCTRL_DOUT0 HW_PINCTRL_DOUT0_SET HW_PINCTRL_DOUT0_CLR HW_PINCTRL_DOUT0_TOG Table 37-61. HW_PINCTRL_DOUT0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x500 0x504 0x508 0x50C DOUT Table 37-62. HW_PINCTRL_DOUT0 Bit Field Descriptions BITS 31:0 DOUT LABEL RW RESET RW 0x00000000 DEFINITION This field selects the output value (0 or 1) for pins configured as GPIO outputs. Each bit in this register corresponds to one of the 32 pins in bank 0. DESCRIPTION: This register contains the data that will be driven out all bank 0 pins which are configured for GPIO output mode. For example, if HW_PINCTRL_MUXSEL0 contains 0x0000000F and HW_PINCTRL_DOE0 contains 0x00000001, then GPIO0[0] will be driven with the value from bit 0 of this register, GPIO0[1] will not be driven, and GPIO0[2:15] will be controlled by the associated primary interfaces. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-65 Pin Control and GPIO 37.4.30 PINCTRL Bank 1 Data Output Register Description The Bank 1 Data Output register provides data for all pins in bank 1 that are configured for GPIO output mode. HW_PINCTRL_DOUT1 HW_PINCTRL_DOUT1_SET HW_PINCTRL_DOUT1_CLR HW_PINCTRL_DOUT1_TOG Table 37-63. HW_PINCTRL_DOUT1 3 1 RSRVD1 0x510 0x514 0x518 0x51C 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 DOUT 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 37-64. HW_PINCTRL_DOUT1 Bit Field Descriptions BITS 31 RSRVD1 30:0 DOUT LABEL RW RESET RO 0x0 RW 0x00000000 DEFINITION Reserved - write 0 to this bit-field. This field selects the output value (0 or 1) for pins configured as GPIO outputs. Each bit in this register corresponds to one of the 31 pins in bank 1. DESCRIPTION: This register contains the data that will be driven out all bank 0 pins which are configured for GPIO output mode. For example, if HW_PINCTRL_MUXSEL0 contains 0x0000000F and HW_PINCTRL_DOE0 contains 0x00000001, then GPIO0[0] will be driven with the value from bit 0 of this register, GPIO0[1] will not be driven, and GPIO0[2:15] will be controlled by the associated primary interfaces. EXAMPLE: Empty Example. 37.4.31 PINCTRL Bank 2 Data Output Register Description The Bank 2 Data Output register provides data for all pins in bank 2 that are configured for GPIO output mode. HW_PINCTRL_DOUT2 HW_PINCTRL_DOUT2_SET HW_PINCTRL_DOUT2_CLR HW_PINCTRL_DOUT2_TOG Table 37-65. HW_PINCTRL_DOUT2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x520 0x524 0x528 0x52C DOUT i.MX23 Applications Processor Reference Manual, Rev. 1 37-66 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-66. HW_PINCTRL_DOUT2 Bit Field Descriptions BITS 31:0 DOUT LABEL RW RESET RW 0x00000000 DEFINITION This field selects the output value (0 or 1) for pins configured as GPIO outputs. Each bit in this register corresponds to one of the 32 pins in bank 2. DESCRIPTION: This register contains the data that will be driven out all bank 0 pins which are configured for GPIO output mode. For example, if HW_PINCTRL_MUXSEL0 contains 0x0000000F and HW_PINCTRL_DOE0 contains 0x00000001, then GPIO0[0] will be driven with the value from bit 0 of this register, GPIO0[1] will not be driven, and GPIO0[2:15] will be controlled by the associated primary interfaces. EXAMPLE: Empty Example. 37.4.32 PINCTRL Bank 0 Data Input Register Description The current value of all bank 0 pins may be read from the PINCTRL Bank 0 Data Input Register. HW_PINCTRL_DIN0 HW_PINCTRL_DIN0_SET HW_PINCTRL_DIN0_CLR HW_PINCTRL_DIN0_TOG Table 37-67. HW_PINCTRL_DIN0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x600 0x604 0x608 0x60C DIN Table 37-68. HW_PINCTRL_DIN0 Bit Field Descriptions BITS 31:0 DIN LABEL RW RESET RO 0x00000000 DEFINITION Each bit in this read-only register corresponds to one of the 32 pins in bank 0. The current state of each pin in bank 0, synchronized to HCLK, may be read here. DESCRIPTION: This register reflects the current values of all the bank 0 pins. The register accurately reflects the state of the pin regardless of the setting of the HW_PINCTRL_MUXSELx or HW_PINCTRL_DOEx registers, but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the HW_PINCTRL_MUXSELx register should be set to 3 (GPIO mode) and the pin's bit in the HW_PINCTRL_DOEx register should be set to 0 (disabled) to insure that the chip is not driving the pin. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-67 Pin Control and GPIO 37.4.33 PINCTRL Bank 1 Data Input Register Description The current value of all bank 1 pins may be read from the PINCTRL Bank 1 Data Input Register. HW_PINCTRL_DIN1 HW_PINCTRL_DIN1_SET HW_PINCTRL_DIN1_CLR HW_PINCTRL_DIN1_TOG Table 37-69. HW_PINCTRL_DIN1 3 1 RSRVD1 0x610 0x614 0x618 0x61C 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 DIN 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 37-70. HW_PINCTRL_DIN1 Bit Field Descriptions BITS 31 RSRVD1 30:0 DIN LABEL RW RESET RO 0x0 RO 0x00000000 DEFINITION Reserved - write 0 to this bit-field. Each bit in this read-only register corresponds to one of the 31 pins in bank 1. The current state of each pin in bank 1, synchronized to HCLK, may be read here. DESCRIPTION: This register reflects the current values of all the bank 1 pins. The register accurately reflects the state of the pin regardless of the setting of the HW_PINCTRL_MUXSELx or HW_PINCTRL_DOEx registers, but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the HW_PINCTRL_MUXSELx register should be set to 3 (GPIO mode) and the pin's bit in the HW_PINCTRL_DOEx register should be set to 0 (disabled) to insure that the chip is not driving the pin. EXAMPLE: Empty Example. 37.4.34 PINCTRL Bank 2 Data Input Register Description The current value of all bank 2 pins may be read from the PINCTRL Bank 2 Data Input Register. HW_PINCTRL_DIN2 HW_PINCTRL_DIN2_SET HW_PINCTRL_DIN2_CLR HW_PINCTRL_DIN2_TOG Table 37-71. HW_PINCTRL_DIN2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x620 0x624 0x628 0x62C DIN i.MX23 Applications Processor Reference Manual, Rev. 1 37-68 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-72. HW_PINCTRL_DIN2 Bit Field Descriptions BITS 31:0 DIN LABEL RW RESET RO 0x00000000 DEFINITION Each bit in this read-only register corresponds to one of the 32 pins in bank 2. The current state of each pin in bank 2, synchronized to HCLK, may be read here. DESCRIPTION: This register reflects the current values of all the bank 2 pins. The register accurately reflects the state of the pin regardless of the setting of the HW_PINCTRL_MUXSELx or HW_PINCTRL_DOEx registers, but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the HW_PINCTRL_MUXSELx register should be set to 3 (GPIO mode) and the pin's bit in the HW_PINCTRL_DOEx register should be set to 0 (disabled) to insure that the chip is not driving the pin. EXAMPLE: Empty Example. 37.4.35 PINCTRL Bank 0 Data Output Enable Register Description The PINCTRL Bank 0 Output Enable Register controls the output enable signal for all pins in bank 0 that are configured for GPIO mode. HW_PINCTRL_DOE0 HW_PINCTRL_DOE0_SET HW_PINCTRL_DOE0_CLR HW_PINCTRL_DOE0_TOG Table 37-73. HW_PINCTRL_DOE0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x700 0x704 0x708 0x70C DOE Table 37-74. HW_PINCTRL_DOE0 Bit Field Descriptions BITS 31:0 DOE LABEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 0. Setting a bit in this register to one allows the chip to drive the corresponding pin in GPIO mode. DESCRIPTION: For pins in bank 0 that are configured as GPIOs, a 1 in this register will enable the corresponding bit value from HW_PINCTRL_DOUTxx register to be driven out the pin, and a 0 in this register will disable the corresponding driver. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-69 Pin Control and GPIO 37.4.36 PINCTRL Bank 1 Data Output Enable Register Description The PINCTRL Bank 1 Output Enable Register controls the output enable signal for all pins in bank 1 that are configured for GPIO mode. HW_PINCTRL_DOE1 HW_PINCTRL_DOE1_SET HW_PINCTRL_DOE1_CLR HW_PINCTRL_DOE1_TOG Table 37-75. HW_PINCTRL_DOE1 3 1 RSRVD1 0x710 0x714 0x718 0x71C 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 DOE 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 37-76. HW_PINCTRL_DOE1 Bit Field Descriptions BITS 31 RSRVD1 30:0 DOE LABEL RW RESET RO 0x0 RW 0x00000000 DEFINITION Reserved - write 0 to this bit-field. Each bit in this register corresponds to one of the 31 pins in bank 1. Setting a bit in this register to one allows the chip to drive the corresponding pin in GPIO mode. DESCRIPTION: For pins in bank 1 that are configured as GPIOs, a 1 in this register will enable the corresponding bit value from HW_PINCTRL_DOUTxx register to be driven out the pin, and a 0 in this register will disable the corresponding driver. EXAMPLE: Empty Example. 37.4.37 PINCTRL Bank 2 Data Output Enable Register Description The PINCTRL Bank 2 Output Enable Register controls the output enable signal for all pins in bank 2 that are configured for GPIO mode. HW_PINCTRL_DOE2 HW_PINCTRL_DOE2_SET HW_PINCTRL_DOE2_CLR HW_PINCTRL_DOE2_TOG Table 37-77. HW_PINCTRL_DOE2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x720 0x724 0x728 0x72C DOE i.MX23 Applications Processor Reference Manual, Rev. 1 37-70 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-78. HW_PINCTRL_DOE2 Bit Field Descriptions BITS 31:0 DOE LABEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 2. Setting a bit in this register to one allows the chip to drive the corresponding pin in GPIO mode. DESCRIPTION: For pins in bank 2 that are configured as GPIOs, a 1 in this register will enable the corresponding bit value from HW_PINCTRL_DOUTxx register to be driven out the pin, and a 0 in this register will disable the corresponding driver. EXAMPLE: Empty Example. 37.4.38 PINCTRL Bank 0 Interrupt Select Register Description The Bank 0 Interrupt Select register selects which of the bank 0 pins may be used as interrupt sources. HW_PINCTRL_PIN2IRQ0 HW_PINCTRL_PIN2IRQ0_SET HW_PINCTRL_PIN2IRQ0_CLR HW_PINCTRL_PIN2IRQ0_TOG Table 37-79. HW_PINCTRL_PIN2IRQ0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x800 0x804 0x808 0x80C PIN2IRQ Table 37-80. HW_PINCTRL_PIN2IRQ0 Bit Field Descriptions BITS 31:0 PIN2IRQ LABEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 0: 0= Deselect the pin's interrupt functionality. 1= Select the pin to be used as an interrupt source. DESCRIPTION: As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register selects which pins in bank 0 can be used to generate interrupts. If the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the HW_PINCTRL_IRQLEVEL0 and HW_PINCTRL_IRQPOL0 registers) will set the corresponding bit in the HW_PINCTRL_IRQSTAT0 register. If the pin is additionally enabled in the HW_PINCTRL_IRQEN0 register, then the interrupt will be propagated to the interrupt collector as interrupt GPIO0. For example, if this register contains 0x00000014, then pins GPIO0[2] and GPIO0[4] can be used as interrupt pins, and no other pins in bank 0 will cause bits to be set in the HW_PINCTRL_IRQSTAT0 register. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-71 Pin Control and GPIO EXAMPLE: Empty Example. 37.4.39 PINCTRL Bank 1 Interrupt Select Register Description The Bank 1 Interrupt Select register selects which of the bank 1 pins may be used as interrupt sources. HW_PINCTRL_PIN2IRQ1 HW_PINCTRL_PIN2IRQ1_SET HW_PINCTRL_PIN2IRQ1_CLR HW_PINCTRL_PIN2IRQ1_TOG Table 37-81. HW_PINCTRL_PIN2IRQ1 3 1 RSRVD1 0x810 0x814 0x818 0x81C 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 PIN2IRQ 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 37-82. HW_PINCTRL_PIN2IRQ1 Bit Field Descriptions BITS 31 RSRVD1 30:0 PIN2IRQ LABEL RW RESET RO 0x0 RW 0x00000000 DEFINITION Reserved - write 0 to this bit-field. Each bit in this register corresponds to one of the 31 pins in bank 1: 0= Deselect the pin's interrupt functionality. 1= Select the pin to be used as an interrupt source. DESCRIPTION: As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register selects which pins in bank 1 can be used to generate interrupts. If the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the HW_PINCTRL_IRQLEVEL1 and HW_PINCTRL_IRQPOL1 registers) will set the corresponding bit in the HW_PINCTRL_IRQSTAT1 register. If the pin is additionally enabled in the HW_PINCTRL_IRQEN0 register, then the interrupt will be propagated to the interrupt collector as interrupt GPIO1. For example, if this register contains 0x00000014, then pins GPIO1[2] and GPIO1[4] can be used as interrupt pins, and no other pins in bank 0 will cause bits to be set in the HW_PINCTRL_IRQSTAT1 register. EXAMPLE: Empty Example. 37.4.40 PINCTRL Bank 2 Interrupt Select Register Description The Bank 2 Interrupt Select register selects which of the bank 2 pins may be used as interrupt sources. HW_PINCTRL_PIN2IRQ2 HW_PINCTRL_PIN2IRQ2_SET HW_PINCTRL_PIN2IRQ2_CLR 0x820 0x824 0x828 i.MX23 Applications Processor Reference Manual, Rev. 1 37-72 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO HW_PINCTRL_PIN2IRQ2_TOG Table 37-83. HW_PINCTRL_PIN2IRQ2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0x82C 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PIN2IRQ Table 37-84. HW_PINCTRL_PIN2IRQ2 Bit Field Descriptions BITS 31:0 PIN2IRQ LABEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 2: 0= Deselect the pin's interrupt functionality. 1= Select the pin to be used as an interrupt source. DESCRIPTION: As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register selects which pins in bank 2 can be used to generate interrupts. If the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the HW_PINCTRL_IRQLEVEL2 and HW_PINCTRL_IRQPOL2 registers) will set the corresponding bit in the HW_PINCTRL_IRQSTAT2 register. If the pin is additionally enabled in the HW_PINCTRL_IRQEN0 register, then the interrupt will be propagated to the interrupt collector as interrupt GPIO2. For example, if this register contains 0x00000014, then pins GPIO2[2] and GPIO2[4] can be used as interrupt pins, and no other pins in bank 0 will cause bits to be set in the HW_PINCTRL_IRQSTAT2 register. EXAMPLE: Empty Example. 37.4.41 PINCTRL Bank 0 Interrupt Mask Register Description The PINCTRL Bank 0 Interrupt Mask Register contains interrupt enable masks for the pins in bank 0. HW_PINCTRL_IRQEN0 HW_PINCTRL_IRQEN0_SET HW_PINCTRL_IRQEN0_CLR HW_PINCTRL_IRQEN0_TOG Table 37-85. HW_PINCTRL_IRQEN0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x900 0x904 0x908 0x90C IRQEN i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-73 Pin Control and GPIO Table 37-86. HW_PINCTRL_IRQEN0 Bit Field Descriptions BITS 31:0 IRQEN LABEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 0: 1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT0. 0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT0. DESCRIPTION: As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register masks the interrupt sources from the pins in bank 0. If a bit is set in this register and the same bit is set in HW_PINCTRL_IRQSTAT0, an interrupt will be propagated to the interrupt collector as interrupt GPIO0. For example, if this register contains 0x00000014, then only bits 2 and 4 in HW_PINCTRL_IRQSTAT0 (corresponding to pins GPIO0[2] and GPIO0[4]) will cause interrupts from bank 0. EXAMPLE: Empty Example. 37.4.42 PINCTRL Bank 1 Interrupt Mask Register Description The PINCTRL Bank 1 Interrupt Mask Register contains interrupt enable masks for the pins in bank 1. HW_PINCTRL_IRQEN1 HW_PINCTRL_IRQEN1_SET HW_PINCTRL_IRQEN1_CLR HW_PINCTRL_IRQEN1_TOG Table 37-87. HW_PINCTRL_IRQEN1 3 1 RSRVD1 0x910 0x914 0x918 0x91C 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 IRQEN 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 37-88. HW_PINCTRL_IRQEN1 Bit Field Descriptions BITS 31 RSRVD1 30:0 IRQEN LABEL RW RESET RO 0x0 RW 0x00000000 DEFINITION Reserved - write 0 to this bit-field. Each bit in this register corresponds to one of the 31 pins in bank 1: 1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT1. 0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT1. i.MX23 Applications Processor Reference Manual, Rev. 1 37-74 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO DESCRIPTION: As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register masks the interrupt sources from the pins in bank 1. If a bit is set in this register and the same bit is set in HW_PINCTRL_IRQSTAT1, an interrupt will be propagated to the interrupt collector as interrupt GPIO1. For example, if this register contains 0x00000014, then only bits 2 and 4 in HW_PINCTRL_IRQSTAT1 (corresponding to pins GPIO1[2] and GPIO1[4]) will cause interrupts from bank 1. EXAMPLE: Empty Example. 37.4.43 PINCTRL Bank 2 Interrupt Mask Register Description The PINCTRL Bank 2 Interrupt Mask Register contains interrupt enable masks for the pins in bank 2. HW_PINCTRL_IRQEN2 HW_PINCTRL_IRQEN2_SET HW_PINCTRL_IRQEN2_CLR HW_PINCTRL_IRQEN2_TOG Table 37-89. HW_PINCTRL_IRQEN2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0x920 0x924 0x928 0x92C IRQEN Table 37-90. HW_PINCTRL_IRQEN2 Bit Field Descriptions BITS 31:0 IRQEN LABEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 2: 1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT2. 0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT2. DESCRIPTION: As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register masks the interrupt sources from the pins in bank 2. If a bit is set in this register and the same bit is set in HW_PINCTRL_IRQSTAT2, an interrupt will be propagated to the interrupt collector as interrupt GPIO2. For example, if this register contains 0x00000014, then only bits 2 and 4 in HW_PINCTRL_IRQSTAT2 (corresponding to pins GPIO2[2] and GPIO2[4]) will cause interrupts from bank 2. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-75 Pin Control and GPIO 37.4.44 PINCTRL Bank 0 Interrupt Level/Edge Register Description The PINCTRL Bank 0 Interrupt Level/Edge Register selects level or edge sensitivity for interrupt requests for the pins in bank 0. HW_PINCTRL_IRQLEVEL0 HW_PINCTRL_IRQLEVEL0_SET HW_PINCTRL_IRQLEVEL0_CLR HW_PINCTRL_IRQLEVEL0_TOG 0xa00 0xa04 0xa08 0xa0C Table 37-91. HW_PINCTRL_IRQLEVEL0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 IRQLEVEL Table 37-92. HW_PINCTRL_IRQLEVEL0 Bit Field Descriptions BITS LABEL 31:0 IRQLEVEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 0: 1= Level detection; 0= Edge detection. DESCRIPTION: This register selects level or edge detection for interrupt generation. Each pin in bank 0 that is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting bits in this register and HW_PINCTRL_IRQPOL0 (see below) appropriately. EXAMPLE: Empty Example. 37.4.45 PINCTRL Bank 1 Interrupt Level/Edge Register Description The PINCTRL Bank 1 Interrupt Level/Edge Register selects level or edge sensitivity for interrupt requests for the pins in bank 1. HW_PINCTRL_IRQLEVEL1 HW_PINCTRL_IRQLEVEL1_SET HW_PINCTRL_IRQLEVEL1_CLR HW_PINCTRL_IRQLEVEL1_TOG 0xa10 0xa14 0xa18 0xa1C Table 37-93. HW_PINCTRL_IRQLEVEL1 3 1 RSRVD1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 IRQLEVEL 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 37-76 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-94. HW_PINCTRL_IRQLEVEL1 Bit Field Descriptions BITS LABEL 31 RSRVD1 30:0 IRQLEVEL RW RESET RO 0x0 RW 0x00000000 DEFINITION Reserved - write 0 to this bit-field. Each bit in this register corresponds to one of the 31 pins in bank 1: 1= Level detection; 0= Edge detection. DESCRIPTION: This register selects level or edge detection for interrupt generation. Each pin in bank 1 that is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting bits in this register and HW_PINCTRL_IRQPOL1 (see below) appropriately. EXAMPLE: Empty Example. 37.4.46 PINCTRL Bank 2 Interrupt Level/Edge Register Description The PINCTRL Bank 2 Interrupt Level/Edge Register selects level or edge sensitivity for interrupt requests for the pins in bank 2. HW_PINCTRL_IRQLEVEL2 HW_PINCTRL_IRQLEVEL2_SET HW_PINCTRL_IRQLEVEL2_CLR HW_PINCTRL_IRQLEVEL2_TOG 0xa20 0xa24 0xa28 0xa2C Table 37-95. HW_PINCTRL_IRQLEVEL2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 IRQLEVEL Table 37-96. HW_PINCTRL_IRQLEVEL2 Bit Field Descriptions BITS LABEL 31:0 IRQLEVEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 2: 1= Level detection; 0= Edge detection. DESCRIPTION: This register selects level or edge detection for interrupt generation. Each pin in bank 2 that is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting bits in this register and HW_PINCTRL_IRQPOL2 (see below) appropriately. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-77 Pin Control and GPIO 37.4.47 PINCTRL Bank 0 Interrupt Polarity Register Description The PINCTRL Bank 0 Interrupt Polarity Register selects the polarity for interrupt requests for the pins in bank 0. HW_PINCTRL_IRQPOL0 HW_PINCTRL_IRQPOL0_SET HW_PINCTRL_IRQPOL0_CLR HW_PINCTRL_IRQPOL0_TOG Table 37-97. HW_PINCTRL_IRQPOL0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0xb00 0xb04 0xb08 0xb0C IRQPOL Table 37-98. HW_PINCTRL_IRQPOL0 Bit Field Descriptions BITS 31:0 IRQPOL LABEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 0: 0= Low or falling edge; 1= High or rising edge. DESCRIPTION: This register selects the polarity for interrupt generation. Each pin in bank 0 which is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting this register and HW_PINCTRL_IRQLEVEL0 (see above) appropriately. EXAMPLE: Empty Example. 37.4.48 PINCTRL Bank 1 Interrupt Polarity Register Description The PINCTRL Bank 1 Interrupt Polarity Register selects the polarity for interrupt requests for the pins in bank 1. HW_PINCTRL_IRQPOL1 HW_PINCTRL_IRQPOL1_SET HW_PINCTRL_IRQPOL1_CLR HW_PINCTRL_IRQPOL1_TOG Table 37-99. HW_PINCTRL_IRQPOL1 3 1 RSRVD1 0xb10 0xb14 0xb18 0xb1C 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 IRQPOL 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 i.MX23 Applications Processor Reference Manual, Rev. 1 37-78 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-100. HW_PINCTRL_IRQPOL1 Bit Field Descriptions BITS 31 RSRVD1 30:0 IRQPOL LABEL RW RESET RO 0x0 RW 0x00000000 DEFINITION Reserved - write 0 to this bit-field. Each bit in this register corresponds to one of the 31 pins in bank 1: 0= Low or falling edge; 1= High or rising edge. DESCRIPTION: This register selects the polarity for interrupt generation. Each pin in bank 1 which is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting this register and HW_PINCTRL_IRQLEVEL1 (see above) appropriately. EXAMPLE: Empty Example. 37.4.49 PINCTRL Bank 2 Interrupt Polarity Register Description The PINCTRL Bank 2 Interrupt Polarity Register selects the polarity for interrupt requests for the pins in bank 2. HW_PINCTRL_IRQPOL2 HW_PINCTRL_IRQPOL2_SET HW_PINCTRL_IRQPOL2_CLR HW_PINCTRL_IRQPOL2_TOG Table 37-101. HW_PINCTRL_IRQPOL2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0xb20 0xb24 0xb28 0xb2C IRQPOL Table 37-102. HW_PINCTRL_IRQPOL2 Bit Field Descriptions BITS 31:0 IRQPOL LABEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 2: 0= Low or falling edge; 1= High or rising edge. DESCRIPTION: This register selects the polarity for interrupt generation. Each pin in bank 2 which is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting this register and HW_PINCTRL_IRQLEVEL2 (see above) appropriately. EXAMPLE: Empty Example. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-79 Pin Control and GPIO 37.4.50 PINCTRL Bank 0 Interrupt Status Register Description The PINCTRL Bank 0 Interrupt Status Register reflects pending interrupt status for the pins in bank 0. HW_PINCTRL_IRQSTAT0 HW_PINCTRL_IRQSTAT0_SET HW_PINCTRL_IRQSTAT0_CLR HW_PINCTRL_IRQSTAT0_TOG 0xc00 0xc04 0xc08 0xc0C Table 37-103. HW_PINCTRL_IRQSTAT0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 IRQSTAT Table 37-104. HW_PINCTRL_IRQSTAT0 Bit Field Descriptions BITS 31:0 IRQSTAT LABEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 0: 0= No interrupt pending; 1= Interrupt pending. DESCRIPTION: This register reflects the pending interrupt status for pins in bank 0. Bits in this register are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling edge) occurs on a bank 0 pin which has been enabled as an interrupts source in the HW_PINCTRL_PIN2IRQ0 register. Software may clear any bit in this register by writing a 1 to the bit at the SCT clear address, e.g., HW_PINCTRL_IRQSTAT0_CLR. Status bits for pins configured as level sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in HW_PINCTRL_PIN2IRQ0. If a bit is set in this register, and the corresponding bit is also set in the HW_PINCNTRL_IRQEN0 mask register, then the GPIO0 interrupt will be asserted to the interrupt collector. EXAMPLE: Empty Example. 37.4.51 PINCTRL Bank 1 Interrupt Status Register Description The PINCTRL Bank 1 Interrupt Status Register reflects pending interrupt status for the pins in bank 1. HW_PINCTRL_IRQSTAT1 HW_PINCTRL_IRQSTAT1_SET HW_PINCTRL_IRQSTAT1_CLR HW_PINCTRL_IRQSTAT1_TOG 0xc10 0xc14 0xc18 0xc1C i.MX23 Applications Processor Reference Manual, Rev. 1 37-80 Preliminary--Subject to Change Without Notice Freescale Semiconductor Pin Control and GPIO Table 37-105. HW_PINCTRL_IRQSTAT1 3 1 RSRVD1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 IRQSTAT 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 Table 37-106. HW_PINCTRL_IRQSTAT1 Bit Field Descriptions BITS 31 RSRVD1 30:0 IRQSTAT LABEL RW RESET RO 0x0 RW 0x00000000 DEFINITION Reserved - write 0 to this bit-field. Each bit in this register corresponds to one of the 31 pins in bank 1: 0= No interrupt pending; 1= Interrupt pending. DESCRIPTION: This register reflects the pending interrupt status for pins in bank 1. Bits in this register are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling edge) occurs on a bank 1 pin which has been enabled as an interrupts source in the HW_PINCTRL_PIN2IRQ1 register. Software may clear any bit in this register by writing a 1 to the bit at the SCT clear address, e.g., HW_PINCTRL_IRQSTAT1_CLR. Status bits for pins configured as level sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in HW_PINCTRL_PIN2IRQ1. If a bit is set in this register, and the corresponding bit is also set in the HW_PINCNTRL_IRQEN1 mask register, then the GPIO1 interrupt will be asserted to the interrupt collector. EXAMPLE: Empty Example. 37.4.52 PINCTRL Bank 2 Interrupt Status Register Description The PINCTRL Bank 2 Interrupt Status Register reflects pending interrupt status for the pins in bank 2. HW_PINCTRL_IRQSTAT2 HW_PINCTRL_IRQSTAT2_SET HW_PINCTRL_IRQSTAT2_CLR HW_PINCTRL_IRQSTAT2_TOG 0xc20 0xc24 0xc28 0xc2C Table 37-107. HW_PINCTRL_IRQSTAT2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 IRQSTAT i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37-81 Pin Control and GPIO Table 37-108. HW_PINCTRL_IRQSTAT2 Bit Field Descriptions BITS 31:0 IRQSTAT LABEL RW RESET RW 0x00000000 DEFINITION Each bit in this register corresponds to one of the 32 pins in bank 2: 0= No interrupt pending; 1= Interrupt pending. DESCRIPTION: This register reflects the pending interrupt status for pins in bank 2. Bits in this register are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling edge) occurs on a bank 2 pin which has been enabled as an interrupts source in the HW_PINCTRL_PIN2IRQ2 register. Software may clear any bit in this register by writing a 1 to the bit at the SCT clear address, e.g., HW_PINCTRL_IRQSTAT2_CLR. Status bits for pins configured as level sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in HW_PINCTRL_PIN2IRQ2. If a bit is set in this register, and the corresponding bit is also set in the HW_PINCNTRL_IRQEN2 mask register, then the GPIO2 interrupt will be asserted to the interrupt collector. EXAMPLE: Empty Example. PINCTRL Block pinctrl, Revision 1.19 i.MX23 Applications Processor Reference Manual, Rev. 1 37-82 Preliminary--Subject to Change Without Notice Freescale Semiconductor Digital Video Encoder Programmers' Manual Chapter 38 Digital Video Encoder Programmers' Manual 38.1 Functional Overview The DVE receives pixel data in 8-bit Cb,Cr,Y coding representing either interlaced or progressive image and produces 10-bit outputs to drive video DACs. A number of different NTSC and PAL formats are supported. The input data can be received on a single 8-bit port clocked at 27 MHz in CbYCrY order or on a pair of such ports, one luma and one chroma, both clocked at 27MHz. Only the latter can support the data rate for progressive. When the 16-bit mode is used for interlaced input, the data is expected to change at 13.5 MHz, but it is still clocked in at 27 MHz. Synchronization of internal line and pixel counters to the incoming stream can use input strobes (horizontal and vertical/field), or embedded D1 SAV and EAV codes. Alternatively, the internal counters can free-run and output horizontal and vertical, and field signals can be generated to provide sync to the picture source. The video output in interlaced mode always includes the composite, CVBS, signal. The remaining three video output channels can provide the three color components of component-video or can provide the Y and C signals for S-video. The color components are produced by a fully programmable matrixing. Thus either RGB, YUV, YPbPc or some other combination can be produced. A sync signal can optionally be inserted on one or more of these component signals. (This sync signal can include, as desired, closed caption, CGMS, WSS and macrovision elements.) The DVE is controlled through 21 read/writeable registers, most of which are 32-bits wide or close to it. These are addressed from the ASIC's host_interface via 32-bit wide data ports and a 4-bit address. Since there are more than 16 registers, an indirect addressing scheme is necessary. The registers provide complete control over the video filtering, output format, and synchronization. Closed caption is supported with data writes to a dedicated register to enter the byte-pair to be sent on line 21 of either field. Handshaking signals are provided to permit timely entry of the data for one or both fields. CGMS (NTSC interlaced and progressive) and WSS ( interlaced PAL) are supported by writes to another register that includes enable bits and the 14-bit payload. Macrovision is fully supported both for interlaced and progressive modes. 38.2 Block Diagram and Implementation Overview Figure 38-1 is a block diagram of the DVE. Discussion of the individual blocks follows. the figure. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. 38-1 Digital Video Encoder Programmers' Manual O_CVBS D/A D/A D/A D/A A C O_Y D CC HI OU O_C MI_G MI_B B Int MI_R M_R Int Int G M_G M_B MX Y_RGB_BLANK Y_Y C_U C_V R WU CU L_U, L_V L_Y B MV YU LU DU D_Y D_CBCR Figure 38-1. Block Diagram of DVE i.MX23 Applications Processor Reference Manual, Rev. 1 38-2 Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. SG ES Freescale Semiconductor FU Digital Video Encoder Programmers' Manual 38.2.1 DU -- Data Input Unit This block receives the input video data, separates luma from chroma and sends them to the L_unit. If enabled, it generates color bars instead. In the case of the D1 input mode, it parses the control codes and generates appropriate horizontal and vertical blanking signals. 38.2.2 ES -- External Sync Unit This block receives the input sync signals (slave mode) or the sync signals generated by DU (D1 mode) and creates the horizontal and vertical reset signals that drive the sync block. These can be derived from rising or falling edges of input blanking signals, can be delayed by programmable amounts and accommodate the fixed pipeline-delay of the L-unit so that the sync signals produced by SG are defined in relation to the outputs of the L-unit. 38.2.3 SG -- Sync Generation Unit This block produces all the major timing and synchronization signals including sync, blanking and active video. The signals required to format closed caption and macrovision are also produced. Additional timing for special purposed is based on pixel and line counts outputted by this block. Signals used to format the activities of other blocks are shown in the diagram as unlabeled lines. In addition, all blocks use a pair of 27-MHz signals that toggle at 13.5 and 6.75 MHz rates. These are used to strobe interlaced pixels and to distinguish the color components, Cb or U and Cr or V. 38.2.4 FU -- Frequency Generation Unit This block generates the color subcarrier and also the sinusoid used in closed caption lead-in. The frequency and phase of the color subcarrier are programmable; the frequency of the closed caption waveform is hard-wired. 38.2.5 LU -- Low-pass and Other Signal Conditioning Filter Unit This block separates and up-samples the color components, performs low-pass filtering on both luma and chroma, and performs sharpness enhancement on the luma. 38.2.6 MX -- RGB Matrix Unit This block matrixes the filtered Y,U, and V to produce RGB or YPbPr component outputs. The 12-bit matrix coefficients are fully programmable on the range [-4,4). (N.B., one of the YUV to RGB matrix coefficients is greater than 2.0.) A signal is received from YU (dashed line labeled Y_RGB_BLANK in the diagram) that comprises sync, blanking and other signals (e.g., CGMS, macrovision, etc.) that are placed on the Y signal in CVBS or S-video. Under program control these luma-related signals can be imposed on one or more of the component outputs (e.g., Y of YPbPr). i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. 38-3 Digital Video Encoder Programmers' Manual 38.2.7 YU -- Y(luma)-main Unit This block produces the interlaced luma output (apart from interpolation to twice the pixel rate.) It scales the luma as appropriate for NTSC or PAL (rather for 714:286 vs 700:300 systems), and adds it to a base signal containing sync, blanking, pedestal and various special signals. It edge-shapes so that rise/fall constraints are met on sync edges, special signals and envelopes. This base signal is sent to the MX block, as discussed above, except that there may be some differences between the version appropriate for component and composite signals. (E.g, component might be 700:300 and composite 714:286.) 38.2.8 CU -- Chroma-main Unit This block produces the interlaced, base-band chroma output (apart from interpolation to twice the pixel rate.) It scales the chroma as appropriate for NTSC or PAL and adds the base-band form of the color burst. It insures that rise/fall constraints are met on burst edges and signal envelope. 38.2.9 Int -- Interpolation Block There are three copies of this block. In progressive mode, they interpolate the 3 component signals to 54 MHz. In interlaced modes, they interpolate both the component and composite signals to 27 MHz. They do this by time-share multiplexing the two groups of signals. Tthe main filter pipeline runs at 54 MHz in the progressive and 27 MHz in the interlaced case.. 38.2.10 OU -- (Composite) Output Unit This block produces the chroma part of the composite video signal by multiplying in-phase and quadrature base-band chroma signals by the corresponding sinusoids received from FU. The final composite output is then obtained by adding in the interpolated luma signal. 38.2.11 D/A -- D/A Selection Muxes There are 4 of these, one for each DAC output. As shown in the diagram, DAC-A outputs composite in interlaced or 0 in progressive modes. The others can output either component video or S-video under program control. (In the latter case, only 2 of the 3 are needed, so "D/A-C" continues to output one component output. Despite its being labeled as "B," it could in fact be any linear combination of YUV or even just Y_RGB_BLANK. 38.2.12 MV -- Macrovision Unit This block supports macrovision and will not be discussed in detail here. 38.2.13 WU -- WSS and CGMS Unit This block supports WSS for interlaced-PAL (625-line systems) and CGMS for both interlaced and progressive NTSC (525-line systems.) In both cases a special frequency is generated by phase accumulation and the requisite signal constructed on the proper line. The WSS signal is 14-data bits (bi-phase encoded) following a fixed run-in and start-code sequence. The CGMS is 14-data bits following i.MX23 Applications Processor Reference Manual, Rev. 1 38-4 Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. Freescale Semiconductor Digital Video Encoder Programmers' Manual a leading "10" pair and followed by a 6-bit CRC. The CRC is generated by logic in the WU block. Thus apart from enables, the payload in each case is 14-bits which are programmed via the host interface. 38.2.14 CC -- Closed Caption Unit The timing signals and clock for the closed caption are produced by the SU. The function of the cc-block is simply to enable closed caption output on top and/or bottom field and to receive and shift out the appropriate 16-bit data words. 38.2.15 HI -- Host Interface Unit This block holds the registers that are written by the external host to set-up and control the DVE. All registers can be read as well as written. Many registers have default values that can be used simply by identifying the picture format (e.g, NTSC, PAL-B, etc.), of which 8 are pre-defined. Other registers provide support for macrovision, closed-caption, WSS or CGMS. The host interfaces with this set of registers via a 32-bit data bus and a 4-bit address bus, plus strobe and R/W control. 38.3 Registers The host reads and writes registers in the HI_unit, "HI" in Figure 38-1. The DVE pins prefixed "hi_" are inputs to this unit used to write its registers. The signals prefixed "dv_hi" are driven by the HI_unit, as is dv_illeg_acc. Table 38-1 lists the registers writeable by the host in the DVE. An address such as "3" means that this register is written directly at address 3. An address such as "8.1" means that this register is written in a two step operation: first register "7" is written with the "subaddress", "1" in the example. Then the desired register value is written to address "8." This indirect addressing is necessary because there are more registers than the 16 permitted by a 4-bit address. Most registers concatenate a number of fields having different functions. The field column indicates what portion of the corresponding address holds the data described in the right column. Fields named with an initial "H_" are outputs of the HI_unit with that name. Unless otherwise noted fields marked "reserved" are "don't care" when written and are read as 0. Table 38-1. Registers in the HI_unit Writeable by Host Address Field Register/Field Contents 0 9:0 11:10 13:12 H_cnfg_s[9:0]: vector of controls for the ES block (see detailed description below) H_clk_phs[1:0]: sent to SG block; permits adjusting phase of pixel clock set at line-end H_cc_enbl[1:0] : closed caption enable (line 21) [0]: enables insertion in odd (top) field [1]: enables insertion in even (bottom) field H_color_bar_en: enable insertion of internally generated color bars 14 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. 38-5 Digital Video Encoder Programmers' Manual Table 38-1. Registers in the HI_unit Writeable by Host (continued) Address Field Register/Field Contents 23:15 25:24 H_cnfg_l[8:0]: vector of controls for the LU block (see detailed description below) H_cgain[1:0]: controls chroma gain for composite 00: NTSC gain 01: PAL gain 1x: no gain H_cnfg_y[4:0]: vector of controls for the YU block (see detailed description below) default_picform H_cnfg_m[9:0]: vector of controls for the MX block (see detailed description below) H_Svideo: enables S-video output on DACs B and D H_ydel_adj: delays luma versus chroma for composite output. Luma lags chroma by - 4 + H_ydel_adj cycles of 27 MHz clock In other words, if H_ydel_adj is zero, the luma leads by 4 cycles and if H_ydel_adj is 7, luma lags by 3 cycles reserved H_ysharp_bw: controls the filter bandwidth inside the ysharp block (see detailed description below) reserved H_HLC[9:0]: pixel count (pixels per line minus 1) H_VSO[9:0]: offset of internal vertical (frame) reset from external vertical sync H_HSO[10:0]: offset of internal horizontal (line) reset from external horizontal sync reserved H_phase_inc[31:0]: defines the frequency of the color subcarrier (see below) H_phase_offset[31:0]: phase offset for the color subcarrier wss_cgms_data[13:0]: payload for either wss or cgms cgms_enbl: enable cgms wss_enbl: enable wss reserved cc_data[15:0]: data to be outputted on line 21 (see discussion below) 30:26 31 1 9:0 10 13:11 14 15 31:16 2 9:0 19:10 30:20 31 3 4 5 31:0 31:0 13:0 14 15 31:16 6 15:0 i.MX23 Applications Processor Reference Manual, Rev. 1 38-6 Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. Freescale Semiconductor Digital Video Encoder Programmers' Manual Table 38-1. Registers in the HI_unit Writeable by Host (continued) Address Field Register/Field Contents 17:16 31:18 7 3:0 31:4 8.0 11:0 23:12 31:24 8.1 3:0 15:4 27:16 31:28 8.2 7:0 19:8 31:20 8.3 11:0 19:12 27:20 31:28 9.0 9.1 9.2 9.3 9.4 31:0 31:0 31:0 31:0 10:0 11 19:12 31:20 10.0 9:0 cc_fill[1:0]: flags to control and monitor data insertion on upper and lower fields reserved subaddr[3:0]: sets subaddress (after ".") in accessing next three register groups reserved bcoef_cb[11:0]: cb coefficient in b output bcoef_cr[11:0]: cr coefficient in b output bcoef_y[7:0]: y coefficient in b output bcoef_y[11:8]: y coefficient in b output gcoef_cb[11:0]: cb coefficient in g output gcoef_cr[11:0]: cr coefficient in g output gcoef_y[3:0]: y coefficient in g output gcoef_y[11:4]: y coefficient in g output rcoef_cb{11:0]: cb coefficient in r output rcoef_cr[11:0]: cr coefficient in r output rcoef_y[11:0]: y coefficient in r output H_PBA[7:0]: defines V component of color burst H_NBA[7:0]: defines U component of color burst reserved {N7,N6,N5,N4,N3,N2,N1}: registers defined in macrovision specs {N11[13:0],N10,N9,N8}: registers defined in macrovision specs {N14,N13,N12,N11[14]}: registers defined in macrovision specs {N0,N20,N19,N18,N17,N16,N15}: registers defined in macrovision specs {N22,N21}: registers defined in macrovision specs reserved macv_tst[7:0]: reserved -- must be written to 0 reserved sync_strt[9:0]: start of sync pulse in line or half-line (pixel count less 1) i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. 38-7 Digital Video Encoder Programmers' Manual Table 38-1. Registers in the HI_unit Writeable by Host (continued) Address Field Register/Field Contents 19:10 29:20 31:30 10.1 9:0 sync_end[9:0]: normal end of sync pulse in first half-line of video line (pixel count less 1) sync_srend[9:0]: end of sync pulse in each half line in serration region of vertical blanking (pixel count less 1) reserved sync_eqend[9:0]: end of sync puls in each half line in equalization regions of vertical blanking (pixel count less 1) actv_strt[9:0]: (horizontal) start of active video (pixel count less 1) actv_end[9:0]: (horizontal) end of active video (pixel count less 1) reserved nbrst_strt[9:0]: start of normal color burst (pixel count less 1) wbrst_strt[9:0]: start of wide color burst for macrovision (pixel count less 1) brst_end[9:0]: end of normal or wide color burst (pixel count less 1) reserved vstrt_subph[5:0]: last half-line of post-equalization; followed by "sub-phase" -- vertical blanking lines after post-equalization vstrt_actv[5:0]: last half-line of sub_phase; followed by active video vstrt_preeq[9:0]: last half-line of active video; followed by pre-equalization last_fld_ln[9:0]: last half-line of field -- usually same as vstrt_preeq vstrt_serra[5:0]: last half-line of pre-equalization; followed by serration vstrt_posteq[5:0]:last half-line of serration; followed by post-equalization H_y_blank_ctrl[1:0]: goes to YU (see discussion below) H_cs_invert_ctrl: goes to MV (see discussion below) H_agc_lvl_ctrl[1:0]: goes to MV (see discussion below) H_bruchb[1:0]: goes to SG (see discussion below) H_fsc_phase_rst[1:0]: goes to SG (see discussion below) 19:10 29:20 31:30 10.2 9:0 19:10 29:20 31:30 10.3 5:0 11:6 21:12 31:22 10.4 5:0 11:6 13:12 14 16:15 18:17 20:19 i.MX23 Applications Processor Reference Manual, Rev. 1 38-8 Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. Freescale Semiconductor Digital Video Encoder Programmers' Manual Table 38-1. Registers in the HI_unit Writeable by Host (continued) Address Field Register/Field Contents 21 22 31:23 H_pal_fsc_phase_alt: goes to SG (see discussion below) H_ntsc_ln_cnt: goes to SG (see discussion below) H_lpf_rst_off[8:0]: goes to ES (see discussion below) Apart from subaddr[3:0], discussed above, and default_picform which is used within the HI unit and will be discussed below, the register fields without a "H_" prefix" are assembed into larger buses for distribution. These buses are identified as follows: H_wss_cgms_word = {wss_enbl,cgms_enbl,wss_cgms_data[13:0]} H_cc_word = {cc_fill,cc_data[15:0]} H_mx_coef_bus ={rcoef_y, rcoef_cr, rcoef_cb, gcoef_y, gcoef_cr, gcoef_cb, bcoef_y, bcoef_cr, bcoef_cb} H_MACV_SU = {N20,N19,N18,N17,N16} H_MACV_EU={N21,N15,N14,N13,N12,N11,N10,N9,N8,N7,N6,N5,N4,N3,N2,N1} H_MACV_CTRL = N0 H_MACV_RGB = N22 H_PICFORM[133:0] = {vstrt_posteq, vstrt_serra, ast_fld_ln, vstrt_preeq, vstrt_actv, vstrt_subph, brst_end, wbrst_strt, nbrst_strt, actv_end, actv_strt, sync_eqend, sync_srend, sync_end, sync_strt} H_wss_cgms_word combines the controls and data for CGMS/WSS and is sent to WU. H_cc_word combines the controls and data for closed caption and is sent to CC. H_mx_coef_bus combines all the matrix coefficient for creating the component outputs and is sent to MX. H_MACV_SU contains those macrovision registers that relate to generation of timing signals and is sent to SG. H_MACV_EU contains most of the other macrovision registers and is sent to MV. H_MACV_CTRL holds the master control register for macrovision and is sent to MV. H_MACV_RGB holds a special control bit for insertion of macrovision on the component output and is sent to YU. H_PICFORM[133:0] combines all the parameters (apart from H_HLC) for defining the video format -half-lines per field and the locations of sync, blanking, burst and active video. It is sent to SG. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. 38-9 Digital Video Encoder Programmers' Manual 38.4 38.4.1 Function and Programming of Controls Register 0 fsync_enbl = H_cnfg_s[9], fsync_phs = H_cnfg_s[8], hsync_phs = H_cnfg_s[7], vsync_phs = H_cnfg_s[6], T_SYNC_MODE = H_cnfg_s[5:3]; T_ENCD_MODE = H_cnfg_s[2:0]. In register 0, H_cnfg_s[9:0], contains the following signals: T_ENCD_MODE identifies the video mode: 000: NTSC-M Mode 001: PAL-B Mode 010: PAL-M Mode 011: PAL-N Mode 100: PAL-CN Mode 101: NTSC with 700:300 scaling on "G" 110: PAL-60 Mode 111: NTSC progressive T_SYNC_MODE identifies the manner in which the input is synchronized to the display 000: Ext slave: 8-bit Y/C in, SYNC in 001: Ext slave: 16-bit Y/C in, SYNC in 010: Master: 011: Master: 1xx: D1 mode: 8-bit Y/C in, SYNC out 16-bit Y/C in, SYNC out 8-bit Y/C in, SYNC out In external-sync ("slave") mode, the rising edge of an external P_HSYNC_IN is used to derive the horizontal sync for the DVE block if hsync_phs = 0; otherwise the falling edge is used.. Similarly vsync_phs, selects the active edge of P_VSYNC_IN to generate the internal vertical timing in external sync mode. The actual horizontal reset is delayed relative to the designated edge of P_HSYNC_IN by H_HSO cycles of the 27-MHz clock, and the vertical reset is delayed by H_VSO lines relative to P_VSYNC_IN. (H_HSO and H_VSO are in register 2.) (In D1 mode, horizontal sync is taken from the leading edge of EAV and vertical sync from that of SFB. H_HSO and H_VSO are not used to delay the horizontal and vertical resets in this case.) i.MX23 Applications Processor Reference Manual, Rev. 1 38-10 Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. Freescale Semiconductor Digital Video Encoder Programmers' Manual The fsync_enbl and fsync_phs bits relate the internal field polarity to those of the input and/or output signals in interlaced modes. In the ASIC application, fsync_enbl can be taken to be 0; fsync_phs can be set to 1 for NTSC and to 0 for PAL. The 27 MHz clock is divided to generate 13.5 and 6.75 MHz timing signals. In 8-bit input mode these distinguish Cb,Y1,Cr,Y2. The H_clk_phs[1:0] can be used to adjust this phase at the beginning of a line. The value 00 has been used in all cases simulated to date. Closed caption is enabled for the NTSC upper field by H_cc_enbl[0] and for the lower field by H_cc_enbl[1]. (H_cc_word[17:0] is used to by the host to program the specific closed caption data, field by field.) When H_color_bar_en = 1, internally generated color bars are used as the video source instead of the video input data. The filtering of the video input is controlled by H_cnfg_l[8:0] = {ys_gainsel[1:0], ys_gainsgn, coefsel_clpf, ylpf_coefsel, sel_ysharp, sel_clpf, sel_ylpf, yd_offsetsel}. These parameters have the following significance: ys_gainsel[1:0] controls the degree of luma sharpness enhancement by luma sharpness filter: 00=3dB, 01=6dB, 10=9dB, 11=12dB. ys_gainsgn controls the sign of sharpness modification, 1 = negative, 0 = positive. coefsel_clpf controls the chroma low pass filter bandwidth: 1=0.6MHz, 0=1.3MHz. ylpf_coefsel controls the luma low pass filter bandwidth: 1=4.2MHz, 0=5.5MHz. sel_ysharp enables the luma sharpness filter. sel_clpf enables the chroma low pass filter sel_ylpf enables the luma low pass filter yd_offsetsel controls the luma offset: 1 = subtract 16 from luma, 0 = do not subtract The filtering is discussed further in a subsequent section. The next two fields mainly affect the composite output: H_cnfg_y[4:0] acts on the luma and H_cgain[1:0] on the chroma: cgain[1:0] controls the chroma gain: 00 = NTSC, 01 = PAL, 1x = no gain. H_cnfg_y consists of the following fields: tst_ygain_sel[1:0] = H_cnfg_y[1:0] controls the luma gain: 00 = NTSC, 01 = PAL, 1x = no gain. no_ped = H_cnfg_y[2]can be set to prevent insertion of a black pedestal as required by NTSC-J pal_shape = H_cnfg_y[3] is set to impose a 250 nSec edge shape as required by PAL, otherwise the steeper edges specified by NTSC are used. add_YPbPr_ped = H_cnfg_y[4] permits inserting a black pedestal when sync is inserted on one (or more) of the component signals. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. 38-11 Digital Video Encoder Programmers' Manual Finally, the msb, "default_picform," permits use of a set of default parameters, tailored to the mode defined by T_ENCD_MODE to be used in place of the registers a.0-a.4. This will be discussed further below. 38.4.2 Register 1 Register 1, holds additional key controls that must always be specified. H_cnfg_m controls the offset of the components signals. (The rgbmatrix outputs are signed 10-bit numbers. An offset is required to make the DAC inputs positive.) The offset can be either a fixed number or a sync/banking signal generated for this purpose by YU labeled Y_RGB_BLANK in Figure 1.. H_cnfg_m = {g_use_sync,rb_use_sync,rgb_blank_val[7:0]} g_use_sync: use the sync/blanking signal to offset the green output (This is the Y of YPbPr if the matrix coefficents are the unit matrix.) rb_use_sync: use the sync/blanking signal to offset the red and blue outputs. rgb_blank_va[7:0]: this defines the fixed offset used when the sync/blanking signal is not used as the offset. (This 8-bit value is multipled by 4 to create the 10-bit positive offset.) The other controls in this register are ysharp_bw, ydel_adj and Svideo. Their function was identified in the Table above. 38.4.3 Register 2 Register 2 holds values used to define the video line and field and to accommodate the format of the video input. These values must be set. However, in the ASIC environment, once they are calibrated for a particular format they never have to be changed. H_HSO[10:0] defines the horizontal linestart in counts of CK27 following the external sync edge (or EAV code in the case of D1) as discussed above in relation to hsync_phs. H_VSO[9:0] similarly defines the vertical fieldstart in units of lines following the designated edge of the external vertical sync (or SFB rising edge in D1). H_HLC[9:0] is a pixel count (pixels per line minus 1). It is set to 857 for NTSC (interlaced and progressive) and to 863 for PAL. 38.4.4 Registers 3 and 4 In register 3, H_phase_inc[31:0] defines the frequency of the color subcarrier. It is 32'h 21f07c1f for NTSC and 32'h 2a098acb for PAL-B. It is relevant only to the composite output. The units are such that a phase increment of 360o is entered as 32'h ffffffff. in register 4, H_phase_offset[31:0]; this is added to the phase as otherwise generated. The unit are the same as for phase_inc. It can ordinarily be set to 0; i.MX23 Applications Processor Reference Manual, Rev. 1 38-12 Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. Freescale Semiconductor Digital Video Encoder Programmers' Manual 38.4.5 Register 5 Register 5 is used to enable either WSS or CGMS, and to specify the data to be transmitted. The register contents are as follows: wss_enbl = enables WSS insertion for 625-line modes cgms_enbl enables CGMS insertion for 525-line modes (both interlaced and progresive.) wss_cgms_data[13:0] contains the data to be inserted. The run-in and start code for WSS are generated by the logic and do not have to be entered. Similarly the leading 2'b10 and the final CRC check word for the CGMS are automatically generated by the logic. 38.4.6 Register 6 Register 6,is used to load the closed caption data. Insertion of this data is only supported for 525-line interlaced systems.) The fields have the following significance on a write cc_fill[1:0] holds bits used to determine whether the two-bytes in cc_data are to be inserted in the odd (upper) field or the even (lower) field cc_data[15:0] is the actual data to be inserted. When this register is read, the cc_fill field holds flag bits indicating whether the corresponding data transfer has taken place. The host would use this register as follows: To program line 21 of the upper field, poll register 6 until cc_fill[0] is zero. Then write the required closed caption data to cc_data[15:0] with cc_fill[0] set to 1. This write to register 6 causes the data to be copied into a register in the cc_block that holds the next upper-field pair of bytes. Reading register 6 at this point would echo the data just written in bits 15:0 and a "1" in bit 16. This bit would continue to be read as a 1 until the data is transferred to a shift register at the beginning of the line 21 on which it is to be outputted. Any time thereafter the data for the corresponding line in the upper field of the next frame can be entered. The data for line 21 of the even field is similarly associated with c_fill[1]: it is set on a write to cause the data to be entered in a holding register; read as a one so long as that register should not be overwritten; and cleared to a 0 when the output on the corresponding line has started and the register is free for reprogramming. 38.4.7 Register group 8 The register 8 group must be written to define the rgbmatrix for the component output. The matrix coefficients are 12-bit signed quantities defined on the ranges (-2,+2). Together they form an 108-bit bus, H_mx_coef_bus[107:0], organized as {rcoef_y, rcoef_cr, rcoef_cb, gcoef_y, gcoef_cr, gcoef_cb,bcoef_y, bcoef_cr, bcoef_cb}. Here rcoef_y, for example, is the coefficient of y in forming the red output. The coefficient bus is entered as follows: H_mx_coef_bus[107:0] = {reg_8.3[11:0],reg_8.2,reg_8.1,reg_8.0}. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. 38-13 Digital Video Encoder Programmers' Manual The matrices used include the unit matrix for YPbPr 12'h0,12'h200,12'h0, 12'h200,12'h0,12'h0, 12'h0,12'h0,12'h200}; and the matrix used for RGB output 12'h260,12'h341,12'h0, 12'h260,12'he58,12'hf34, 12'h260,12'h0,12'h41d}. The remaining fields in register 8.3 are used to define the color burst. They are nba[7:0] = reg_8.3[27:20] = 8'h c8 (-56) pba[7:0] = reg_8.3[19:12] = 8'h 00 for NTSC and nba[7:0] = reg_8.3[27:20] = 8'h d6 (-42) pba[7:0] = reg_8.3[19:12] = 8'h 2a (+42) for PAL-B. 38.4.8 Macrovision Registers Macrovision (register group 9) is on by default, configured for NTSC interlaced. This has no effect on the component outputs so long as the sync does not appear on them, i.e., so long as g_use_sync = 0 and rb_use_sync = 0. 38.4.9 Register group 10 The first group of parameters in the register 10 group define the features of a video line either in active video region or in the vertical sync regions. The features are defined on the basis of "pixel_cnt[9:0]". For interlaced formats, pixel_cnt[8:0] is the pixel count in the half line incremented at the 13.5 MHz rate, and pixel_cnt[9] is a flag set to 0 for the first half-line of a video line and set to 1 for the second half line. The pixel_cnt[8:0] is reset to zero after H_HLC cycles of 27 MHz. (That is the total length of the half-line is H_HLC + 1 cycles of 27 MHz. For progressive NTSC, pixel_cnt[9:0] is incremented for full line which has H_HLC + 1 pixels at 27 MHz. The location of the zero of pixel_cnt defines the start of the front-porch region of the video line. In all cases, the falling edge of sync is defined by sync_strt; the falling edge occurs immediately after pixel number "sync_strt." These falling edges are thus absolutely regular throughout the active video and vertical blanking regions. For interlaced formats, there is a sync pulse in each half-line of the pre-equalization, serration and post-equalization segmets of vertical blanking. Otherwise the sync pulse occurs only in the first half-line. (There is no second half line in the pregressive case.) i.MX23 Applications Processor Reference Manual, Rev. 1 38-14 Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. Freescale Semiconductor Digital Video Encoder Programmers' Manual All other horizontal features are located in the same way: a pixel count after the beginning of the half-line (interlaced) or line (progressive.) Thus on active video lines, the last pixel of the sync pulse is given by "sync_end." The end for the serration pulse is "sync_srend" and that for the equalization pulse is "sync_eqend." The start and end of the color burst, and the start of active video are given in exactly the same manner. Normally all these quantities refer to the first half-line so their bit-9 is zero. For interlaced, the end of active video, specified by actv_end[9:0], is typically in the second half line. Thus actv_end[9] is "1" and does not represent an increment of 512 pixels but rather the number in a half line. (For NTSC the number of pixels per half-line is 429.) Vertical formatting uses a half-line counter for interlaced formats, a line counter for progressive. Each region is programmed by specifying the last half-line of the preceding region. Field begins with the pre-equalization region, then comes serration followed by post-equalization, sub-phase and active video. The field size is defined by last_fld_ln. Ordinarily the pre-equalization region begins with the first line of the field so that last_fld_ln and vstrt_preeq are the same quantity. In NTSC for example, pre-equalization begins with the first half line of the field and occupies 3 full lines. The comes serration. Thus vstrt_serra is 5 which is the last half line of the 6 occupied by the pre-equalization regions. Similarly, the serration also occupies 3 lines, so its last half-line is 11. It is followed by the post-equalization region, so that vstrt_posteq = 11, and so forth for the subsequent regions. In particular, there are 525 half lines in the field, so last_fld_ln = vstrt_preeq = 524. The remaining parameters in register 10.4 form a rather miscellaneous group of controls H_y_blank_ctrl[1:0] goes to YU where it controls the blanking level 00: 700:300 blanking for progressive 01: 714:286 blanking on both composite and component 10: 714:286 for blanking for composite and 700:300 blanking for component 11: 700:300 blanking for PAL systems H_agc_lvl_ctrl[1:0] goes to MV for control of AGC levels 00: for "mixed NTSC" -i.e., 714:286 on composite and 700:300 on component 01: for NTSC 10: for PAL 11: for progressive H_cs_invert_ctrl goes to MV to disable illegal modes of color-stripe inversion H_bruchb[1:0] goes to SG to control mode of Bruch blanking 00: for progressive 01: for 525 line cases with NTSC color 10: for PAL-M and Pal-60 11: other PAL cases H_fsc_phase_rst[1:0] goes to SG to control timing of color subcarrier phase reset 00: for progressive i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. 38-15 Digital Video Encoder Programmers' Manual 01: for NTSC 10: for PAL-M, PAL-N and Pal-60 11: other PAL cases H_pal_fsc_phase_alt goes to SG to enable PAL-manner of phase alternation by field of color subcarrier H_ntsc_ln_cnt goes to SG to align even-odd field identification with internal field count; expected value is "1" for ntsc and "0" for PAL-B H_lpf_rst_off[8:0] goes to ES to program the time to generate a pulse so as to preload a pipeline in the y_delay module of the L_unit. The value is found by simulation to be 272 for NTSC in D1 mode, 284 for PAL in D1 mode, and 136 for progressive in external sync mode. If "default_picform" in register 0 is set to1, all the parameters programmable through the register-10 group are instead assigned hardwired values determined by T_ENCD_MODE. However, if even one of these parameters needs to be given a different value, the entire register-10 group must be written and default_picform set to 0. To make this process easier, the hardwired values for all registers and modes are given in Table 38-2. Table 38-2. Hardwired Registers Values mode 10.0 10.1 10.2 10.3 10.4 000 NTSC 001 PAL-B 010 PAL-M 011 PAL-N 100 PAL-CN 101 mixed NTSC 110 PAL-60 111 prog NTSC 17b1340 e 17c1340 e 17b1340 e 17b1340 e 17c1340 e 17b1340 e 17b1340 e 32a1380f 3a42242 d 3a72642 d 3a72642 d 3a725c2 d 3a72642 d 3a42242 d 3a72642 d 359224xx (*) 07b1445 9 0771405 8 07f1505c 07e1505 c 07a1405 8 07b1445 9 07f1505c xxxxxxxx (*) 8320ca5 1 9c270c4e 8320ca5 1 9c270c51 9c270c4e 8320ca5 1 8320ca5 1 8320bacx (*) 884a92c 5 0471f244 0443a2c 5 0471b2c 5 0471f244 044252c 5 0443a2c 5 022202c 5 (*) The parameters sync_eqend, wbrst_strt, nbrst_strt, brst_end, vstrt_subph are not used for progressive. The corresponding fields are "don't care." i.MX23 Applications Processor Reference Manual, Rev. 1 38-16 Preliminary--Subject to Change Without Notice This page is reproduced with permission of the Sarnoff Corporation. Freescale Semiconductor Chapter 39 Register Macro Usage This chapter provides background on the i.MX23 register set and illustrates a consistent use of the C macros for registers. The examples provided here show how to use the hardware register macros generated from the chip database. 39.1 Background The i.MX23 SOC is built on a 32-bit architecture using an ARM926 core. All hardware blocks are controlled and accessed through 32-bit wide registers. The design of these registers is maintained in a database that is part of the overall chip design. As part of the chip build process, a set of C include files are generated from the register descriptions. These include files provide a consistent set of C defines and macros that should be used to access the hardware registers. The i.MX23 SOC has a complex architecture that uses multiple buses to segment I/O traffic and clock domains. To facilitate low power consumption, clocks are set to just meet application demands. In general, the I/O buses and associated hardware blocks run at speeds much slower than the CPU. As a result, reading a hardware register incurs a potentially large number of wait cycles, as the CPU must wait for the register data to travel multiple buses and bridges. The SOC does provide write buffering, meaning the CPU does not wait for register write transactions to complete. From the CPU perspective, register writes occur much faster than reads. Most of the 32-bit registers are subdivided into smaller functional fields. These bit fields can be any number of bits wide and are usually packed. Thus, most fields do not align on byte or half-word boundaries. A common operation is to update one field without disturbing the contents of the remaining fields in the register. Normally, this requires a read-modify-write (RMW) operation, where the CPU reads the register, modifies the target field, then writes the results back to the register. As already noted, this is an expensive operation in terms of CPU cycles, because of the initial register read. To address this issue, most hardware registers are implemented as a set, including registers that can be used to either set, clear, or toggle (SCT) individual bits of the primary register. When writing to an SCT register, all bits set to 1 perform the associated operation on the primary register, while all bits set to 0 are not affected. The SCT registers always read back 0, and should be considered write-only. The SCT registers are not implemented if the primary register is read-only. With this architecture, it is possible to update one or more fields using only register writes. First, all bits of the target fields are cleared by a write to the associated clear register, then the desired value of the tari.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39-1 Register Macro Usage get fields is written to the set register. This sequence of two writes is referred to as a clear-set (CS) operation. A CS operation does have one potential drawback. Whenever a field is modified, the hardware sees a value of 0 before the final value is written. For most fields, passing through the 0 state is not a problem. Nonetheless, this behavior is something to consider when using a CS operation. Also, a CS operation is not required for fields that are one bit wide. While the CS operation works in this case, it is more efficient to simply set or clear the target bit (i.e., one write instead of two). A simple set or clear operation is also atomic, while a CS operation is not. Note that not all macros for set, clear, or toggle (SCT) are atomic. For registers that do not provide hardware support for this functionality, these macros are implemented as a sequence of read/modify/write operations. When atomic operation is required, the developer should pay attention to this detail, because unexpected behavior might result if an interrupt occurs in the middle of the critical section comprising the update sequence. 39.2 Naming Convention The generated include files and macros follow a consistent naming convention that matches the SOC documentation. This prevents name-space collisions and makes the macros easier to remember. // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // The include file for a specific hardware module is named: regs i.MX23 Applications Processor Reference Manual, Rev. 1 39-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Macro Usage // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // Macros and defines that relate to the fields of a register are named: BM_ The C++ style comments above represent a single-instance block. For multiple-instance blocks, the macros are similar, but have an instance number as the first parameter where needed. (Differences only shown below.) Note: x is the block instance number. If shown, v is the value field for the macro. // // // // // // // // // // // // // // // // HW_ i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39-3 Register Macro Usage // // // // // // Macros and defines that relate to the fields of a register are named: BW_ 39.2.1 Multi-Instance Blocks Additionally, newer silicon architecture adds the concept of Multi-Instance Blocks which is similar to Multi-Instance Registers, although a Multi-Instance Block may also contain Multi-Instance Registers (There are none in the i.MX23). In order to accommodate that (and additional chips going forward) Multi-Instance Blocks have a required additional parameter specifying the block number but use otherwise identical nomenclature. This also allows runtime usage of different blocks (perhaps unifying driver models) without recompilation or near-duplication of code and run-time selection of macros. The i.MX23 SOC starts all block instances from 1. 39.2.1.1 Examples The SSP has two instances (numbered 1 and 2). To access the CTRL0 register in that block, instead of having two separate include files with hard coded macros, one can use the following: HW_SSP_CTRL0_WR(instance, value); where instance is 1 or 2, and value is (in this case) the 32 bit value to be written to the SSP_CTRL0 register in the block specified by instance. 39.3 Examples The following examples show how to code common register operations using the predefined include files. Each example shows preferred and alternate syntax and also shows constructs to avoid. Summaries are provided toward the end. The examples are valid C and will compile without errors. The reader is encouraged to compile this file and examine the resulting assembly code. 39.3.1 Setting 1-Bit Wide Field // Preferred (one atomic write to SET register) HW_GPMI_CTRL0_SET(BM_GPMI_CTRL0_UDMA); // Alternate (same as above, just different syntax) BF_SET(GPMI_CTRL0, UDMA); // Avoid BW_GPMI_CTRL0_UDMA(1); BF_WR(GPMI_CTRL0, UDMA, 1); HW_GPMI_CTRL0.B.UDMA = 1; // writes 1 to _CLR then 1 to _SET register // same as above, just different syntax // RMW i.MX23 Applications Processor Reference Manual, Rev. 1 39-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Macro Usage 39.3.2 Clearing 1-Bit Wide Field // Preferred (one atomic write to _CLR register) HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_DEV_IRQ_EN); // Alternate (same as above, just different syntax) BF_CLR(GPMI_CTRL0, DEV_IRQ_EN); // Avoid BW_GPMI_CTRL0_DEV_IRQ_EN(0); BF_WR(GPMI_CTRL0, DEV_IRQ_EN, 0); HW_GPMI_CTRL0.B.DEV_IRQ_EN = 0; // writes 1 to _CLR then 0 to _SET register // same as above, just different syntax // RMW 39.3.3 Toggling 1-Bit Wide Field // Preferred (one atomic write to _TOG register) HW_GPMI_CTRL0_TOG(BM_GPMI_CTRL0_RUN); // Alternate (same as above, just different syntax) BF_TOG(GPMI_CTRL0, RUN); // Avoid HW_GPMI_CTRL0.B.RUN ^= 1; // RMW 39.3.4 Modifying n-Bit Wide Field // Preferred (does CS operation or byte/halfword write if the field is // 8 or 16 bits wide and properly aligned) BW_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE); BW_GPMI_CTRL0_COMMAND_MODE(iMode); BW_GPMI_CTRL0_XFER_COUNT(2); // this does a halfword write // Alternate (same as above, just different syntax) BF_WR(GPMI_CTRL0, COMMAND_MODE, BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE); BF_WR(GPMI_CTRL0, COMMAND_MODE, iMode); BF_WR(GPMI_CTRL0, XFER_COUNT, 2); // this does a halfword write // Avoid (RMW) HW_GPMI_CTRL0.B.COMMAND_MODE = BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE; HW_GPMI_CTRL0.B.COMMAND_MODE = iMode; 39.3.5 Modifying Multiple Fields // Preferred (explicit CS operation) HW_GPMI_CTRL0_CLR( OR3(BM_GPMI_CTRL0, RUN, DEV_IRQ_EN, COMMAND_MODE) ); HW_GPMI_CTRL0_SET( OR3(BF_GPMI_CTRL0, RUN(iRun), DEV_IRQ_EN(1), COMMAND_MODE_V(READ_AND_COMPARE)) ); // Alternate (same as above, just different syntax) BF_CS3(GPMI_CTRL0, RUN, iRun, DEV_IRQ_EN, 1, COMMAND_MODE, BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE); // Avoid (multiple RMW - the HW_GPMI_CTRL0.B.RUN HW_GPMI_CTRL0.B.DEV_IRQ_EN HW_GPMI_CTRL0.B.COMMAND_MODE C = = = compiler does NOT merge into one RMW) iRun; 1; BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE; i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39-5 Register Macro Usage 39.3.6 Writing Entire Register (All Fields Updated at Once) // Preferred HW_GPMI_CTRL0_WR(BM_GPMI_CTRL0_SFTRST); // all other fields are set to 0 // Alternate (same as above, just different syntax) HW_GPMI_CTRL0.U = BM_GPMI_CTRL0_SFTRST; 39.3.7 Reading a Bit Field // Preferred iRun = HW_GPMI_CTRL0.B.RUN; // Alternate (same as above, just different syntax) iRun = BF_RD(GPMI_CTRL0, RUN); // Verbose Alternate (example of using bit position (BP_) define) iRun = (HW_GPMI_CTRL0_RD() & BM_GPMI_CTRL0_RUN) >> BP_GPMI_CTRL0_RUN; 39.3.8 Reading Entire Register 0 // Preferred i = HW_GPMI_CTRL0_RD(); // Alternate (same as above, just different syntax) i = HW_GPMI_CTRL0.U; 39.3.9 Accessing Multiple Instance Register // Preferred for (i = 0; i < HW_TIMROT_TIMCTRLn_COUNT; i++) { // Set 1-bit wide field HW_TIMROT_TIMCTRLn_SET(i, BM_TIMROT_TIMCTRLn_IRQ_EN); // Write n-bit wide field BW_TIMROT_TIMCTRLn_PRESCALE(i, BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1); // Write multiple fields HW_TIMROT_TIMCTRLn_CLR(i, OR2(BM_TIMROT_TIMCTRLn, RELOAD, SELECT)); HW_TIMROT_TIMCTRLn_CLR(i, OR2(BF_TIMROT_TIMCTRLn, RELOAD(1), SELECT_V(1KHZ_XTAL))); // Read a field iRun = HW_TIMROT_TIMCTRLn(i).B.IRQ; } // Alternate (same as above, just different syntax) for (i = 0; i < HW_TIMROT_TIMCTRLn_COUNT; i++) { // Set 1-bit wide field BF_SETn(TIMROT_TIMCTRLn, i, IRQ_EN); // Write n-bit wide field BF_WRn(TIMROT_TIMCTRLn, i, PRESCALE, BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1); // Write multiple fields i.MX23 Applications Processor Reference Manual, Rev. 1 39-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Macro Usage BF_CS2n(TIMROT_TIMCTRLn, i, RELOAD, 1, SELECT, BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL); // Read a field iRun = BF_RDn(TIMROT_TIMCTRLn, i, IRQ); } 39.3.10 Correct Way to Soft Reset a Block // Prepare for soft-reset by making sure that SFTRST is not currently // asserted. Also clear CLKGATE so we can wait for its assertion below. HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST); // Wait at least a microsecond for SFTRST to deassert. In actuality, we // need to wait 3 GPMI clocks, but this is much easier to implement. musecs = hw_profile_GetMicroseconds(); while (HW_GPMI_CTRL0.B.SFTRST || (hw_profile_GetMicroseconds() - musecs < DDI_NAND_HAL_GPMI_SOFT_RESET_LATENCY)); // Also clear CLKGATE so we can wait for its assertion below. HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE); // Now soft-reset the hardware. HW_GPMI_CTRL0_SET(BM_GPMI_CTRL0_SFTRST); // Poll until clock is in the gated state before subsequently // clearing soft reset and clock gate. while (!HW_GPMI_CTRL0.B.CLKGATE) { ; // busy wait } // bring GPMI_CTRL0 out of reset HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST); // Wait at least a microsecond for SFTRST to deassert. In actuality, we // need to wait 3 GPMI clocks, but this is much easier to implement. musecs = hw_profile_GetMicroseconds(); while (HW_GPMI_CTRL0.B.SFTRST || (hw_profile_GetMicroseconds() - musecs < DDI_NAND_HAL_GPMI_SOFT_RESET_LATENCY)); HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE); // Poll until clock is in the NON-gated state before returning. while (HW_GPMI_CTRL0.B.CLKGATE) { ; // busy wait } 39.3.10.1 Pinmux Selection During Reset For proper I2C operation, the appropriate pinmux(s) must be selected before taking the block out of reset. Failure to select the I2C pinmux selections before taking the block out of reset will cause the I2C clock to operate incorrectly and will require another I2C hardware reset. i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39-7 Register Macro Usage 39.3.10.1.1 Correct and Incorrect Reset Examples Incorrect: Clear I2C SFTRST/CLKGATE ... Setup ... I2C PinMux Selections ** I2C will not operate. Correct: I2C PinMux Selections Clear I2C SFTRST/CLKGATE ... Setup ... ** I2C operates correctly. 39.4 Summary Preferred // Setting, clearing, toggling 1-bit wide field HW_GPMI_CTRL0_SET(BM_GPMI_CTRL0_UDMA); HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_DEV_IRQ_EN); HW_GPMI_CTRL0_TOG(BM_GPMI_CTRL0_RUN); // Modifying n-bit wide field BW_GPMI_CTRL0_XFER_COUNT(2); // Modifying multiple fields HW_GPMI_CTRL0_CLR( OR3(BM_GPMI_CTRL0, RUN, DEV_IRQ_EN, COMMAND_MODE) ); HW_GPMI_CTRL0_SET( OR3(BF_GPMI_CTRL0, RUN(iRun), DEV_IRQ_EN(1), COMMAND_MODE_V(READ_AND_COMPARE)) ); // Reading a bit field iRun = HW_GPMI_CTRL0.B.RUN; // Writing or reading entire register (all fields updated at once) HW_GPMI_CTRL0_WR(BM_GPMI_CTRL0_SFTRST); i = HW_GPMI_CTRL0_RD(); 39.5 Summary Alternate Syntax // Setting, clearing, toggling 1-bit wide field BF_SET(GPMI_CTRL0, UDMA); BF_CLR(GPMI_CTRL0, DEV_IRQ_EN); BF_TOG(GPMI_CTRL0, RUN); // Modifying n-bit wide field BF_WR(GPMI_CTRL0, XFER_COUNT, 2); // Modifying multiple fields BF_CS3(GPMI_CTRL0, RUN, iRun, DEV_IRQ_EN, 1, COMMAND_MODE, BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE); // Reading a bit field iRun = BF_RD(GPMI_CTRL0, RUN); i.MX23 Applications Processor Reference Manual, Rev. 1 39-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Macro Usage // Writing or reading entire register (all fields updated at once) HW_GPMI_CTRL0.U = BM_GPMI_CTRL0_SFTRST; i = HW_GPMI_CTRL0.U; 39.6 Assembly Example // The generated include files are safe to use with assembly code as well. Not // all of the defines make sense in the assembly context, but many should prove // useful. // // HW_ i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39-9 Register Macro Usage i.MX23 Applications Processor Reference Manual, Rev. 1 39-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 40 Memory Map The following table shows the memory map in the i.MX23 as seen by the processor. Any blank entries indicate that nothing is mapped at that address. No accesses should be made to these addresses since the results are indeterminate. The Decode Block column indicates the decode group to which each peripheral belongs. Most peripherals reside on the APBH or APBX peripheral busses. Table 40-1. Address Map for i.MX23 DECODE BLOCK DEVICE MNEMONIC START ADDRESS END ADDRESS SIZE AHB On-chip RAM On-chip RAM alias External Memory Default Slave OCRAM OCRAM 0x00000000 0x00008000 0x40000000 0x60000000 0x00007FFF 0x3FFFFFFF 0x5FFFFFFF 0x7FFFFFFF 32KB 512MB 512MB i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 40-1 Memory Map Table 40-1. Address Map for i.MX23 (continued) DECODE BLOCK DEVICE MNEMONIC START ADDRESS END ADDRESS SIZE APBH Interrupt Controller APBH DMA Reed-Solomon ECC BCH ECC General Purpose Media Interface Sync Serial Port 1 Embedded Trace Module Pin Control Digital Control External Memory Interface APBX DMA Data CoProcessor Pixel Pipeline One-time Programmable Array Controller AXI Control LCD Interface Sync Serial Port 2 TV Encoder Reserved ICOLL APBHDMA ECC8 BCH GPMI 0x80000000 0x80002000 0x80004000 0x80006000 0x80008000 0x8000A000 0x8000C000 0x8000E000 0x80001FFF 0x80003FFF 0x80005FFF 0x80007FFF 0x80009FFF 0x8000BFFF 0x8000DFFF 0x8000FFFF 0x80011FFF 0x80013FFF 0x80015FFF 0x80017FFF 0x80019FFF 0x8001BFFF 0x8001DFFF 0x8001FFFF 0x80021FFF 0x80023FFF 0x80025FFF 0x80027FFF 0x80029FFF 0x8002BFFF 0x8002DFFF 0x8002FFFF 0x80031FFF 0x80033FFF 0x80035FFF 0x80037FFF 0x80039FFF 0x8003BFFF 0x8003DFFF 0X8003FFFF 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB SSP1 ETM PINCTRL DIGCTL EMI APBXDMA DCP PXP OCOTP AXI LCDIF SSP2 TVENC 0x80010000 0x80012000 0x80014000 0x80016000 0x80018000 0x8001A000 0x8001C000 0x8001E000 0x80020000 0x80022000 0x80024000 0x80026000 0x80028000 0x8002A000 0x8002C000 0x8002E000 0x80030000 0x80032000 0x80034000 0x80036000 0x80038000 0x8003A000 0x8003C000 0X8003E000 i.MX23 Applications Processor Reference Manual, Rev. 1 40-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Memory Map Table 40-1. Address Map for i.MX23 (continued) DECODE BLOCK DEVICE MNEMONIC START ADDRESS END ADDRESS SIZE APBX Clock Controller Sync Audio Interface Power Control Sync Audio Interface Digital Audio Filter Output Digital Audio Filter Input Low Resolution ADC Sony/Phillips Digital Audio Interface I2C Real Time Clock CLKCTRL SAIF1 PWR SAIF2 AUDIOOUT 0x80040000 0x80042000 0x80044000 0x80046000 0x80048000 0x8004A000 0x80041FFF 0x80043FFF 0x80045FFF 0x80047FFF 0x80049FFF 0x8004BFFF 0x8004DFFF 0x8004FFFF 0x80051FFF 0x80053FFF 0x80055FFF 0x80057FFF 0x80059FFF 0x8005BFFF 0x8005DFFF 0x8005FFFF 0x80061FFF 0x80063FFF 0x80065FFF 0x80067FFF 0x80069FFF 0x8006BFFF 0x8006DFFF 0x8006FFFF 0x80071FFF 0x80073FFF 0x80075FFF 0x80077FFF 0x80079FFF 0x8007BFFF 0x8007DFFF 0x8007FFFF 0x800BFFFF 0x800CFFFF 0x800DFFFF 0x800EFFFF 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 256KB 64KB 64KB 64KB AUDIOIN 0x8004C000 0x8004E000 LRADC SPDIF 0x80050000 0x80052000 0x80054000 0x80056000 I2C RTC 0x80058000 0x8005A000 0x8005C000 0x8005E000 0x80060000 0x80062000 Pulse Width Modulation Timers/Rotary Interface Application UART 1 Application UART 2 Debug UART PWM TIMROT APPUART1 APPUART2 DBGUART 0x80064000 0x80066000 0x80068000 0x8006A000 0x8006C000 0x8006E000 0x80070000 0x80072000 0x80074000 0x80076000 0x80078000 0x8007A000 USB Physical Interface AHB USB Controller USBPHY USB 0x8007C000 0x8007E000 0x80080000 0x800C0000 0x800D0000 DRAM Registers DRAM 0x800E0000 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 40-3 Memory Map Table 40-1. Address Map for i.MX23 (continued) DECODE BLOCK DEVICE MNEMONIC START ADDRESS END ADDRESS SIZE DRAM Registers ROM ROM alias DRAM OCROM OCROM 0x800F0000 0x80100000 0xC0000000 0xC0010000 0x800FFFFF 0xBFFFFFFF 0xC000FFFF 0xFFFFFFFF 64KB 64KB i.MX23 Applications Processor Reference Manual, Rev. 1 40-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 41 i.MX23 Part Numbers and Ordering Information The i.MX23 family comprises a set of parts targeted at specific applications and customers. Table 41-1 summarizes the family members and provides part numbers for order placement. Table 41-1. Part Numbers for i.MX23 Family Members Description Part Number Package Speed Ambient Temperature Range i.MX233, Industrial, 169BGA i.MX233, Industrial, 128QFP i.MX233, Commercial, 169BGA i.MX233, Commercial, 128QFP MCIMX233CJM4B MCIMX233CAG4B MCIMX233DJM4B MCIMX233DAG4B 169-pin BGA 128-pin LQFP 169-pin BGA 128-pin LQFP 454 MHz 454 MHz 454 MHz 454 MHz -40 to 85 -40 to 85 -10 to 70 -10 to 70 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 41-1 i.MX23 Part Numbers and Ordering Information i.MX23 Applications Processor Reference Manual, Rev. 1 41-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Chapter 42 Package Drawings The i.MX23 is offered in two different packages, which are illustrated in this chapter: * * Section 42.1, "169-Pin Ball Grid Array (BGA)" Section 42.2, "128-Pin Low-Profile Quad Flat Package (LQFP)" i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 42-1 Package Drawings 42.1 169-Pin Ball Grid Array (BGA) DETAIL B aaa 2x C E B A 13 12 10 8 6 4 2 PIN A1 INDEX Pin A1 1 A B C D E F G H J K L M N 11 9 7 5 3 D (DATUM A) e D1 aaa 2x C (DATUM B) e E1 TOP VIEW DETAIL A BOTTOM VIEW f NX b eee M fff M f CAB C SIDE VIEW e 4 8 bbb C DETAIL B A SEATING PLANE A1 5 NX C ddd C 6 DETAIL A 169 fpBGA (11 x 11 mm) ALL DIMENSIONS ARE IN MILLIMETERS . DIMENSIONAL REFERENCES REF. A A1 D D1 E E1 b e f aaa bbb ddd eee fff M N 13 169 0.60 0.37 10.80 MIN. 1.14 0.21 10.80 NOM. 1.30 0.28 11.00 9.60 BSC 11.00 9.60 BSC 0.43 0.80 BSC 0.70 0.80 0.10 0.10 0.15 0.15 0.08 0.49 11.20 MAX. 1.43 0.35 11.20 'e' REPRESENTS THE BASIC SOLDER BALL GRID PITCH . 'M' REPRESENTS THE BASIC SOLDER BALL MATRIX SIZE. SYMBOL 'N' IS THE NUMBER OF BALLS IN THE BALL MATRIX . 'b' IS MEASURABLE AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM C. DIMENSION 'ddd' IS MEASURED PARALLEL TO PRIMARY DATUM C . PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. SOLDER BALL DIAMETER 'b' REFERS TO POST REFLOW CONDITION . THE PRE-REFLOW DIAMETER IS 0.40mm. SUBSTRATE MATERIAL BASE IS BT RESIN. THE OVERALL PACKAGE THICKNESS 'A' ALREADY CONSIDERS COLLAPSE BALLS. DIMENSIONING AND TOLERENCING PER ASME Y 14.5-1994. PACKAGE DIMENSIONS TAKE REFERENCE TO JEDEC MO-205 F. Figure 42-1. 169-Pin BGA Package Drawing i.MX23 Applications Processor Reference Manual, Rev. 1 42-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Package Drawings 42.2 128-Pin Low-Profile Quad Flat Package (LQFP) Figure 42-2. 128-Pin Low-Profile Quad Flat Pack (LQFP) Package Drawing i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 42-3 Package Drawings i.MX23 Applications Processor Reference Manual, Rev. 1 42-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Appendix A Revision History This appendix provides a list of the major differences between the i.MX23 Applications Processor Reference Manual Reference Manual, Revision 0 through Revision 1. A.1 Changes From Revision 0 to Revision 1 Major changes to the i.MX23 Applications Processor Reference Manual Reference Manual, from Revision 0 to Revision 1, are as follows: Section, Page Changes Book Chapter 2/2-1 Chapter 12/12-1 Added Sarnoff DVE Chapter. Added revision history as Appendix A. Updated 169BGA Operating States Table Added 128QFP Operating States Table Added 128QFP EMICLK data. Updated Power Supply Characteristics table Updated VDD5V Absolute Maximum specification. Updated 169-BGA Package Thermal Impedance value. Added DCDC Efficiency curves. Added Denali Databahn User Manual content: i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice A-1 Revision History i.MX23 Applications Processor Reference Manual, Rev. 1 A-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Appendix B Register Names Table B-1 lists the i.MX23 register names and addresses in alphabetical order by register mnemonic. Table B-1. Register Names and Addresses Register Name DFLPT_PTE_2048 HW_APBH_CH0_BAR HW_APBH_CH0_CMD HW_APBH_CH0_CURCMDAR HW_APBH_CH0_DEBUG1 HW_APBH_CH0_DEBUG2 HW_APBH_CH0_NXTCMDAR HW_APBH_CH0_SEMA HW_APBH_CH1_BAR HW_APBH_CH1_CMD HW_APBH_CH1_CURCMDAR HW_APBH_CH1_DEBUG1 HW_APBH_CH1_DEBUG2 HW_APBH_CH1_NXTCMDAR HW_APBH_CH1_SEMA HW_APBH_CH2_BAR HW_APBH_CH2_CMD HW_APBH_CH2_CURCMDAR HW_APBH_CH2_DEBUG1 HW_APBH_CH2_DEBUG2 HW_APBH_CH2_NXTCMDAR HW_APBH_CH2_SEMA HW_APBH_CH3_BAR HW_APBH_CH3_CMD HW_APBH_CH3_CURCMDAR HW_APBH_CH3_DEBUG1 Address 0x800C2000 0x80004070 0x80004060 0x80004040 0x80004090 0x800040A0 0x80004050 0x80004080 0x800040E0 0x800040D0 0x800040B0 0x80004100 0x80004110 0x800040C0 0x800040F0 0x80004150 0x80004140 0x80004120 0x80004170 0x80004180 0x80004130 0x80004160 0x800041C0 0x800041B0 0x80004190 0x800041E0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-1 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_APBH_CH3_DEBUG2 HW_APBH_CH3_NXTCMDAR HW_APBH_CH3_SEMA HW_APBH_CH4_BAR HW_APBH_CH4_CMD HW_APBH_CH4_CURCMDAR HW_APBH_CH4_DEBUG1 HW_APBH_CH4_DEBUG2 HW_APBH_CH4_NXTCMDAR HW_APBH_CH4_SEMA HW_APBH_CH5_BAR HW_APBH_CH5_CMD HW_APBH_CH5_CURCMDAR HW_APBH_CH5_DEBUG1 HW_APBH_CH5_DEBUG2 HW_APBH_CH5_NXTCMDAR HW_APBH_CH5_SEMA HW_APBH_CH6_BAR HW_APBH_CH6_CMD HW_APBH_CH6_CURCMDAR HW_APBH_CH6_DEBUG1 HW_APBH_CH6_DEBUG2 HW_APBH_CH6_NXTCMDAR HW_APBH_CH6_SEMA HW_APBH_CH7_BAR HW_APBH_CH7_CMD HW_APBH_CH7_CURCMDAR HW_APBH_CH7_DEBUG1 HW_APBH_CH7_DEBUG2 HW_APBH_CH7_NXTCMDAR HW_APBH_CH7_SEMA HW_APBH_CTRL0 HW_APBH_CTRL0_CLR Address 0x800041F0 0x800041A0 0x800041D0 0x80004230 0x80004220 0x80004200 0x80004250 0x80004260 0x80004210 0x80004240 0x800042A0 0x80004290 0x80004270 0x800042C0 0x800042D0 0x80004280 0x800042B0 0x80004310 0x80004300 0x800042E0 0x80004330 0x80004340 0x800042F0 0x80004320 0x80004380 0x80004370 0x80004350 0x800043A0 0x800043B0 0x80004360 0x80004390 0x80004000 0x80004008 i.MX23 Applications Processor Reference Manual, Rev. 1 B-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_APBH_CTRL0_SET HW_APBH_CTRL0_TOG HW_APBH_CTRL1 HW_APBH_CTRL1_CLR HW_APBH_CTRL1_SET HW_APBH_CTRL1_TOG HW_APBH_CTRL2 HW_APBH_CTRL2_CLR HW_APBH_CTRL2_SET HW_APBH_CTRL2_TOG HW_APBH_DEVSEL HW_APBH_VERSION HW_APBX_CH0_BAR HW_APBX_CH0_CMD HW_APBX_CH0_CURCMDAR HW_APBX_CH0_DEBUG1 HW_APBX_CH0_DEBUG2 HW_APBX_CH0_NXTCMDAR HW_APBX_CH0_SEMA HW_APBX_CH1_BAR HW_APBX_CH1_CMD HW_APBX_CH1_CURCMDAR HW_APBX_CH1_DEBUG1 HW_APBX_CH1_DEBUG2 HW_APBX_CH1_NXTCMDAR HW_APBX_CH1_SEMA HW_APBX_CH10_BAR HW_APBX_CH10_CMD HW_APBX_CH10_CURCMDAR HW_APBX_CH10_DEBUG1 HW_APBX_CH10_DEBUG2 HW_APBX_CH10_NXTCMDAR HW_APBX_CH10_SEMA Address 0x80004004 0x8000400C 0x80004010 0x80004018 0x80004014 0x8000401C 0x80004020 0x80004028 0x80004024 0x8000402C 0x80004030 0x800043F0 0x80024130 0x80024120 0x80024100 0x80024150 0x80024160 0x80024110 0x80024140 0x800241A0 0x80024190 0x80024170 0x800241C0 0x800241D0 0x80024180 0x800241B0 0x80024590 0x80024580 0x80024560 0x800245B0 0x800245C0 0x80024570 0x800245A0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-3 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_APBX_CH11_BAR HW_APBX_CH11_CMD HW_APBX_CH11_CURCMDAR HW_APBX_CH11_DEBUG1 HW_APBX_CH11_DEBUG2 HW_APBX_CH11_NXTCMDAR HW_APBX_CH11_SEMA HW_APBX_CH12_BAR HW_APBX_CH12_CMD HW_APBX_CH12_CURCMDAR HW_APBX_CH12_DEBUG1 HW_APBX_CH12_DEBUG2 HW_APBX_CH12_NXTCMDAR HW_APBX_CH12_SEMA HW_APBX_CH13_BAR HW_APBX_CH13_CMD HW_APBX_CH13_CURCMDAR HW_APBX_CH13_DEBUG1 HW_APBX_CH13_DEBUG2 HW_APBX_CH13_NXTCMDAR HW_APBX_CH13_SEMA HW_APBX_CH14_BAR HW_APBX_CH14_CMD HW_APBX_CH14_CURCMDAR HW_APBX_CH14_DEBUG1 HW_APBX_CH14_DEBUG2 HW_APBX_CH14_NXTCMDAR HW_APBX_CH14_SEMA HW_APBX_CH15_BAR HW_APBX_CH15_CMD HW_APBX_CH15_CURCMDAR HW_APBX_CH15_DEBUG1 HW_APBX_CH15_DEBUG2 Address 0x80024600 0x800245F0 0x800245D0 0x80024620 0x80024630 0x800245E0 0x80024610 0x80024670 0x80024660 0x80024640 0x80024690 0x800246A0 0x80024650 0x80024680 0x800246E0 0x800246D0 0x800246B0 0x80024700 0x80024710 0x800246C0 0x800246F0 0x80024750 0x80024740 0x80024720 0x80024770 0x80024780 0x80024730 0x80024760 0x800247C0 0x800247B0 0x80024790 0x800247E0 0x800247F0 i.MX23 Applications Processor Reference Manual, Rev. 1 B-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_APBX_CH15_NXTCMDAR HW_APBX_CH15_SEMA HW_APBX_CH2_BAR HW_APBX_CH2_CMD HW_APBX_CH2_CURCMDAR HW_APBX_CH2_DEBUG1 HW_APBX_CH2_DEBUG2 HW_APBX_CH2_NXTCMDAR HW_APBX_CH2_SEMA HW_APBX_CH3_BAR HW_APBX_CH3_CMD HW_APBX_CH3_CURCMDAR HW_APBX_CH3_DEBUG1 HW_APBX_CH3_DEBUG2 HW_APBX_CH3_NXTCMDAR HW_APBX_CH3_SEMA HW_APBX_CH4_BAR HW_APBX_CH4_CMD HW_APBX_CH4_CURCMDAR HW_APBX_CH4_DEBUG1 HW_APBX_CH4_DEBUG2 HW_APBX_CH4_NXTCMDAR HW_APBX_CH4_SEMA HW_APBX_CH5_BAR HW_APBX_CH5_CMD HW_APBX_CH5_CURCMDAR HW_APBX_CH5_DEBUG1 HW_APBX_CH5_DEBUG2 HW_APBX_CH5_NXTCMDAR HW_APBX_CH5_SEMA HW_APBX_CH6_BAR HW_APBX_CH6_CMD HW_APBX_CH6_CURCMDAR Address 0x800247A0 0x800247D0 0x80024210 0x80024200 0x800241E0 0x80024230 0x80024240 0x800241F0 0x80024220 0x80024280 0x80024270 0x80024250 0x800242A0 0x800242B0 0x80024260 0x80024290 0x800242F0 0x800242E0 0x800242C0 0x80024310 0x80024320 0x800242D0 0x80024300 0x80024360 0x80024350 0x80024330 0x80024380 0x80024390 0x80024340 0x80024370 0x800243D0 0x800243C0 0x800243A0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-5 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_APBX_CH6_DEBUG1 HW_APBX_CH6_DEBUG2 HW_APBX_CH6_NXTCMDAR HW_APBX_CH6_SEMA HW_APBX_CH7_BAR HW_APBX_CH7_CMD HW_APBX_CH7_CURCMDAR HW_APBX_CH7_DEBUG1 HW_APBX_CH7_DEBUG2 HW_APBX_CH7_NXTCMDAR HW_APBX_CH7_SEMA HW_APBX_CH8_BAR HW_APBX_CH8_CMD HW_APBX_CH8_CURCMDAR HW_APBX_CH8_DEBUG1 HW_APBX_CH8_DEBUG2 HW_APBX_CH8_NXTCMDAR HW_APBX_CH8_SEMA HW_APBX_CH9_BAR HW_APBX_CH9_CMD HW_APBX_CH9_CURCMDAR HW_APBX_CH9_DEBUG1 HW_APBX_CH9_DEBUG2 HW_APBX_CH9_NXTCMDAR HW_APBX_CH9_SEMA HW_APBX_CHANNEL_CTRL HW_APBX_CHANNEL_CTRL_CLR HW_APBX_CHANNEL_CTRL_SET HW_APBX_CHANNEL_CTRL_TOG HW_APBX_CTRL0 HW_APBX_CTRL0_CLR HW_APBX_CTRL0_SET HW_APBX_CTRL0_TOG Address 0x800243F0 0x80024400 0x800243B0 0x800243E0 0x80024440 0x80024430 0x80024410 0x80024460 0x80024470 0x80024420 0x80024450 0x800244B0 0x800244A0 0x80024480 0x800244D0 0x800244E0 0x80024490 0x800244C0 0x80024520 0x80024510 0x800244F0 0x80024540 0x80024550 0x80024500 0x80024530 0x80024030 0x80024038 0x80024034 0x8002403C 0x80024000 0x80024008 0x80024004 0x8002400C i.MX23 Applications Processor Reference Manual, Rev. 1 B-6 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_APBX_CTRL1 HW_APBX_CTRL1_CLR HW_APBX_CTRL1_SET HW_APBX_CTRL1_TOG HW_APBX_CTRL2 HW_APBX_CTRL2_CLR HW_APBX_CTRL2_SET HW_APBX_CTRL2_TOG HW_APBX_DEVSEL HW_APBX_VERSION HW_AUDIOIN_ADCDEBUG HW_AUDIOIN_ADCDEBUG_CLR HW_AUDIOIN_ADCDEBUG_SET HW_AUDIOIN_ADCDEBUG_TOG HW_AUDIOIN_ADCSRR HW_AUDIOIN_ADCSRR_CLR HW_AUDIOIN_ADCSRR_SET HW_AUDIOIN_ADCSRR_TOG HW_AUDIOIN_ADCVOL HW_AUDIOIN_ADCVOL_CLR HW_AUDIOIN_ADCVOL_SET HW_AUDIOIN_ADCVOL_TOG HW_AUDIOIN_ADCVOLUME HW_AUDIOIN_ADCVOLUME_CLR HW_AUDIOIN_ADCVOLUME_SET HW_AUDIOIN_ADCVOLUME_TOG HW_AUDIOIN_ANACLKCTRL HW_AUDIOIN_ANACLKCTRL_CLR HW_AUDIOIN_ANACLKCTRL_SET HW_AUDIOIN_ANACLKCTRL_TOG HW_AUDIOIN_CTRL HW_AUDIOIN_CTRL_CLR HW_AUDIOIN_CTRL_SET Address 0x80024010 0x80024018 0x80024014 0x8002401C 0x80024020 0x80024028 0x80024024 0x8002402C 0x80024040 0x80024800 0x8004C040 0x8004C048 0x8004C044 0x8004C04C 0x8004C020 0x8004C028 0x8004C024 0x8004C02C 0x8004C050 0x8004C058 0x8004C054 0x8004C05C 0x8004C030 0x8004C038 0x8004C034 0x8004C03C 0x8004C070 0x8004C078 0x8004C074 0x8004C07C 0x8004C000 0x8004C008 0x8004C004 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-7 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_AUDIOIN_CTRL_TOG HW_AUDIOIN_DATA HW_AUDIOIN_DATA_CLR HW_AUDIOIN_DATA_SET HW_AUDIOIN_DATA_TOG HW_AUDIOIN_MICLINE HW_AUDIOIN_MICLINE_CLR HW_AUDIOIN_MICLINE_SET HW_AUDIOIN_MICLINE_TOG HW_AUDIOIN_STAT HW_AUDIOIN_STAT_CLR HW_AUDIOIN_STAT_SET HW_AUDIOIN_STAT_TOG HW_AUDIOOUT_ANACLKCTRL HW_AUDIOOUT_ANACLKCTRL_CLR HW_AUDIOOUT_ANACLKCTRL_SET HW_AUDIOOUT_ANACLKCTRL_TOG HW_AUDIOOUT_ANACTRL HW_AUDIOOUT_ANACTRL_CLR HW_AUDIOOUT_ANACTRL_SET HW_AUDIOOUT_ANACTRL_TOG HW_AUDIOOUT_BISTCTRL HW_AUDIOOUT_BISTCTRL_CLR HW_AUDIOOUT_BISTCTRL_SET HW_AUDIOOUT_BISTCTRL_TOG HW_AUDIOOUT_BISTSTAT0 HW_AUDIOOUT_BISTSTAT0_CLR HW_AUDIOOUT_BISTSTAT0_SET HW_AUDIOOUT_BISTSTAT0_TOG HW_AUDIOOUT_BISTSTAT1 HW_AUDIOOUT_BISTSTAT1_CLR HW_AUDIOOUT_BISTSTAT1_SET HW_AUDIOOUT_BISTSTAT1_TOG Address 0x8004C00C 0x8004C080 0x8004C088 0x8004C084 0x8004C08C 0x8004C060 0x8004C068 0x8004C064 0x8004C06C 0x8004C010 0x8004C018 0x8004C014 0x8004C01C 0x800480e0 0x800480e8 0x800480e4 0x800480eC 0x80048090 0x80048098 0x80048094 0x8004809C 0x800480b0 0x800480b8 0x800480b4 0x800480bC 0x800480c0 0x800480c8 0x800480c4 0x800480cC 0x800480d0 0x800480d8 0x800480d4 0x800480dC i.MX23 Applications Processor Reference Manual, Rev. 1 B-8 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_AUDIOOUT_CTRL HW_AUDIOOUT_CTRL_CLR HW_AUDIOOUT_CTRL_SET HW_AUDIOOUT_CTRL_TOG HW_AUDIOOUT_DACDEBUG HW_AUDIOOUT_DACDEBUG_CLR HW_AUDIOOUT_DACDEBUG_SET HW_AUDIOOUT_DACDEBUG_TOG HW_AUDIOOUT_DACSRR HW_AUDIOOUT_DACSRR_CLR HW_AUDIOOUT_DACSRR_SET HW_AUDIOOUT_DACSRR_TOG HW_AUDIOOUT_DACVOLUME HW_AUDIOOUT_DACVOLUME_CLR HW_AUDIOOUT_DACVOLUME_SET HW_AUDIOOUT_DACVOLUME_TOG HW_AUDIOOUT_DATA HW_AUDIOOUT_DATA_CLR HW_AUDIOOUT_DATA_SET HW_AUDIOOUT_DATA_TOG HW_AUDIOOUT_HPVOL HW_AUDIOOUT_HPVOL_CLR HW_AUDIOOUT_HPVOL_SET HW_AUDIOOUT_HPVOL_TOG HW_AUDIOOUT_PWRDN HW_AUDIOOUT_PWRDN_CLR HW_AUDIOOUT_PWRDN_SET HW_AUDIOOUT_PWRDN_TOG HW_AUDIOOUT_REFCTRL HW_AUDIOOUT_REFCTRL_CLR HW_AUDIOOUT_REFCTRL_SET HW_AUDIOOUT_REFCTRL_TOG HW_AUDIOOUT_RESERVED Address 0x80048000 0x80048008 0x80048004 0x8004800C 0x80048040 0x80048048 0x80048044 0x8004804C 0x80048020 0x80048028 0x80048024 0x8004802C 0x80048030 0x80048038 0x80048034 0x8004803C 0x800480f0 0x800480f8 0x800480f4 0x800480fC 0x80048050 0x80048058 0x80048054 0x8004805C 0x80048070 0x80048078 0x80048074 0x8004807C 0x80048080 0x80048088 0x80048084 0x8004808C 0x80048060 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-9 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_AUDIOOUT_RESERVED_CLR HW_AUDIOOUT_RESERVED_SET HW_AUDIOOUT_RESERVED_TOG HW_AUDIOOUT_SPEAKERCTRL HW_AUDIOOUT_SPEAKERCTRL_CLR HW_AUDIOOUT_SPEAKERCTRL_SET HW_AUDIOOUT_SPEAKERCTRL_TOG HW_AUDIOOUT_STAT HW_AUDIOOUT_STAT_CLR HW_AUDIOOUT_STAT_SET HW_AUDIOOUT_STAT_TOG HW_AUDIOOUT_TEST HW_AUDIOOUT_TEST_CLR HW_AUDIOOUT_TEST_SET HW_AUDIOOUT_TEST_TOG HW_AUDIOOUT_VERSION HW_BCH_BLOCKNAME HW_BCH_CTRL HW_BCH_CTRL_CLR HW_BCH_CTRL_SET HW_BCH_CTRL_TOG HW_BCH_DATAPTR HW_BCH_DBGAHBMREAD HW_BCH_DBGCSFEREAD HW_BCH_DBGKESREAD HW_BCH_DBGSYNDGENREAD HW_BCH_DEBUG0 HW_BCH_DEBUG0_CLR HW_BCH_DEBUG0_SET HW_BCH_DEBUG0_TOG HW_BCH_ENCODEPTR HW_BCH_FLASH0LAYOUT0 HW_BCH_FLASH0LAYOUT1 Address 0x80048068 0x80048064 0x8004806C 0x80048100 0x80048108 0x80048104 0x8004810C 0x80048010 0x80048018 0x80048014 0x8004801C 0x800480a0 0x800480a8 0x800480a4 0x800480aC 0x80048200 0x8000A150 0x8000A000 0x8000A008 0x8000A004 0x8000A00C 0x8000A040 0x8000A140 0x8000A120 0x8000A110 0x8000A130 0x8000A100 0x8000A108 0x8000A104 0x8000A10C 0x8000A030 0x8000a080 0x8000a090 i.MX23 Applications Processor Reference Manual, Rev. 1 B-10 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_BCH_FLASH1LAYOUT0 HW_BCH_FLASH1LAYOUT1 HW_BCH_FLASH2LAYOUT0 HW_BCH_FLASH2LAYOUT1 HW_BCH_FLASH3LAYOUT0 HW_BCH_FLASH3LAYOUT1 HW_BCH_LAYOUTSELECT HW_BCH_METAPTR HW_BCH_MODE HW_BCH_STATUS0 HW_BCH_VERSION HW_CLKCTRL_CLKSEQ HW_CLKCTRL_CLKSEQ_CLR HW_CLKCTRL_CLKSEQ_SET HW_CLKCTRL_CLKSEQ_TOG HW_CLKCTRL_CPU HW_CLKCTRL_CPU_CLR HW_CLKCTRL_CPU_SET HW_CLKCTRL_CPU_TOG HW_CLKCTRL_EMI HW_CLKCTRL_ETM HW_CLKCTRL_FRAC HW_CLKCTRL_FRAC_CLR HW_CLKCTRL_FRAC_SET HW_CLKCTRL_FRAC_TOG HW_CLKCTRL_FRAC1 HW_CLKCTRL_FRAC1_CLR HW_CLKCTRL_FRAC1_SET HW_CLKCTRL_FRAC1_TOG HW_CLKCTRL_GPMI HW_CLKCTRL_HBUS HW_CLKCTRL_HBUS_CLR HW_CLKCTRL_HBUS_SET Address 0x8000a0a0 0x8000a0b0 0x8000a0c0 0x8000a0d0 0x8000a0e0 0x8000a0f0 0x8000A070 0x8000A050 0x8000A020 0x8000A010 0x8000A160 0x80040110 0x80040118 0x80040114 0x8004011c 0x80040020 0x80040028 0x80040024 0x8004002c 0x800400a0 0x800400e0 0x800400f0 0x800400f8 0x800400f4 0x800400fC 0x80040100 0x80040108 0x80040104 0x8004010C 0x80040080 0x80040030 0x80040038 0x80040034 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-11 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_CLKCTRL_HBUS_TOG HW_CLKCTRL_IR HW_CLKCTRL_PIX HW_CLKCTRL_PLLCTRL0 HW_CLKCTRL_PLLCTRL0_CLR HW_CLKCTRL_PLLCTRL0_SET HW_CLKCTRL_PLLCTRL0_TOG HW_CLKCTRL_PLLCTRL1 HW_CLKCTRL_RESET HW_CLKCTRL_SAIF HW_CLKCTRL_SPDIF HW_CLKCTRL_SSP HW_CLKCTRL_STATUS HW_CLKCTRL_TV HW_CLKCTRL_VERSION HW_CLKCTRL_XBUS HW_CLKCTRL_XTAL HW_CLKCTRL_XTAL_CLR HW_CLKCTRL_XTAL_SET HW_CLKCTRL_XTAL_TOG HW_DCP_CAPABILITY0 HW_DCP_CAPABILITY1 HW_DCP_CH0CMDPTR HW_DCP_CH0OPTS HW_DCP_CH0OPTS_CLR HW_DCP_CH0OPTS_SET HW_DCP_CH0OPTS_TOG HW_DCP_CH0SEMA HW_DCP_CH0STAT HW_DCP_CH0STAT_CLR HW_DCP_CH0STAT_SET HW_DCP_CH0STAT_TOG HW_DCP_CH1CMDPTR Address 0x8004003c 0x800400b0 0x80040060 0x80040000 0x80040008 0x80040004 0x8004000C 0x80040010 0x80040120 0x800400c0 0x80040090 0x80040070 0x80040130 0x800400d0 0x80040140 0x80040040 0x80040050 0x80040058 0x80040054 0x8004005C 0x80028030 0x80028040 0x80028100 0x80028130 0x80028138 0x80028134 0x8002813C 0x80028110 0x80028120 0x80028128 0x80028124 0x8002812C 0x80028140 i.MX23 Applications Processor Reference Manual, Rev. 1 B-12 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_DCP_CH1OPTS HW_DCP_CH1OPTS_CLR HW_DCP_CH1OPTS_SET HW_DCP_CH1OPTS_TOG HW_DCP_CH1SEMA HW_DCP_CH1STAT HW_DCP_CH1STAT_CLR HW_DCP_CH1STAT_SET HW_DCP_CH1STAT_TOG HW_DCP_CH2CMDPTR HW_DCP_CH2OPTS HW_DCP_CH2OPTS_CLR HW_DCP_CH2OPTS_SET HW_DCP_CH2OPTS_TOG HW_DCP_CH2SEMA HW_DCP_CH2STAT HW_DCP_CH2STAT_CLR HW_DCP_CH2STAT_SET HW_DCP_CH2STAT_TOG HW_DCP_CH3CMDPTR HW_DCP_CH3OPTS HW_DCP_CH3OPTS_CLR HW_DCP_CH3OPTS_SET HW_DCP_CH3OPTS_TOG HW_DCP_CH3SEMA HW_DCP_CH3STAT HW_DCP_CH3STAT_CLR HW_DCP_CH3STAT_SET HW_DCP_CH3STAT_TOG HW_DCP_CHANNELCTRL HW_DCP_CHANNELCTRL_CLR HW_DCP_CHANNELCTRL_SET HW_DCP_CHANNELCTRL_TOG Address 0x80028170 0x80028178 0x80028174 0x8002817C 0x80028150 0x80028160 0x80028168 0x80028164 0x8002816C 0x80028180 0x800281B0 0x800281B8 0x800281B4 0x800281BC 0x80028190 0x800281A0 0x800281A8 0x800281A4 0x800281AC 0x800281C0 0x800281F0 0x800281F8 0x800281F4 0x800281FC 0x800281D0 0x800281E0 0x800281E8 0x800281E4 0x800281EC 0x80028020 0x80028028 0x80028024 0x8002802C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-13 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_DCP_CONTEXT HW_DCP_CSCCHROMAU HW_DCP_CSCCHROMAV HW_DCP_CSCCLIP HW_DCP_CSCCOEFF0 HW_DCP_CSCCOEFF1 HW_DCP_CSCCOEFF2 HW_DCP_CSCCTRL0 HW_DCP_CSCCTRL0_CLR HW_DCP_CSCCTRL0_SET HW_DCP_CSCCTRL0_TOG HW_DCP_CSCINBUFPARAM HW_DCP_CSCLUMA HW_DCP_CSCOUTBUFPARAM HW_DCP_CSCRGB HW_DCP_CSCSTAT HW_DCP_CSCSTAT_CLR HW_DCP_CSCSTAT_SET HW_DCP_CSCSTAT_TOG HW_DCP_CSCXSCALE HW_DCP_CSCYSCALE HW_DCP_CTRL HW_DCP_CTRL_CLR HW_DCP_CTRL_SET HW_DCP_CTRL_TOG HW_DCP_DBGDATA HW_DCP_DBGSELECT HW_DCP_KEY HW_DCP_KEYDATA HW_DCP_PACKET0 HW_DCP_PACKET1 HW_DCP_PACKET2 HW_DCP_PACKET3 Address 0x80028050 0x80028360 0x80028370 0x800283D0 0x80028380 0x80028390 0x800283A0 0x80028300 0x80028308 0x80028304 0x8002830C 0x80028330 0x80028350 0x80028320 0x80028340 0x80028310 0x80028318 0x80028314 0x8002831C 0x800283E0 0x800283F0 0x80028000 0x80028008 0x80028004 0x8002800C 0x80028410 0x80028400 0x80028060 0x80028070 0x80028080 0x80028090 0x800280A0 0x800280B0 i.MX23 Applications Processor Reference Manual, Rev. 1 B-14 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_DCP_PACKET4 HW_DCP_PACKET5 HW_DCP_PACKET6 HW_DCP_PAGETABLE HW_DCP_STAT HW_DCP_STAT_CLR HW_DCP_STAT_SET HW_DCP_STAT_TOG HW_DCP_VERSION HW_DIGCTL_AHB_STATS_SELECT HW_DIGCTL_ARMCACHE HW_DIGCTL_CHIPID HW_DIGCTL_CTRL HW_DIGCTL_CTRL_CLR HW_DIGCTL_CTRL_SET HW_DIGCTL_CTRL_TOG HW_DIGCTL_DBG HW_DIGCTL_DBGRD HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH HW_DIGCTL_DEBUG_TRAP_ADDR_LOW HW_DIGCTL_EMICLK_DELAY HW_DIGCTL_ENTROPY HW_DIGCTL_ENTROPY_LATCHED HW_DIGCTL_HCLKCOUNT HW_DIGCTL_HCLKCOUNT_CLR HW_DIGCTL_HCLKCOUNT_SET HW_DIGCTL_HCLKCOUNT_TOG HW_DIGCTL_L0_AHB_ACTIVE_CYCLES HW_DIGCTL_L0_AHB_DATA_CYCLES HW_DIGCTL_L0_AHB_DATA_STALLED HW_DIGCTL_L1_AHB_ACTIVE_CYCLES HW_DIGCTL_L1_AHB_DATA_CYCLES HW_DIGCTL_L1_AHB_DATA_STALLED Address 0x800280C0 0x800280D0 0x800280E0 0x80028420 0x80028010 0x80028018 0x80028014 0x8002801C 0x80028430 0x8001C330 0x8001C2B0 0x8001C310 0x8001C000 0x8001C008 0x8001C004 0x8001C00C 0x8001C0E0 0x8001C0D0 0x8001C2D0 0x8001C2C0 0x8001C500 0x8001C090 0x8001C0A0 0x8001C020 0x8001C028 0x8001C024 0x8001C02C 0x8001C340 0x8001C360 0x8001C350 0x8001C370 0x8001C390 0x8001C380 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-15 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_DIGCTL_L2_AHB_ACTIVE_CYCLES HW_DIGCTL_L2_AHB_DATA_CYCLES HW_DIGCTL_L2_AHB_DATA_STALLED HW_DIGCTL_L3_AHB_ACTIVE_CYCLES HW_DIGCTL_L3_AHB_DATA_CYCLES HW_DIGCTL_L3_AHB_DATA_STALLED HW_DIGCTL_MICROSECONDS HW_DIGCTL_MICROSECONDS_CLR HW_DIGCTL_MICROSECONDS_SET HW_DIGCTL_MICROSECONDS_TOG HW_DIGCTL_MPTE0_LOC HW_DIGCTL_MPTE1_LOC HW_DIGCTL_MPTE10_LOC HW_DIGCTL_MPTE11_LOC HW_DIGCTL_MPTE12_LOC HW_DIGCTL_MPTE13_LOC HW_DIGCTL_MPTE14_LOC HW_DIGCTL_MPTE15_LOC HW_DIGCTL_MPTE2_LOC HW_DIGCTL_MPTE3_LOC HW_DIGCTL_MPTE4_LOC HW_DIGCTL_MPTE5_LOC HW_DIGCTL_MPTE6_LOC HW_DIGCTL_MPTE7_LOC HW_DIGCTL_MPTE8_LOC HW_DIGCTL_MPTE9_LOC HW_DIGCTL_OCRAM_BIST_CSR HW_DIGCTL_OCRAM_BIST_CSR_CLR HW_DIGCTL_OCRAM_BIST_CSR_SET HW_DIGCTL_OCRAM_BIST_CSR_TOG HW_DIGCTL_OCRAM_STATUS0 HW_DIGCTL_OCRAM_STATUS0_CLR HW_DIGCTL_OCRAM_STATUS0_SET Address 0x8001C3A0 0x8001C3C0 0x8001C3B0 0x8001C3D0 0x8001C3F0 0x8001C3E0 0x8001C0C0 0x8001C0C8 0x8001C0C4 0x8001C0CC 0x8001C400 0x8001C410 0x8001C4A0 0x8001C4B0 0x8001C4C0 0x8001C4D0 0x8001C4E0 0x8001C4F0 0x8001C420 0x8001C430 0x8001C440 0x8001C450 0x8001C460 0x8001C470 0x8001C480 0x8001C490 0x8001C0F0 0x8001C0F8 0x8001C0F4 0x8001C0FC 0x8001C110 0x8001C118 0x8001C114 i.MX23 Applications Processor Reference Manual, Rev. 1 B-16 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_DIGCTL_OCRAM_STATUS0_TOG HW_DIGCTL_OCRAM_STATUS1 HW_DIGCTL_OCRAM_STATUS1_CLR HW_DIGCTL_OCRAM_STATUS1_SET HW_DIGCTL_OCRAM_STATUS1_TOG HW_DIGCTL_OCRAM_STATUS10 HW_DIGCTL_OCRAM_STATUS10_CLR HW_DIGCTL_OCRAM_STATUS10_SET HW_DIGCTL_OCRAM_STATUS10_TOG HW_DIGCTL_OCRAM_STATUS11 HW_DIGCTL_OCRAM_STATUS11_CLR HW_DIGCTL_OCRAM_STATUS11_SET HW_DIGCTL_OCRAM_STATUS11_TOG HW_DIGCTL_OCRAM_STATUS12 HW_DIGCTL_OCRAM_STATUS12_CLR HW_DIGCTL_OCRAM_STATUS12_SET HW_DIGCTL_OCRAM_STATUS12_TOG HW_DIGCTL_OCRAM_STATUS13 HW_DIGCTL_OCRAM_STATUS13_CLR HW_DIGCTL_OCRAM_STATUS13_SET HW_DIGCTL_OCRAM_STATUS13_TOG HW_DIGCTL_OCRAM_STATUS2 HW_DIGCTL_OCRAM_STATUS2_CLR HW_DIGCTL_OCRAM_STATUS2_SET HW_DIGCTL_OCRAM_STATUS2_TOG HW_DIGCTL_OCRAM_STATUS3 HW_DIGCTL_OCRAM_STATUS3_CLR HW_DIGCTL_OCRAM_STATUS3_SET HW_DIGCTL_OCRAM_STATUS3_TOG HW_DIGCTL_OCRAM_STATUS4 HW_DIGCTL_OCRAM_STATUS4_CLR HW_DIGCTL_OCRAM_STATUS4_SET HW_DIGCTL_OCRAM_STATUS4_TOG Address 0x8001C11C 0x8001C120 0x8001C128 0x8001C124 0x8001C12C 0x8001C1B0 0x8001C1B8 0x8001C1B4 0x8001C1BC 0x8001C1C0 0x8001C1C8 0x8001C1C4 0x8001C1CC 0x8001C1D0 0x8001C1D8 0x8001C1D4 0x8001C1DC 0x8001C1E0 0x8001C1E8 0x8001C1E4 0x8001C1EC 0x8001C130 0x8001C138 0x8001C134 0x8001C13C 0x8001C140 0x8001C148 0x8001C144 0x8001C14C 0x8001C150 0x8001C158 0x8001C154 0x8001C15C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-17 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_DIGCTL_OCRAM_STATUS5 HW_DIGCTL_OCRAM_STATUS5_CLR HW_DIGCTL_OCRAM_STATUS5_SET HW_DIGCTL_OCRAM_STATUS5_TOG HW_DIGCTL_OCRAM_STATUS6 HW_DIGCTL_OCRAM_STATUS6_CLR HW_DIGCTL_OCRAM_STATUS6_SET HW_DIGCTL_OCRAM_STATUS6_TOG HW_DIGCTL_OCRAM_STATUS7 HW_DIGCTL_OCRAM_STATUS7_CLR HW_DIGCTL_OCRAM_STATUS7_SET HW_DIGCTL_OCRAM_STATUS7_TOG HW_DIGCTL_OCRAM_STATUS8 HW_DIGCTL_OCRAM_STATUS8_CLR HW_DIGCTL_OCRAM_STATUS8_SET HW_DIGCTL_OCRAM_STATUS8_TOG HW_DIGCTL_OCRAM_STATUS9 HW_DIGCTL_OCRAM_STATUS9_CLR HW_DIGCTL_OCRAM_STATUS9_SET HW_DIGCTL_OCRAM_STATUS9_TOG HW_DIGCTL_RAMCTRL HW_DIGCTL_RAMCTRL_CLR HW_DIGCTL_RAMCTRL_SET HW_DIGCTL_RAMCTRL_TOG HW_DIGCTL_RAMREPAIR HW_DIGCTL_RAMREPAIR_CLR HW_DIGCTL_RAMREPAIR_SET HW_DIGCTL_RAMREPAIR_TOG HW_DIGCTL_ROMCTRL HW_DIGCTL_ROMCTRL_CLR HW_DIGCTL_ROMCTRL_SET HW_DIGCTL_ROMCTRL_TOG HW_DIGCTL_SCRATCH0 Address 0x8001C160 0x8001C168 0x8001C164 0x8001C16C 0x8001C170 0x8001C178 0x8001C174 0x8001C17C 0x8001C180 0x8001C188 0x8001C184 0x8001C18C 0x8001C190 0x8001C198 0x8001C194 0x8001C19C 0x8001C1A0 0x8001C1A8 0x8001C1A4 0x8001C1AC 0x8001C030 0x8001C038 0x8001C034 0x8001C03C 0x8001C040 0x8001C048 0x8001C044 0x8001C04C 0x8001C050 0x8001C058 0x8001C054 0x8001C05C 0x8001C290 i.MX23 Applications Processor Reference Manual, Rev. 1 B-18 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_DIGCTL_SCRATCH1 HW_DIGCTL_SGTL HW_DIGCTL_SJTAGDBG HW_DIGCTL_SJTAGDBG_CLR HW_DIGCTL_SJTAGDBG_SET HW_DIGCTL_SJTAGDBG_TOG HW_DIGCTL_STATUS HW_DIGCTL_STATUS_CLR HW_DIGCTL_STATUS_SET HW_DIGCTL_STATUS_TOG HW_DIGCTL_WRITEONCE HW_DRAM_CTL00 HW_DRAM_CTL01 HW_DRAM_CTL02 HW_DRAM_CTL03 HW_DRAM_CTL04 HW_DRAM_CTL05 HW_DRAM_CTL06 HW_DRAM_CTL07 HW_DRAM_CTL08 HW_DRAM_CTL09 HW_DRAM_CTL10 HW_DRAM_CTL11 HW_DRAM_CTL12 HW_DRAM_CTL13 HW_DRAM_CTL14 HW_DRAM_CTL15 HW_DRAM_CTL16 HW_DRAM_CTL17 HW_DRAM_CTL18 HW_DRAM_CTL19 HW_DRAM_CTL20 HW_DRAM_CTL21 Address 0x8001C2A0 0x8001C300 0x8001C0B0 0x8001C0B8 0x8001C0B4 0x8001C0BC 0x8001C010 0x8001C018 0x8001C014 0x8001C01C 0x8001C060 0x800E0000 0x800E0004 0x800E0008 0x800E000C 0x800E0010 0x800E0014 0x800E0018 0x800E001C 0x800E0020 0x800E0024 0x800E0028 0x800E002C 0x800E0030 0x800E0034 0x800E0038 0x800E003C 0x800E0040 0x800E0044 0x800E0048 0x800E004C 0x800E0050 0x800E0054 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-19 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_DRAM_CTL22 HW_DRAM_CTL23 HW_DRAM_CTL24 HW_DRAM_CTL25 HW_DRAM_CTL26 HW_DRAM_CTL27 HW_DRAM_CTL28 HW_DRAM_CTL29 HW_DRAM_CTL30 HW_DRAM_CTL31 HW_DRAM_CTL32 HW_DRAM_CTL33 HW_DRAM_CTL34 HW_DRAM_CTL35 HW_DRAM_CTL36 HW_DRAM_CTL37 HW_DRAM_CTL38 HW_DRAM_CTL39 HW_DRAM_CTL40 HW_ECC8_BLOCKNAME HW_ECC8_CTRL HW_ECC8_CTRL_CLR HW_ECC8_CTRL_SET HW_ECC8_CTRL_TOG HW_ECC8_DBGAHBMREAD HW_ECC8_DBGCSFEREAD HW_ECC8_DBGKESREAD HW_ECC8_DBGSYNDGENREAD HW_ECC8_DEBUG0 HW_ECC8_DEBUG0_CLR HW_ECC8_DEBUG0_SET HW_ECC8_DEBUG0_TOG HW_ECC8_STATUS0 Address 0x800E0058 0x800E005C 0x800E0060 0x800E0064 0x800E0068 0x800E006C 0x800E0070 0x800E0074 0x800E0078 0x800E007C 0x800E0080 0x800E0084 0x800E0088 0x800E008C 0x800E0090 0x800E0094 0x800E0098 0x800E009C 0x800E00A0 0x80008080 0x80008000 0x80008008 0x80008004 0x8000800C 0x80008070 0x80008050 0x80008040 0x80008060 0x80008030 0x80008038 0x80008034 0x8000803C 0x80008010 i.MX23 Applications Processor Reference Manual, Rev. 1 B-20 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ECC8_STATUS1 HW_ECC8_VERSION HW_EMI_CTRL HW_EMI_CTRL_CLR HW_EMI_CTRL_SET HW_EMI_CTRL_TOG HW_EMI_DDR_TEST_MODE_CSR HW_EMI_DDR_TEST_MODE_CSR_CLR HW_EMI_DDR_TEST_MODE_CSR_SET HW_EMI_DDR_TEST_MODE_CSR_TOG HW_EMI_DDR_TEST_MODE_STATUS0 HW_EMI_DDR_TEST_MODE_STATUS1 HW_EMI_DDR_TEST_MODE_STATUS2 HW_EMI_DDR_TEST_MODE_STATUS3 HW_EMI_VERSION HW_GPMI_AUXILIARY HW_GPMI_COMPARE HW_GPMI_CTRL0 HW_GPMI_CTRL0_CLR HW_GPMI_CTRL0_SET HW_GPMI_CTRL0_TOG HW_GPMI_CTRL1 HW_GPMI_CTRL1_CLR HW_GPMI_CTRL1_SET HW_GPMI_CTRL1_TOG HW_GPMI_DATA HW_GPMI_DEBUG HW_GPMI_DEBUG2 HW_GPMI_DEBUG3 HW_GPMI_ECCCOUNT HW_GPMI_ECCCTRL HW_GPMI_ECCCTRL_CLR HW_GPMI_ECCCTRL_SET Address 0x80008020 0x800080a0 0x80020000 0x80020008 0x80020004 0x8002000C 0x80020030 0x80020038 0x80020034 0x8002003C 0x80020090 0x800200A0 0x800200B0 0x800200C0 0x800200F0 0x8000C050 0x8000C010 0x8000C000 0x8000C008 0x8000C004 0x8000C00C 0x8000C060 0x8000C068 0x8000C064 0x8000C06C 0x8000C0A0 0x8000C0C0 0x8000C0E0 0x8000C0F0 0x8000C030 0x8000C020 0x8000C028 0x8000C024 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-21 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_GPMI_ECCCTRL_TOG HW_GPMI_PAYLOAD HW_GPMI_STAT HW_GPMI_TIMING0 HW_GPMI_TIMING1 HW_GPMI_TIMING2 HW_GPMI_VERSION HW_I2C_CTRL0 HW_I2C_CTRL0_CLR HW_I2C_CTRL0_SET HW_I2C_CTRL0_TOG HW_I2C_CTRL1 HW_I2C_CTRL1_CLR HW_I2C_CTRL1_SET HW_I2C_CTRL1_TOG HW_I2C_DATA HW_I2C_DEBUG0 HW_I2C_DEBUG0_CLR HW_I2C_DEBUG0_SET HW_I2C_DEBUG0_TOG HW_I2C_DEBUG1 HW_I2C_DEBUG1_CLR HW_I2C_DEBUG1_SET HW_I2C_DEBUG1_TOG HW_I2C_STAT HW_I2C_TIMING0 HW_I2C_TIMING0_CLR HW_I2C_TIMING0_SET HW_I2C_TIMING0_TOG HW_I2C_TIMING1 HW_I2C_TIMING1_CLR HW_I2C_TIMING1_SET HW_I2C_TIMING1_TOG Address 0x8000C02C 0x8000C040 0x8000C0B0 0x8000C070 0x8000C080 0x8000C090 0x8000C0D0 0x80058000 0x80058008 0x80058004 0x8005800C 0x80058040 0x80058048 0x80058044 0x8005804C 0x80058060 0x80058070 0x80058078 0x80058074 0x8005807C 0x80058080 0x80058088 0x80058084 0x8005808C 0x80058050 0x80058010 0x80058018 0x80058014 0x8005801C 0x80058020 0x80058028 0x80058024 0x8005802C i.MX23 Applications Processor Reference Manual, Rev. 1 B-22 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_I2C_TIMING2 HW_I2C_TIMING2_CLR HW_I2C_TIMING2_SET HW_I2C_TIMING2_TOG HW_I2C_VERSION HW_ICOLL_CTRL HW_ICOLL_CTRL_CLR HW_ICOLL_CTRL_SET HW_ICOLL_CTRL_TOG HW_ICOLL_DBGFLAG HW_ICOLL_DBGFLAG_CLR HW_ICOLL_DBGFLAG_SET HW_ICOLL_DBGFLAG_TOG HW_ICOLL_DBGREAD0 HW_ICOLL_DBGREAD0_CLR HW_ICOLL_DBGREAD0_SET HW_ICOLL_DBGREAD0_TOG HW_ICOLL_DBGREAD1 HW_ICOLL_DBGREAD1_CLR HW_ICOLL_DBGREAD1_SET HW_ICOLL_DBGREAD1_TOG HW_ICOLL_DBGREQUEST0 HW_ICOLL_DBGREQUEST0_CLR HW_ICOLL_DBGREQUEST0_SET HW_ICOLL_DBGREQUEST0_TOG HW_ICOLL_DBGREQUEST1 HW_ICOLL_DBGREQUEST1_CLR HW_ICOLL_DBGREQUEST1_SET HW_ICOLL_DBGREQUEST1_TOG HW_ICOLL_DBGREQUEST2 HW_ICOLL_DBGREQUEST2_CLR HW_ICOLL_DBGREQUEST2_SET HW_ICOLL_DBGREQUEST2_TOG Address 0x80058030 0x80058038 0x80058034 0x8005803C 0x80058090 0x80000020 0x80000028 0x80000024 0x8000002C 0x80001150 0x80001158 0x80001154 0x8000115C 0x80001130 0x80001138 0x80001134 0x8000113C 0x80001140 0x80001148 0x80001144 0x8000114C 0x80001160 0x80001168 0x80001164 0x8000116C 0x80001170 0x80001178 0x80001174 0x8000117C 0x80001180 0x80001188 0x80001184 0x8000118C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-23 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_DBGREQUEST3 HW_ICOLL_DBGREQUEST3_CLR HW_ICOLL_DBGREQUEST3_SET HW_ICOLL_DBGREQUEST3_TOG HW_ICOLL_DEBUG HW_ICOLL_DEBUG_CLR HW_ICOLL_DEBUG_SET HW_ICOLL_DEBUG_TOG HW_ICOLL_INTERRUPT0 HW_ICOLL_INTERRUPT0_CLR HW_ICOLL_INTERRUPT0_SET HW_ICOLL_INTERRUPT0_TOG HW_ICOLL_INTERRUPT1 HW_ICOLL_INTERRUPT1_CLR HW_ICOLL_INTERRUPT1_SET HW_ICOLL_INTERRUPT1_TOG HW_ICOLL_INTERRUPT10 HW_ICOLL_INTERRUPT10_CLR HW_ICOLL_INTERRUPT10_SET HW_ICOLL_INTERRUPT10_TOG HW_ICOLL_INTERRUPT100 HW_ICOLL_INTERRUPT100_CLR HW_ICOLL_INTERRUPT100_SET HW_ICOLL_INTERRUPT100_TOG HW_ICOLL_INTERRUPT101 HW_ICOLL_INTERRUPT101_CLR HW_ICOLL_INTERRUPT101_SET HW_ICOLL_INTERRUPT101_TOG HW_ICOLL_INTERRUPT102 HW_ICOLL_INTERRUPT102_CLR HW_ICOLL_INTERRUPT102_SET HW_ICOLL_INTERRUPT102_TOG HW_ICOLL_INTERRUPT103 Address 0x80001190 0x80001198 0x80001194 0x8000119C 0x80001120 0x80001128 0x80001124 0x8000112C 0x80000120 0x80000128 0x80000124 0x8000012C 0x80000130 0x80000138 0x80000134 0x8000013C 0x800001C0 0x800001C8 0x800001C4 0x800001CC 0x80000760 0x80000768 0x80000764 0x8000076C 0x80000770 0x80000778 0x80000774 0x8000077C 0x80000780 0x80000788 0x80000784 0x8000078C 0x80000790 i.MX23 Applications Processor Reference Manual, Rev. 1 B-24 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT103_CLR HW_ICOLL_INTERRUPT103_SET HW_ICOLL_INTERRUPT103_TOG HW_ICOLL_INTERRUPT104 HW_ICOLL_INTERRUPT104_CLR HW_ICOLL_INTERRUPT104_SET HW_ICOLL_INTERRUPT104_TOG HW_ICOLL_INTERRUPT105 HW_ICOLL_INTERRUPT105_CLR HW_ICOLL_INTERRUPT105_SET HW_ICOLL_INTERRUPT105_TOG HW_ICOLL_INTERRUPT106 HW_ICOLL_INTERRUPT106_CLR HW_ICOLL_INTERRUPT106_SET HW_ICOLL_INTERRUPT106_TOG HW_ICOLL_INTERRUPT107 HW_ICOLL_INTERRUPT107_CLR HW_ICOLL_INTERRUPT107_SET HW_ICOLL_INTERRUPT107_TOG HW_ICOLL_INTERRUPT108 HW_ICOLL_INTERRUPT108_CLR HW_ICOLL_INTERRUPT108_SET HW_ICOLL_INTERRUPT108_TOG HW_ICOLL_INTERRUPT109 HW_ICOLL_INTERRUPT109_CLR HW_ICOLL_INTERRUPT109_SET HW_ICOLL_INTERRUPT109_TOG HW_ICOLL_INTERRUPT11 HW_ICOLL_INTERRUPT11_CLR HW_ICOLL_INTERRUPT11_SET HW_ICOLL_INTERRUPT11_TOG HW_ICOLL_INTERRUPT110 HW_ICOLL_INTERRUPT110_CLR Address 0x80000798 0x80000794 0x8000079C 0x800007A0 0x800007A8 0x800007A4 0x800007AC 0x800007B0 0x800007B8 0x800007B4 0x800007BC 0x800007C0 0x800007C8 0x800007C4 0x800007CC 0x800007D0 0x800007D8 0x800007D4 0x800007DC 0x800007E0 0x800007E8 0x800007E4 0x800007EC 0x800007F0 0x800007F8 0x800007F4 0x800007FC 0x800001D0 0x800001D8 0x800001D4 0x800001DC 0x80000800 0x80000808 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-25 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT110_SET HW_ICOLL_INTERRUPT110_TOG HW_ICOLL_INTERRUPT111 HW_ICOLL_INTERRUPT111_CLR HW_ICOLL_INTERRUPT111_SET HW_ICOLL_INTERRUPT111_TOG HW_ICOLL_INTERRUPT112 HW_ICOLL_INTERRUPT112_CLR HW_ICOLL_INTERRUPT112_SET HW_ICOLL_INTERRUPT112_TOG HW_ICOLL_INTERRUPT113 HW_ICOLL_INTERRUPT113_CLR HW_ICOLL_INTERRUPT113_SET HW_ICOLL_INTERRUPT113_TOG HW_ICOLL_INTERRUPT114 HW_ICOLL_INTERRUPT114_CLR HW_ICOLL_INTERRUPT114_SET HW_ICOLL_INTERRUPT114_TOG HW_ICOLL_INTERRUPT115 HW_ICOLL_INTERRUPT115_CLR HW_ICOLL_INTERRUPT115_SET HW_ICOLL_INTERRUPT115_TOG HW_ICOLL_INTERRUPT116 HW_ICOLL_INTERRUPT116_CLR HW_ICOLL_INTERRUPT116_SET HW_ICOLL_INTERRUPT116_TOG HW_ICOLL_INTERRUPT117 HW_ICOLL_INTERRUPT117_CLR HW_ICOLL_INTERRUPT117_SET HW_ICOLL_INTERRUPT117_TOG HW_ICOLL_INTERRUPT118 HW_ICOLL_INTERRUPT118_CLR HW_ICOLL_INTERRUPT118_SET Address 0x80000804 0x8000080C 0x80000810 0x80000818 0x80000814 0x8000081C 0x80000820 0x80000828 0x80000824 0x8000082C 0x80000830 0x80000838 0x80000834 0x8000083C 0x80000840 0x80000848 0x80000844 0x8000084C 0x80000850 0x80000858 0x80000854 0x8000085C 0x80000860 0x80000868 0x80000864 0x8000086C 0x80000870 0x80000878 0x80000874 0x8000087C 0x80000880 0x80000888 0x80000884 i.MX23 Applications Processor Reference Manual, Rev. 1 B-26 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT118_TOG HW_ICOLL_INTERRUPT119 HW_ICOLL_INTERRUPT119_CLR HW_ICOLL_INTERRUPT119_SET HW_ICOLL_INTERRUPT119_TOG HW_ICOLL_INTERRUPT12 HW_ICOLL_INTERRUPT12_CLR HW_ICOLL_INTERRUPT12_SET HW_ICOLL_INTERRUPT12_TOG HW_ICOLL_INTERRUPT120 HW_ICOLL_INTERRUPT120_CLR HW_ICOLL_INTERRUPT120_SET HW_ICOLL_INTERRUPT120_TOG HW_ICOLL_INTERRUPT121 HW_ICOLL_INTERRUPT121_CLR HW_ICOLL_INTERRUPT121_SET HW_ICOLL_INTERRUPT121_TOG HW_ICOLL_INTERRUPT122 HW_ICOLL_INTERRUPT122_CLR HW_ICOLL_INTERRUPT122_SET HW_ICOLL_INTERRUPT122_TOG HW_ICOLL_INTERRUPT123 HW_ICOLL_INTERRUPT123_CLR HW_ICOLL_INTERRUPT123_SET HW_ICOLL_INTERRUPT123_TOG HW_ICOLL_INTERRUPT124 HW_ICOLL_INTERRUPT124_CLR HW_ICOLL_INTERRUPT124_SET HW_ICOLL_INTERRUPT124_TOG HW_ICOLL_INTERRUPT125 HW_ICOLL_INTERRUPT125_CLR HW_ICOLL_INTERRUPT125_SET HW_ICOLL_INTERRUPT125_TOG Address 0x8000088C 0x80000890 0x80000898 0x80000894 0x8000089C 0x800001E0 0x800001E8 0x800001E4 0x800001EC 0x800008A0 0x800008A8 0x800008A4 0x800008AC 0x800008B0 0x800008B8 0x800008B4 0x800008BC 0x800008C0 0x800008C8 0x800008C4 0x800008CC 0x800008D0 0x800008D8 0x800008D4 0x800008DC 0x800008E0 0x800008E8 0x800008E4 0x800008EC 0x800008F0 0x800008F8 0x800008F4 0x800008FC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-27 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT126 HW_ICOLL_INTERRUPT126_CLR HW_ICOLL_INTERRUPT126_SET HW_ICOLL_INTERRUPT126_TOG HW_ICOLL_INTERRUPT127 HW_ICOLL_INTERRUPT127_CLR HW_ICOLL_INTERRUPT127_SET HW_ICOLL_INTERRUPT127_TOG HW_ICOLL_INTERRUPT13 HW_ICOLL_INTERRUPT13_CLR HW_ICOLL_INTERRUPT13_SET HW_ICOLL_INTERRUPT13_TOG HW_ICOLL_INTERRUPT14 HW_ICOLL_INTERRUPT14_CLR HW_ICOLL_INTERRUPT14_SET HW_ICOLL_INTERRUPT14_TOG HW_ICOLL_INTERRUPT15 HW_ICOLL_INTERRUPT15_CLR HW_ICOLL_INTERRUPT15_SET HW_ICOLL_INTERRUPT15_TOG HW_ICOLL_INTERRUPT16 HW_ICOLL_INTERRUPT16_CLR HW_ICOLL_INTERRUPT16_SET HW_ICOLL_INTERRUPT16_TOG HW_ICOLL_INTERRUPT17 HW_ICOLL_INTERRUPT17_CLR HW_ICOLL_INTERRUPT17_SET HW_ICOLL_INTERRUPT17_TOG HW_ICOLL_INTERRUPT18 HW_ICOLL_INTERRUPT18_CLR HW_ICOLL_INTERRUPT18_SET HW_ICOLL_INTERRUPT18_TOG HW_ICOLL_INTERRUPT19 Address 0x80000900 0x80000908 0x80000904 0x8000090C 0x80000910 0x80000918 0x80000914 0x8000091C 0x800001F0 0x800001F8 0x800001F4 0x800001FC 0x80000200 0x80000208 0x80000204 0x8000020C 0x80000210 0x80000218 0x80000214 0x8000021C 0x80000220 0x80000228 0x80000224 0x8000022C 0x80000230 0x80000238 0x80000234 0x8000023C 0x80000240 0x80000248 0x80000244 0x8000024C 0x80000250 i.MX23 Applications Processor Reference Manual, Rev. 1 B-28 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT19_CLR HW_ICOLL_INTERRUPT19_SET HW_ICOLL_INTERRUPT19_TOG HW_ICOLL_INTERRUPT2 HW_ICOLL_INTERRUPT2_CLR HW_ICOLL_INTERRUPT2_SET HW_ICOLL_INTERRUPT2_TOG HW_ICOLL_INTERRUPT20 HW_ICOLL_INTERRUPT20_CLR HW_ICOLL_INTERRUPT20_SET HW_ICOLL_INTERRUPT20_TOG HW_ICOLL_INTERRUPT21 HW_ICOLL_INTERRUPT21_CLR HW_ICOLL_INTERRUPT21_SET HW_ICOLL_INTERRUPT21_TOG HW_ICOLL_INTERRUPT22 HW_ICOLL_INTERRUPT22_CLR HW_ICOLL_INTERRUPT22_SET HW_ICOLL_INTERRUPT22_TOG HW_ICOLL_INTERRUPT23 HW_ICOLL_INTERRUPT23_CLR HW_ICOLL_INTERRUPT23_SET HW_ICOLL_INTERRUPT23_TOG HW_ICOLL_INTERRUPT24 HW_ICOLL_INTERRUPT24_CLR HW_ICOLL_INTERRUPT24_SET HW_ICOLL_INTERRUPT24_TOG HW_ICOLL_INTERRUPT25 HW_ICOLL_INTERRUPT25_CLR HW_ICOLL_INTERRUPT25_SET HW_ICOLL_INTERRUPT25_TOG HW_ICOLL_INTERRUPT26 HW_ICOLL_INTERRUPT26_CLR Address 0x80000258 0x80000254 0x8000025C 0x80000140 0x80000148 0x80000144 0x8000014C 0x80000260 0x80000268 0x80000264 0x8000026C 0x80000270 0x80000278 0x80000274 0x8000027C 0x80000280 0x80000288 0x80000284 0x8000028C 0x80000290 0x80000298 0x80000294 0x8000029C 0x800002A0 0x800002A8 0x800002A4 0x800002AC 0x800002B0 0x800002B8 0x800002B4 0x800002BC 0x800002C0 0x800002C8 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-29 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT26_SET HW_ICOLL_INTERRUPT26_TOG HW_ICOLL_INTERRUPT27 HW_ICOLL_INTERRUPT27_CLR HW_ICOLL_INTERRUPT27_SET HW_ICOLL_INTERRUPT27_TOG HW_ICOLL_INTERRUPT28 HW_ICOLL_INTERRUPT28_CLR HW_ICOLL_INTERRUPT28_SET HW_ICOLL_INTERRUPT28_TOG HW_ICOLL_INTERRUPT29 HW_ICOLL_INTERRUPT29_CLR HW_ICOLL_INTERRUPT29_SET HW_ICOLL_INTERRUPT29_TOG HW_ICOLL_INTERRUPT3 HW_ICOLL_INTERRUPT3_CLR HW_ICOLL_INTERRUPT3_SET HW_ICOLL_INTERRUPT3_TOG HW_ICOLL_INTERRUPT30 HW_ICOLL_INTERRUPT30_CLR HW_ICOLL_INTERRUPT30_SET HW_ICOLL_INTERRUPT30_TOG HW_ICOLL_INTERRUPT31 HW_ICOLL_INTERRUPT31_CLR HW_ICOLL_INTERRUPT31_SET HW_ICOLL_INTERRUPT31_TOG HW_ICOLL_INTERRUPT32 HW_ICOLL_INTERRUPT32_CLR HW_ICOLL_INTERRUPT32_SET HW_ICOLL_INTERRUPT32_TOG HW_ICOLL_INTERRUPT33 HW_ICOLL_INTERRUPT33_CLR HW_ICOLL_INTERRUPT33_SET Address 0x800002C4 0x800002CC 0x800002D0 0x800002D8 0x800002D4 0x800002DC 0x800002E0 0x800002E8 0x800002E4 0x800002EC 0x800002F0 0x800002F8 0x800002F4 0x800002FC 0x80000150 0x80000158 0x80000154 0x8000015C 0x80000300 0x80000308 0x80000304 0x8000030C 0x80000310 0x80000318 0x80000314 0x8000031C 0x80000320 0x80000328 0x80000324 0x8000032C 0x80000330 0x80000338 0x80000334 i.MX23 Applications Processor Reference Manual, Rev. 1 B-30 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT33_TOG HW_ICOLL_INTERRUPT34 HW_ICOLL_INTERRUPT34_CLR HW_ICOLL_INTERRUPT34_SET HW_ICOLL_INTERRUPT34_TOG HW_ICOLL_INTERRUPT35 HW_ICOLL_INTERRUPT35_CLR HW_ICOLL_INTERRUPT35_SET HW_ICOLL_INTERRUPT35_TOG HW_ICOLL_INTERRUPT36 HW_ICOLL_INTERRUPT36_CLR HW_ICOLL_INTERRUPT36_SET HW_ICOLL_INTERRUPT36_TOG HW_ICOLL_INTERRUPT37 HW_ICOLL_INTERRUPT37_CLR HW_ICOLL_INTERRUPT37_SET HW_ICOLL_INTERRUPT37_TOG HW_ICOLL_INTERRUPT38 HW_ICOLL_INTERRUPT38_CLR HW_ICOLL_INTERRUPT38_SET HW_ICOLL_INTERRUPT38_TOG HW_ICOLL_INTERRUPT39 HW_ICOLL_INTERRUPT39_CLR HW_ICOLL_INTERRUPT39_SET HW_ICOLL_INTERRUPT39_TOG HW_ICOLL_INTERRUPT4 HW_ICOLL_INTERRUPT4_CLR HW_ICOLL_INTERRUPT4_SET HW_ICOLL_INTERRUPT4_TOG HW_ICOLL_INTERRUPT40 HW_ICOLL_INTERRUPT40_CLR HW_ICOLL_INTERRUPT40_SET HW_ICOLL_INTERRUPT40_TOG Address 0x8000033C 0x80000340 0x80000348 0x80000344 0x8000034C 0x80000350 0x80000358 0x80000354 0x8000035C 0x80000360 0x80000368 0x80000364 0x8000036C 0x80000370 0x80000378 0x80000374 0x8000037C 0x80000380 0x80000388 0x80000384 0x8000038C 0x80000390 0x80000398 0x80000394 0x8000039C 0x80000160 0x80000168 0x80000164 0x8000016C 0x800003A0 0x800003A8 0x800003A4 0x800003AC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-31 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT41 HW_ICOLL_INTERRUPT41_CLR HW_ICOLL_INTERRUPT41_SET HW_ICOLL_INTERRUPT41_TOG HW_ICOLL_INTERRUPT42 HW_ICOLL_INTERRUPT42_CLR HW_ICOLL_INTERRUPT42_SET HW_ICOLL_INTERRUPT42_TOG HW_ICOLL_INTERRUPT43 HW_ICOLL_INTERRUPT43_CLR HW_ICOLL_INTERRUPT43_SET HW_ICOLL_INTERRUPT43_TOG HW_ICOLL_INTERRUPT44 HW_ICOLL_INTERRUPT44_CLR HW_ICOLL_INTERRUPT44_SET HW_ICOLL_INTERRUPT44_TOG HW_ICOLL_INTERRUPT45 HW_ICOLL_INTERRUPT45_CLR HW_ICOLL_INTERRUPT45_SET HW_ICOLL_INTERRUPT45_TOG HW_ICOLL_INTERRUPT46 HW_ICOLL_INTERRUPT46_CLR HW_ICOLL_INTERRUPT46_SET HW_ICOLL_INTERRUPT46_TOG HW_ICOLL_INTERRUPT47 HW_ICOLL_INTERRUPT47_CLR HW_ICOLL_INTERRUPT47_SET HW_ICOLL_INTERRUPT47_TOG HW_ICOLL_INTERRUPT48 HW_ICOLL_INTERRUPT48_CLR HW_ICOLL_INTERRUPT48_SET HW_ICOLL_INTERRUPT48_TOG HW_ICOLL_INTERRUPT49 Address 0x800003B0 0x800003B8 0x800003B4 0x800003BC 0x800003C0 0x800003C8 0x800003C4 0x800003CC 0x800003D0 0x800003D8 0x800003D4 0x800003DC 0x800003E0 0x800003E8 0x800003E4 0x800003EC 0x800003F0 0x800003F8 0x800003F4 0x800003FC 0x80000400 0x80000408 0x80000404 0x8000040C 0x80000410 0x80000418 0x80000414 0x8000041C 0x80000420 0x80000428 0x80000424 0x8000042C 0x80000430 i.MX23 Applications Processor Reference Manual, Rev. 1 B-32 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT49_CLR HW_ICOLL_INTERRUPT49_SET HW_ICOLL_INTERRUPT49_TOG HW_ICOLL_INTERRUPT5 HW_ICOLL_INTERRUPT5_CLR HW_ICOLL_INTERRUPT5_SET HW_ICOLL_INTERRUPT5_TOG HW_ICOLL_INTERRUPT50 HW_ICOLL_INTERRUPT50_CLR HW_ICOLL_INTERRUPT50_SET HW_ICOLL_INTERRUPT50_TOG HW_ICOLL_INTERRUPT51 HW_ICOLL_INTERRUPT51_CLR HW_ICOLL_INTERRUPT51_SET HW_ICOLL_INTERRUPT51_TOG HW_ICOLL_INTERRUPT52 HW_ICOLL_INTERRUPT52_CLR HW_ICOLL_INTERRUPT52_SET HW_ICOLL_INTERRUPT52_TOG HW_ICOLL_INTERRUPT53 HW_ICOLL_INTERRUPT53_CLR HW_ICOLL_INTERRUPT53_SET HW_ICOLL_INTERRUPT53_TOG HW_ICOLL_INTERRUPT54 HW_ICOLL_INTERRUPT54_CLR HW_ICOLL_INTERRUPT54_SET HW_ICOLL_INTERRUPT54_TOG HW_ICOLL_INTERRUPT55 HW_ICOLL_INTERRUPT55_CLR HW_ICOLL_INTERRUPT55_SET HW_ICOLL_INTERRUPT55_TOG HW_ICOLL_INTERRUPT56 HW_ICOLL_INTERRUPT56_CLR Address 0x80000438 0x80000434 0x8000043C 0x80000170 0x80000178 0x80000174 0x8000017C 0x80000440 0x80000448 0x80000444 0x8000044C 0x80000450 0x80000458 0x80000454 0x8000045C 0x80000460 0x80000468 0x80000464 0x8000046C 0x80000470 0x80000478 0x80000474 0x8000047C 0x80000480 0x80000488 0x80000484 0x8000048C 0x80000490 0x80000498 0x80000494 0x8000049C 0x800004A0 0x800004A8 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-33 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT56_SET HW_ICOLL_INTERRUPT56_TOG HW_ICOLL_INTERRUPT57 HW_ICOLL_INTERRUPT57_CLR HW_ICOLL_INTERRUPT57_SET HW_ICOLL_INTERRUPT57_TOG HW_ICOLL_INTERRUPT58 HW_ICOLL_INTERRUPT58_CLR HW_ICOLL_INTERRUPT58_SET HW_ICOLL_INTERRUPT58_TOG HW_ICOLL_INTERRUPT59 HW_ICOLL_INTERRUPT59_CLR HW_ICOLL_INTERRUPT59_SET HW_ICOLL_INTERRUPT59_TOG HW_ICOLL_INTERRUPT6 HW_ICOLL_INTERRUPT6_CLR HW_ICOLL_INTERRUPT6_SET HW_ICOLL_INTERRUPT6_TOG HW_ICOLL_INTERRUPT60 HW_ICOLL_INTERRUPT60_CLR HW_ICOLL_INTERRUPT60_SET HW_ICOLL_INTERRUPT60_TOG HW_ICOLL_INTERRUPT61 HW_ICOLL_INTERRUPT61_CLR HW_ICOLL_INTERRUPT61_SET HW_ICOLL_INTERRUPT61_TOG HW_ICOLL_INTERRUPT62 HW_ICOLL_INTERRUPT62_CLR HW_ICOLL_INTERRUPT62_SET HW_ICOLL_INTERRUPT62_TOG HW_ICOLL_INTERRUPT63 HW_ICOLL_INTERRUPT63_CLR HW_ICOLL_INTERRUPT63_SET Address 0x800004A4 0x800004AC 0x800004B0 0x800004B8 0x800004B4 0x800004BC 0x800004C0 0x800004C8 0x800004C4 0x800004CC 0x800004D0 0x800004D8 0x800004D4 0x800004DC 0x80000180 0x80000188 0x80000184 0x8000018C 0x800004E0 0x800004E8 0x800004E4 0x800004EC 0x800004F0 0x800004F8 0x800004F4 0x800004FC 0x80000500 0x80000508 0x80000504 0x8000050C 0x80000510 0x80000518 0x80000514 i.MX23 Applications Processor Reference Manual, Rev. 1 B-34 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT63_TOG HW_ICOLL_INTERRUPT64 HW_ICOLL_INTERRUPT64_CLR HW_ICOLL_INTERRUPT64_SET HW_ICOLL_INTERRUPT64_TOG HW_ICOLL_INTERRUPT65 HW_ICOLL_INTERRUPT65_CLR HW_ICOLL_INTERRUPT65_SET HW_ICOLL_INTERRUPT65_TOG HW_ICOLL_INTERRUPT66 HW_ICOLL_INTERRUPT66_CLR HW_ICOLL_INTERRUPT66_SET HW_ICOLL_INTERRUPT66_TOG HW_ICOLL_INTERRUPT67 HW_ICOLL_INTERRUPT67_CLR HW_ICOLL_INTERRUPT67_SET HW_ICOLL_INTERRUPT67_TOG HW_ICOLL_INTERRUPT68 HW_ICOLL_INTERRUPT68_CLR HW_ICOLL_INTERRUPT68_SET HW_ICOLL_INTERRUPT68_TOG HW_ICOLL_INTERRUPT69 HW_ICOLL_INTERRUPT69_CLR HW_ICOLL_INTERRUPT69_SET HW_ICOLL_INTERRUPT69_TOG HW_ICOLL_INTERRUPT7 HW_ICOLL_INTERRUPT7_CLR HW_ICOLL_INTERRUPT7_SET HW_ICOLL_INTERRUPT7_TOG HW_ICOLL_INTERRUPT70 HW_ICOLL_INTERRUPT70_CLR HW_ICOLL_INTERRUPT70_SET HW_ICOLL_INTERRUPT70_TOG Address 0x8000051C 0x80000520 0x80000528 0x80000524 0x8000052C 0x80000530 0x80000538 0x80000534 0x8000053C 0x80000540 0x80000548 0x80000544 0x8000054C 0x80000550 0x80000558 0x80000554 0x8000055C 0x80000560 0x80000568 0x80000564 0x8000056C 0x80000570 0x80000578 0x80000574 0x8000057C 0x80000190 0x80000198 0x80000194 0x8000019C 0x80000580 0x80000588 0x80000584 0x8000058C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-35 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT71 HW_ICOLL_INTERRUPT71_CLR HW_ICOLL_INTERRUPT71_SET HW_ICOLL_INTERRUPT71_TOG HW_ICOLL_INTERRUPT72 HW_ICOLL_INTERRUPT72_CLR HW_ICOLL_INTERRUPT72_SET HW_ICOLL_INTERRUPT72_TOG HW_ICOLL_INTERRUPT73 HW_ICOLL_INTERRUPT73_CLR HW_ICOLL_INTERRUPT73_SET HW_ICOLL_INTERRUPT73_TOG HW_ICOLL_INTERRUPT74 HW_ICOLL_INTERRUPT74_CLR HW_ICOLL_INTERRUPT74_SET HW_ICOLL_INTERRUPT74_TOG HW_ICOLL_INTERRUPT75 HW_ICOLL_INTERRUPT75_CLR HW_ICOLL_INTERRUPT75_SET HW_ICOLL_INTERRUPT75_TOG HW_ICOLL_INTERRUPT76 HW_ICOLL_INTERRUPT76_CLR HW_ICOLL_INTERRUPT76_SET HW_ICOLL_INTERRUPT76_TOG HW_ICOLL_INTERRUPT77 HW_ICOLL_INTERRUPT77_CLR HW_ICOLL_INTERRUPT77_SET HW_ICOLL_INTERRUPT77_TOG HW_ICOLL_INTERRUPT78 HW_ICOLL_INTERRUPT78_CLR HW_ICOLL_INTERRUPT78_SET HW_ICOLL_INTERRUPT78_TOG HW_ICOLL_INTERRUPT79 Address 0x80000590 0x80000598 0x80000594 0x8000059C 0x800005A0 0x800005A8 0x800005A4 0x800005AC 0x800005B0 0x800005B8 0x800005B4 0x800005BC 0x800005C0 0x800005C8 0x800005C4 0x800005CC 0x800005D0 0x800005D8 0x800005D4 0x800005DC 0x800005E0 0x800005E8 0x800005E4 0x800005EC 0x800005F0 0x800005F8 0x800005F4 0x800005FC 0x80000600 0x80000608 0x80000604 0x8000060C 0x80000610 i.MX23 Applications Processor Reference Manual, Rev. 1 B-36 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT79_CLR HW_ICOLL_INTERRUPT79_SET HW_ICOLL_INTERRUPT79_TOG HW_ICOLL_INTERRUPT8 HW_ICOLL_INTERRUPT8_CLR HW_ICOLL_INTERRUPT8_SET HW_ICOLL_INTERRUPT8_TOG HW_ICOLL_INTERRUPT80 HW_ICOLL_INTERRUPT80_CLR HW_ICOLL_INTERRUPT80_SET HW_ICOLL_INTERRUPT80_TOG HW_ICOLL_INTERRUPT81 HW_ICOLL_INTERRUPT81_CLR HW_ICOLL_INTERRUPT81_SET HW_ICOLL_INTERRUPT81_TOG HW_ICOLL_INTERRUPT82 HW_ICOLL_INTERRUPT82_CLR HW_ICOLL_INTERRUPT82_SET HW_ICOLL_INTERRUPT82_TOG HW_ICOLL_INTERRUPT83 HW_ICOLL_INTERRUPT83_CLR HW_ICOLL_INTERRUPT83_SET HW_ICOLL_INTERRUPT83_TOG HW_ICOLL_INTERRUPT84 HW_ICOLL_INTERRUPT84_CLR HW_ICOLL_INTERRUPT84_SET HW_ICOLL_INTERRUPT84_TOG HW_ICOLL_INTERRUPT85 HW_ICOLL_INTERRUPT85_CLR HW_ICOLL_INTERRUPT85_SET HW_ICOLL_INTERRUPT85_TOG HW_ICOLL_INTERRUPT86 HW_ICOLL_INTERRUPT86_CLR Address 0x80000618 0x80000614 0x8000061C 0x800001A0 0x800001A8 0x800001A4 0x800001AC 0x80000620 0x80000628 0x80000624 0x8000062C 0x80000630 0x80000638 0x80000634 0x8000063C 0x80000640 0x80000648 0x80000644 0x8000064C 0x80000650 0x80000658 0x80000654 0x8000065C 0x80000660 0x80000668 0x80000664 0x8000066C 0x80000670 0x80000678 0x80000674 0x8000067C 0x80000680 0x80000688 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-37 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT86_SET HW_ICOLL_INTERRUPT86_TOG HW_ICOLL_INTERRUPT87 HW_ICOLL_INTERRUPT87_CLR HW_ICOLL_INTERRUPT87_SET HW_ICOLL_INTERRUPT87_TOG HW_ICOLL_INTERRUPT88 HW_ICOLL_INTERRUPT88_CLR HW_ICOLL_INTERRUPT88_SET HW_ICOLL_INTERRUPT88_TOG HW_ICOLL_INTERRUPT89 HW_ICOLL_INTERRUPT89_CLR HW_ICOLL_INTERRUPT89_SET HW_ICOLL_INTERRUPT89_TOG HW_ICOLL_INTERRUPT9 HW_ICOLL_INTERRUPT9_CLR HW_ICOLL_INTERRUPT9_SET HW_ICOLL_INTERRUPT9_TOG HW_ICOLL_INTERRUPT90 HW_ICOLL_INTERRUPT90_CLR HW_ICOLL_INTERRUPT90_SET HW_ICOLL_INTERRUPT90_TOG HW_ICOLL_INTERRUPT91 HW_ICOLL_INTERRUPT91_CLR HW_ICOLL_INTERRUPT91_SET HW_ICOLL_INTERRUPT91_TOG HW_ICOLL_INTERRUPT92 HW_ICOLL_INTERRUPT92_CLR HW_ICOLL_INTERRUPT92_SET HW_ICOLL_INTERRUPT92_TOG HW_ICOLL_INTERRUPT93 HW_ICOLL_INTERRUPT93_CLR HW_ICOLL_INTERRUPT93_SET Address 0x80000684 0x8000068C 0x80000690 0x80000698 0x80000694 0x8000069C 0x800006A0 0x800006A8 0x800006A4 0x800006AC 0x800006B0 0x800006B8 0x800006B4 0x800006BC 0x800001B0 0x800001B8 0x800001B4 0x800001BC 0x800006C0 0x800006C8 0x800006C4 0x800006CC 0x800006D0 0x800006D8 0x800006D4 0x800006DC 0x800006E0 0x800006E8 0x800006E4 0x800006EC 0x800006F0 0x800006F8 0x800006F4 i.MX23 Applications Processor Reference Manual, Rev. 1 B-38 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_INTERRUPT93_TOG HW_ICOLL_INTERRUPT94 HW_ICOLL_INTERRUPT94_CLR HW_ICOLL_INTERRUPT94_SET HW_ICOLL_INTERRUPT94_TOG HW_ICOLL_INTERRUPT95 HW_ICOLL_INTERRUPT95_CLR HW_ICOLL_INTERRUPT95_SET HW_ICOLL_INTERRUPT95_TOG HW_ICOLL_INTERRUPT96 HW_ICOLL_INTERRUPT96_CLR HW_ICOLL_INTERRUPT96_SET HW_ICOLL_INTERRUPT96_TOG HW_ICOLL_INTERRUPT97 HW_ICOLL_INTERRUPT97_CLR HW_ICOLL_INTERRUPT97_SET HW_ICOLL_INTERRUPT97_TOG HW_ICOLL_INTERRUPT98 HW_ICOLL_INTERRUPT98_CLR HW_ICOLL_INTERRUPT98_SET HW_ICOLL_INTERRUPT98_TOG HW_ICOLL_INTERRUPT99 HW_ICOLL_INTERRUPT99_CLR HW_ICOLL_INTERRUPT99_SET HW_ICOLL_INTERRUPT99_TOG HW_ICOLL_LEVELACK HW_ICOLL_RAW0 HW_ICOLL_RAW0_CLR HW_ICOLL_RAW0_SET HW_ICOLL_RAW0_TOG HW_ICOLL_RAW1 HW_ICOLL_RAW1_CLR HW_ICOLL_RAW1_SET Address 0x800006FC 0x80000700 0x80000708 0x80000704 0x8000070C 0x80000710 0x80000718 0x80000714 0x8000071C 0x80000720 0x80000728 0x80000724 0x8000072C 0x80000730 0x80000738 0x80000734 0x8000073C 0x80000740 0x80000748 0x80000744 0x8000074C 0x80000750 0x80000758 0x80000754 0x8000075C 0x80000010 0x800000A0 0x800000A8 0x800000A4 0x800000AC 0x800000B0 0x800000B8 0x800000B4 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-39 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_ICOLL_RAW1_TOG HW_ICOLL_RAW2 HW_ICOLL_RAW2_CLR HW_ICOLL_RAW2_SET HW_ICOLL_RAW2_TOG HW_ICOLL_RAW3 HW_ICOLL_RAW3_CLR HW_ICOLL_RAW3_SET HW_ICOLL_RAW3_TOG HW_ICOLL_STAT HW_ICOLL_VBASE HW_ICOLL_VBASE_CLR HW_ICOLL_VBASE_SET HW_ICOLL_VBASE_TOG HW_ICOLL_VECTOR HW_ICOLL_VECTOR_CLR HW_ICOLL_VECTOR_SET HW_ICOLL_VECTOR_TOG HW_ICOLL_VERSION HW_IR_CTRL HW_IR_CTRL_CLR HW_IR_CTRL_SET HW_IR_CTRL_TOG HW_IR_DATA HW_IR_DBGCTRL HW_IR_DBGCTRL_CLR HW_IR_DBGCTRL_SET HW_IR_DBGCTRL_TOG HW_IR_DEBUG HW_IR_INTR HW_IR_INTR_CLR HW_IR_INTR_SET HW_IR_INTR_TOG Address 0x800000BC 0x800000C0 0x800000C8 0x800000C4 0x800000CC 0x800000D0 0x800000D8 0x800000D4 0x800000DC 0x80000070 0x80000040 0x80000048 0x80000044 0x8000004C 0x80000000 0x80000008 0x80000004 0x8000000C 0x800011E0 0x80078000 0x80078008 0x80078004 0x8007800C 0x80078050 0x80078030 0x80078038 0x80078034 0x8007803C 0x80078090 0x80078040 0x80078048 0x80078044 0x8007804C i.MX23 Applications Processor Reference Manual, Rev. 1 B-40 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_IR_RXDMA HW_IR_RXDMA_CLR HW_IR_RXDMA_SET HW_IR_RXDMA_TOG HW_IR_SI_READ HW_IR_STAT HW_IR_TCCTRL HW_IR_TCCTRL_CLR HW_IR_TCCTRL_SET HW_IR_TCCTRL_TOG HW_IR_TXDMA HW_IR_TXDMA_CLR HW_IR_TXDMA_SET HW_IR_TXDMA_TOG HW_IR_VERSION HW_LCDIF_BM_ERROR_STAT HW_LCDIF_CSC_COEFF0 HW_LCDIF_CSC_COEFF1 HW_LCDIF_CSC_COEFF2 HW_LCDIF_CSC_COEFF3 HW_LCDIF_CSC_COEFF4 HW_LCDIF_CSC_LIMIT HW_LCDIF_CSC_OFFSET HW_LCDIF_CTRL HW_LCDIF_CTRL_CLR HW_LCDIF_CTRL_SET HW_LCDIF_CTRL_TOG HW_LCDIF_CTRL1 HW_LCDIF_CTRL1_CLR HW_LCDIF_CTRL1_SET HW_LCDIF_CTRL1_TOG HW_LCDIF_CUR_BUF HW_LCDIF_DATA Address 0x80078020 0x80078028 0x80078024 0x8007802C 0x80078080 0x80078060 0x80078070 0x80078078 0x80078074 0x8007807C 0x80078010 0x80078018 0x80078014 0x8007801C 0x800780a0 0x800301c0 0x80030110 0x80030120 0x80030130 0x80030140 0x80030150 0x80030170 0x80030160 0x80030000 0x80030008 0x80030004 0x8003000C 0x80030010 0x80030018 0x80030014 0x8003001C 0x80030030 0x800301b0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-41 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_LCDIF_DEBUG0 HW_LCDIF_DEBUG1 HW_LCDIF_DVICTRL0 HW_LCDIF_DVICTRL1 HW_LCDIF_DVICTRL2 HW_LCDIF_DVICTRL3 HW_LCDIF_DVICTRL4 HW_LCDIF_NEXT_BUF HW_LCDIF_PAGETABLE HW_LCDIF_PIN_SHARING_CTRL0 HW_LCDIF_PIN_SHARING_CTRL0_CLR HW_LCDIF_PIN_SHARING_CTRL0_SET HW_LCDIF_PIN_SHARING_CTRL0_TOG HW_LCDIF_PIN_SHARING_CTRL1 HW_LCDIF_PIN_SHARING_CTRL2 HW_LCDIF_STAT HW_LCDIF_TIMING HW_LCDIF_TRANSFER_COUNT HW_LCDIF_VDCTRL0 HW_LCDIF_VDCTRL0_CLR HW_LCDIF_VDCTRL0_SET HW_LCDIF_VDCTRL0_TOG HW_LCDIF_VDCTRL1 HW_LCDIF_VDCTRL2 HW_LCDIF_VDCTRL3 HW_LCDIF_VDCTRL4 HW_LCDIF_VERSION HW_LRADC_CH0 HW_LRADC_CH0_CLR HW_LRADC_CH0_SET HW_LRADC_CH0_TOG HW_LRADC_CH1 HW_LRADC_CH1_CLR Address 0x800301f0 0x80030200 0x800300c0 0x800300d0 0x800300e0 0x800300f0 0x80030100 0x80030040 0x80030050 0x80030180 0x80030188 0x80030184 0x8003018C 0x80030190 0x800301a0 0x800301d0 0x80030060 0x80030020 0x80030070 0x80030078 0x80030074 0x8003007C 0x80030080 0x80030090 0x800300a0 0x800300b0 0x800301e0 0x80050050 0x80050058 0x80050054 0x8005005C 0x80050060 0x80050068 i.MX23 Applications Processor Reference Manual, Rev. 1 B-42 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_LRADC_CH1_SET HW_LRADC_CH1_TOG HW_LRADC_CH2 HW_LRADC_CH2_CLR HW_LRADC_CH2_SET HW_LRADC_CH2_TOG HW_LRADC_CH3 HW_LRADC_CH3_CLR HW_LRADC_CH3_SET HW_LRADC_CH3_TOG HW_LRADC_CH4 HW_LRADC_CH4_CLR HW_LRADC_CH4_SET HW_LRADC_CH4_TOG HW_LRADC_CH5 HW_LRADC_CH5_CLR HW_LRADC_CH5_SET HW_LRADC_CH5_TOG HW_LRADC_CH6 HW_LRADC_CH6_CLR HW_LRADC_CH6_SET HW_LRADC_CH6_TOG HW_LRADC_CH7 HW_LRADC_CH7_CLR HW_LRADC_CH7_SET HW_LRADC_CH7_TOG HW_LRADC_CONVERSION HW_LRADC_CONVERSION_CLR HW_LRADC_CONVERSION_SET HW_LRADC_CONVERSION_TOG HW_LRADC_CTRL0 HW_LRADC_CTRL0_CLR HW_LRADC_CTRL0_SET Address 0x80050064 0x8005006C 0x80050070 0x80050078 0x80050074 0x8005007C 0x80050080 0x80050088 0x80050084 0x8005008C 0x80050090 0x80050098 0x80050094 0x8005009C 0x800500A0 0x800500A8 0x800500A4 0x800500AC 0x800500B0 0x800500B8 0x800500B4 0x800500BC 0x800500C0 0x800500C8 0x800500C4 0x800500CC 0x80050130 0x80050138 0x80050134 0x8005013C 0x80050000 0x80050008 0x80050004 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-43 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_LRADC_CTRL0_TOG HW_LRADC_CTRL1 HW_LRADC_CTRL1_CLR HW_LRADC_CTRL1_SET HW_LRADC_CTRL1_TOG HW_LRADC_CTRL2 HW_LRADC_CTRL2_CLR HW_LRADC_CTRL2_SET HW_LRADC_CTRL2_TOG HW_LRADC_CTRL3 HW_LRADC_CTRL3_CLR HW_LRADC_CTRL3_SET HW_LRADC_CTRL3_TOG HW_LRADC_CTRL4 HW_LRADC_CTRL4_CLR HW_LRADC_CTRL4_SET HW_LRADC_CTRL4_TOG HW_LRADC_DEBUG0 HW_LRADC_DEBUG0_CLR HW_LRADC_DEBUG0_SET HW_LRADC_DEBUG0_TOG HW_LRADC_DEBUG1 HW_LRADC_DEBUG1_CLR HW_LRADC_DEBUG1_SET HW_LRADC_DEBUG1_TOG HW_LRADC_DELAY0 HW_LRADC_DELAY0_CLR HW_LRADC_DELAY0_SET HW_LRADC_DELAY0_TOG HW_LRADC_DELAY1 HW_LRADC_DELAY1_CLR HW_LRADC_DELAY1_SET HW_LRADC_DELAY1_TOG Address 0x8005000C 0x80050010 0x80050018 0x80050014 0x8005001C 0x80050020 0x80050028 0x80050024 0x8005002C 0x80050030 0x80050038 0x80050034 0x8005003C 0x80050140 0x80050148 0x80050144 0x8005014C 0x80050110 0x80050118 0x80050114 0x8005011C 0x80050120 0x80050128 0x80050124 0x8005012C 0x800500D0 0x800500D8 0x800500D4 0x800500DC 0x800500E0 0x800500E8 0x800500E4 0x800500EC i.MX23 Applications Processor Reference Manual, Rev. 1 B-44 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_LRADC_DELAY2 HW_LRADC_DELAY2_CLR HW_LRADC_DELAY2_SET HW_LRADC_DELAY2_TOG HW_LRADC_DELAY3 HW_LRADC_DELAY3_CLR HW_LRADC_DELAY3_SET HW_LRADC_DELAY3_TOG HW_LRADC_STATUS HW_LRADC_STATUS_CLR HW_LRADC_STATUS_SET HW_LRADC_STATUS_TOG HW_LRADC_VERSION HW_OCOTP_CRYPTO0 HW_OCOTP_CRYPTO1 HW_OCOTP_CRYPTO2 HW_OCOTP_CRYPTO3 HW_OCOTP_CTRL HW_OCOTP_CTRL_CLR HW_OCOTP_CTRL_SET HW_OCOTP_CTRL_TOG HW_OCOTP_CUST0 HW_OCOTP_CUST1 HW_OCOTP_CUST2 HW_OCOTP_CUST3 HW_OCOTP_CUSTCAP HW_OCOTP_DATA HW_OCOTP_HWCAP0 HW_OCOTP_HWCAP1 HW_OCOTP_HWCAP2 HW_OCOTP_HWCAP3 HW_OCOTP_HWCAP4 HW_OCOTP_HWCAP5 Address 0x800500F0 0x800500F8 0x800500F4 0x800500FC 0x80050100 0x80050108 0x80050104 0x8005010C 0x80050040 0x80050048 0x80050044 0x8005004C 0x80050150 0x8002C060 0x8002C070 0x8002C080 0x8002C090 0x8002C000 0x8002C008 0x8002C004 0x8002C00C 0x8002C020 0x8002C030 0x8002C040 0x8002C050 0x8002C110 0x8002C010 0x8002C0A0 0x8002C0B0 0x8002C0C0 0x8002C0D0 0x8002C0E0 0x8002C0F0 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-45 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_OCOTP_LOCK HW_OCOTP_OPS0 HW_OCOTP_OPS1 HW_OCOTP_OPS2 HW_OCOTP_OPS3 HW_OCOTP_ROM0 HW_OCOTP_ROM1 HW_OCOTP_ROM2 HW_OCOTP_ROM3 HW_OCOTP_ROM4 HW_OCOTP_ROM5 HW_OCOTP_ROM6 HW_OCOTP_ROM7 HW_OCOTP_SWCAP HW_OCOTP_UN0 HW_OCOTP_UN1 HW_OCOTP_UN2 HW_OCOTP_VERSION HW_PINCTRL_CTRL HW_PINCTRL_CTRL_CLR HW_PINCTRL_CTRL_SET HW_PINCTRL_CTRL_TOG HW_PINCTRL_DIN0 HW_PINCTRL_DIN0_CLR HW_PINCTRL_DIN0_SET HW_PINCTRL_DIN0_TOG HW_PINCTRL_DIN1 HW_PINCTRL_DIN1_CLR HW_PINCTRL_DIN1_SET HW_PINCTRL_DIN1_TOG HW_PINCTRL_DIN2 HW_PINCTRL_DIN2_CLR HW_PINCTRL_DIN2_SET Address 0x8002C120 0x8002C130 0x8002C140 0x8002C150 0x8002C160 0x8002C1A0 0x8002C1B0 0x8002C1C0 0x8002C1D0 0x8002C1E0 0x8002C1F0 0x8002C200 0x8002C210 0x8002C100 0x8002C170 0x8002C180 0x8002C190 0x8002C220 0x80018000 0x80018008 0x80018004 0x8001800C 0x80018600 0x80018608 0x80018604 0x8001860C 0x80018610 0x80018618 0x80018614 0x8001861C 0x80018620 0x80018628 0x80018624 i.MX23 Applications Processor Reference Manual, Rev. 1 B-46 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_PINCTRL_DIN2_TOG HW_PINCTRL_DOE0 HW_PINCTRL_DOE0_CLR HW_PINCTRL_DOE0_SET HW_PINCTRL_DOE0_TOG HW_PINCTRL_DOE1 HW_PINCTRL_DOE1_CLR HW_PINCTRL_DOE1_SET HW_PINCTRL_DOE1_TOG HW_PINCTRL_DOE2 HW_PINCTRL_DOE2_CLR HW_PINCTRL_DOE2_SET HW_PINCTRL_DOE2_TOG HW_PINCTRL_DOUT0 HW_PINCTRL_DOUT0_CLR HW_PINCTRL_DOUT0_SET HW_PINCTRL_DOUT0_TOG HW_PINCTRL_DOUT1 HW_PINCTRL_DOUT1_CLR HW_PINCTRL_DOUT1_SET HW_PINCTRL_DOUT1_TOG HW_PINCTRL_DOUT2 HW_PINCTRL_DOUT2_CLR HW_PINCTRL_DOUT2_SET HW_PINCTRL_DOUT2_TOG HW_PINCTRL_DRIVE0 HW_PINCTRL_DRIVE0_CLR HW_PINCTRL_DRIVE0_SET HW_PINCTRL_DRIVE0_TOG HW_PINCTRL_DRIVE1 HW_PINCTRL_DRIVE1_CLR HW_PINCTRL_DRIVE1_SET HW_PINCTRL_DRIVE1_TOG Address 0x8001862C 0x80018700 0x80018708 0x80018704 0x8001870C 0x80018710 0x80018718 0x80018714 0x8001871C 0x80018720 0x80018728 0x80018724 0x8001872C 0x80018500 0x80018508 0x80018504 0x8001850C 0x80018510 0x80018518 0x80018514 0x8001851C 0x80018520 0x80018528 0x80018524 0x8001852C 0x80018200 0x80018208 0x80018204 0x8001820C 0x80018210 0x80018218 0x80018214 0x8001821C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-47 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_PINCTRL_DRIVE10 HW_PINCTRL_DRIVE10_CLR HW_PINCTRL_DRIVE10_SET HW_PINCTRL_DRIVE10_TOG HW_PINCTRL_DRIVE11 HW_PINCTRL_DRIVE11_CLR HW_PINCTRL_DRIVE11_SET HW_PINCTRL_DRIVE11_TOG HW_PINCTRL_DRIVE12 HW_PINCTRL_DRIVE12_CLR HW_PINCTRL_DRIVE12_SET HW_PINCTRL_DRIVE12_TOG HW_PINCTRL_DRIVE13 HW_PINCTRL_DRIVE13_CLR HW_PINCTRL_DRIVE13_SET HW_PINCTRL_DRIVE13_TOG HW_PINCTRL_DRIVE14 HW_PINCTRL_DRIVE14_CLR HW_PINCTRL_DRIVE14_SET HW_PINCTRL_DRIVE14_TOG HW_PINCTRL_DRIVE2 HW_PINCTRL_DRIVE2_CLR HW_PINCTRL_DRIVE2_SET HW_PINCTRL_DRIVE2_TOG HW_PINCTRL_DRIVE3 HW_PINCTRL_DRIVE3_CLR HW_PINCTRL_DRIVE3_SET HW_PINCTRL_DRIVE3_TOG HW_PINCTRL_DRIVE4 HW_PINCTRL_DRIVE4_CLR HW_PINCTRL_DRIVE4_SET HW_PINCTRL_DRIVE4_TOG HW_PINCTRL_DRIVE5 Address 0x800182a0 0x800182a8 0x800182a4 0x800182aC 0x800182b0 0x800182b8 0x800182b4 0x800182bC 0x800182c0 0x800182c8 0x800182c4 0x800182cC 0x800182d0 0x800182d8 0x800182d4 0x800182dC 0x800182e0 0x800182e8 0x800182e4 0x800182eC 0x80018220 0x80018228 0x80018224 0x8001822C 0x80018230 0x80018238 0x80018234 0x8001823C 0x80018240 0x80018248 0x80018244 0x8001824C 0x80018250 i.MX23 Applications Processor Reference Manual, Rev. 1 B-48 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_PINCTRL_DRIVE5_CLR HW_PINCTRL_DRIVE5_SET HW_PINCTRL_DRIVE5_TOG HW_PINCTRL_DRIVE6 HW_PINCTRL_DRIVE6_CLR HW_PINCTRL_DRIVE6_SET HW_PINCTRL_DRIVE6_TOG HW_PINCTRL_DRIVE7 HW_PINCTRL_DRIVE7_CLR HW_PINCTRL_DRIVE7_SET HW_PINCTRL_DRIVE7_TOG HW_PINCTRL_DRIVE8 HW_PINCTRL_DRIVE8_CLR HW_PINCTRL_DRIVE8_SET HW_PINCTRL_DRIVE8_TOG HW_PINCTRL_DRIVE9 HW_PINCTRL_DRIVE9_CLR HW_PINCTRL_DRIVE9_SET HW_PINCTRL_DRIVE9_TOG HW_PINCTRL_IRQEN0 HW_PINCTRL_IRQEN0_CLR HW_PINCTRL_IRQEN0_SET HW_PINCTRL_IRQEN0_TOG HW_PINCTRL_IRQEN1 HW_PINCTRL_IRQEN1_CLR HW_PINCTRL_IRQEN1_SET HW_PINCTRL_IRQEN1_TOG HW_PINCTRL_IRQEN2 HW_PINCTRL_IRQEN2_CLR HW_PINCTRL_IRQEN2_SET HW_PINCTRL_IRQEN2_TOG HW_PINCTRL_IRQLEVEL0 HW_PINCTRL_IRQLEVEL0_CLR Address 0x80018258 0x80018254 0x8001825C 0x80018260 0x80018268 0x80018264 0x8001826C 0x80018270 0x80018278 0x80018274 0x8001827C 0x80018280 0x80018288 0x80018284 0x8001828C 0x80018290 0x80018298 0x80018294 0x8001829C 0x80018900 0x80018908 0x80018904 0x8001890C 0x80018910 0x80018918 0x80018914 0x8001891C 0x80018920 0x80018928 0x80018924 0x8001892C 0x80018a00 0x80018a08 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-49 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_PINCTRL_IRQLEVEL0_SET HW_PINCTRL_IRQLEVEL0_TOG HW_PINCTRL_IRQLEVEL1 HW_PINCTRL_IRQLEVEL1_CLR HW_PINCTRL_IRQLEVEL1_SET HW_PINCTRL_IRQLEVEL1_TOG HW_PINCTRL_IRQLEVEL2 HW_PINCTRL_IRQLEVEL2_CLR HW_PINCTRL_IRQLEVEL2_SET HW_PINCTRL_IRQLEVEL2_TOG HW_PINCTRL_IRQPOL0 HW_PINCTRL_IRQPOL0_CLR HW_PINCTRL_IRQPOL0_SET HW_PINCTRL_IRQPOL0_TOG HW_PINCTRL_IRQPOL1 HW_PINCTRL_IRQPOL1_CLR HW_PINCTRL_IRQPOL1_SET HW_PINCTRL_IRQPOL1_TOG HW_PINCTRL_IRQPOL2 HW_PINCTRL_IRQPOL2_CLR HW_PINCTRL_IRQPOL2_SET HW_PINCTRL_IRQPOL2_TOG HW_PINCTRL_IRQSTAT0 HW_PINCTRL_IRQSTAT0_CLR HW_PINCTRL_IRQSTAT0_SET HW_PINCTRL_IRQSTAT0_TOG HW_PINCTRL_IRQSTAT1 HW_PINCTRL_IRQSTAT1_CLR HW_PINCTRL_IRQSTAT1_SET HW_PINCTRL_IRQSTAT1_TOG HW_PINCTRL_IRQSTAT2 HW_PINCTRL_IRQSTAT2_CLR HW_PINCTRL_IRQSTAT2_SET Address 0x80018a04 0x80018a0C 0x80018a10 0x80018a18 0x80018a14 0x80018a1C 0x80018a20 0x80018a28 0x80018a24 0x80018a2C 0x80018b00 0x80018b08 0x80018b04 0x80018b0C 0x80018b10 0x80018b18 0x80018b14 0x80018b1C 0x80018b20 0x80018b28 0x80018b24 0x80018b2C 0x80018c00 0x80018c08 0x80018c04 0x80018c0C 0x80018c10 0x80018c18 0x80018c14 0x80018c1C 0x80018c20 0x80018c28 0x80018c24 i.MX23 Applications Processor Reference Manual, Rev. 1 B-50 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_PINCTRL_IRQSTAT2_TOG HW_PINCTRL_MUXSEL0 HW_PINCTRL_MUXSEL0_CLR HW_PINCTRL_MUXSEL0_SET HW_PINCTRL_MUXSEL0_TOG HW_PINCTRL_MUXSEL1 HW_PINCTRL_MUXSEL1_CLR HW_PINCTRL_MUXSEL1_SET HW_PINCTRL_MUXSEL1_TOG HW_PINCTRL_MUXSEL2 HW_PINCTRL_MUXSEL2_CLR HW_PINCTRL_MUXSEL2_SET HW_PINCTRL_MUXSEL2_TOG HW_PINCTRL_MUXSEL3 HW_PINCTRL_MUXSEL3_CLR HW_PINCTRL_MUXSEL3_SET HW_PINCTRL_MUXSEL3_TOG HW_PINCTRL_MUXSEL4 HW_PINCTRL_MUXSEL4_CLR HW_PINCTRL_MUXSEL4_SET HW_PINCTRL_MUXSEL4_TOG HW_PINCTRL_MUXSEL5 HW_PINCTRL_MUXSEL5_CLR HW_PINCTRL_MUXSEL5_SET HW_PINCTRL_MUXSEL5_TOG HW_PINCTRL_MUXSEL6 HW_PINCTRL_MUXSEL6_CLR HW_PINCTRL_MUXSEL6_SET HW_PINCTRL_MUXSEL6_TOG HW_PINCTRL_MUXSEL7 HW_PINCTRL_MUXSEL7_CLR HW_PINCTRL_MUXSEL7_SET HW_PINCTRL_MUXSEL7_TOG Address 0x80018c2C 0x80018100 0x80018108 0x80018104 0x8001810C 0x80018110 0x80018118 0x80018114 0x8001811C 0x80018120 0x80018128 0x80018124 0x8001812C 0x80018130 0x80018138 0x80018134 0x8001813C 0x80018140 0x80018148 0x80018144 0x8001814C 0x80018150 0x80018158 0x80018154 0x8001815C 0x80018160 0x80018168 0x80018164 0x8001816C 0x80018170 0x80018178 0x80018174 0x8001817C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-51 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_PINCTRL_PIN2IRQ0 HW_PINCTRL_PIN2IRQ0_CLR HW_PINCTRL_PIN2IRQ0_SET HW_PINCTRL_PIN2IRQ0_TOG HW_PINCTRL_PIN2IRQ1 HW_PINCTRL_PIN2IRQ1_CLR HW_PINCTRL_PIN2IRQ1_SET HW_PINCTRL_PIN2IRQ1_TOG HW_PINCTRL_PIN2IRQ2 HW_PINCTRL_PIN2IRQ2_CLR HW_PINCTRL_PIN2IRQ2_SET HW_PINCTRL_PIN2IRQ2_TOG HW_PINCTRL_PULL0 HW_PINCTRL_PULL0_CLR HW_PINCTRL_PULL0_SET HW_PINCTRL_PULL0_TOG HW_PINCTRL_PULL1 HW_PINCTRL_PULL1_CLR HW_PINCTRL_PULL1_SET HW_PINCTRL_PULL1_TOG HW_PINCTRL_PULL2 HW_PINCTRL_PULL2_CLR HW_PINCTRL_PULL2_SET HW_PINCTRL_PULL2_TOG HW_PINCTRL_PULL3 HW_PINCTRL_PULL3_CLR HW_PINCTRL_PULL3_SET HW_PINCTRL_PULL3_TOG HW_POWER_5VCTRL HW_POWER_5VCTRL_CLR HW_POWER_5VCTRL_SET HW_POWER_5VCTRL_TOG HW_POWER_BATTMONITOR Address 0x80018800 0x80018808 0x80018804 0x8001880C 0x80018810 0x80018818 0x80018814 0x8001881C 0x80018820 0x80018828 0x80018824 0x8001882C 0x80018400 0x80018408 0x80018404 0x8001840C 0x80018410 0x80018418 0x80018414 0x8001841C 0x80018420 0x80018428 0x80018424 0x8001842C 0x80018430 0x80018438 0x80018434 0x8001843C 0x80044010 0x80044018 0x80044014 0x8004401C 0x800440E0 i.MX23 Applications Processor Reference Manual, Rev. 1 B-52 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_POWER_CHARGE HW_POWER_CHARGE_CLR HW_POWER_CHARGE_SET HW_POWER_CHARGE_TOG HW_POWER_CTRL HW_POWER_CTRL_CLR HW_POWER_CTRL_SET HW_POWER_CTRL_TOG HW_POWER_DCDC4P2 HW_POWER_DCLIMITS HW_POWER_DEBUG HW_POWER_DEBUG_CLR HW_POWER_DEBUG_SET HW_POWER_DEBUG_TOG HW_POWER_LOOPCTRL HW_POWER_LOOPCTRL_CLR HW_POWER_LOOPCTRL_SET HW_POWER_LOOPCTRL_TOG HW_POWER_MINPWR HW_POWER_MINPWR_CLR HW_POWER_MINPWR_SET HW_POWER_MINPWR_TOG HW_POWER_MISC HW_POWER_RESET HW_POWER_RESET_CLR HW_POWER_RESET_SET HW_POWER_RESET_TOG HW_POWER_SPECIAL HW_POWER_SPECIAL_CLR HW_POWER_SPECIAL_SET HW_POWER_SPECIAL_TOG HW_POWER_SPEED HW_POWER_SPEED_CLR Address 0x80044030 0x80044038 0x80044034 0x8004403C 0x80044000 0x80044008 0x80044004 0x8004400C 0x80044080 0x800440A0 0x80044110 0x80044118 0x80044114 0x8004411C 0x800440B0 0x800440B8 0x800440B4 0x800440BC 0x80044020 0x80044028 0x80044024 0x8004402C 0x80044090 0x80044100 0x80044108 0x80044104 0x8004410C 0x80044120 0x80044128 0x80044124 0x8004412C 0x800440D0 0x800440D8 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-53 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_POWER_SPEED_SET HW_POWER_SPEED_TOG HW_POWER_STS HW_POWER_VDDACTRL HW_POWER_VDDDCTRL HW_POWER_VDDIOCTRL HW_POWER_VDDMEMCTRL HW_POWER_VERSION HW_PWM_ACTIVE0 HW_PWM_ACTIVE0_CLR HW_PWM_ACTIVE0_SET HW_PWM_ACTIVE0_TOG HW_PWM_ACTIVE1 HW_PWM_ACTIVE1_CLR HW_PWM_ACTIVE1_SET HW_PWM_ACTIVE1_TOG HW_PWM_ACTIVE2 HW_PWM_ACTIVE2_CLR HW_PWM_ACTIVE2_SET HW_PWM_ACTIVE2_TOG HW_PWM_ACTIVE3 HW_PWM_ACTIVE3_CLR HW_PWM_ACTIVE3_SET HW_PWM_ACTIVE3_TOG HW_PWM_ACTIVE4 HW_PWM_ACTIVE4_CLR HW_PWM_ACTIVE4_SET HW_PWM_ACTIVE4_TOG HW_PWM_CTRL HW_PWM_CTRL_CLR HW_PWM_CTRL_SET HW_PWM_CTRL_TOG HW_PWM_PERIOD0 Address 0x800440D4 0x800440DC 0x800440C0 0x80044050 0x80044040 0x80044060 0x80044070 0x80044130 0x80064010 0x80064018 0x80064014 0x8006401C 0x80064030 0x80064038 0x80064034 0x8006403C 0x80064050 0x80064058 0x80064054 0x8006405C 0x80064070 0x80064078 0x80064074 0x8006407C 0x80064090 0x80064098 0x80064094 0x8006409C 0x80064000 0x80064008 0x80064004 0x8006400C 0x80064020 i.MX23 Applications Processor Reference Manual, Rev. 1 B-54 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_PWM_PERIOD0_CLR HW_PWM_PERIOD0_SET HW_PWM_PERIOD0_TOG HW_PWM_PERIOD1 HW_PWM_PERIOD1_CLR HW_PWM_PERIOD1_SET HW_PWM_PERIOD1_TOG HW_PWM_PERIOD2 HW_PWM_PERIOD2_CLR HW_PWM_PERIOD2_SET HW_PWM_PERIOD2_TOG HW_PWM_PERIOD3 HW_PWM_PERIOD3_CLR HW_PWM_PERIOD3_SET HW_PWM_PERIOD3_TOG HW_PWM_PERIOD4 HW_PWM_PERIOD4_CLR HW_PWM_PERIOD4_SET HW_PWM_PERIOD4_TOG HW_PWM_VERSION HW_PXP_CSCCOEFF0 HW_PXP_CSCCOEFF1 HW_PXP_CSCCOEFF2 HW_PXP_CTRL HW_PXP_CTRL_CLR HW_PXP_CTRL_SET HW_PXP_CTRL_TOG HW_PXP_DEBUG HW_PXP_DEBUGCTRL HW_PXP_NEXT HW_PXP_NEXT_CLR HW_PXP_NEXT_SET HW_PXP_NEXT_TOG Address 0x80064028 0x80064024 0x8006402C 0x80064040 0x80064048 0x80064044 0x8006404C 0x80064060 0x80064068 0x80064064 0x8006406C 0x80064080 0x80064088 0x80064084 0x8006408C 0x800640A0 0x800640A8 0x800640A4 0x800640AC 0x800640b0 0x8002A0D0 0x8002A0E0 0x8002A0F0 0x8002A000 0x8002A008 0x8002A004 0x8002A00C 0x8002A1E0 0x8002A1D0 0x8002A100 0x8002A108 0x8002A104 0x8002A10C i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-55 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_PXP_OL0 HW_PXP_OL0PARAM HW_PXP_OL0PARAM2 HW_PXP_OL0SIZE HW_PXP_OL1 HW_PXP_OL1PARAM HW_PXP_OL1PARAM2 HW_PXP_OL1SIZE HW_PXP_OL2 HW_PXP_OL2PARAM HW_PXP_OL2PARAM2 HW_PXP_OL2SIZE HW_PXP_OL3 HW_PXP_OL3PARAM HW_PXP_OL3PARAM2 HW_PXP_OL3SIZE HW_PXP_OL4 HW_PXP_OL4PARAM HW_PXP_OL4PARAM2 HW_PXP_OL4SIZE HW_PXP_OL5 HW_PXP_OL5PARAM HW_PXP_OL5PARAM2 HW_PXP_OL5SIZE HW_PXP_OL6 HW_PXP_OL6PARAM HW_PXP_OL6PARAM2 HW_PXP_OL6SIZE HW_PXP_OL7 HW_PXP_OL7PARAM HW_PXP_OL7PARAM2 HW_PXP_OL7SIZE HW_PXP_OLCOLORKEYHIGH Address 0x8002a200 0x8002a220 0x8002a230 0x8002a210 0x8002a240 0x8002a260 0x8002a270 0x8002a250 0x8002a280 0x8002a2a0 0x8002a2b0 0x8002a290 0x8002a2c0 0x8002a2e0 0x8002a2f0 0x8002a2d0 0x8002a300 0x8002a320 0x8002a330 0x8002a310 0x8002a340 0x8002a360 0x8002a370 0x8002a350 0x8002a380 0x8002a3a0 0x8002a3b0 0x8002a390 0x8002a3c0 0x8002a3e0 0x8002a3f0 0x8002a3d0 0x8002A1B0 i.MX23 Applications Processor Reference Manual, Rev. 1 B-56 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_PXP_OLCOLORKEYLOW HW_PXP_PAGETABLE HW_PXP_RGBBUF HW_PXP_RGBBUF2 HW_PXP_RGBSIZE HW_PXP_S0BACKGROUND HW_PXP_S0BUF HW_PXP_S0COLORKEYHIGH HW_PXP_S0COLORKEYLOW HW_PXP_S0CROP HW_PXP_S0OFFSET HW_PXP_S0PARAM HW_PXP_S0SCALE HW_PXP_S0UBUF HW_PXP_S0VBUF HW_PXP_STAT HW_PXP_STAT_CLR HW_PXP_STAT_SET HW_PXP_STAT_TOG HW_PXP_VERSION HW_RTC_ALARM HW_RTC_ALARM_CLR HW_RTC_ALARM_SET HW_RTC_ALARM_TOG HW_RTC_CTRL HW_RTC_CTRL_CLR HW_RTC_CTRL_SET HW_RTC_CTRL_TOG HW_RTC_DEBUG HW_RTC_DEBUG_CLR HW_RTC_DEBUG_SET HW_RTC_DEBUG_TOG HW_RTC_MILLISECONDS Address 0x8002A1A0 0x8002A170 0x8002A020 0x8002A030 0x8002A040 0x8002A090 0x8002A050 0x8002A190 0x8002A180 0x8002A0A0 0x8002A0C0 0x8002A080 0x8002A0B0 0x8002A060 0x8002A070 0x8002A010 0x8002A018 0x8002A014 0x8002A01C 0x8002A1F0 0x8005C040 0x8005C048 0x8005C044 0x8005C04C 0x8005C000 0x8005C008 0x8005C004 0x8005C00C 0x8005C0C0 0x8005C0C8 0x8005C0C4 0x8005C0CC 0x8005C020 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-57 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_RTC_MILLISECONDS_CLR HW_RTC_MILLISECONDS_SET HW_RTC_MILLISECONDS_TOG HW_RTC_PERSISTENT0 HW_RTC_PERSISTENT0_CLR HW_RTC_PERSISTENT0_SET HW_RTC_PERSISTENT0_TOG HW_RTC_PERSISTENT1 HW_RTC_PERSISTENT1_CLR HW_RTC_PERSISTENT1_SET HW_RTC_PERSISTENT1_TOG HW_RTC_PERSISTENT2 HW_RTC_PERSISTENT2_CLR HW_RTC_PERSISTENT2_SET HW_RTC_PERSISTENT2_TOG HW_RTC_PERSISTENT3 HW_RTC_PERSISTENT3_CLR HW_RTC_PERSISTENT3_SET HW_RTC_PERSISTENT3_TOG HW_RTC_PERSISTENT4 HW_RTC_PERSISTENT4_CLR HW_RTC_PERSISTENT4_SET HW_RTC_PERSISTENT4_TOG HW_RTC_PERSISTENT5 HW_RTC_PERSISTENT5_CLR HW_RTC_PERSISTENT5_SET HW_RTC_PERSISTENT5_TOG HW_RTC_SECONDS HW_RTC_SECONDS_CLR HW_RTC_SECONDS_SET HW_RTC_SECONDS_TOG HW_RTC_STAT HW_RTC_STAT_CLR Address 0x8005C028 0x8005C024 0x8005C02C 0x8005C060 0x8005C068 0x8005C064 0x8005C06C 0x8005C070 0x8005C078 0x8005C074 0x8005C07C 0x8005C080 0x8005C088 0x8005C084 0x8005C08C 0x8005C090 0x8005C098 0x8005C094 0x8005C09C 0x8005C0A0 0x8005C0A8 0x8005C0A4 0x8005C0AC 0x8005C0B0 0x8005C0B8 0x8005C0B4 0x8005C0BC 0x8005C030 0x8005C038 0x8005C034 0x8005C03C 0x8005C010 0x8005C018 i.MX23 Applications Processor Reference Manual, Rev. 1 B-58 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_RTC_STAT_SET HW_RTC_STAT_TOG HW_RTC_VERSION HW_RTC_WATCHDOG HW_RTC_WATCHDOG_CLR HW_RTC_WATCHDOG_SET HW_RTC_WATCHDOG_TOG HW_SAIF_CTRL HW_SAIF_CTRL_CLR HW_SAIF_CTRL_SET HW_SAIF_CTRL_TOG HW_SAIF_DATA HW_SAIF_DATA_CLR HW_SAIF_DATA_SET HW_SAIF_DATA_TOG HW_SAIF_STAT HW_SAIF_STAT_CLR HW_SAIF_STAT_SET HW_SAIF_STAT_TOG HW_SAIF_VERSION HW_SPDIF_CTRL HW_SPDIF_CTRL_CLR HW_SPDIF_CTRL_SET HW_SPDIF_CTRL_TOG HW_SPDIF_DATA HW_SPDIF_DATA_CLR HW_SPDIF_DATA_SET HW_SPDIF_DATA_TOG HW_SPDIF_DEBUG HW_SPDIF_DEBUG_CLR HW_SPDIF_DEBUG_SET HW_SPDIF_DEBUG_TOG HW_SPDIF_FRAMECTRL Address 0x8005C014 0x8005C01C 0x8005C0D0 0x8005C050 0x8005C058 0x8005C054 0x8005C05C 0x80042000 0x80042008 0x80042004 0x8004200C 0x80042020 0x80042028 0x80042024 0x8004202C 0x80042010 0x80042018 0x80042014 0x8004201C 0x80042030 0x80054000 0x80054008 0x80054004 0x8005400C 0x80054050 0x80054058 0x80054054 0x8005405C 0x80054040 0x80054048 0x80054044 0x8005404C 0x80054020 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-59 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_SPDIF_FRAMECTRL_CLR HW_SPDIF_FRAMECTRL_SET HW_SPDIF_FRAMECTRL_TOG HW_SPDIF_SRR HW_SPDIF_SRR_CLR HW_SPDIF_SRR_SET HW_SPDIF_SRR_TOG HW_SPDIF_STAT HW_SPDIF_STAT_CLR HW_SPDIF_STAT_SET HW_SPDIF_STAT_TOG HW_SPDIF_VERSION HW_SSP_CMD0 HW_SSP_CMD0_CLR HW_SSP_CMD0_SET HW_SSP_CMD0_TOG HW_SSP_CMD1 HW_SSP_COMPMASK HW_SSP_COMPREF HW_SSP_CTRL0 HW_SSP_CTRL0_CLR HW_SSP_CTRL0_SET HW_SSP_CTRL0_TOG HW_SSP_CTRL1 HW_SSP_CTRL1_CLR HW_SSP_CTRL1_SET HW_SSP_CTRL1_TOG HW_SSP_DATA HW_SSP_DEBUG HW_SSP_SDRESP0 HW_SSP_SDRESP1 HW_SSP_SDRESP2 HW_SSP_SDRESP3 Address 0x80054028 0x80054024 0x8005402C 0x80054030 0x80054038 0x80054034 0x8005403C 0x80054010 0x80054018 0x80054014 0x8005401C 0x80054060 0x80010010 0x80010018 0x80010014 0x8001001C 0x80010020 0x80010040 0x80010030 0x80010000 0x80010008 0x80010004 0x8001000C 0x80010060 0x80010068 0x80010064 0x8001006C 0x80010070 0x80010100 0x80010080 0x80010090 0x800100A0 0x800100B0 i.MX23 Applications Processor Reference Manual, Rev. 1 B-60 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_SSP_STATUS HW_SSP_TIMING HW_SSP_VERSION HW_TIMROT_ROTCOUNT HW_TIMROT_ROTCTRL HW_TIMROT_ROTCTRL_CLR HW_TIMROT_ROTCTRL_SET HW_TIMROT_ROTCTRL_TOG HW_TIMROT_TIMCOUNT0 HW_TIMROT_TIMCOUNT1 HW_TIMROT_TIMCOUNT2 HW_TIMROT_TIMCOUNT3 HW_TIMROT_TIMCTRL0 HW_TIMROT_TIMCTRL0_CLR HW_TIMROT_TIMCTRL0_SET HW_TIMROT_TIMCTRL0_TOG HW_TIMROT_TIMCTRL1 HW_TIMROT_TIMCTRL1_CLR HW_TIMROT_TIMCTRL1_SET HW_TIMROT_TIMCTRL1_TOG HW_TIMROT_TIMCTRL2 HW_TIMROT_TIMCTRL2_CLR HW_TIMROT_TIMCTRL2_SET HW_TIMROT_TIMCTRL2_TOG HW_TIMROT_TIMCTRL3 HW_TIMROT_TIMCTRL3_CLR HW_TIMROT_TIMCTRL3_SET HW_TIMROT_TIMCTRL3_TOG HW_TIMROT_VERSION HW_TVENC_CLOSEDCAPTION HW_TVENC_CLOSEDCAPTION_CLR HW_TVENC_CLOSEDCAPTION_SET HW_TVENC_CLOSEDCAPTION_TOG Address 0x800100C0 0x80010050 0x80010110 0x80068010 0x80068000 0x80068008 0x80068004 0x8006800C 0x80068030 0x80068050 0x80068070 0x80068090 0x80068020 0x80068028 0x80068024 0x8006802C 0x80068040 0x80068048 0x80068044 0x8006804C 0x80068060 0x80068068 0x80068064 0x8006806C 0x80068080 0x80068088 0x80068084 0x8006808C 0x800680a0 0x800380f0 0x800380f8 0x800380f4 0x800380fC i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-61 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_TVENC_COLORBURST HW_TVENC_COLORBURST_CLR HW_TVENC_COLORBURST_SET HW_TVENC_COLORBURST_TOG HW_TVENC_COLORSUB0 HW_TVENC_COLORSUB0_CLR HW_TVENC_COLORSUB0_SET HW_TVENC_COLORSUB0_TOG HW_TVENC_COLORSUB1 HW_TVENC_COLORSUB1_CLR HW_TVENC_COLORSUB1_SET HW_TVENC_COLORSUB1_TOG HW_TVENC_CONFIG HW_TVENC_CONFIG_CLR HW_TVENC_CONFIG_SET HW_TVENC_CONFIG_TOG HW_TVENC_COPYPROTECT HW_TVENC_COPYPROTECT_CLR HW_TVENC_COPYPROTECT_SET HW_TVENC_COPYPROTECT_TOG HW_TVENC_CTRL HW_TVENC_CTRL_CLR HW_TVENC_CTRL_SET HW_TVENC_CTRL_TOG HW_TVENC_DACCTRL HW_TVENC_DACCTRL_CLR HW_TVENC_DACCTRL_SET HW_TVENC_DACCTRL_TOG HW_TVENC_DACSTATUS HW_TVENC_DACSTATUS_CLR HW_TVENC_DACSTATUS_SET HW_TVENC_DACSTATUS_TOG HW_TVENC_FILTCTRL Address 0x80038140 0x80038148 0x80038144 0x8003814C 0x800380c0 0x800380c8 0x800380c4 0x800380cC 0x800380d0 0x800380d8 0x800380d4 0x800380dC 0x80038010 0x80038018 0x80038014 0x8003801C 0x800380e0 0x800380e8 0x800380e4 0x800380eC 0x80038000 0x80038008 0x80038004 0x8003800C 0x800381a0 0x800381a8 0x800381a4 0x800381aC 0x800381b0 0x800381b8 0x800381b4 0x800381bC 0x80038020 i.MX23 Applications Processor Reference Manual, Rev. 1 B-62 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_TVENC_FILTCTRL_CLR HW_TVENC_FILTCTRL_SET HW_TVENC_FILTCTRL_TOG HW_TVENC_HTIMINGACTIVE HW_TVENC_HTIMINGACTIVE_CLR HW_TVENC_HTIMINGACTIVE_SET HW_TVENC_HTIMINGACTIVE_TOG HW_TVENC_HTIMINGBURST0 HW_TVENC_HTIMINGBURST0_CLR HW_TVENC_HTIMINGBURST0_SET HW_TVENC_HTIMINGBURST0_TOG HW_TVENC_HTIMINGBURST1 HW_TVENC_HTIMINGBURST1_CLR HW_TVENC_HTIMINGBURST1_SET HW_TVENC_HTIMINGBURST1_TOG HW_TVENC_HTIMINGSYNC0 HW_TVENC_HTIMINGSYNC0_CLR HW_TVENC_HTIMINGSYNC0_SET HW_TVENC_HTIMINGSYNC0_TOG HW_TVENC_HTIMINGSYNC1 HW_TVENC_HTIMINGSYNC1_CLR HW_TVENC_HTIMINGSYNC1_SET HW_TVENC_HTIMINGSYNC1_TOG HW_TVENC_MACROVISION0 HW_TVENC_MACROVISION0_CLR HW_TVENC_MACROVISION0_SET HW_TVENC_MACROVISION0_TOG HW_TVENC_MACROVISION1 HW_TVENC_MACROVISION1_CLR HW_TVENC_MACROVISION1_SET HW_TVENC_MACROVISION1_TOG HW_TVENC_MACROVISION2 HW_TVENC_MACROVISION2_CLR Address 0x80038028 0x80038024 0x8003802C 0x80038060 0x80038068 0x80038064 0x8003806C 0x80038070 0x80038078 0x80038074 0x8003807C 0x80038080 0x80038088 0x80038084 0x8003808C 0x80038040 0x80038048 0x80038044 0x8003804C 0x80038050 0x80038058 0x80038054 0x8003805C 0x80038150 0x80038158 0x80038154 0x8003815C 0x80038160 0x80038168 0x80038164 0x8003816C 0x80038170 0x80038178 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-63 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_TVENC_MACROVISION2_SET HW_TVENC_MACROVISION2_TOG HW_TVENC_MACROVISION3 HW_TVENC_MACROVISION3_CLR HW_TVENC_MACROVISION3_SET HW_TVENC_MACROVISION3_TOG HW_TVENC_MACROVISION4 HW_TVENC_MACROVISION4_CLR HW_TVENC_MACROVISION4_SET HW_TVENC_MACROVISION4_TOG HW_TVENC_MISC HW_TVENC_MISC_CLR HW_TVENC_MISC_SET HW_TVENC_MISC_TOG HW_TVENC_SYNCOFFSET HW_TVENC_SYNCOFFSET_CLR HW_TVENC_SYNCOFFSET_SET HW_TVENC_SYNCOFFSET_TOG HW_TVENC_VDACTEST HW_TVENC_VDACTEST_CLR HW_TVENC_VDACTEST_SET HW_TVENC_VDACTEST_TOG HW_TVENC_VERSION HW_TVENC_VTIMING0 HW_TVENC_VTIMING0_CLR HW_TVENC_VTIMING0_SET HW_TVENC_VTIMING0_TOG HW_TVENC_VTIMING1 HW_TVENC_VTIMING1_CLR HW_TVENC_VTIMING1_SET HW_TVENC_VTIMING1_TOG HW_UARTAPP_CTRL0 HW_UARTAPP_CTRL0_CLR Address 0x80038174 0x8003817C 0x80038180 0x80038188 0x80038184 0x8003818C 0x80038190 0x80038198 0x80038194 0x8003819C 0x800380b0 0x800380b8 0x800380b4 0x800380bC 0x80038030 0x80038038 0x80038034 0x8003803C 0x800381c0 0x800381c8 0x800381c4 0x800381cC 0x800381d0 0x80038090 0x80038098 0x80038094 0x8003809C 0x800380a0 0x800380a8 0x800380a4 0x800380aC 0x8006C000 0x8006C008 i.MX23 Applications Processor Reference Manual, Rev. 1 B-64 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_UARTAPP_CTRL0_SET HW_UARTAPP_CTRL0_TOG HW_UARTAPP_CTRL1 HW_UARTAPP_CTRL1_CLR HW_UARTAPP_CTRL1_SET HW_UARTAPP_CTRL1_TOG HW_UARTAPP_CTRL2 HW_UARTAPP_CTRL2_CLR HW_UARTAPP_CTRL2_SET HW_UARTAPP_CTRL2_TOG HW_UARTAPP_DATA HW_UARTAPP_DEBUG HW_UARTAPP_INTR HW_UARTAPP_INTR_CLR HW_UARTAPP_INTR_SET HW_UARTAPP_INTR_TOG HW_UARTAPP_LINECTRL HW_UARTAPP_LINECTRL_CLR HW_UARTAPP_LINECTRL_SET HW_UARTAPP_LINECTRL_TOG HW_UARTAPP_LINECTRL2 HW_UARTAPP_LINECTRL2_CLR HW_UARTAPP_LINECTRL2_SET HW_UARTAPP_LINECTRL2_TOG HW_UARTAPP_STAT HW_UARTAPP_VERSION HW_UARTDBGCR HW_UARTDBGDMACR HW_UARTDBGDR HW_UARTDBGFBRD HW_UARTDBGFR HW_UARTDBGIBRD HW_UARTDBGICR Address 0x8006C004 0x8006C00C 0x8006C010 0x8006C018 0x8006C014 0x8006C01C 0x8006C020 0x8006C028 0x8006C024 0x8006C02C 0x8006C060 0x8006C080 0x8006C050 0x8006C058 0x8006C054 0x8006C05C 0x8006C030 0x8006C038 0x8006C034 0x8006C03C 0x8006C040 0x8006C048 0x8006C044 0x8006C04C 0x8006C070 0x8006C090 0x80070030 0x80070048 0x80070000 0x80070028 0x80070018 0x80070024 0x80070044 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-65 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_UARTDBGIFLS HW_UARTDBGILPR HW_UARTDBGIMSC HW_UARTDBGLCR_H HW_UARTDBGMIS HW_UARTDBGRIS HW_UARTDBGRSR_ECR HW_USBCTRL_ASYNCLISTADDR HW_USBCTRL_BURSTSIZE HW_USBCTRL_CAPLENGTH HW_USBCTRL_DCCPARAMS HW_USBCTRL_DCIVERSION HW_USBCTRL_DEVICEADDR HW_USBCTRL_ENDPOINTLISTADDR HW_USBCTRL_ENDPTCOMPLETE HW_USBCTRL_ENDPTCTRL0 HW_USBCTRL_ENDPTCTRL1 HW_USBCTRL_ENDPTCTRL2 HW_USBCTRL_ENDPTCTRL3 HW_USBCTRL_ENDPTCTRL4 HW_USBCTRL_ENDPTFLUSH HW_USBCTRL_ENDPTNAK HW_USBCTRL_ENDPTNAKEN HW_USBCTRL_ENDPTPRIME HW_USBCTRL_ENDPTSETUPSTAT HW_USBCTRL_ENDPTSTAT HW_USBCTRL_FRINDEX HW_USBCTRL_GPTIMER0CTRL HW_USBCTRL_GPTIMER0LD HW_USBCTRL_GPTIMER1CTRL HW_USBCTRL_GPTIMER1LD HW_USBCTRL_HCCPARAMS HW_USBCTRL_HCSPARAMS Address 0x80070034 0x80070020 0x80070038 0x8007002C 0x80070040 0x8007003C 0x80070004 0x80080158 0x80080160 0x80080100 0x80080124 0x80080120 0x80080154 0x80080158 0x800801bc 0x800801c0 0x800801c4 0x800801c8 0x800801cc 0x800801d0 0x800801b4 0x80080178 0x8008017c 0x800801b0 0x800801ac 0x800801b8 0x8008014c 0x80080084 0x80080080 0x8008008c 0x80080088 0x80080108 0x80080104 i.MX23 Applications Processor Reference Manual, Rev. 1 B-66 Preliminary--Subject to Change Without Notice Freescale Semiconductor Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_USBCTRL_HWDEVICE HW_USBCTRL_HWGENERAL HW_USBCTRL_HWHOST HW_USBCTRL_HWRXBUF HW_USBCTRL_HWTXBUF HW_USBCTRL_IC_USB HW_USBCTRL_ID HW_USBCTRL_OTGSC HW_USBCTRL_PERIODICLISTBASE HW_USBCTRL_PORTSC1 HW_USBCTRL_SBUSCFG HW_USBCTRL_TTCTRL HW_USBCTRL_TXFILLTUNING HW_USBCTRL_ULPI HW_USBCTRL_USBCMD HW_USBCTRL_USBINTR HW_USBCTRL_USBMODE HW_USBCTRL_USBSTS HW_USBPHY_CTRL HW_USBPHY_CTRL_CLR HW_USBPHY_CTRL_SET HW_USBPHY_CTRL_TOG HW_USBPHY_DEBUG HW_USBPHY_DEBUG_CLR HW_USBPHY_DEBUG_SET HW_USBPHY_DEBUG_TOG HW_USBPHY_DEBUG0_STATUS HW_USBPHY_DEBUG1 HW_USBPHY_DEBUG1_CLR HW_USBPHY_DEBUG1_SET HW_USBPHY_DEBUG1_TOG HW_USBPHY_IP HW_USBPHY_IP_CLR Address 0x8008000c 0x80080004 0x80080008 0x80080014 0x80080010 0x8008016c 0x80080000 0x800801a4 0x80080154 0x80080184 0x80080090 0x8008015c 0x80080164 0x80080170 0x80080140 0x80080148 0x800801a8 0x80080144 0x8007c030 0x8007c038 0x8007c034 0x8007c03c 0x8007c050 0x8007c058 0x8007c054 0x8007c05c 0x8007c060 0x8007c070 0x8007c078 0x8007c074 0x8007c07c 0x8007c090 0x8007c098 i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice B-67 Register Names Table B-1. Register Names and Addresses (continued) Register Name HW_USBPHY_IP_SET HW_USBPHY_IP_TOG HW_USBPHY_PWD HW_USBPHY_PWD_CLR HW_USBPHY_PWD_SET HW_USBPHY_PWD_TOG HW_USBPHY_RX HW_USBPHY_RX_CLR HW_USBPHY_RX_SET HW_USBPHY_RX_TOG HW_USBPHY_STATUS HW_USBPHY_TX HW_USBPHY_TX_CLR HW_USBPHY_TX_SET HW_USBPHY_TX_TOG HW_USBPHY_VERSION Address 0x8007c094 0x8007c09c 0x8007c000 0x8007c008 0x8007c004 0x8007c00c 0x8007c020 0x8007c028 0x8007c024 0x8007c02c 0x8007c040 0x8007c010 0x8007c018 0x8007c014 0x8007c01c 0x8007c080 i.MX23 Applications Processor Reference Manual, Rev. 1 B-68 Preliminary--Subject to Change Without Notice Freescale Semiconductor Appendix C Acronyms and Abbreviations This appendix includes definitions for many of the acronyms and abbreviations found in this product data sheet. AAC: AC: ADC: AES: AHB: AIO: AMBA: APB: APBH: APBX: ARC: ARM: AVC: BATT: BCB: BGA: BIST: BKPT: BLTC: CBC CCS: CE: CLKCTRL: CP: CPUCLK: CRC: CSC: CTS: DABT: DAC: dB: Advanced Audio Coding Audio Coding Analog-to-Digital Converter Advanced Encryption Standard Advanced High-performance Bus Analog Input/Output Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Advanced Peripheral Bus--HCLK Domain Advanced Peripheral Bus--XCLK Domain ARC International (corporate name) Advanced RISC Machine (formerly Acorn RISC Machine) Adaptive Voltage Control Battery Boot Control Block Ball Grid Array Built-In Self-Test Breakpoint Boot Loader Transaction Controller Cipher Block Chaining Command Completion Signaling Consumer Electronics Clock Control Charge Pump Processor (ARM CPU) Clock Cyclic Redundancy Check Color-Space Conversion Clear To Send Data Abort Digital-to-Analog Converter Decibel i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice C-1 Acronyms and Abbreviations DCP: DBBT: DES: DFD: DIGCTL: DIO: DiVX: DMA: DVI: ECB: ECC: EL: EMI: EMICLK: ETM: FIQ: FLPT: FREQ: FS: FSM: GPIO: GPMI: GPMICLK: HCLK: HID: HS: HW: H.264: ICOLL: IrDA: IROVCLK: IRCLK: IRQ: ISR: JEDEC: JPEG: JTAG: LDLB: LFE: Li-Ion: Data Co-Processor Discovered Bad Block Table Data Encryption Standard Digital Fractional Divider Digital Control Digital Input/Output Digital video codec created by DivXNetworks, Inc. Direct Memory Access Digital Video Interface (ITU-R BT.656 mode) Electronic Book Code Error Correction Code Electroluminescent External Memory Interface EMI Clock Embedded Trace Macrocell Fast Peripheral Interrupt First-Level Page Table Frequency Full-Speed Finite State Machine General-Purpose Input/Output General-Purpose Media Interface GMPI Clock Main and HBUS Peripherals Clock Human Interface Device High-Speed Hardware High-Compression Digital Video Codec Interrupt Collector Infrared Data Association IR Clock (sourced from PLL) IR Clock (source from IROVCLK) Normal Peripheral Interrupt Interrupt Service Register Joint Electron Device Engineering Council Joint Photographic Experts Group (computer image format) Joint Test Action Group Logical Drive Layout Block Low Frequency Effects Lithium Ion (battery type) i.MX23 Applications Processor Reference Manual, Rev. 1 C-2 Preliminary--Subject to Change Without Notice Freescale Semiconductor Acronyms and Abbreviations LJ: LQFP: LRADC: LSB: MATT: MBR: MMC: MPEG4: MP3: MSB: Mux: NCB: NiMH: NRZI: NTSC: OCRAM: OCOTP: OTP: PABT: PAL: PCM: PDA: PDDRM: PFD: PFM: PHY: PLL: PITC: PWM: RHID: RJ: RTC: RTS: RMW: SAIF: SB: SDIO: SDK: SHA: SJTAG: Left-Justified Low-Profile Quad Flat Pack Low Resolution ADC Least Significant Bit Multi-chip Attachment mode Master Boot Record Multi-Media Card Motion Picture Experts Group 4 (standard for compressed video at 64 kbps) Moving Picture Experts Group Layer-3 Audio Most Significant Bit Multiplexer NAND Control Block Nickel Metal Hydride Non-Return to Zero Inverted National Television Systems Committee On-chip Random Access Memory On-chip, One Time Programmable One Time Programmable Instruction Pre-Fetch Abort Phase Alternating Line Pulse Code Modulation Personal Digital Assistant Portable Device Digital Rights Management (DRM9) Phase Fractional Divider Pulse Frequency Modulation Physical Layer Protocol Phase-Locked Loop Plug-In Transfer Controller Pulse Width Modulation Recovery Human Interface Device Right-Justified Real-Time Clock Request To Send Read-Modify-Write Serial Audio Interface Safe Boot Secure Digital Input/Output Software Development Kit Secure Hash Algorithm Serial JTAG i.MX23 Applications Processor Reference Manual, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice C-3 Acronyms and Abbreviations SNR: SOC: SPDIF: SPDIFCLK: SPI: SSI: SSP: SWI: TAP: TBD: TDEA THD: TPC: UNDEF: UDMA: UTMI: VAG: VBG: VCO: VDDA: VDDD: VMI: WMDRM10: WMA: XCLK: Signal-to-Noise Ratio System-on-a-Chip Sony-Philips Digital Interface Format SPDIF Clock Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Software Interrupt Test Access Port To Be Determined Triple Data Encryption Algorithm Total Harmonic Distortion Transfer Protocol Commands Undefined instruction Ultra Direct Memory Access USB 2.0 Transceiver Macrocell Interface Analog Ground Voltage Internal Bandgap Voltage Variable Crystal Oscillator Analog Power Digital Power Virtual Memory Interface Windows Media(R) Digital Rights Management 10 (Janus) Windows Media(R) Audio XBUS Peripherals Clock i.MX23 Applications Processor Reference Manual, Rev. 1 C-4 Preliminary--Subject to Change Without Notice Freescale Semiconductor |
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